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Rename USARTx to start at 0

This commit is contained in:
Stefan Kerkmann 2021-03-25 21:56:29 +01:00
parent 031cd8325f
commit 3edcc0f80b
9 changed files with 366 additions and 416 deletions
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124
os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.c
View File

@ -34,18 +34,18 @@
/* Driver exported variables. */ /* Driver exported variables. */
/*===========================================================================*/ /*===========================================================================*/
/** @brief USART0 serial driver identifier.*/
#if GD32_SERIAL_USE_USART0 || defined(__DOXYGEN__)
SerialDriver SD1;
#endif
/** @brief USART1 serial driver identifier.*/ /** @brief USART1 serial driver identifier.*/
#if GD32_SERIAL_USE_USART1 || defined(__DOXYGEN__) #if GD32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
SerialDriver SD1; SerialDriver SD2;
#endif #endif
/** @brief USART2 serial driver identifier.*/ /** @brief USART2 serial driver identifier.*/
#if GD32_SERIAL_USE_USART2 || defined(__DOXYGEN__) #if GD32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
SerialDriver SD2;
#endif
/** @brief USART3 serial driver identifier.*/
#if GD32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
SerialDriver SD3; SerialDriver SD3;
#endif #endif
@ -88,7 +88,7 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
USART_TypeDef *u = sdp->usart; USART_TypeDef *u = sdp->usart;
/* Baud rate setting.*/ /* Baud rate setting.*/
if (sdp->usart == USART1) if (sdp->usart == USART0)
fck = GD32_PCLK2 / config->speed; fck = GD32_PCLK2 / config->speed;
else else
fck = GD32_PCLK1 / config->speed; fck = GD32_PCLK1 / config->speed;
@ -207,27 +207,27 @@ static void serve_interrupt(SerialDriver *sdp) {
} }
} }
#if GD32_SERIAL_USE_USART1 || defined(__DOXYGEN__) #if GD32_SERIAL_USE_USART0 || defined(__DOXYGEN__)
static void notify1(io_queue_t *qp) { static void notify1(io_queue_t *qp) {
(void)qp;
USART0->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
}
#endif
#if GD32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
static void notify2(io_queue_t *qp) {
(void)qp; (void)qp;
USART1->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE; USART1->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
} }
#endif #endif
#if GD32_SERIAL_USE_USART2 || defined(__DOXYGEN__) #if GD32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
static void notify2(io_queue_t *qp) {
(void)qp;
USART2->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
}
#endif
#if GD32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
static void notify3(io_queue_t *qp) { static void notify3(io_queue_t *qp) {
(void)qp; (void)qp;
USART3->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE; USART2->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
} }
#endif #endif
@ -251,6 +251,25 @@ static void notify5(io_queue_t *qp) {
/* Driver interrupt handlers. */ /* Driver interrupt handlers. */
/*===========================================================================*/ /*===========================================================================*/
#if GD32_SERIAL_USE_USART0 || defined(__DOXYGEN__)
#if !defined(GD32_USART0_HANDLER)
#error "GD32_USART0_HANDLER not defined"
#endif
/**
* @brief USART0 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_USART0_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD1);
OSAL_IRQ_EPILOGUE();
}
#endif
#if GD32_SERIAL_USE_USART1 || defined(__DOXYGEN__) #if GD32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
#if !defined(GD32_USART1_HANDLER) #if !defined(GD32_USART1_HANDLER)
#error "GD32_USART1_HANDLER not defined" #error "GD32_USART1_HANDLER not defined"
@ -264,7 +283,7 @@ OSAL_IRQ_HANDLER(GD32_USART1_HANDLER) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD1); serve_interrupt(&SD2);
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
@ -283,25 +302,6 @@ OSAL_IRQ_HANDLER(GD32_USART2_HANDLER) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD2);
OSAL_IRQ_EPILOGUE();
}
#endif
#if GD32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
#if !defined(GD32_USART3_HANDLER)
#error "GD32_USART3_HANDLER not defined"
#endif
/**
* @brief USART3 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_USART3_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_interrupt(&SD3); serve_interrupt(&SD3);
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
@ -357,19 +357,19 @@ OSAL_IRQ_HANDLER(GD32_UART5_HANDLER) {
*/ */
void sd_lld_init(void) { void sd_lld_init(void) {
#if GD32_SERIAL_USE_USART1 #if GD32_SERIAL_USE_USART0
sdObjectInit(&SD1, NULL, notify1); sdObjectInit(&SD1, NULL, notify1);
SD1.usart = USART1; SD1.usart = USART0;
#endif
#if GD32_SERIAL_USE_USART1
sdObjectInit(&SD2, NULL, notify2);
SD2.usart = USART1;
#endif #endif
#if GD32_SERIAL_USE_USART2 #if GD32_SERIAL_USE_USART2
sdObjectInit(&SD2, NULL, notify2);
SD2.usart = USART2;
#endif
#if GD32_SERIAL_USE_USART3
sdObjectInit(&SD3, NULL, notify3); sdObjectInit(&SD3, NULL, notify3);
SD3.usart = USART3; SD3.usart = USART2;
#endif #endif
#if GD32_SERIAL_USE_UART4 #if GD32_SERIAL_USE_UART4
@ -399,24 +399,24 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
config = &default_config; config = &default_config;
if (sdp->state == SD_STOP) { if (sdp->state == SD_STOP) {
#if GD32_SERIAL_USE_USART1 #if GD32_SERIAL_USE_USART0
if (&SD1 == sdp) { if (&SD1 == sdp) {
rccEnableUSART0(true);
eclicEnableVector(GD32_USART0_NUMBER, GD32_SERIAL_USART0_PRIORITY, GD32_SERIAL_USART0_TRIGGER);
}
#endif
#if GD32_SERIAL_USE_USART1
if (&SD2 == sdp) {
rccEnableUSART1(true); rccEnableUSART1(true);
eclicEnableVector(GD32_USART1_NUMBER, GD32_SERIAL_USART1_PRIORITY, GD32_SERIAL_USART1_TRIGGER); eclicEnableVector(GD32_USART1_NUMBER, GD32_SERIAL_USART1_PRIORITY, GD32_SERIAL_USART1_TRIGGER);
} }
#endif #endif
#if GD32_SERIAL_USE_USART2 #if GD32_SERIAL_USE_USART2
if (&SD2 == sdp) { if (&SD3 == sdp) {
rccEnableUSART2(true); rccEnableUSART2(true);
eclicEnableVector(GD32_USART2_NUMBER, GD32_SERIAL_USART2_PRIORITY, GD32_SERIAL_USART2_TRIGGER); eclicEnableVector(GD32_USART2_NUMBER, GD32_SERIAL_USART2_PRIORITY, GD32_SERIAL_USART2_TRIGGER);
} }
#endif #endif
#if GD32_SERIAL_USE_USART3
if (&SD3 == sdp) {
rccEnableUSART3(true);
eclicEnableVector(GD32_USART3_NUMBER, GD32_SERIAL_USART3_PRIORITY, GD32_SERIAL_USART3_TRIGGER);
}
#endif
#if GD32_SERIAL_USE_UART4 #if GD32_SERIAL_USE_UART4
if (&SD4 == sdp) { if (&SD4 == sdp) {
rccEnableUART4(true); rccEnableUART4(true);
@ -446,27 +446,27 @@ void sd_lld_stop(SerialDriver *sdp) {
if (sdp->state == SD_READY) { if (sdp->state == SD_READY) {
usart_deinit(sdp->usart); usart_deinit(sdp->usart);
#if GD32_SERIAL_USE_USART1 #if GD32_SERIAL_USE_USART0
if (&SD1 == sdp) { if (&SD1 == sdp) {
rccDisableUSART0();
eclicDisableVector(GD32_USART0_NUMBER);
return;
}
#endif
#if GD32_SERIAL_USE_USART1
if (&SD2 == sdp) {
rccDisableUSART1(); rccDisableUSART1();
eclicDisableVector(GD32_USART1_NUMBER); eclicDisableVector(GD32_USART1_NUMBER);
return; return;
} }
#endif #endif
#if GD32_SERIAL_USE_USART2 #if GD32_SERIAL_USE_USART2
if (&SD2 == sdp) { if (&SD3 == sdp) {
rccDisableUSART2(); rccDisableUSART2();
eclicDisableVector(GD32_USART2_NUMBER); eclicDisableVector(GD32_USART2_NUMBER);
return; return;
} }
#endif #endif
#if GD32_SERIAL_USE_USART3
if (&SD3 == sdp) {
rccDisableUSART3();
eclicDisableVector(GD32_USART3_NUMBER);
return;
}
#endif
#if GD32_SERIAL_USE_UART4 #if GD32_SERIAL_USE_UART4
if (&SD4 == sdp) { if (&SD4 == sdp) {
rccDisableUART4(); rccDisableUART4();

60
os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.h
View File

@ -39,6 +39,15 @@
* @name Configuration options * @name Configuration options
* @{ * @{
*/ */
/**
* @brief USART0 driver enable switch.
* @details If set to @p TRUE the support for USART0 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_SERIAL_USE_USART0) || defined(__DOXYGEN__)
#define GD32_SERIAL_USE_USART0 FALSE
#endif
/** /**
* @brief USART1 driver enable switch. * @brief USART1 driver enable switch.
* @details If set to @p TRUE the support for USART1 is included. * @details If set to @p TRUE the support for USART1 is included.
@ -57,15 +66,6 @@
#define GD32_SERIAL_USE_USART2 FALSE #define GD32_SERIAL_USE_USART2 FALSE
#endif #endif
/**
* @brief USART3 driver enable switch.
* @details If set to @p TRUE the support for USART3 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_SERIAL_USE_USART3) || defined(__DOXYGEN__)
#define GD32_SERIAL_USE_USART3 FALSE
#endif
/** /**
* @brief UART4 driver enable switch. * @brief UART4 driver enable switch.
* @details If set to @p TRUE the support for UART4 is included. * @details If set to @p TRUE the support for UART4 is included.
@ -84,6 +84,13 @@
#define GD32_SERIAL_USE_UART5 FALSE #define GD32_SERIAL_USE_UART5 FALSE
#endif #endif
/**
* @brief USART0 interrupt priority level setting.
*/
#if !defined(GD32_SERIAL_USART0_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SERIAL_USART0_PRIORITY 12
#endif
/** /**
* @brief USART1 interrupt priority level setting. * @brief USART1 interrupt priority level setting.
*/ */
@ -98,13 +105,6 @@
#define GD32_SERIAL_USART2_PRIORITY 12 #define GD32_SERIAL_USART2_PRIORITY 12
#endif #endif
/**
* @brief USART3 interrupt priority level setting.
*/
#if !defined(GD32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SERIAL_USART3_PRIORITY 12
#endif
/** /**
* @brief UART4 interrupt priority level setting. * @brief UART4 interrupt priority level setting.
*/ */
@ -124,6 +124,10 @@
/* Derived constants and error checks. */ /* Derived constants and error checks. */
/*===========================================================================*/ /*===========================================================================*/
#if GD32_SERIAL_USE_USART0 && !GD32_HAS_USART0
#error "USART0 not present in the selected device"
#endif
#if GD32_SERIAL_USE_USART1 && !GD32_HAS_USART1 #if GD32_SERIAL_USE_USART1 && !GD32_HAS_USART1
#error "USART1 not present in the selected device" #error "USART1 not present in the selected device"
#endif #endif
@ -132,10 +136,6 @@
#error "USART2 not present in the selected device" #error "USART2 not present in the selected device"
#endif #endif
#if GD32_SERIAL_USE_USART3 && !GD32_HAS_USART3
#error "USART3 not present in the selected device"
#endif
#if GD32_SERIAL_USE_UART4 && !GD32_HAS_UART4 #if GD32_SERIAL_USE_UART4 && !GD32_HAS_UART4
#error "UART4 not present in the selected device" #error "UART4 not present in the selected device"
#endif #endif
@ -144,12 +144,17 @@
#error "UART5 not present in the selected device" #error "UART5 not present in the selected device"
#endif #endif
#if !GD32_SERIAL_USE_USART1 && !GD32_SERIAL_USE_USART2 && \ #if !GD32_SERIAL_USE_USART0 && !GD32_SERIAL_USE_USART1 && \
!GD32_SERIAL_USE_USART3 && !GD32_SERIAL_USE_UART4 && \ !GD32_SERIAL_USE_USART2 && !GD32_SERIAL_USE_UART4 && \
!GD32_SERIAL_USE_UART5 !GD32_SERIAL_USE_UART5
#error "SERIAL driver activated but no USART/UART peripheral assigned" #error "SERIAL driver activated but no USART/UART peripheral assigned"
#endif #endif
#if GD32_SERIAL_USE_USART0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_USART0_PRIORITY)
#error "Invalid IRQ priority assigned to USART0"
#endif
#if GD32_SERIAL_USE_USART1 && \ #if GD32_SERIAL_USE_USART1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_USART1_PRIORITY) !OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_USART1_PRIORITY)
#error "Invalid IRQ priority assigned to USART1" #error "Invalid IRQ priority assigned to USART1"
@ -160,11 +165,6 @@
#error "Invalid IRQ priority assigned to USART2" #error "Invalid IRQ priority assigned to USART2"
#endif #endif
#if GD32_SERIAL_USE_USART3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_USART3_PRIORITY)
#error "Invalid IRQ priority assigned to USART3"
#endif
#if GD32_SERIAL_USE_UART4 && \ #if GD32_SERIAL_USE_UART4 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_UART4_PRIORITY) !OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_UART4_PRIORITY)
#error "Invalid IRQ priority assigned to UART4" #error "Invalid IRQ priority assigned to UART4"
@ -244,13 +244,13 @@ typedef struct {
/* External declarations. */ /* External declarations. */
/*===========================================================================*/ /*===========================================================================*/
#if GD32_SERIAL_USE_USART1 && !defined(__DOXYGEN__) #if GD32_SERIAL_USE_USART0 && !defined(__DOXYGEN__)
extern SerialDriver SD1; extern SerialDriver SD1;
#endif #endif
#if GD32_SERIAL_USE_USART2 && !defined(__DOXYGEN__) #if GD32_SERIAL_USE_USART1 && !defined(__DOXYGEN__)
extern SerialDriver SD2; extern SerialDriver SD2;
#endif #endif
#if GD32_SERIAL_USE_USART3 && !defined(__DOXYGEN__) #if GD32_SERIAL_USE_USART2 && !defined(__DOXYGEN__)
extern SerialDriver SD3; extern SerialDriver SD3;
#endif #endif
#if GD32_SERIAL_USE_UART4 && !defined(__DOXYGEN__) #if GD32_SERIAL_USE_UART4 && !defined(__DOXYGEN__)

202
os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.c
View File

@ -30,6 +30,14 @@
/* Driver local definitions. */ /* Driver local definitions. */
/*===========================================================================*/ /*===========================================================================*/
#define USART0_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_UART_USART0_RX_DMA_STREAM, \
GD32_USART0_RX_DMA_CHN)
#define USART0_TX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_UART_USART0_TX_DMA_STREAM, \
GD32_USART0_TX_DMA_CHN)
#define USART1_RX_DMA_CHANNEL \ #define USART1_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_UART_USART1_RX_DMA_STREAM, \ GD32_DMA_GETCHANNEL(GD32_UART_USART1_RX_DMA_STREAM, \
GD32_USART1_RX_DMA_CHN) GD32_USART1_RX_DMA_CHN)
@ -46,14 +54,6 @@
GD32_DMA_GETCHANNEL(GD32_UART_USART2_TX_DMA_STREAM, \ GD32_DMA_GETCHANNEL(GD32_UART_USART2_TX_DMA_STREAM, \
GD32_USART2_TX_DMA_CHN) GD32_USART2_TX_DMA_CHN)
#define USART3_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_UART_USART3_RX_DMA_STREAM, \
GD32_USART3_RX_DMA_CHN)
#define USART3_TX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_UART_USART3_TX_DMA_STREAM, \
GD32_USART3_TX_DMA_CHN)
#define UART4_RX_DMA_CHANNEL \ #define UART4_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_UART_UART4_RX_DMA_STREAM, \ GD32_DMA_GETCHANNEL(GD32_UART_UART4_RX_DMA_STREAM, \
GD32_UART4_RX_DMA_CHN) GD32_UART4_RX_DMA_CHN)
@ -70,30 +70,6 @@
GD32_DMA_GETCHANNEL(GD32_UART_UART5_TX_DMA_STREAM, \ GD32_DMA_GETCHANNEL(GD32_UART_UART5_TX_DMA_STREAM, \
GD32_UART5_TX_DMA_CHN) GD32_UART5_TX_DMA_CHN)
#define USART6_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_UART_USART6_RX_DMA_STREAM, \
GD32_USART6_RX_DMA_CHN)
#define USART6_TX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_UART_USART6_TX_DMA_STREAM, \
GD32_USART6_TX_DMA_CHN)
#define UART7_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_UART_UART7_RX_DMA_STREAM, \
GD32_UART7_RX_DMA_CHN)
#define UART7_TX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_UART_UART7_TX_DMA_STREAM, \
GD32_UART7_TX_DMA_CHN)
#define UART8_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_UART_UART8_RX_DMA_STREAM, \
GD32_UART8_RX_DMA_CHN)
#define UART8_TX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_UART_UART8_TX_DMA_STREAM, \
GD32_UART8_TX_DMA_CHN)
#define GD32_UART45_CR2_CHECK_MASK \ #define GD32_UART45_CR2_CHECK_MASK \
(USART_CTL1_STB_0 | USART_CTL1_CKEN | USART_CTL1_CPL | USART_CTL1_CPH | \ (USART_CTL1_STB_0 | USART_CTL1_CKEN | USART_CTL1_CPL | USART_CTL1_CPH | \
USART_CTL1_CLEN) USART_CTL1_CLEN)
@ -106,18 +82,18 @@
/* Driver exported variables. */ /* Driver exported variables. */
/*===========================================================================*/ /*===========================================================================*/
/** @brief USART0 UART driver identifier.*/
#if GD32_UART_USE_USART0 || defined(__DOXYGEN__)
UARTDriver UARTD1;
#endif
/** @brief USART1 UART driver identifier.*/ /** @brief USART1 UART driver identifier.*/
#if GD32_UART_USE_USART1 || defined(__DOXYGEN__) #if GD32_UART_USE_USART1 || defined(__DOXYGEN__)
UARTDriver UARTD1; UARTDriver UARTD2;
#endif #endif
/** @brief USART2 UART driver identifier.*/ /** @brief USART2 UART driver identifier.*/
#if GD32_UART_USE_USART2 || defined(__DOXYGEN__) #if GD32_UART_USE_USART2 || defined(__DOXYGEN__)
UARTDriver UARTD2;
#endif
/** @brief USART3 UART driver identifier.*/
#if GD32_UART_USE_USART3 || defined(__DOXYGEN__)
UARTDriver UARTD3; UARTDriver UARTD3;
#endif #endif
@ -131,21 +107,6 @@ UARTDriver UARTD4;
UARTDriver UARTD5; UARTDriver UARTD5;
#endif #endif
/** @brief USART6 UART driver identifier.*/
#if GD32_UART_USE_USART6 || defined(__DOXYGEN__)
UARTDriver UARTD6;
#endif
/** @brief UART7 UART driver identifier.*/
#if GD32_UART_USE_UART7 || defined(__DOXYGEN__)
UARTDriver UARTD7;
#endif
/** @brief UART8 UART driver identifier.*/
#if GD32_UART_USE_UART8 || defined(__DOXYGEN__)
UARTDriver UARTD8;
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Driver local variables and types. */ /* Driver local variables and types. */
/*===========================================================================*/ /*===========================================================================*/
@ -230,22 +191,11 @@ static void usart_start(UARTDriver *uartp) {
usart_stop(uartp); usart_stop(uartp);
/* Baud rate setting.*/ /* Baud rate setting.*/
#if GD32_HAS_USART6 if (uartp->usart == USART0)
if ((uartp->usart == USART1) || (uartp->usart == USART6))
#else
if (uartp->usart == USART1)
#endif
fck = GD32_PCLK2 / uartp->config->speed; fck = GD32_PCLK2 / uartp->config->speed;
else else
fck = GD32_PCLK1 / uartp->config->speed; fck = GD32_PCLK1 / uartp->config->speed;
/* Correcting USARTDIV when oversampling by 8 instead of 16.
Fraction is still 4 bits wide, but only lower 3 bits used.
Mantissa is doubled, but Fraction is left the same.*/
#if defined(USART_CTL0_OVER8)
if (uartp->config->ctl0 & USART_CTL0_OVER8)
fck = ((fck & ~7) * 2) | (fck & 7);
#endif
u->BAUD = fck; u->BAUD = fck;
/* Resetting eventual pending status flags.*/ /* Resetting eventual pending status flags.*/
@ -359,6 +309,25 @@ static void serve_usart_irq(UARTDriver *uartp) {
/* Driver interrupt handlers. */ /* Driver interrupt handlers. */
/*===========================================================================*/ /*===========================================================================*/
#if GD32_UART_USE_USART0 || defined(__DOXYGEN__)
#if !defined(GD32_USART0_HANDLER)
#error "GD32_USART0_HANDLER not defined"
#endif
/**
* @brief USART0 IRQ handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_USART0_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD1);
OSAL_IRQ_EPILOGUE();
}
#endif /* GD32_UART_USE_USART0 */
#if GD32_UART_USE_USART1 || defined(__DOXYGEN__) #if GD32_UART_USE_USART1 || defined(__DOXYGEN__)
#if !defined(GD32_USART1_HANDLER) #if !defined(GD32_USART1_HANDLER)
#error "GD32_USART1_HANDLER not defined" #error "GD32_USART1_HANDLER not defined"
@ -372,7 +341,7 @@ OSAL_IRQ_HANDLER(GD32_USART1_HANDLER) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD1); serve_usart_irq(&UARTD2);
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
@ -391,30 +360,11 @@ OSAL_IRQ_HANDLER(GD32_USART2_HANDLER) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD2);
OSAL_IRQ_EPILOGUE();
}
#endif /* GD32_UART_USE_USART2 */
#if GD32_UART_USE_USART3 || defined(__DOXYGEN__)
#if !defined(GD32_USART3_HANDLER)
#error "GD32_USART3_HANDLER not defined"
#endif
/**
* @brief USART3 IRQ handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_USART3_HANDLER) {
OSAL_IRQ_PROLOGUE();
serve_usart_irq(&UARTD3); serve_usart_irq(&UARTD3);
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
#endif /* GD32_UART_USE_USART3 */ #endif /* GD32_UART_USE_USART2 */
#if GD32_UART_USE_UART4 || defined(__DOXYGEN__) #if GD32_UART_USE_UART4 || defined(__DOXYGEN__)
#if !defined(GD32_UART4_HANDLER) #if !defined(GD32_UART4_HANDLER)
@ -465,27 +415,27 @@ OSAL_IRQ_HANDLER(GD32_UART5_HANDLER) {
*/ */
void uart_lld_init(void) { void uart_lld_init(void) {
#if GD32_UART_USE_USART1 #if GD32_UART_USE_USART0
uartObjectInit(&UARTD1); uartObjectInit(&UARTD1);
UARTD1.usart = USART1; UARTD1.usart = USART0;
UARTD1.dmarxmode = GD32_DMA_CTL_ERRIE; UARTD1.dmarxmode = GD32_DMA_CTL_ERRIE;
UARTD1.dmatxmode = GD32_DMA_CTL_ERRIE; UARTD1.dmatxmode = GD32_DMA_CTL_ERRIE;
UARTD1.dmarx = NULL; UARTD1.dmarx = NULL;
UARTD1.dmatx = NULL; UARTD1.dmatx = NULL;
#endif #endif
#if GD32_UART_USE_USART2 #if GD32_UART_USE_USART1
uartObjectInit(&UARTD2); uartObjectInit(&UARTD2);
UARTD2.usart = USART2; UARTD2.usart = USART1;
UARTD2.dmarxmode = GD32_DMA_CTL_ERRIE; UARTD2.dmarxmode = GD32_DMA_CTL_ERRIE;
UARTD2.dmatxmode = GD32_DMA_CTL_ERRIE; UARTD2.dmatxmode = GD32_DMA_CTL_ERRIE;
UARTD2.dmarx = NULL; UARTD2.dmarx = NULL;
UARTD2.dmatx = NULL; UARTD2.dmatx = NULL;
#endif #endif
#if GD32_UART_USE_USART3 #if GD32_UART_USE_USART2
uartObjectInit(&UARTD3); uartObjectInit(&UARTD3);
UARTD3.usart = USART3; UARTD3.usart = USART2;
UARTD3.dmarxmode = GD32_DMA_CTL_ERRIE; UARTD3.dmarxmode = GD32_DMA_CTL_ERRIE;
UARTD3.dmatxmode = GD32_DMA_CTL_ERRIE; UARTD3.dmatxmode = GD32_DMA_CTL_ERRIE;
UARTD3.dmarx = NULL; UARTD3.dmarx = NULL;
@ -521,8 +471,30 @@ void uart_lld_init(void) {
void uart_lld_start(UARTDriver *uartp) { void uart_lld_start(UARTDriver *uartp) {
if (uartp->state == UART_STOP) { if (uartp->state == UART_STOP) {
#if GD32_UART_USE_USART1 #if GD32_UART_USE_USART0
if (&UARTD1 == uartp) { if (&UARTD1 == uartp) {
uartp->dmarx = dmaStreamAllocI(GD32_UART_USART0_RX_DMA_STREAM,
GD32_UART_USART0_IRQ_PRIORITY,
(gd32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(GD32_UART_USART0_TX_DMA_STREAM,
GD32_UART_USART0_IRQ_PRIORITY,
(gd32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART0(true);
eclicEnableVector(GD32_USART0_NUMBER, GD32_UART_USART0_IRQ_PRIORITY, GD32_UART_USART0_IRQ_TRIGGER);
uartp->dmarxmode |= GD32_DMA_CTL_CHSEL(USART0_RX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_UART_USART0_DMA_PRIORITY);
uartp->dmatxmode |= GD32_DMA_CTL_CHSEL(USART0_TX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_UART_USART0_DMA_PRIORITY);
}
#endif
#if GD32_UART_USE_USART1
if (&UARTD2 == uartp) {
uartp->dmarx = dmaStreamAllocI(GD32_UART_USART1_RX_DMA_STREAM, uartp->dmarx = dmaStreamAllocI(GD32_UART_USART1_RX_DMA_STREAM,
GD32_UART_USART1_IRQ_PRIORITY, GD32_UART_USART1_IRQ_PRIORITY,
(gd32_dmaisr_t)uart_lld_serve_rx_end_irq, (gd32_dmaisr_t)uart_lld_serve_rx_end_irq,
@ -544,7 +516,7 @@ void uart_lld_start(UARTDriver *uartp) {
#endif #endif
#if GD32_UART_USE_USART2 #if GD32_UART_USE_USART2
if (&UARTD2 == uartp) { if (&UARTD3 == uartp) {
uartp->dmarx = dmaStreamAllocI(GD32_UART_USART2_RX_DMA_STREAM, uartp->dmarx = dmaStreamAllocI(GD32_UART_USART2_RX_DMA_STREAM,
GD32_UART_USART2_IRQ_PRIORITY, GD32_UART_USART2_IRQ_PRIORITY,
(gd32_dmaisr_t)uart_lld_serve_rx_end_irq, (gd32_dmaisr_t)uart_lld_serve_rx_end_irq,
@ -565,28 +537,6 @@ void uart_lld_start(UARTDriver *uartp) {
} }
#endif #endif
#if GD32_UART_USE_USART3
if (&UARTD3 == uartp) {
uartp->dmarx = dmaStreamAllocI(GD32_UART_USART3_RX_DMA_STREAM,
GD32_UART_USART3_IRQ_PRIORITY,
(gd32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(GD32_UART_USART3_TX_DMA_STREAM,
GD32_UART_USART3_IRQ_PRIORITY,
(gd32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART3(true);
eclicEnableVector(GD32_USART3_NUMBER, GD32_UART_USART3_IRQ_PRIORITY, GD32_UART_USART3_IRQ_TRIGGER);
uartp->dmarxmode |= GD32_DMA_CTL_CHSEL(USART3_RX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_UART_USART3_DMA_PRIORITY);
uartp->dmatxmode |= GD32_DMA_CTL_CHSEL(USART3_TX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_UART_USART3_DMA_PRIORITY);
}
#endif
#if GD32_UART_USE_UART4 #if GD32_UART_USE_UART4
if (&UARTD4 == uartp) { if (&UARTD4 == uartp) {
@ -675,8 +625,16 @@ void uart_lld_stop(UARTDriver *uartp) {
uartp->dmarx = NULL; uartp->dmarx = NULL;
uartp->dmatx = NULL; uartp->dmatx = NULL;
#if GD32_UART_USE_USART1 #if GD32_UART_USE_USART0
if (&UARTD1 == uartp) { if (&UARTD1 == uartp) {
eclicDisableVector(GD32_USART0_NUMBER);
rccDisableUSART0();
return;
}
#endif
#if GD32_UART_USE_USART1
if (&UARTD2 == uartp) {
eclicDisableVector(GD32_USART1_NUMBER); eclicDisableVector(GD32_USART1_NUMBER);
rccDisableUSART1(); rccDisableUSART1();
return; return;
@ -684,21 +642,13 @@ void uart_lld_stop(UARTDriver *uartp) {
#endif #endif
#if GD32_UART_USE_USART2 #if GD32_UART_USE_USART2
if (&UARTD2 == uartp) { if (&UARTD3 == uartp) {
eclicDisableVector(GD32_USART2_NUMBER); eclicDisableVector(GD32_USART2_NUMBER);
rccDisableUSART2(); rccDisableUSART2();
return; return;
} }
#endif #endif
#if GD32_UART_USE_USART3
if (&UARTD3 == uartp) {
eclicDisableVector(GD32_USART3_NUMBER);
rccDisableUSART3();
return;
}
#endif
#if GD32_UART_USE_UART4 #if GD32_UART_USE_UART4
if (&UARTD4 == uartp) { if (&UARTD4 == uartp) {
eclicDisableVector(GD32_UART4_NUMBER); eclicDisableVector(GD32_UART4_NUMBER);

90
os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.h
View File

@ -39,6 +39,15 @@
* @name Configuration options * @name Configuration options
* @{ * @{
*/ */
/**
* @brief UART driver on USART0 enable switch.
* @details If set to @p TRUE the support for USART0 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_UART_USE_USART0) || defined(__DOXYGEN__)
#define GD32_UART_USE_USART0 FALSE
#endif
/** /**
* @brief UART driver on USART1 enable switch. * @brief UART driver on USART1 enable switch.
* @details If set to @p TRUE the support for USART1 is included. * @details If set to @p TRUE the support for USART1 is included.
@ -57,15 +66,6 @@
#define GD32_UART_USE_USART2 FALSE #define GD32_UART_USE_USART2 FALSE
#endif #endif
/**
* @brief UART driver on USART3 enable switch.
* @details If set to @p TRUE the support for USART3 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_UART_USE_USART3) || defined(__DOXYGEN__)
#define GD32_UART_USE_USART3 FALSE
#endif
/** /**
* @brief UART driver on UART4 enable switch. * @brief UART driver on UART4 enable switch.
* @details If set to @p TRUE the support for UART4 is included. * @details If set to @p TRUE the support for UART4 is included.
@ -84,6 +84,13 @@
#define GD32_UART_USE_UART5 FALSE #define GD32_UART_USE_UART5 FALSE
#endif #endif
/**
* @brief USART0 interrupt priority level setting.
*/
#if !defined(GD32_UART_USART0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_USART0_IRQ_PRIORITY 12
#endif
/** /**
* @brief USART1 interrupt priority level setting. * @brief USART1 interrupt priority level setting.
*/ */
@ -98,13 +105,6 @@
#define GD32_UART_USART2_IRQ_PRIORITY 12 #define GD32_UART_USART2_IRQ_PRIORITY 12
#endif #endif
/**
* @brief USART3 interrupt priority level setting.
*/
#if !defined(GD32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_USART3_IRQ_PRIORITY 12
#endif
/** /**
* @brief UART4 interrupt priority level setting. * @brief UART4 interrupt priority level setting.
*/ */
@ -119,6 +119,16 @@
#define GD32_UART_UART5_IRQ_PRIORITY 12 #define GD32_UART_UART5_IRQ_PRIORITY 12
#endif #endif
/**
* @brief USART0 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA channels but
* because of the channels ordering the RX channel has always priority
* over the TX channel.
*/
#if !defined(GD32_UART_USART0_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_USART0_DMA_PRIORITY 0
#endif
/** /**
* @brief USART1 DMA priority (0..3|lowest..highest). * @brief USART1 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA channels but * @note The priority level is used for both the TX and RX DMA channels but
@ -139,16 +149,6 @@
#define GD32_UART_USART2_DMA_PRIORITY 0 #define GD32_UART_USART2_DMA_PRIORITY 0
#endif #endif
/**
* @brief USART3 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA channels but
* because of the channels ordering the RX channel has always priority
* over the TX channel.
*/
#if !defined(GD32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_USART3_DMA_PRIORITY 0
#endif
/** /**
* @brief UART4 DMA priority (0..3|lowest..highest). * @brief UART4 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA channels but * @note The priority level is used for both the TX and RX DMA channels but
@ -183,6 +183,10 @@
/* Derived constants and error checks. */ /* Derived constants and error checks. */
/*===========================================================================*/ /*===========================================================================*/
#if GD32_UART_USE_USART0 && !GD32_HAS_USART0
#error "USART0 not present in the selected device"
#endif
#if GD32_UART_USE_USART1 && !GD32_HAS_USART1 #if GD32_UART_USE_USART1 && !GD32_HAS_USART1
#error "USART1 not present in the selected device" #error "USART1 not present in the selected device"
#endif #endif
@ -191,10 +195,6 @@
#error "USART2 not present in the selected device" #error "USART2 not present in the selected device"
#endif #endif
#if GD32_UART_USE_USART3 && !GD32_HAS_USART3
#error "USART3 not present in the selected device"
#endif
#if GD32_UART_USE_UART4 && !GD32_HAS_UART4 #if GD32_UART_USE_UART4 && !GD32_HAS_UART4
#error "UART4 not present in the selected device" #error "UART4 not present in the selected device"
#endif #endif
@ -203,12 +203,17 @@
#error "UART5 not present in the selected device" #error "UART5 not present in the selected device"
#endif #endif
#if !GD32_UART_USE_USART1 && !GD32_UART_USE_USART2 && \ #if !GD32_UART_USE_USART0 && !GD32_UART_USE_USART1 && \
!GD32_UART_USE_USART3 && !GD32_UART_USE_UART4 && \ !GD32_UART_USE_USART2 && !GD32_UART_USE_UART4 && \
!GD32_UART_USE_UART5 !GD32_UART_USE_UART5
#error "UART driver activated but no USART/UART peripheral assigned" #error "UART driver activated but no USART/UART peripheral assigned"
#endif #endif
#if GD32_UART_USE_USART0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_USART0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to USART0"
#endif
#if GD32_UART_USE_USART1 && \ #if GD32_UART_USE_USART1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_USART1_IRQ_PRIORITY) !OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_USART1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to USART1" #error "Invalid IRQ priority assigned to USART1"
@ -219,11 +224,6 @@
#error "Invalid IRQ priority assigned to USART2" #error "Invalid IRQ priority assigned to USART2"
#endif #endif
#if GD32_UART_USE_USART3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_USART3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to USART3"
#endif
#if GD32_UART_USE_UART4 && \ #if GD32_UART_USE_UART4 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_UART4_IRQ_PRIORITY) !OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_UART4_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to UART4" #error "Invalid IRQ priority assigned to UART4"
@ -234,6 +234,11 @@
#error "Invalid IRQ priority assigned to UART5" #error "Invalid IRQ priority assigned to UART5"
#endif #endif
#if GD32_UART_USE_USART0 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_UART_USART0_DMA_PRIORITY)
#error "Invalid DMA priority assigned to USART0"
#endif
#if GD32_UART_USE_USART1 && \ #if GD32_UART_USE_USART1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_UART_USART1_DMA_PRIORITY) !GD32_DMA_IS_VALID_PRIORITY(GD32_UART_USART1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to USART1" #error "Invalid DMA priority assigned to USART1"
@ -244,11 +249,6 @@
#error "Invalid DMA priority assigned to USART2" #error "Invalid DMA priority assigned to USART2"
#endif #endif
#if GD32_UART_USE_USART3 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_UART_USART3_DMA_PRIORITY)
#error "Invalid DMA priority assigned to USART3"
#endif
#if GD32_UART_USE_UART4 && \ #if GD32_UART_USE_UART4 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_UART_UART4_DMA_PRIORITY) !GD32_DMA_IS_VALID_PRIORITY(GD32_UART_UART4_DMA_PRIORITY)
#error "Invalid DMA priority assigned to UART4" #error "Invalid DMA priority assigned to UART4"
@ -428,15 +428,15 @@ struct UARTDriver {
/* External declarations. */ /* External declarations. */
/*===========================================================================*/ /*===========================================================================*/
#if GD32_UART_USE_USART1 && !defined(__DOXYGEN__) #if GD32_UART_USE_USART0 && !defined(__DOXYGEN__)
extern UARTDriver UARTD1; extern UARTDriver UARTD1;
#endif #endif
#if GD32_UART_USE_USART2 && !defined(__DOXYGEN__) #if GD32_UART_USE_USART1 && !defined(__DOXYGEN__)
extern UARTDriver UARTD2; extern UARTDriver UARTD2;
#endif #endif
#if GD32_UART_USE_USART3 && !defined(__DOXYGEN__) #if GD32_UART_USE_USART2 && !defined(__DOXYGEN__)
extern UARTDriver UARTD3; extern UARTDriver UARTD3;
#endif #endif

16
os/hal/ports/GD/GD32VF103/gd32_isr.h
View File

@ -91,15 +91,15 @@
/* /*
* USART units. * USART units.
*/ */
#define GD32_USART1_HANDLER vector56 #define GD32_USART0_HANDLER vector56
#define GD32_USART2_HANDLER vector57 #define GD32_USART1_HANDLER vector57
#define GD32_USART3_HANDLER vector58 #define GD32_USART2_HANDLER vector58
#define GD32_UART4_HANDLER vector71 #define GD32_UART4_HANDLER vector71
#define GD32_UART5_HANDLER vector72 #define GD32_UART5_HANDLER vector72
#define GD32_USART1_NUMBER 56 #define GD32_USART0_NUMBER 56
#define GD32_USART2_NUMBER 57 #define GD32_USART1_NUMBER 57
#define GD32_USART3_NUMBER 58 #define GD32_USART2_NUMBER 58
#define GD32_UART4_NUMBER 71 #define GD32_UART4_NUMBER 71
#define GD32_UART5_NUMBER 72 #define GD32_UART5_NUMBER 72
@ -274,18 +274,18 @@
#define GD32_SERIAL_UART5_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_SERIAL_UART5_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_UART7_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_SERIAL_UART7_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_UART8_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_SERIAL_UART8_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_USART0_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_USART1_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_SERIAL_USART1_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_USART2_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_SERIAL_USART2_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_USART3_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_USART6_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_SERIAL_USART6_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_UART4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_UART_UART4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_UART5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_UART_UART5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_UART7_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_UART_UART7_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_UART8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_UART_UART8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_USART0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_USART1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_UART_USART1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_USART2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_UART_USART2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_USART3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_USART6_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_UART_USART6_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_USB_USBFS_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_USB_USBFS_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT

54
os/hal/ports/GD/GD32VF103/gd32_rcc.h
View File

@ -1043,6 +1043,30 @@
* @name USART/UART peripherals specific RCC operations * @name USART/UART peripherals specific RCC operations
* @{ * @{
*/ */
/**
* @brief Enables the USART0 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableUSART0(lp) rccEnableAPB2(RCC_APB2ENR_USART0EN, lp)
/**
* @brief Disables the USART0 peripheral clock.
*
* @api
*/
#define rccDisableUSART0() rccDisableAPB2(RCC_APB2ENR_USART0EN)
/**
* @brief Resets the USART0 peripheral.
*
* @api
*/
#define rccResetUSART0() rccResetAPB2(RCC_APB2RSTR_USART0RST)
/** /**
* @brief Enables the USART1 peripheral clock. * @brief Enables the USART1 peripheral clock.
* @note The @p lp parameter is ignored in this family. * @note The @p lp parameter is ignored in this family.
@ -1051,21 +1075,21 @@
* *
* @api * @api
*/ */
#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) #define rccEnableUSART1(lp) rccEnableAPB1(RCC_APB1ENR_USART1EN, lp)
/** /**
* @brief Disables the USART1 peripheral clock. * @brief Disables the USART1 peripheral clock.
* *
* @api * @api
*/ */
#define rccDisableUSART1() rccDisableAPB2(RCC_APB2ENR_USART1EN) #define rccDisableUSART1() rccDisableAPB1(RCC_APB1ENR_USART1EN)
/** /**
* @brief Resets the USART1 peripheral. * @brief Resets the USART1 peripheral.
* *
* @api * @api
*/ */
#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) #define rccResetUSART1() rccResetAPB1(RCC_APB1RSTR_USART1RST)
/** /**
* @brief Enables the USART2 peripheral clock. * @brief Enables the USART2 peripheral clock.
@ -1091,30 +1115,6 @@
*/ */
#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) #define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
/**
* @brief Enables the USART3 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
/**
* @brief Disables the USART3 peripheral clock.
*
* @api
*/
#define rccDisableUSART3() rccDisableAPB1(RCC_APB1ENR_USART3EN)
/**
* @brief Resets the USART3 peripheral.
*
* @api
*/
#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
/** /**
* @brief Enables the UART4 peripheral clock. * @brief Enables the UART4 peripheral clock.
* @note The @p lp parameter is ignored in this family. * @note The @p lp parameter is ignored in this family.

22
os/hal/ports/GD/GD32VF103/gd32_registry.h
View File

@ -268,24 +268,24 @@
/* USART attributes.*/ /* USART attributes.*/
#if GD32_HAS_USART_01 || GD32_HAS_USART_012 || GD32_HAS_USART_01234 #if GD32_HAS_USART_01 || GD32_HAS_USART_012 || GD32_HAS_USART_01234
#define GD32_HAS_USART1 TRUE #define GD32_HAS_USART0 TRUE
#define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4) #define GD32_UART_USART0_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
#define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3) #define GD32_UART_USART0_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
#define GD32_HAS_USART2 TRUE #define GD32_HAS_USART1 TRUE
#define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 5) #define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 5)
#define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 6) #define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 6)
#else #else
#define GD32_HAS_USART0 FALSE
#define GD32_HAS_USART1 FALSE #define GD32_HAS_USART1 FALSE
#define GD32_HAS_USART2 FALSE
#endif #endif
#if GD32_HAS_USART_012 || GD32_HAS_USART_01234 #if GD32_HAS_USART_012 || GD32_HAS_USART_01234
#define GD32_HAS_USART3 TRUE #define GD32_HAS_USART2 TRUE
#define GD32_UART_USART3_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 2) #define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 2)
#define GD32_UART_USART3_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 1) #define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 1)
#else #else
#define GD32_HAS_USART3 FALSE #define GD32_HAS_USART2 FALSE
#endif #endif
#if GD32_HAS_USART_01234 #if GD32_HAS_USART_01234

94
os/hal/ports/GD/GD32VF103/stm32_registry.h
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@ -228,17 +228,17 @@
#define GD32_HAS_TIM22 FALSE #define GD32_HAS_TIM22 FALSE
/* USART attributes.*/ /* USART attributes.*/
#define GD32_HAS_USART0 TRUE
#define GD32_UART_USART0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_UART_USART0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_USART1 TRUE #define GD32_HAS_USART1 TRUE
#define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5) #define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4) #define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_HAS_USART2 TRUE #define GD32_HAS_USART2 TRUE
#define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6) #define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7) #define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_HAS_USART3 TRUE
#define GD32_UART_USART3_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_UART_USART3_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_HAS_UART4 FALSE #define GD32_HAS_UART4 FALSE
#define GD32_HAS_UART5 FALSE #define GD32_HAS_UART5 FALSE
@ -416,15 +416,15 @@
#define GD32_HAS_TIM22 FALSE #define GD32_HAS_TIM22 FALSE
/* USART attributes.*/ /* USART attributes.*/
#define GD32_HAS_USART0 TRUE
#define GD32_UART_USART0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_UART_USART0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_USART1 TRUE #define GD32_HAS_USART1 TRUE
#define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5) #define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4) #define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_HAS_USART2 TRUE #define GD32_HAS_USART2 FALSE
#define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_HAS_USART3 FALSE
#define GD32_HAS_UART4 FALSE #define GD32_HAS_UART4 FALSE
#define GD32_HAS_UART5 FALSE #define GD32_HAS_UART5 FALSE
#define GD32_HAS_USART6 FALSE #define GD32_HAS_USART6 FALSE
@ -611,17 +611,17 @@
#define GD32_HAS_TIM22 FALSE #define GD32_HAS_TIM22 FALSE
/* USART attributes.*/ /* USART attributes.*/
#define GD32_HAS_USART0 TRUE
#define GD32_UART_USART0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_UART_USART0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_USART1 TRUE #define GD32_HAS_USART1 TRUE
#define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5) #define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4) #define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_HAS_USART2 TRUE #define GD32_HAS_USART2 TRUE
#define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6) #define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7) #define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_HAS_USART3 TRUE
#define GD32_UART_USART3_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_UART_USART3_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_HAS_UART4 FALSE #define GD32_HAS_UART4 FALSE
#define GD32_HAS_UART5 FALSE #define GD32_HAS_UART5 FALSE
@ -848,17 +848,17 @@
#define GD32_HAS_TIM22 FALSE #define GD32_HAS_TIM22 FALSE
/* USART attributes.*/ /* USART attributes.*/
#define GD32_HAS_USART0 TRUE
#define GD32_UART_USART0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_UART_USART0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_USART1 TRUE #define GD32_HAS_USART1 TRUE
#define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5) #define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4) #define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_HAS_USART2 TRUE #define GD32_HAS_USART2 TRUE
#define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6) #define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7) #define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_HAS_USART3 TRUE
#define GD32_UART_USART3_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_UART_USART3_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_HAS_UART4 TRUE #define GD32_HAS_UART4 TRUE
#define GD32_UART_UART4_RX_DMA_STREAM GD32_DMA_STREAM_ID(2, 3) #define GD32_UART_UART4_RX_DMA_STREAM GD32_DMA_STREAM_ID(2, 3)
@ -1106,17 +1106,17 @@
#define GD32_HAS_TIM22 FALSE #define GD32_HAS_TIM22 FALSE
/* USART attributes.*/ /* USART attributes.*/
#define GD32_HAS_USART0 TRUE
#define GD32_UART_USART0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_UART_USART0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_USART1 TRUE #define GD32_HAS_USART1 TRUE
#define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5) #define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4) #define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_HAS_USART2 TRUE #define GD32_HAS_USART2 TRUE
#define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6) #define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7) #define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_HAS_USART3 TRUE
#define GD32_UART_USART3_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_UART_USART3_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_HAS_UART4 TRUE #define GD32_HAS_UART4 TRUE
#define GD32_UART_UART4_RX_DMA_STREAM GD32_DMA_STREAM_ID(2, 3) #define GD32_UART_UART4_RX_DMA_STREAM GD32_DMA_STREAM_ID(2, 3)
@ -1344,17 +1344,17 @@
#define GD32_HAS_TIM22 FALSE #define GD32_HAS_TIM22 FALSE
/* USART attributes.*/ /* USART attributes.*/
#define GD32_HAS_USART0 TRUE
#define GD32_UART_USART0_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_UART_USART0_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_USART1 TRUE #define GD32_HAS_USART1 TRUE
#define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5) #define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4) #define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_HAS_USART2 TRUE #define GD32_HAS_USART2 TRUE
#define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6) #define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7) #define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_HAS_USART3 TRUE
#define GD32_UART_USART3_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_UART_USART3_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_HAS_UART4 TRUE #define GD32_HAS_UART4 TRUE
#define GD32_UART_UART4_RX_DMA_STREAM GD32_DMA_STREAM_ID(2, 3) #define GD32_UART_UART4_RX_DMA_STREAM GD32_DMA_STREAM_ID(2, 3)

120
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -710,8 +710,8 @@ typedef struct
#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U) #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) #define USART1_BASE (APB1PERIPH_BASE + 0x00004400U)
#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) #define USART2_BASE (APB1PERIPH_BASE + 0x00004800U)
#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U) #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U) #define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
#define I2C0_BASE (APB1PERIPH_BASE + 0x00005400U) #define I2C0_BASE (APB1PERIPH_BASE + 0x00005400U)
@ -732,7 +732,7 @@ typedef struct
#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U) #define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U) #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) #define USART0_BASE (APB2PERIPH_BASE + 0x00003800U)
#define SDIO_BASE (PERIPH_BASE + 0x00018000U) #define SDIO_BASE (PERIPH_BASE + 0x00018000U)
@ -798,8 +798,8 @@ typedef struct
#define IWDG ((IWDG_TypeDef *)IWDG_BASE) #define IWDG ((IWDG_TypeDef *)IWDG_BASE)
#define SPI2 ((SPI_TypeDef *)SPI2_BASE) #define SPI2 ((SPI_TypeDef *)SPI2_BASE)
#define SPI3 ((SPI_TypeDef *)SPI3_BASE) #define SPI3 ((SPI_TypeDef *)SPI3_BASE)
#define USART1 ((USART_TypeDef *)USART1_BASE)
#define USART2 ((USART_TypeDef *)USART2_BASE) #define USART2 ((USART_TypeDef *)USART2_BASE)
#define USART3 ((USART_TypeDef *)USART3_BASE)
#define UART4 ((USART_TypeDef *)UART4_BASE) #define UART4 ((USART_TypeDef *)UART4_BASE)
#define UART5 ((USART_TypeDef *)UART5_BASE) #define UART5 ((USART_TypeDef *)UART5_BASE)
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) #define I2C0 ((I2C_TypeDef *)I2C0_BASE)
@ -822,7 +822,7 @@ typedef struct
#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) #define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
#define TIM1 ((TIM_TypeDef *)TIM1_BASE) #define TIM1 ((TIM_TypeDef *)TIM1_BASE)
#define SPI1 ((SPI_TypeDef *)SPI1_BASE) #define SPI1 ((SPI_TypeDef *)SPI1_BASE)
#define USART1 ((USART_TypeDef *)USART1_BASE) #define USART0 ((USART_TypeDef *)USART0_BASE)
#define SDIO ((SDIO_TypeDef *)SDIO_BASE) #define SDIO ((SDIO_TypeDef *)SDIO_BASE)
#define DMA0 ((DMA_TypeDef *)DMA0_BASE) #define DMA0 ((DMA_TypeDef *)DMA0_BASE)
#define DMA1 ((DMA_TypeDef *)DMA1_BASE) #define DMA1 ((DMA_TypeDef *)DMA1_BASE)
@ -1534,9 +1534,9 @@ typedef struct
#define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
#define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART0RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART0RST_Msk (0x1U << RCC_APB2RSTR_USART0RST_Pos) /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_USART0RST RCC_APB2RSTR_USART0RST_Msk /*!< USART0 reset */
#define RCC_APB2RSTR_IOPERST_Pos (6U) #define RCC_APB2RSTR_IOPERST_Pos (6U)
@ -1556,9 +1556,9 @@ typedef struct
#define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Pos (11U)
#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
#define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART1RST_Pos (17U)
#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTR_USART1RST_Msk (0x1U << RCC_APB1RSTR_USART1RST_Pos) /*!< 0x00020000 */
#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_USART1RST RCC_APB1RSTR_USART1RST_Msk /*!< USART 2 reset */
#define RCC_APB1RSTR_I2C0RST_Pos (21U) #define RCC_APB1RSTR_I2C0RST_Pos (21U)
#define RCC_APB1RSTR_I2C0RST_Msk (0x1U << RCC_APB1RSTR_I2C0RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C0RST_Msk (0x1U << RCC_APB1RSTR_I2C0RST_Pos) /*!< 0x00200000 */
#define RCC_APB1RSTR_I2C0RST RCC_APB1RSTR_I2C0RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_I2C0RST RCC_APB1RSTR_I2C0RST_Msk /*!< I2C 1 reset */
@ -1580,9 +1580,9 @@ typedef struct
#define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Pos (14U)
#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
#define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART2RST_Pos (18U)
#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00040000 */
#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 3 reset */
#define RCC_APB1RSTR_I2C1RST_Pos (22U) #define RCC_APB1RSTR_I2C1RST_Pos (22U)
#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00400000 */ #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00400000 */
#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 2 reset */ #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 2 reset */
@ -1670,9 +1670,9 @@ typedef struct
#define RCC_APB2ENR_SPI1EN_Pos (12U) #define RCC_APB2ENR_SPI1EN_Pos (12U)
#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
#define RCC_APB2ENR_USART1EN_Pos (14U) #define RCC_APB2ENR_USART0EN_Pos (14U)
#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ #define RCC_APB2ENR_USART0EN_Msk (0x1U << RCC_APB2ENR_USART0EN_Pos) /*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ #define RCC_APB2ENR_USART0EN RCC_APB2ENR_USART0EN_Msk /*!< USART0 clock enable */
#define RCC_APB2ENR_IOPEEN_Pos (6U) #define RCC_APB2ENR_IOPEEN_Pos (6U)
@ -1692,9 +1692,9 @@ typedef struct
#define RCC_APB1ENR_WWDGEN_Pos (11U) #define RCC_APB1ENR_WWDGEN_Pos (11U)
#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
#define RCC_APB1ENR_USART2EN_Pos (17U) #define RCC_APB1ENR_USART1EN_Pos (17U)
#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ #define RCC_APB1ENR_USART1EN_Msk (0x1U << RCC_APB1ENR_USART1EN_Pos) /*!< 0x00020000 */
#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ #define RCC_APB1ENR_USART1EN RCC_APB1ENR_USART1EN_Msk /*!< USART 2 clock enable */
#define RCC_APB1ENR_I2C0EN_Pos (21U) #define RCC_APB1ENR_I2C0EN_Pos (21U)
#define RCC_APB1ENR_I2C0EN_Msk (0x1U << RCC_APB1ENR_I2C0EN_Pos) /*!< 0x00200000 */ #define RCC_APB1ENR_I2C0EN_Msk (0x1U << RCC_APB1ENR_I2C0EN_Pos) /*!< 0x00200000 */
#define RCC_APB1ENR_I2C0EN RCC_APB1ENR_I2C0EN_Msk /*!< I2C 1 clock enable */ #define RCC_APB1ENR_I2C0EN RCC_APB1ENR_I2C0EN_Msk /*!< I2C 1 clock enable */
@ -1716,9 +1716,9 @@ typedef struct
#define RCC_APB1ENR_SPI2EN_Pos (14U) #define RCC_APB1ENR_SPI2EN_Pos (14U)
#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
#define RCC_APB1ENR_USART3EN_Pos (18U) #define RCC_APB1ENR_USART2EN_Pos (18U)
#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00040000 */
#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 3 clock enable */
#define RCC_APB1ENR_I2C1EN_Pos (22U) #define RCC_APB1ENR_I2C1EN_Pos (22U)
#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00400000 */ #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00400000 */
#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 2 clock enable */ #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 2 clock enable */
@ -2631,25 +2631,25 @@ typedef struct
#define AFIO_PCF0_I2C0_REMAP AFIO_PCF0_I2C0_REMAP_Msk /*!< I2C0 remapping */ #define AFIO_PCF0_I2C0_REMAP AFIO_PCF0_I2C0_REMAP_Msk /*!< I2C0 remapping */
#define AFIO_PCF0_USART0_REMAP_Pos (2U) #define AFIO_PCF0_USART0_REMAP_Pos (2U)
#define AFIO_PCF0_USART0_REMAP_Msk (0x1U << AFIO_PCF0_USART0_REMAP_Pos) /*!< 0x00000004 */ #define AFIO_PCF0_USART0_REMAP_Msk (0x1U << AFIO_PCF0_USART0_REMAP_Pos) /*!< 0x00000004 */
#define AFIO_PCF0_USART0_REMAP AFIO_PCF0_USART0_REMAP_Msk /*!< USART0 remapping */
#define AFIO_PCF0_USART0_REMAP_Pos (3U)
#define AFIO_PCF0_USART0_REMAP_Msk (0x1U << AFIO_PCF0_USART0_REMAP_Pos) /*!< 0x00000008 */
#define AFIO_PCF0_USART0_REMAP AFIO_PCF0_USART0_REMAP_Msk /*!< USART1 remapping */ #define AFIO_PCF0_USART0_REMAP AFIO_PCF0_USART0_REMAP_Msk /*!< USART1 remapping */
#define AFIO_PCF0_USART1_REMAP_Pos (3U)
#define AFIO_PCF0_USART1_REMAP_Msk (0x1U << AFIO_PCF0_USART1_REMAP_Pos) /*!< 0x00000008 */
#define AFIO_PCF0_USART1_REMAP AFIO_PCF0_USART1_REMAP_Msk /*!< USART2 remapping */
#define AFIO_PCF0_USART2_REMAP_Pos (4U) #define AFIO_PCF0_USART1_REMAP_Pos (4U)
#define AFIO_PCF0_USART2_REMAP_Msk (0x3U << AFIO_PCF0_USART2_REMAP_Pos) /*!< 0x00000030 */ #define AFIO_PCF0_USART1_REMAP_Msk (0x3U << AFIO_PCF0_USART1_REMAP_Pos) /*!< 0x00000030 */
#define AFIO_PCF0_USART2_REMAP AFIO_PCF0_USART2_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ #define AFIO_PCF0_USART1_REMAP AFIO_PCF0_USART1_REMAP_Msk /*!< USART2_REMAP[1:0] bits (USART2 remapping) */
#define AFIO_PCF0_USART2_REMAP_0 (0x1U << AFIO_PCF0_USART2_REMAP_Pos) /*!< 0x00000010 */ #define AFIO_PCF0_USART1_REMAP_0 (0x1U << AFIO_PCF0_USART1_REMAP_Pos) /*!< 0x00000010 */
#define AFIO_PCF0_USART2_REMAP_1 (0x2U << AFIO_PCF0_USART2_REMAP_Pos) /*!< 0x00000020 */ #define AFIO_PCF0_USART1_REMAP_1 (0x2U << AFIO_PCF0_USART1_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */ /* USART2_REMAP configuration */
#define AFIO_PCF0_USART2_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ #define AFIO_PCF0_USART1_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_PCF0_USART2_REMAP_PARTIALREMAP_Pos (4U) #define AFIO_PCF0_USART1_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_PCF0_USART2_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_PCF0_USART2_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ #define AFIO_PCF0_USART1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_PCF0_USART1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_PCF0_USART2_REMAP_PARTIALREMAP AFIO_PCF0_USART2_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ #define AFIO_PCF0_USART1_REMAP_PARTIALREMAP AFIO_PCF0_USART1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
#define AFIO_PCF0_USART2_REMAP_FULLREMAP_Pos (4U) #define AFIO_PCF0_USART1_REMAP_FULLREMAP_Pos (4U)
#define AFIO_PCF0_USART2_REMAP_FULLREMAP_Msk (0x3U << AFIO_PCF0_USART2_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ #define AFIO_PCF0_USART1_REMAP_FULLREMAP_Msk (0x3U << AFIO_PCF0_USART1_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
#define AFIO_PCF0_USART2_REMAP_FULLREMAP AFIO_PCF0_USART2_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ #define AFIO_PCF0_USART1_REMAP_FULLREMAP AFIO_PCF0_USART1_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
#define AFIO_PCF0_TIMER0_REMAP_Pos (6U) #define AFIO_PCF0_TIMER0_REMAP_Pos (6U)
#define AFIO_PCF0_TIMER0_REMAP_Msk (0x3U << AFIO_PCF0_TIMER0_REMAP_Pos) /*!< 0x000000C0 */ #define AFIO_PCF0_TIMER0_REMAP_Msk (0x3U << AFIO_PCF0_TIMER0_REMAP_Pos) /*!< 0x000000C0 */
@ -12855,59 +12855,59 @@ typedef struct
/******************** USART Instances : Synchronous mode **********************/ /******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
((INSTANCE) == USART2) || \ ((INSTANCE) == USART1) || \
((INSTANCE) == USART3)) ((INSTANCE) == USART2))
/******************** UART Instances : Asynchronous mode **********************/ /******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \ ((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \ ((INSTANCE) == UART4) || \
((INSTANCE) == UART5)) ((INSTANCE) == UART5))
/******************** UART Instances : Half-Duplex mode **********************/ /******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \ ((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \ ((INSTANCE) == UART4) || \
((INSTANCE) == UART5)) ((INSTANCE) == UART5))
/******************** UART Instances : LIN mode **********************/ /******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \ ((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \ ((INSTANCE) == UART4) || \
((INSTANCE) == UART5)) ((INSTANCE) == UART5))
/****************** UART Instances : Hardware Flow control ********************/ /****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
((INSTANCE) == USART2) || \ ((INSTANCE) == USART1) || \
((INSTANCE) == USART3)) ((INSTANCE) == USART2))
/********************* UART Instances : Smard card mode ***********************/ /********************* UART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
((INSTANCE) == USART2) || \ ((INSTANCE) == USART1) || \
((INSTANCE) == USART3)) ((INSTANCE) == USART2))
/*********************** UART Instances : IRDA mode ***************************/ /*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \ ((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \ ((INSTANCE) == UART4) || \
((INSTANCE) == UART5)) ((INSTANCE) == UART5))
/***************** UART Instances : Multi-Processor mode **********************/ /***************** UART Instances : Multi-Processor mode **********************/
#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \ ((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \ ((INSTANCE) == UART4) || \
((INSTANCE) == UART5)) ((INSTANCE) == UART5))
/***************** UART Instances : DMA mode available **********************/ /***************** UART Instances : DMA mode available **********************/
#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \ ((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4)) ((INSTANCE) == UART4))
/****************************** RTC Instances *********************************/ /****************************** RTC Instances *********************************/