From 4aa9da0f343046281f5d58fe9055dfabe5abe2c0 Mon Sep 17 00:00:00 2001 From: Stefan Kerkmann Date: Tue, 30 Mar 2021 22:03:22 +0200 Subject: [PATCH] Rename ADC registers --- os/hal/ports/GD/GD32VF103/hal_adc_lld.c | 52 +- os/hal/ports/GD/GD32VF103/hal_adc_lld.h | 92 +-- os/hal/ports/GD/GD32VF103/platform.mk | 43 +- os/hal/ports/GD/GD32VF103/stm32f105xc.h | 952 ++++++++++++------------ 4 files changed, 568 insertions(+), 571 deletions(-) diff --git a/os/hal/ports/GD/GD32VF103/hal_adc_lld.c b/os/hal/ports/GD/GD32VF103/hal_adc_lld.c index bb0b4d23..be23fc4a 100644 --- a/os/hal/ports/GD/GD32VF103/hal_adc_lld.c +++ b/os/hal/ports/GD/GD32VF103/hal_adc_lld.c @@ -100,21 +100,21 @@ void adc_lld_init(void) { /* Temporary activation.*/ rccEnableADC1(true); - ADC1->CR1 = 0; - ADC1->CR2 = ADC_CR2_ADON; + ADC1->CTL0 = 0; + ADC1->CTL1 = ADC_CTL1_ADCON; /* Reset calibration just to be safe.*/ - ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; - while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) + ADC1->CTL1 = ADC_CTL1_ADCON | ADC_CTL1_RSTCLB; + while ((ADC1->CTL1 & ADC_CTL1_RSTCLB) != 0) ; /* Calibration.*/ - ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL; - while ((ADC1->CR2 & ADC_CR2_CAL) != 0) + ADC1->CTL1 = ADC_CTL1_ADCON | ADC_CTL1_CLB; + while ((ADC1->CTL1 & ADC_CTL1_CLB) != 0) ; /* Return the ADC in low power mode.*/ - ADC1->CR2 = 0; + ADC1->CTL1 = 0; rccDisableADC1(); #endif } @@ -137,15 +137,15 @@ void adc_lld_start(ADCDriver *adcp) { (gd32_dmaisr_t)adc_lld_serve_rx_interrupt, (void *)adcp); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->RDATA); rccEnableADC1(true); } #endif /* ADC setup, the calibration procedure has already been performed during initialization.*/ - adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; + adcp->adc->CTL0 = 0; + adcp->adc->CTL1 = 0; } } @@ -162,8 +162,8 @@ void adc_lld_stop(ADCDriver *adcp) { if (adcp->state == ADC_READY) { #if GD32_ADC_USE_ADC1 if (&ADCD1 == adcp) { - ADC1->CR1 = 0; - ADC1->CR2 = 0; + ADC1->CTL0 = 0; + ADC1->CTL1 = 0; dmaStreamFreeI(adcp->dmastp); adcp->dmastp = NULL; @@ -182,7 +182,7 @@ void adc_lld_stop(ADCDriver *adcp) { * @notapi */ void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t mode, cr2; + uint32_t mode, ctl1; const ADCConversionGroup *grpp = adcp->grpp; /* DMA setup.*/ @@ -202,19 +202,19 @@ void adc_lld_start_conversion(ADCDriver *adcp) { dmaStreamEnable(adcp->dmastp); /* ADC setup.*/ - adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN; - cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_ADON; - if ((cr2 & (ADC_CR2_EXTTRIG | ADC_CR2_JEXTTRIG)) == 0) - cr2 |= ADC_CR2_CONT; - adcp->adc->CR2 = grpp->cr2 | cr2; - adcp->adc->SMPR1 = grpp->smpr1; - adcp->adc->SMPR2 = grpp->smpr2; - adcp->adc->SQR1 = grpp->sqr1; - adcp->adc->SQR2 = grpp->sqr2; - adcp->adc->SQR3 = grpp->sqr3; + adcp->adc->CTL0 = grpp->ctl0 | ADC_CTL0_SM; + ctl1 = grpp->ctl1 | ADC_CTL1_DMA | ADC_CTL1_ADCON; + if ((ctl1 & (ADC_CTL1_ETERC | ADC_CTL1_ETEIC)) == 0) + ctl1 |= ADC_CTL1_CTN; + adcp->adc->CTL1 = grpp->ctl1 | ctl1; + adcp->adc->SAMPT0 = grpp->sampt0; + adcp->adc->SAMPT1 = grpp->sampt1; + adcp->adc->RSQ0 = grpp->rsq0; + adcp->adc->RSQ1 = grpp->rsq1; + adcp->adc->RSQ2 = grpp->rsq2; - /* ADC start by writing ADC_CR2_ADON a second time.*/ - adcp->adc->CR2 = cr2; + /* ADC start by writing ADC_CTL1_ADCON a second time.*/ + adcp->adc->CTL1 = ctl1; } /** @@ -227,7 +227,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) { void adc_lld_stop_conversion(ADCDriver *adcp) { dmaStreamDisable(adcp->dmastp); - adcp->adc->CR2 = 0; + adcp->adc->CTL1 = 0; } #endif /* HAL_USE_ADC */ diff --git a/os/hal/ports/GD/GD32VF103/hal_adc_lld.h b/os/hal/ports/GD/GD32VF103/hal_adc_lld.h index f789bdac..d604ddcc 100644 --- a/os/hal/ports/GD/GD32VF103/hal_adc_lld.h +++ b/os/hal/ports/GD/GD32VF103/hal_adc_lld.h @@ -35,8 +35,8 @@ * @name Triggers selection * @{ */ -#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ -#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ +#define ADC_CTL1_ETSRC_SRC(n) ((n) << 17) /**< @brief Trigger source. */ +#define ADC_CTL1_ETSRC_SWSTART (7 << 17) /**< @brief Software trigger. */ /** @} */ /** @@ -176,30 +176,30 @@ typedef enum { #define adc_lld_configuration_group_fields \ /* ADC CR1 register initialization data. \ NOTE: All the required bits must be defined into this field except \ - @p ADC_CR1_SCAN that is enforced inside the driver.*/ \ - uint32_t cr1; \ + @p ADC_CTL0_SM that is enforced inside the driver.*/ \ + uint32_t ctl0; \ /* ADC CR2 register initialization data. \ NOTE: All the required bits must be defined into this field except \ - @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are \ + @p ADC_CTL1_DMA, @p ADC_CTL1_CTN and @p ADC_CTL1_ADCON that are \ enforced inside the driver.*/ \ - uint32_t cr2; \ + uint32_t ctl1; \ /* ADC SMPR1 register initialization data. \ NOTE: In this field must be specified the sample times for channels \ 10...17.*/ \ - uint32_t smpr1; \ + uint32_t sampt0; \ /* ADC SMPR2 register initialization data. \ NOTE: In this field must be specified the sample times for channels \ 0...9.*/ \ - uint32_t smpr2; \ + uint32_t sampt1; \ /* ADC SQR1 register initialization data. \ NOTE: Conversion group sequence 13...16 + sequence length.*/ \ - uint32_t sqr1; \ + uint32_t rsq0; \ /* ADC SQR2 register initialization data. \ NOTE: Conversion group sequence 7...12.*/ \ - uint32_t sqr2; \ + uint32_t rsq1; \ /* ADC SQR3 register initialization data. \ NOTE: Conversion group sequence 1...6.*/ \ - uint32_t sqr3 + uint32_t rsq2 /** * @name Sequences building helper macros @@ -208,52 +208,52 @@ typedef enum { /** * @brief Number of channels in a conversion sequence. */ -#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) +#define ADC_RSQ0_NUM_CH(n) (((n) - 1) << 20) -#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ -#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ -#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ -#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ -#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ -#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ +#define ADC_RSQ2_RSQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_RSQ2_RSQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_RSQ2_RSQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_RSQ2_RSQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_RSQ2_RSQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_RSQ2_RSQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ -#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ -#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ -#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ -#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ -#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ -#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ +#define ADC_RSQ1_RSQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_RSQ1_RSQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_RSQ1_RSQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_RSQ1_RSQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_RSQ1_RSQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_RSQ1_RSQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ -#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ -#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ -#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ -#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +#define ADC_RSQ0_RSQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_RSQ0_RSQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_RSQ0_RSQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_RSQ0_RSQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ /** @} */ /** * @name Sampling rate settings helper macros * @{ */ -#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ -#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ -#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ -#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ -#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ -#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ -#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ -#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ -#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ -#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ +#define ADC_SAMPT1_SMP_SPT0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SAMPT1_SMP_SPT1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SAMPT1_SMP_SPT2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SAMPT1_SMP_SPT3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SAMPT1_SMP_SPT4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SAMPT1_SMP_SPT5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SAMPT1_SMP_SPT6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SAMPT1_SMP_SPT7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SAMPT1_SMP_SPT8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SAMPT1_SMP_SPT9(n) ((n) << 27) /**< @brief AN9 sampling time. */ -#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ -#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ -#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ -#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ -#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ -#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ -#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor +#define ADC_SAMPT0_SMP_SPT10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SAMPT0_SMP_SPT11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SAMPT0_SMP_SPT12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SAMPT0_SMP_SPT13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SAMPT0_SMP_SPT14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SAMPT0_SMP_SPT15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SAMPT0_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor sampling time. */ -#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference +#define ADC_SAMPT0_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference sampling time. */ /** @} */ diff --git a/os/hal/ports/GD/GD32VF103/platform.mk b/os/hal/ports/GD/GD32VF103/platform.mk index 93943029..6f060635 100644 --- a/os/hal/ports/GD/GD32VF103/platform.mk +++ b/os/hal/ports/GD/GD32VF103/platform.mk @@ -1,29 +1,32 @@ -# List of all the template platform files. +# Required platform files. +PLATFORMSRC := ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/hal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/common/RISCV-ECLIC/eclic.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/gd32_isr.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/hal_efl_lld.c + +# Required include directories. +PLATFORMINC := ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103 \ + ${CHIBIOS_CONTRIB}/os/hal/ports/common/RISCV-ECLIC + +# Optional platform files. ifeq ($(USE_SMART_BUILD),yes) # Configuration files directory -ifeq ($(CONFDIR),) - CONFDIR = . +ifeq ($(HALCONFDIR),) + ifeq ($(CONFDIR),) + HALCONFDIR = . + else + HALCONFDIR := $(CONFDIR) + endif endif -HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define")) - -PLATFORMSRC := ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/common/RISCV-ECLIC/eclic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/gd32_isr.c - -else -PLATFORMSRC = ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/common/RISCV-ECLIC/eclic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/gd32_isr.c -endif - -# Required include directories -PLATFORMINC = ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103 \ - ${CHIBIOS_CONTRIB}/os/hal/ports/common/RISCV-ECLIC +HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define")) ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/GD/GD32VF103/hal_adc_lld.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/GD/GD32VF103/hal_adc_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/GD/GD32VF103/hal_adc_lld.c endif # Drivers compatible with the platform. @@ -41,4 +44,4 @@ include ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/xWDG/driver.mk # Shared variables ALLCSRC += $(PLATFORMSRC) -ALLINC += $(PLATFORMINC) +ALLINC += $(PLATFORMINC) \ No newline at end of file diff --git a/os/hal/ports/GD/GD32VF103/stm32f105xc.h b/os/hal/ports/GD/GD32VF103/stm32f105xc.h index ba5b30d6..56613ee6 100644 --- a/os/hal/ports/GD/GD32VF103/stm32f105xc.h +++ b/os/hal/ports/GD/GD32VF103/stm32f105xc.h @@ -91,35 +91,37 @@ typedef struct { - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; + __IO uint32_t STAT; + __IO uint32_t CTL0; + __IO uint32_t CTL1; + __IO uint32_t SAMPT0; + __IO uint32_t SAMPT1; + __IO uint32_t IOFF0; + __IO uint32_t IOFF1; + __IO uint32_t IOFF2; + __IO uint32_t IOFF3; + __IO uint32_t WDHT; + __IO uint32_t WDLT; + __IO uint32_t RSQ0; + __IO uint32_t RSQ1; + __IO uint32_t RSQ2; + __IO uint32_t ISQ; + __IO uint32_t IDATA0; + __IO uint32_t IDATA1; + __IO uint32_t IDATA2; + __IO uint32_t IDATA3; + __IO uint32_t RDATA; + uint32_t RESERVED[12]; + __IO uint32_t OVSAMPCTL; } ADC_TypeDef; typedef struct { - __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ - __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ + __IO uint32_t STAT; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ + __IO uint32_t CTL0; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ + __IO uint32_t CTL1; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ uint32_t RESERVED[16]; - __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ + __IO uint32_t RDATA; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ } ADC_Common_TypeDef; /** @@ -3864,522 +3866,514 @@ typedef struct */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD_Pos (0U) -#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ -#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_SR_EOS_Pos (1U) -#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */ -#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_SR_JEOS_Pos (2U) -#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ -#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_SR_JSTRT_Pos (3U) -#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ -#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ -#define ADC_SR_STRT_Pos (4U) -#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ -#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ +/******************** Bit definition for ADC_STAT register ********************/ +#define ADC_STAT_WDE_Pos (0U) +#define ADC_STAT_WDE_Msk (0x1U << ADC_STAT_WDE_Pos) /*!< 0x00000001 */ +#define ADC_STAT_WDE ADC_STAT_WDE_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_STAT_EOC_Pos (1U) +#define ADC_STAT_EOC_Msk (0x1U << ADC_STAT_EOC_Pos) /*!< 0x00000002 */ +#define ADC_STAT_EOC ADC_STAT_EOC_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_STAT_EOIC_Pos (2U) +#define ADC_STAT_EOIC_Msk (0x1U << ADC_STAT_EOIC_Pos) /*!< 0x00000004 */ +#define ADC_STAT_EOIC ADC_STAT_EOIC_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_STAT_STIC_Pos (3U) +#define ADC_STAT_STIC_Msk (0x1U << ADC_STAT_STIC_Pos) /*!< 0x00000008 */ +#define ADC_STAT_STIC ADC_STAT_STIC_Msk /*!< ADC group injected conversion start flag */ +#define ADC_STAT_STRC_Pos (4U) +#define ADC_STAT_STRC_Msk (0x1U << ADC_STAT_STRC_Pos) /*!< 0x00000010 */ +#define ADC_STAT_STRC ADC_STAT_STRC_Msk /*!< ADC group regular conversion start flag */ -/* Legacy defines */ -#define ADC_SR_EOC (ADC_SR_EOS) -#define ADC_SR_JEOC (ADC_SR_JEOS) +/******************* Bit definition for ADC_CTL0 register ********************/ +#define ADC_CTL0_WDCHSEL_Pos (0U) +#define ADC_CTL0_WDCHSEL_Msk (0x1FU << ADC_CTL0_WDCHSEL_Pos) /*!< 0x0000001F */ +#define ADC_CTL0_WDCHSEL ADC_CTL0_WDCHSEL_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CTL0_WDCHSEL_0 (0x01U << ADC_CTL0_WDCHSEL_Pos) /*!< 0x00000001 */ +#define ADC_CTL0_WDCHSEL_1 (0x02U << ADC_CTL0_WDCHSEL_Pos) /*!< 0x00000002 */ +#define ADC_CTL0_WDCHSEL_2 (0x04U << ADC_CTL0_WDCHSEL_Pos) /*!< 0x00000004 */ +#define ADC_CTL0_WDCHSEL_3 (0x08U << ADC_CTL0_WDCHSEL_Pos) /*!< 0x00000008 */ +#define ADC_CTL0_WDCHSEL_4 (0x10U << ADC_CTL0_WDCHSEL_Pos) /*!< 0x00000010 */ -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH_Pos (0U) -#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ -#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ -#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ -#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ -#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ -#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_CTL0_EOCIE_Pos (5U) +#define ADC_CTL0_EOCIE_Msk (0x1U << ADC_CTL0_EOCIE_Pos) /*!< 0x00000020 */ +#define ADC_CTL0_EOCIE ADC_CTL0_EOCIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_CTL0_WDEIE_Pos (6U) +#define ADC_CTL0_WDEIE_Msk (0x1U << ADC_CTL0_WDEIE_Pos) /*!< 0x00000040 */ +#define ADC_CTL0_WDEIE ADC_CTL0_WDEIE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_CTL0_EOICIE_Pos (7U) +#define ADC_CTL0_EOICIE_Msk (0x1U << ADC_CTL0_EOICIE_Pos) /*!< 0x00000080 */ +#define ADC_CTL0_EOICIE ADC_CTL0_EOICIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_CTL0_SM_Pos (8U) +#define ADC_CTL0_SM_Msk (0x1U << ADC_CTL0_SM_Pos) /*!< 0x00000100 */ +#define ADC_CTL0_SM ADC_CTL0_SM_Msk /*!< ADC scan mode */ +#define ADC_CTL0_WDSC_Pos (9U) +#define ADC_CTL0_WDSC_Msk (0x1U << ADC_CTL0_WDSC_Pos) /*!< 0x00000200 */ +#define ADC_CTL0_WDSC ADC_CTL0_WDSC_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CTL0_ICA_Pos (10U) +#define ADC_CTL0_ICA_Msk (0x1U << ADC_CTL0_ICA_Pos) /*!< 0x00000400 */ +#define ADC_CTL0_ICA ADC_CTL0_ICA_Msk /*!< ADC group injected automatic trigger mode */ +#define ADC_CTL0_DISRC_Pos (11U) +#define ADC_CTL0_DISRC_Msk (0x1U << ADC_CTL0_DISRC_Pos) /*!< 0x00000800 */ +#define ADC_CTL0_DISRC ADC_CTL0_DISRC_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CTL0_DISIC_Pos (12U) +#define ADC_CTL0_DISIC_Msk (0x1U << ADC_CTL0_DISIC_Pos) /*!< 0x00001000 */ +#define ADC_CTL0_DISIC ADC_CTL0_DISIC_Msk /*!< ADC group injected sequencer discontinuous mode */ -#define ADC_CR1_EOSIE_Pos (5U) -#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ -#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_CR1_AWDIE_Pos (6U) -#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ -#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_CR1_JEOSIE_Pos (7U) -#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ -#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_CR1_SCAN_Pos (8U) -#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ -#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ -#define ADC_CR1_AWDSGL_Pos (9U) -#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ -#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CR1_JAUTO_Pos (10U) -#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ -#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ -#define ADC_CR1_DISCEN_Pos (11U) -#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ -#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CR1_JDISCEN_Pos (12U) -#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ -#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CTL0_DISNUM_Pos (13U) +#define ADC_CTL0_DISNUM_Msk (0x7U << ADC_CTL0_DISNUM_Pos) /*!< 0x0000E000 */ +#define ADC_CTL0_DISNUM ADC_CTL0_DISNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CTL0_DISNUM_0 (0x1U << ADC_CTL0_DISNUM_Pos) /*!< 0x00002000 */ +#define ADC_CTL0_DISNUM_1 (0x2U << ADC_CTL0_DISNUM_Pos) /*!< 0x00004000 */ +#define ADC_CTL0_DISNUM_2 (0x4U << ADC_CTL0_DISNUM_Pos) /*!< 0x00008000 */ -#define ADC_CR1_DISCNUM_Pos (13U) -#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ -#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ -#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ -#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ +#define ADC_CTL0_SYNCM_Pos (16U) +#define ADC_CTL0_SYNCM_Msk (0xFU << ADC_CTL0_SYNCM_Pos) /*!< 0x000F0000 */ +#define ADC_CTL0_SYNCM ADC_CTL0_SYNCM_Msk /*!< ADC multimode mode selection */ +#define ADC_CTL0_SYNCM_0 (0x1U << ADC_CTL0_SYNCM_Pos) /*!< 0x00010000 */ +#define ADC_CTL0_SYNCM_1 (0x2U << ADC_CTL0_SYNCM_Pos) /*!< 0x00020000 */ +#define ADC_CTL0_SYNCM_2 (0x4U << ADC_CTL0_SYNCM_Pos) /*!< 0x00040000 */ +#define ADC_CTL0_SYNCM_3 (0x8U << ADC_CTL0_SYNCM_Pos) /*!< 0x00080000 */ -#define ADC_CR1_DUALMOD_Pos (16U) -#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ -#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ -#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ -#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ -#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ -#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ +#define ADC_CTL0_IWDEN_Pos (22U) +#define ADC_CTL0_IWDEN_Msk (0x1U << ADC_CTL0_IWDEN_Pos) /*!< 0x00400000 */ +#define ADC_CTL0_IWDEN ADC_CTL0_IWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CTL0_RWDEN_Pos (23U) +#define ADC_CTL0_RWDEN_Msk (0x1U << ADC_CTL0_RWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CTL0_RWDEN ADC_CTL0_RWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CR1_JAWDEN_Pos (22U) -#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ -#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CR1_AWDEN_Pos (23U) -#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ -#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +/******************* Bit definition for ADC_CTL1 register ********************/ +#define ADC_CTL1_ADCON_Pos (0U) +#define ADC_CTL1_ADCON_Msk (0x1U << ADC_CTL1_ADCON_Pos) /*!< 0x00000001 */ +#define ADC_CTL1_ADCON ADC_CTL1_ADCON_Msk /*!< ADC enable */ +#define ADC_CTL1_CTN_Pos (1U) +#define ADC_CTL1_CTN_Msk (0x1U << ADC_CTL1_CTN_Pos) /*!< 0x00000002 */ +#define ADC_CTL1_CTN ADC_CTL1_CTN_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CTL1_CLB_Pos (2U) +#define ADC_CTL1_CLB_Msk (0x1U << ADC_CTL1_CLB_Pos) /*!< 0x00000004 */ +#define ADC_CTL1_CLB ADC_CTL1_CLB_Msk /*!< ADC calibration start */ +#define ADC_CTL1_RSTCLB_Pos (3U) +#define ADC_CTL1_RSTCLB_Msk (0x1U << ADC_CTL1_RSTCLB_Pos) /*!< 0x00000008 */ +#define ADC_CTL1_RSTCLB ADC_CTL1_RSTCLB_Msk /*!< ADC calibration reset */ +#define ADC_CTL1_DMA_Pos (8U) +#define ADC_CTL1_DMA_Msk (0x1U << ADC_CTL1_DMA_Pos) /*!< 0x00000100 */ +#define ADC_CTL1_DMA ADC_CTL1_DMA_Msk /*!< ADC DMA transfer enable */ +#define ADC_CTL1_DAL_Pos (11U) +#define ADC_CTL1_DAL_Msk (0x1U << ADC_CTL1_DAL_Pos) /*!< 0x00000800 */ +#define ADC_CTL1_DAL ADC_CTL1_DAL_Msk /*!< ADC data alignement */ -/* Legacy defines */ -#define ADC_CR1_EOCIE (ADC_CR1_EOSIE) -#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) +#define ADC_CTL1_ETSIC_Pos (12U) +#define ADC_CTL1_ETSIC_Msk (0x7U << ADC_CTL1_ETSIC_Pos) /*!< 0x00007000 */ +#define ADC_CTL1_ETSIC ADC_CTL1_ETSIC_Msk /*!< ADC group injected external trigger source */ +#define ADC_CTL1_ETSIC_0 (0x1U << ADC_CTL1_ETSIC_Pos) /*!< 0x00001000 */ +#define ADC_CTL1_ETSIC_1 (0x2U << ADC_CTL1_ETSIC_Pos) /*!< 0x00002000 */ +#define ADC_CTL1_ETSIC_2 (0x4U << ADC_CTL1_ETSIC_Pos) /*!< 0x00004000 */ -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON_Pos (0U) -#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ -#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ -#define ADC_CR2_CONT_Pos (1U) -#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ -#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CR2_CAL_Pos (2U) -#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ -#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ -#define ADC_CR2_RSTCAL_Pos (3U) -#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ -#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ -#define ADC_CR2_DMA_Pos (8U) -#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ -#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ -#define ADC_CR2_ALIGN_Pos (11U) -#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ -#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CTL1_ETEIC_Pos (15U) +#define ADC_CTL1_ETEIC_Msk (0x1U << ADC_CTL1_ETEIC_Pos) /*!< 0x00008000 */ +#define ADC_CTL1_ETEIC ADC_CTL1_ETEIC_Msk /*!< ADC group injected external trigger enable */ -#define ADC_CR2_JEXTSEL_Pos (12U) -#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ -#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ -#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ -#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ +#define ADC_CTL1_ETSRC_Pos (17U) +#define ADC_CTL1_ETSRC_Msk (0x7U << ADC_CTL1_ETSRC_Pos) /*!< 0x000E0000 */ +#define ADC_CTL1_ETSRC ADC_CTL1_ETSRC_Msk /*!< ADC group regular external trigger source */ +#define ADC_CTL1_ETSRC_0 (0x1U << ADC_CTL1_ETSRC_Pos) /*!< 0x00020000 */ +#define ADC_CTL1_ETSRC_1 (0x2U << ADC_CTL1_ETSRC_Pos) /*!< 0x00040000 */ +#define ADC_CTL1_ETSRC_2 (0x4U << ADC_CTL1_ETSRC_Pos) /*!< 0x00080000 */ -#define ADC_CR2_JEXTTRIG_Pos (15U) -#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ -#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ +#define ADC_CTL1_ETERC_Pos (20U) +#define ADC_CTL1_ETERC_Msk (0x1U << ADC_CTL1_ETERC_Pos) /*!< 0x00100000 */ +#define ADC_CTL1_ETERC ADC_CTL1_ETERC_Msk /*!< ADC group regular external trigger enable */ +#define ADC_CTL1_SWICST_Pos (21U) +#define ADC_CTL1_SWICST_Msk (0x1U << ADC_CTL1_SWICST_Pos) /*!< 0x00200000 */ +#define ADC_CTL1_SWICST ADC_CTL1_SWICST_Msk /*!< ADC group injected conversion start */ +#define ADC_CTL1_SWRCST_Pos (22U) +#define ADC_CTL1_SWRCST_Msk (0x1U << ADC_CTL1_SWRCST_Pos) /*!< 0x00400000 */ +#define ADC_CTL1_SWRCST ADC_CTL1_SWRCST_Msk /*!< ADC group regular conversion start */ +#define ADC_CTL1_TSVREN_Pos (23U) +#define ADC_CTL1_TSVREN_Msk (0x1U << ADC_CTL1_TSVREN_Pos) /*!< 0x00800000 */ +#define ADC_CTL1_TSVREN ADC_CTL1_TSVREN_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ -#define ADC_CR2_EXTSEL_Pos (17U) -#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ -#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ -#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ -#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ +/****************** Bit definition for ADC_SAMPT0 register *******************/ +#define ADC_SAMPT0_SPT10_Pos (0U) +#define ADC_SAMPT0_SPT10_Msk (0x7U << ADC_SAMPT0_SPT10_Pos) /*!< 0x00000007 */ +#define ADC_SAMPT0_SPT10 ADC_SAMPT0_SPT10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SAMPT0_SPT10_0 (0x1U << ADC_SAMPT0_SPT10_Pos) /*!< 0x00000001 */ +#define ADC_SAMPT0_SPT10_1 (0x2U << ADC_SAMPT0_SPT10_Pos) /*!< 0x00000002 */ +#define ADC_SAMPT0_SPT10_2 (0x4U << ADC_SAMPT0_SPT10_Pos) /*!< 0x00000004 */ -#define ADC_CR2_EXTTRIG_Pos (20U) -#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ -#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ -#define ADC_CR2_JSWSTART_Pos (21U) -#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ -#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR2_SWSTART_Pos (22U) -#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ -#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR2_TSVREFE_Pos (23U) -#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ -#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ +#define ADC_SAMPT0_SPT11_Pos (3U) +#define ADC_SAMPT0_SPT11_Msk (0x7U << ADC_SAMPT0_SPT11_Pos) /*!< 0x00000038 */ +#define ADC_SAMPT0_SPT11 ADC_SAMPT0_SPT11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SAMPT0_SPT11_0 (0x1U << ADC_SAMPT0_SPT11_Pos) /*!< 0x00000008 */ +#define ADC_SAMPT0_SPT11_1 (0x2U << ADC_SAMPT0_SPT11_Pos) /*!< 0x00000010 */ +#define ADC_SAMPT0_SPT11_2 (0x4U << ADC_SAMPT0_SPT11_Pos) /*!< 0x00000020 */ -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10_Pos (0U) -#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ -#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SAMPT0_SPT12_Pos (6U) +#define ADC_SAMPT0_SPT12_Msk (0x7U << ADC_SAMPT0_SPT12_Pos) /*!< 0x000001C0 */ +#define ADC_SAMPT0_SPT12 ADC_SAMPT0_SPT12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SAMPT0_SPT12_0 (0x1U << ADC_SAMPT0_SPT12_Pos) /*!< 0x00000040 */ +#define ADC_SAMPT0_SPT12_1 (0x2U << ADC_SAMPT0_SPT12_Pos) /*!< 0x00000080 */ +#define ADC_SAMPT0_SPT12_2 (0x4U << ADC_SAMPT0_SPT12_Pos) /*!< 0x00000100 */ -#define ADC_SMPR1_SMP11_Pos (3U) -#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ -#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SAMPT0_SPT13_Pos (9U) +#define ADC_SAMPT0_SPT13_Msk (0x7U << ADC_SAMPT0_SPT13_Pos) /*!< 0x00000E00 */ +#define ADC_SAMPT0_SPT13 ADC_SAMPT0_SPT13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SAMPT0_SPT13_0 (0x1U << ADC_SAMPT0_SPT13_Pos) /*!< 0x00000200 */ +#define ADC_SAMPT0_SPT13_1 (0x2U << ADC_SAMPT0_SPT13_Pos) /*!< 0x00000400 */ +#define ADC_SAMPT0_SPT13_2 (0x4U << ADC_SAMPT0_SPT13_Pos) /*!< 0x00000800 */ -#define ADC_SMPR1_SMP12_Pos (6U) -#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SAMPT0_SPT14_Pos (12U) +#define ADC_SAMPT0_SPT14_Msk (0x7U << ADC_SAMPT0_SPT14_Pos) /*!< 0x00007000 */ +#define ADC_SAMPT0_SPT14 ADC_SAMPT0_SPT14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SAMPT0_SPT14_0 (0x1U << ADC_SAMPT0_SPT14_Pos) /*!< 0x00001000 */ +#define ADC_SAMPT0_SPT14_1 (0x2U << ADC_SAMPT0_SPT14_Pos) /*!< 0x00002000 */ +#define ADC_SAMPT0_SPT14_2 (0x4U << ADC_SAMPT0_SPT14_Pos) /*!< 0x00004000 */ -#define ADC_SMPR1_SMP13_Pos (9U) -#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ +#define ADC_SAMPT0_SPT15_Pos (15U) +#define ADC_SAMPT0_SPT15_Msk (0x7U << ADC_SAMPT0_SPT15_Pos) /*!< 0x00038000 */ +#define ADC_SAMPT0_SPT15 ADC_SAMPT0_SPT15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SAMPT0_SPT15_0 (0x1U << ADC_SAMPT0_SPT15_Pos) /*!< 0x00008000 */ +#define ADC_SAMPT0_SPT15_1 (0x2U << ADC_SAMPT0_SPT15_Pos) /*!< 0x00010000 */ +#define ADC_SAMPT0_SPT15_2 (0x4U << ADC_SAMPT0_SPT15_Pos) /*!< 0x00020000 */ -#define ADC_SMPR1_SMP14_Pos (12U) -#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ -#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ +#define ADC_SAMPT0_SPT16_Pos (18U) +#define ADC_SAMPT0_SPT16_Msk (0x7U << ADC_SAMPT0_SPT16_Pos) /*!< 0x001C0000 */ +#define ADC_SAMPT0_SPT16 ADC_SAMPT0_SPT16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SAMPT0_SPT16_0 (0x1U << ADC_SAMPT0_SPT16_Pos) /*!< 0x00040000 */ +#define ADC_SAMPT0_SPT16_1 (0x2U << ADC_SAMPT0_SPT16_Pos) /*!< 0x00080000 */ +#define ADC_SAMPT0_SPT16_2 (0x4U << ADC_SAMPT0_SPT16_Pos) /*!< 0x00100000 */ -#define ADC_SMPR1_SMP15_Pos (15U) -#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ -#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ +#define ADC_SAMPT0_SPT17_Pos (21U) +#define ADC_SAMPT0_SPT17_Msk (0x7U << ADC_SAMPT0_SPT17_Pos) /*!< 0x00E00000 */ +#define ADC_SAMPT0_SPT17 ADC_SAMPT0_SPT17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SAMPT0_SPT17_0 (0x1U << ADC_SAMPT0_SPT17_Pos) /*!< 0x00200000 */ +#define ADC_SAMPT0_SPT17_1 (0x2U << ADC_SAMPT0_SPT17_Pos) /*!< 0x00400000 */ +#define ADC_SAMPT0_SPT17_2 (0x4U << ADC_SAMPT0_SPT17_Pos) /*!< 0x00800000 */ -#define ADC_SMPR1_SMP16_Pos (18U) -#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ +/****************** Bit definition for ADC_SAMPT1 register *******************/ +#define ADC_SAMPT1_SPT0_Pos (0U) +#define ADC_SAMPT1_SPT0_Msk (0x7U << ADC_SAMPT1_SPT0_Pos) /*!< 0x00000007 */ +#define ADC_SAMPT1_SPT0 ADC_SAMPT1_SPT0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SAMPT1_SPT0_0 (0x1U << ADC_SAMPT1_SPT0_Pos) /*!< 0x00000001 */ +#define ADC_SAMPT1_SPT0_1 (0x2U << ADC_SAMPT1_SPT0_Pos) /*!< 0x00000002 */ +#define ADC_SAMPT1_SPT0_2 (0x4U << ADC_SAMPT1_SPT0_Pos) /*!< 0x00000004 */ -#define ADC_SMPR1_SMP17_Pos (21U) -#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ +#define ADC_SAMPT1_SPT1_Pos (3U) +#define ADC_SAMPT1_SPT1_Msk (0x7U << ADC_SAMPT1_SPT1_Pos) /*!< 0x00000038 */ +#define ADC_SAMPT1_SPT1 ADC_SAMPT1_SPT1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SAMPT1_SPT1_0 (0x1U << ADC_SAMPT1_SPT1_Pos) /*!< 0x00000008 */ +#define ADC_SAMPT1_SPT1_1 (0x2U << ADC_SAMPT1_SPT1_Pos) /*!< 0x00000010 */ +#define ADC_SAMPT1_SPT1_2 (0x4U << ADC_SAMPT1_SPT1_Pos) /*!< 0x00000020 */ -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0_Pos (0U) -#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ -#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SAMPT1_SPT2_Pos (6U) +#define ADC_SAMPT1_SPT2_Msk (0x7U << ADC_SAMPT1_SPT2_Pos) /*!< 0x000001C0 */ +#define ADC_SAMPT1_SPT2 ADC_SAMPT1_SPT2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SAMPT1_SPT2_0 (0x1U << ADC_SAMPT1_SPT2_Pos) /*!< 0x00000040 */ +#define ADC_SAMPT1_SPT2_1 (0x2U << ADC_SAMPT1_SPT2_Pos) /*!< 0x00000080 */ +#define ADC_SAMPT1_SPT2_2 (0x4U << ADC_SAMPT1_SPT2_Pos) /*!< 0x00000100 */ -#define ADC_SMPR2_SMP1_Pos (3U) -#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ -#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SAMPT1_SPT3_Pos (9U) +#define ADC_SAMPT1_SPT3_Msk (0x7U << ADC_SAMPT1_SPT3_Pos) /*!< 0x00000E00 */ +#define ADC_SAMPT1_SPT3 ADC_SAMPT1_SPT3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SAMPT1_SPT3_0 (0x1U << ADC_SAMPT1_SPT3_Pos) /*!< 0x00000200 */ +#define ADC_SAMPT1_SPT3_1 (0x2U << ADC_SAMPT1_SPT3_Pos) /*!< 0x00000400 */ +#define ADC_SAMPT1_SPT3_2 (0x4U << ADC_SAMPT1_SPT3_Pos) /*!< 0x00000800 */ -#define ADC_SMPR2_SMP2_Pos (6U) -#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SAMPT1_SPT4_Pos (12U) +#define ADC_SAMPT1_SPT4_Msk (0x7U << ADC_SAMPT1_SPT4_Pos) /*!< 0x00007000 */ +#define ADC_SAMPT1_SPT4 ADC_SAMPT1_SPT4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SAMPT1_SPT4_0 (0x1U << ADC_SAMPT1_SPT4_Pos) /*!< 0x00001000 */ +#define ADC_SAMPT1_SPT4_1 (0x2U << ADC_SAMPT1_SPT4_Pos) /*!< 0x00002000 */ +#define ADC_SAMPT1_SPT4_2 (0x4U << ADC_SAMPT1_SPT4_Pos) /*!< 0x00004000 */ -#define ADC_SMPR2_SMP3_Pos (9U) -#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SAMPT1_SPT5_Pos (15U) +#define ADC_SAMPT1_SPT5_Msk (0x7U << ADC_SAMPT1_SPT5_Pos) /*!< 0x00038000 */ +#define ADC_SAMPT1_SPT5 ADC_SAMPT1_SPT5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SAMPT1_SPT5_0 (0x1U << ADC_SAMPT1_SPT5_Pos) /*!< 0x00008000 */ +#define ADC_SAMPT1_SPT5_1 (0x2U << ADC_SAMPT1_SPT5_Pos) /*!< 0x00010000 */ +#define ADC_SAMPT1_SPT5_2 (0x4U << ADC_SAMPT1_SPT5_Pos) /*!< 0x00020000 */ -#define ADC_SMPR2_SMP4_Pos (12U) -#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ -#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SAMPT1_SPT6_Pos (18U) +#define ADC_SAMPT1_SPT6_Msk (0x7U << ADC_SAMPT1_SPT6_Pos) /*!< 0x001C0000 */ +#define ADC_SAMPT1_SPT6 ADC_SAMPT1_SPT6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SAMPT1_SPT6_0 (0x1U << ADC_SAMPT1_SPT6_Pos) /*!< 0x00040000 */ +#define ADC_SAMPT1_SPT6_1 (0x2U << ADC_SAMPT1_SPT6_Pos) /*!< 0x00080000 */ +#define ADC_SAMPT1_SPT6_2 (0x4U << ADC_SAMPT1_SPT6_Pos) /*!< 0x00100000 */ -#define ADC_SMPR2_SMP5_Pos (15U) -#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ -#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SAMPT1_SPT7_Pos (21U) +#define ADC_SAMPT1_SPT7_Msk (0x7U << ADC_SAMPT1_SPT7_Pos) /*!< 0x00E00000 */ +#define ADC_SAMPT1_SPT7 ADC_SAMPT1_SPT7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SAMPT1_SPT7_0 (0x1U << ADC_SAMPT1_SPT7_Pos) /*!< 0x00200000 */ +#define ADC_SAMPT1_SPT7_1 (0x2U << ADC_SAMPT1_SPT7_Pos) /*!< 0x00400000 */ +#define ADC_SAMPT1_SPT7_2 (0x4U << ADC_SAMPT1_SPT7_Pos) /*!< 0x00800000 */ -#define ADC_SMPR2_SMP6_Pos (18U) -#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SAMPT1_SPT8_Pos (24U) +#define ADC_SAMPT1_SPT8_Msk (0x7U << ADC_SAMPT1_SPT8_Pos) /*!< 0x07000000 */ +#define ADC_SAMPT1_SPT8 ADC_SAMPT1_SPT8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SAMPT1_SPT8_0 (0x1U << ADC_SAMPT1_SPT8_Pos) /*!< 0x01000000 */ +#define ADC_SAMPT1_SPT8_1 (0x2U << ADC_SAMPT1_SPT8_Pos) /*!< 0x02000000 */ +#define ADC_SAMPT1_SPT8_2 (0x4U << ADC_SAMPT1_SPT8_Pos) /*!< 0x04000000 */ -#define ADC_SMPR2_SMP7_Pos (21U) -#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SAMPT1_SPT9_Pos (27U) +#define ADC_SAMPT1_SPT9_Msk (0x7U << ADC_SAMPT1_SPT9_Pos) /*!< 0x38000000 */ +#define ADC_SAMPT1_SPT9 ADC_SAMPT1_SPT9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SAMPT1_SPT9_0 (0x1U << ADC_SAMPT1_SPT9_Pos) /*!< 0x08000000 */ +#define ADC_SAMPT1_SPT9_1 (0x2U << ADC_SAMPT1_SPT9_Pos) /*!< 0x10000000 */ +#define ADC_SAMPT1_SPT9_2 (0x4U << ADC_SAMPT1_SPT9_Pos) /*!< 0x20000000 */ -#define ADC_SMPR2_SMP8_Pos (24U) -#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ -#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ +/****************** Bit definition for ADC_IOFF0 register *******************/ +#define ADC_IOFF0_IOFF_Pos (0U) +#define ADC_IOFF0_IOFF_Msk (0xFFFU << ADC_IOFF0_IOFF_Pos) /*!< 0x00000FFF */ +#define ADC_IOFF0_IOFF ADC_IOFF0_IOFF_Msk /*!< ADC group injected sequencer rank 1 offset value */ -#define ADC_SMPR2_SMP9_Pos (27U) -#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ -#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ +/****************** Bit definition for ADC_IOFF1 register *******************/ +#define ADC_IOFF1_IOFF_Pos (0U) +#define ADC_IOFF1_IOFF_Msk (0xFFFU << ADC_IOFF1_IOFF_Pos) /*!< 0x00000FFF */ +#define ADC_IOFF1_IOFF ADC_IOFF1_IOFF_Msk /*!< ADC group injected sequencer rank 2 offset value */ -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1_Pos (0U) -#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ +/****************** Bit definition for ADC_IOFF2 register *******************/ +#define ADC_IOFF2_IOFF_Pos (0U) +#define ADC_IOFF2_IOFF_Msk (0xFFFU << ADC_IOFF2_IOFF_Pos) /*!< 0x00000FFF */ +#define ADC_IOFF2_IOFF ADC_IOFF2_IOFF_Msk /*!< ADC group injected sequencer rank 3 offset value */ -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2_Pos (0U) -#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ +/****************** Bit definition for ADC_IOFF3 register *******************/ +#define ADC_IOFF3_IOFF_Pos (0U) +#define ADC_IOFF3_IOFF_Msk (0xFFFU << ADC_IOFF3_IOFF_Pos) /*!< 0x00000FFF */ +#define ADC_IOFF3_IOFF ADC_IOFF3_IOFF_Msk /*!< ADC group injected sequencer rank 4 offset value */ -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3_Pos (0U) -#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ +/******************* Bit definition for ADC_WDHT register ********************/ +#define ADC_WDHT_WDHT_Pos (0U) +#define ADC_WDHT_WDHT_Msk (0xFFFU << ADC_WDHT_WDHT_Pos) /*!< 0x00000FFF */ +#define ADC_WDHT_WDHT ADC_WDHT_WDHT_Msk /*!< ADC analog watchdog 1 threshold high */ -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4_Pos (0U) -#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ -#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ +/******************* Bit definition for ADC_WDLT register ********************/ +#define ADC_WDLT_WDLT_Pos (0U) +#define ADC_WDLT_WDLT_Msk (0xFFFU << ADC_WDLT_WDLT_Pos) /*!< 0x00000FFF */ +#define ADC_WDLT_WDLT ADC_WDLT_WDLT_Msk /*!< ADC analog watchdog 1 threshold low */ -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT_Pos (0U) -#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ -#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ +/******************* Bit definition for ADC_RSQ0 register *******************/ +#define ADC_RSQ0_RSQ13_Pos (0U) +#define ADC_RSQ0_RSQ13_Msk (0x1FU << ADC_RSQ0_RSQ13_Pos) /*!< 0x0000001F */ +#define ADC_RSQ0_RSQ13 ADC_RSQ0_RSQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_RSQ0_RSQ13_0 (0x01U << ADC_RSQ0_RSQ13_Pos) /*!< 0x00000001 */ +#define ADC_RSQ0_RSQ13_1 (0x02U << ADC_RSQ0_RSQ13_Pos) /*!< 0x00000002 */ +#define ADC_RSQ0_RSQ13_2 (0x04U << ADC_RSQ0_RSQ13_Pos) /*!< 0x00000004 */ +#define ADC_RSQ0_RSQ13_3 (0x08U << ADC_RSQ0_RSQ13_Pos) /*!< 0x00000008 */ +#define ADC_RSQ0_RSQ13_4 (0x10U << ADC_RSQ0_RSQ13_Pos) /*!< 0x00000010 */ -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT_Pos (0U) -#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ -#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_RSQ0_RSQ14_Pos (5U) +#define ADC_RSQ0_RSQ14_Msk (0x1FU << ADC_RSQ0_RSQ14_Pos) /*!< 0x000003E0 */ +#define ADC_RSQ0_RSQ14 ADC_RSQ0_RSQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_RSQ0_RSQ14_0 (0x01U << ADC_RSQ0_RSQ14_Pos) /*!< 0x00000020 */ +#define ADC_RSQ0_RSQ14_1 (0x02U << ADC_RSQ0_RSQ14_Pos) /*!< 0x00000040 */ +#define ADC_RSQ0_RSQ14_2 (0x04U << ADC_RSQ0_RSQ14_Pos) /*!< 0x00000080 */ +#define ADC_RSQ0_RSQ14_3 (0x08U << ADC_RSQ0_RSQ14_Pos) /*!< 0x00000100 */ +#define ADC_RSQ0_RSQ14_4 (0x10U << ADC_RSQ0_RSQ14_Pos) /*!< 0x00000200 */ -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13_Pos (0U) -#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ -#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ -#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ +#define ADC_RSQ0_RSQ15_Pos (10U) +#define ADC_RSQ0_RSQ15_Msk (0x1FU << ADC_RSQ0_RSQ15_Pos) /*!< 0x00007C00 */ +#define ADC_RSQ0_RSQ15 ADC_RSQ0_RSQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_RSQ0_RSQ15_0 (0x01U << ADC_RSQ0_RSQ15_Pos) /*!< 0x00000400 */ +#define ADC_RSQ0_RSQ15_1 (0x02U << ADC_RSQ0_RSQ15_Pos) /*!< 0x00000800 */ +#define ADC_RSQ0_RSQ15_2 (0x04U << ADC_RSQ0_RSQ15_Pos) /*!< 0x00001000 */ +#define ADC_RSQ0_RSQ15_3 (0x08U << ADC_RSQ0_RSQ15_Pos) /*!< 0x00002000 */ +#define ADC_RSQ0_RSQ15_4 (0x10U << ADC_RSQ0_RSQ15_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ14_Pos (5U) -#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ -#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ -#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ +#define ADC_RSQ0_RSQ16_Pos (15U) +#define ADC_RSQ0_RSQ16_Msk (0x1FU << ADC_RSQ0_RSQ16_Pos) /*!< 0x000F8000 */ +#define ADC_RSQ0_RSQ16 ADC_RSQ0_RSQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_RSQ0_RSQ16_0 (0x01U << ADC_RSQ0_RSQ16_Pos) /*!< 0x00008000 */ +#define ADC_RSQ0_RSQ16_1 (0x02U << ADC_RSQ0_RSQ16_Pos) /*!< 0x00010000 */ +#define ADC_RSQ0_RSQ16_2 (0x04U << ADC_RSQ0_RSQ16_Pos) /*!< 0x00020000 */ +#define ADC_RSQ0_RSQ16_3 (0x08U << ADC_RSQ0_RSQ16_Pos) /*!< 0x00040000 */ +#define ADC_RSQ0_RSQ16_4 (0x10U << ADC_RSQ0_RSQ16_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ15_Pos (10U) -#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ -#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ -#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ -#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ +#define ADC_RSQ0_RL_Pos (20U) +#define ADC_RSQ0_RL_Msk (0xFU << ADC_RSQ0_RL_Pos) /*!< 0x00F00000 */ +#define ADC_RSQ0_RL ADC_RSQ0_RL_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_RSQ0_RL_0 (0x1U << ADC_RSQ0_RL_Pos) /*!< 0x00100000 */ +#define ADC_RSQ0_RL_1 (0x2U << ADC_RSQ0_RL_Pos) /*!< 0x00200000 */ +#define ADC_RSQ0_RL_2 (0x4U << ADC_RSQ0_RL_Pos) /*!< 0x00400000 */ +#define ADC_RSQ0_RL_3 (0x8U << ADC_RSQ0_RL_Pos) /*!< 0x00800000 */ -#define ADC_SQR1_SQ16_Pos (15U) -#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ -#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ -#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ -#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ +/******************* Bit definition for ADC_RSQ1 register *******************/ +#define ADC_RSQ1_RSQ7_Pos (0U) +#define ADC_RSQ1_RSQ7_Msk (0x1FU << ADC_RSQ1_RSQ7_Pos) /*!< 0x0000001F */ +#define ADC_RSQ1_RSQ7 ADC_RSQ1_RSQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_RSQ1_RSQ7_0 (0x01U << ADC_RSQ1_RSQ7_Pos) /*!< 0x00000001 */ +#define ADC_RSQ1_RSQ7_1 (0x02U << ADC_RSQ1_RSQ7_Pos) /*!< 0x00000002 */ +#define ADC_RSQ1_RSQ7_2 (0x04U << ADC_RSQ1_RSQ7_Pos) /*!< 0x00000004 */ +#define ADC_RSQ1_RSQ7_3 (0x08U << ADC_RSQ1_RSQ7_Pos) /*!< 0x00000008 */ +#define ADC_RSQ1_RSQ7_4 (0x10U << ADC_RSQ1_RSQ7_Pos) /*!< 0x00000010 */ -#define ADC_SQR1_L_Pos (20U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ -#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ +#define ADC_RSQ1_RSQ8_Pos (5U) +#define ADC_RSQ1_RSQ8_Msk (0x1FU << ADC_RSQ1_RSQ8_Pos) /*!< 0x000003E0 */ +#define ADC_RSQ1_RSQ8 ADC_RSQ1_RSQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_RSQ1_RSQ8_0 (0x01U << ADC_RSQ1_RSQ8_Pos) /*!< 0x00000020 */ +#define ADC_RSQ1_RSQ8_1 (0x02U << ADC_RSQ1_RSQ8_Pos) /*!< 0x00000040 */ +#define ADC_RSQ1_RSQ8_2 (0x04U << ADC_RSQ1_RSQ8_Pos) /*!< 0x00000080 */ +#define ADC_RSQ1_RSQ8_3 (0x08U << ADC_RSQ1_RSQ8_Pos) /*!< 0x00000100 */ +#define ADC_RSQ1_RSQ8_4 (0x10U << ADC_RSQ1_RSQ8_Pos) /*!< 0x00000200 */ -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7_Pos (0U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ -#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ +#define ADC_RSQ1_RSQ9_Pos (10U) +#define ADC_RSQ1_RSQ9_Msk (0x1FU << ADC_RSQ1_RSQ9_Pos) /*!< 0x00007C00 */ +#define ADC_RSQ1_RSQ9 ADC_RSQ1_RSQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_RSQ1_RSQ9_0 (0x01U << ADC_RSQ1_RSQ9_Pos) /*!< 0x00000400 */ +#define ADC_RSQ1_RSQ9_1 (0x02U << ADC_RSQ1_RSQ9_Pos) /*!< 0x00000800 */ +#define ADC_RSQ1_RSQ9_2 (0x04U << ADC_RSQ1_RSQ9_Pos) /*!< 0x00001000 */ +#define ADC_RSQ1_RSQ9_3 (0x08U << ADC_RSQ1_RSQ9_Pos) /*!< 0x00002000 */ +#define ADC_RSQ1_RSQ9_4 (0x10U << ADC_RSQ1_RSQ9_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ8_Pos (5U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ -#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ +#define ADC_RSQ1_RSQ10_Pos (15U) +#define ADC_RSQ1_RSQ10_Msk (0x1FU << ADC_RSQ1_RSQ10_Pos) /*!< 0x000F8000 */ +#define ADC_RSQ1_RSQ10 ADC_RSQ1_RSQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_RSQ1_RSQ10_0 (0x01U << ADC_RSQ1_RSQ10_Pos) /*!< 0x00008000 */ +#define ADC_RSQ1_RSQ10_1 (0x02U << ADC_RSQ1_RSQ10_Pos) /*!< 0x00010000 */ +#define ADC_RSQ1_RSQ10_2 (0x04U << ADC_RSQ1_RSQ10_Pos) /*!< 0x00020000 */ +#define ADC_RSQ1_RSQ10_3 (0x08U << ADC_RSQ1_RSQ10_Pos) /*!< 0x00040000 */ +#define ADC_RSQ1_RSQ10_4 (0x10U << ADC_RSQ1_RSQ10_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ9_Pos (10U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ -#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ +#define ADC_RSQ1_RSQ11_Pos (20U) +#define ADC_RSQ1_RSQ11_Msk (0x1FU << ADC_RSQ1_RSQ11_Pos) /*!< 0x01F00000 */ +#define ADC_RSQ1_RSQ11 ADC_RSQ1_RSQ11_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_RSQ1_RSQ11_0 (0x01U << ADC_RSQ1_RSQ11_Pos) /*!< 0x00100000 */ +#define ADC_RSQ1_RSQ11_1 (0x02U << ADC_RSQ1_RSQ11_Pos) /*!< 0x00200000 */ +#define ADC_RSQ1_RSQ11_2 (0x04U << ADC_RSQ1_RSQ11_Pos) /*!< 0x00400000 */ +#define ADC_RSQ1_RSQ11_3 (0x08U << ADC_RSQ1_RSQ11_Pos) /*!< 0x00800000 */ +#define ADC_RSQ1_RSQ11_4 (0x10U << ADC_RSQ1_RSQ11_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ10_Pos (15U) -#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ -#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ -#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ -#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ +#define ADC_RSQ1_RSQ12_Pos (25U) +#define ADC_RSQ1_RSQ12_Msk (0x1FU << ADC_RSQ1_RSQ12_Pos) /*!< 0x3E000000 */ +#define ADC_RSQ1_RSQ12 ADC_RSQ1_RSQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_RSQ1_RSQ12_0 (0x01U << ADC_RSQ1_RSQ12_Pos) /*!< 0x02000000 */ +#define ADC_RSQ1_RSQ12_1 (0x02U << ADC_RSQ1_RSQ12_Pos) /*!< 0x04000000 */ +#define ADC_RSQ1_RSQ12_2 (0x04U << ADC_RSQ1_RSQ12_Pos) /*!< 0x08000000 */ +#define ADC_RSQ1_RSQ12_3 (0x08U << ADC_RSQ1_RSQ12_Pos) /*!< 0x10000000 */ +#define ADC_RSQ1_RSQ12_4 (0x10U << ADC_RSQ1_RSQ12_Pos) /*!< 0x20000000 */ -#define ADC_SQR2_SQ11_Pos (20U) -#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ -#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ -#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ -#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ +/******************* Bit definition for ADC_RSQ2 register *******************/ +#define ADC_RSQ2_RSQ1_Pos (0U) +#define ADC_RSQ2_RSQ1_Msk (0x1FU << ADC_RSQ2_RSQ1_Pos) /*!< 0x0000001F */ +#define ADC_RSQ2_RSQ1 ADC_RSQ2_RSQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_RSQ2_RSQ1_0 (0x01U << ADC_RSQ2_RSQ1_Pos) /*!< 0x00000001 */ +#define ADC_RSQ2_RSQ1_1 (0x02U << ADC_RSQ2_RSQ1_Pos) /*!< 0x00000002 */ +#define ADC_RSQ2_RSQ1_2 (0x04U << ADC_RSQ2_RSQ1_Pos) /*!< 0x00000004 */ +#define ADC_RSQ2_RSQ1_3 (0x08U << ADC_RSQ2_RSQ1_Pos) /*!< 0x00000008 */ +#define ADC_RSQ2_RSQ1_4 (0x10U << ADC_RSQ2_RSQ1_Pos) /*!< 0x00000010 */ -#define ADC_SQR2_SQ12_Pos (25U) -#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ -#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ -#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ +#define ADC_RSQ2_RSQ2_Pos (5U) +#define ADC_RSQ2_RSQ2_Msk (0x1FU << ADC_RSQ2_RSQ2_Pos) /*!< 0x000003E0 */ +#define ADC_RSQ2_RSQ2 ADC_RSQ2_RSQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_RSQ2_RSQ2_0 (0x01U << ADC_RSQ2_RSQ2_Pos) /*!< 0x00000020 */ +#define ADC_RSQ2_RSQ2_1 (0x02U << ADC_RSQ2_RSQ2_Pos) /*!< 0x00000040 */ +#define ADC_RSQ2_RSQ2_2 (0x04U << ADC_RSQ2_RSQ2_Pos) /*!< 0x00000080 */ +#define ADC_RSQ2_RSQ2_3 (0x08U << ADC_RSQ2_RSQ2_Pos) /*!< 0x00000100 */ +#define ADC_RSQ2_RSQ2_4 (0x10U << ADC_RSQ2_RSQ2_Pos) /*!< 0x00000200 */ -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1_Pos (0U) -#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ -#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ +#define ADC_RSQ2_RSQ3_Pos (10U) +#define ADC_RSQ2_RSQ3_Msk (0x1FU << ADC_RSQ2_RSQ3_Pos) /*!< 0x00007C00 */ +#define ADC_RSQ2_RSQ3 ADC_RSQ2_RSQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_RSQ2_RSQ3_0 (0x01U << ADC_RSQ2_RSQ3_Pos) /*!< 0x00000400 */ +#define ADC_RSQ2_RSQ3_1 (0x02U << ADC_RSQ2_RSQ3_Pos) /*!< 0x00000800 */ +#define ADC_RSQ2_RSQ3_2 (0x04U << ADC_RSQ2_RSQ3_Pos) /*!< 0x00001000 */ +#define ADC_RSQ2_RSQ3_3 (0x08U << ADC_RSQ2_RSQ3_Pos) /*!< 0x00002000 */ +#define ADC_RSQ2_RSQ3_4 (0x10U << ADC_RSQ2_RSQ3_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ2_Pos (5U) -#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ -#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ -#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ +#define ADC_RSQ2_RSQ4_Pos (15U) +#define ADC_RSQ2_RSQ4_Msk (0x1FU << ADC_RSQ2_RSQ4_Pos) /*!< 0x000F8000 */ +#define ADC_RSQ2_RSQ4 ADC_RSQ2_RSQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_RSQ2_RSQ4_0 (0x01U << ADC_RSQ2_RSQ4_Pos) /*!< 0x00008000 */ +#define ADC_RSQ2_RSQ4_1 (0x02U << ADC_RSQ2_RSQ4_Pos) /*!< 0x00010000 */ +#define ADC_RSQ2_RSQ4_2 (0x04U << ADC_RSQ2_RSQ4_Pos) /*!< 0x00020000 */ +#define ADC_RSQ2_RSQ4_3 (0x08U << ADC_RSQ2_RSQ4_Pos) /*!< 0x00040000 */ +#define ADC_RSQ2_RSQ4_4 (0x10U << ADC_RSQ2_RSQ4_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ3_Pos (10U) -#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ -#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ -#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ -#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ +#define ADC_RSQ2_RSQ5_Pos (20U) +#define ADC_RSQ2_RSQ5_Msk (0x1FU << ADC_RSQ2_RSQ5_Pos) /*!< 0x01F00000 */ +#define ADC_RSQ2_RSQ5 ADC_RSQ2_RSQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_RSQ2_RSQ5_0 (0x01U << ADC_RSQ2_RSQ5_Pos) /*!< 0x00100000 */ +#define ADC_RSQ2_RSQ5_1 (0x02U << ADC_RSQ2_RSQ5_Pos) /*!< 0x00200000 */ +#define ADC_RSQ2_RSQ5_2 (0x04U << ADC_RSQ2_RSQ5_Pos) /*!< 0x00400000 */ +#define ADC_RSQ2_RSQ5_3 (0x08U << ADC_RSQ2_RSQ5_Pos) /*!< 0x00800000 */ +#define ADC_RSQ2_RSQ5_4 (0x10U << ADC_RSQ2_RSQ5_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ4_Pos (15U) -#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ -#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ -#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ -#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ +#define ADC_RSQ2_RSQ6_Pos (25U) +#define ADC_RSQ2_RSQ6_Msk (0x1FU << ADC_RSQ2_RSQ6_Pos) /*!< 0x3E000000 */ +#define ADC_RSQ2_RSQ6 ADC_RSQ2_RSQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_RSQ2_RSQ6_0 (0x01U << ADC_RSQ2_RSQ6_Pos) /*!< 0x02000000 */ +#define ADC_RSQ2_RSQ6_1 (0x02U << ADC_RSQ2_RSQ6_Pos) /*!< 0x04000000 */ +#define ADC_RSQ2_RSQ6_2 (0x04U << ADC_RSQ2_RSQ6_Pos) /*!< 0x08000000 */ +#define ADC_RSQ2_RSQ6_3 (0x08U << ADC_RSQ2_RSQ6_Pos) /*!< 0x10000000 */ +#define ADC_RSQ2_RSQ6_4 (0x10U << ADC_RSQ2_RSQ6_Pos) /*!< 0x20000000 */ -#define ADC_SQR3_SQ5_Pos (20U) -#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ -#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ -#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ -#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ +/******************* Bit definition for ADC_ISQ register *******************/ +#define ADC_ISQ_ISQ1_Pos (0U) +#define ADC_ISQ_ISQ1_Msk (0x1FU << ADC_ISQ_ISQ1_Pos) /*!< 0x0000001F */ +#define ADC_ISQ_ISQ1 ADC_ISQ_ISQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_ISQ_ISQ1_0 (0x01U << ADC_ISQ_ISQ1_Pos) /*!< 0x00000001 */ +#define ADC_ISQ_ISQ1_1 (0x02U << ADC_ISQ_ISQ1_Pos) /*!< 0x00000002 */ +#define ADC_ISQ_ISQ1_2 (0x04U << ADC_ISQ_ISQ1_Pos) /*!< 0x00000004 */ +#define ADC_ISQ_ISQ1_3 (0x08U << ADC_ISQ_ISQ1_Pos) /*!< 0x00000008 */ +#define ADC_ISQ_ISQ1_4 (0x10U << ADC_ISQ_ISQ1_Pos) /*!< 0x00000010 */ -#define ADC_SQR3_SQ6_Pos (25U) -#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ -#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ -#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ +#define ADC_ISQ_ISQ2_Pos (5U) +#define ADC_ISQ_ISQ2_Msk (0x1FU << ADC_ISQ_ISQ2_Pos) /*!< 0x000003E0 */ +#define ADC_ISQ_ISQ2 ADC_ISQ_ISQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_ISQ_ISQ2_0 (0x01U << ADC_ISQ_ISQ2_Pos) /*!< 0x00000020 */ +#define ADC_ISQ_ISQ2_1 (0x02U << ADC_ISQ_ISQ2_Pos) /*!< 0x00000040 */ +#define ADC_ISQ_ISQ2_2 (0x04U << ADC_ISQ_ISQ2_Pos) /*!< 0x00000080 */ +#define ADC_ISQ_ISQ2_3 (0x08U << ADC_ISQ_ISQ2_Pos) /*!< 0x00000100 */ +#define ADC_ISQ_ISQ2_4 (0x10U << ADC_ISQ_ISQ2_Pos) /*!< 0x00000200 */ -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1_Pos (0U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ -#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ +#define ADC_ISQ_ISQ3_Pos (10U) +#define ADC_ISQ_ISQ3_Msk (0x1FU << ADC_ISQ_ISQ3_Pos) /*!< 0x00007C00 */ +#define ADC_ISQ_ISQ3 ADC_ISQ_ISQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_ISQ_ISQ3_0 (0x01U << ADC_ISQ_ISQ3_Pos) /*!< 0x00000400 */ +#define ADC_ISQ_ISQ3_1 (0x02U << ADC_ISQ_ISQ3_Pos) /*!< 0x00000800 */ +#define ADC_ISQ_ISQ3_2 (0x04U << ADC_ISQ_ISQ3_Pos) /*!< 0x00001000 */ +#define ADC_ISQ_ISQ3_3 (0x08U << ADC_ISQ_ISQ3_Pos) /*!< 0x00002000 */ +#define ADC_ISQ_ISQ3_4 (0x10U << ADC_ISQ_ISQ3_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_Pos (5U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ -#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ +#define ADC_ISQ_ISQ4_Pos (15U) +#define ADC_ISQ_ISQ4_Msk (0x1FU << ADC_ISQ_ISQ4_Pos) /*!< 0x000F8000 */ +#define ADC_ISQ_ISQ4 ADC_ISQ_ISQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_ISQ_ISQ4_0 (0x01U << ADC_ISQ_ISQ4_Pos) /*!< 0x00008000 */ +#define ADC_ISQ_ISQ4_1 (0x02U << ADC_ISQ_ISQ4_Pos) /*!< 0x00010000 */ +#define ADC_ISQ_ISQ4_2 (0x04U << ADC_ISQ_ISQ4_Pos) /*!< 0x00020000 */ +#define ADC_ISQ_ISQ4_3 (0x08U << ADC_ISQ_ISQ4_Pos) /*!< 0x00040000 */ +#define ADC_ISQ_ISQ4_4 (0x10U << ADC_ISQ_ISQ4_Pos) /*!< 0x00080000 */ -#define ADC_JSQR_JSQ3_Pos (10U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ -#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ +#define ADC_ISQ_IL_Pos (20U) +#define ADC_ISQ_IL_Msk (0x3U << ADC_ISQ_IL_Pos) /*!< 0x00300000 */ +#define ADC_ISQ_IL ADC_ISQ_IL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_ISQ_IL_0 (0x1U << ADC_ISQ_IL_Pos) /*!< 0x00100000 */ +#define ADC_ISQ_IL_1 (0x2U << ADC_ISQ_IL_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ4_Pos (15U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ -#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ +/******************* Bit definition for ADC_IDATA0 register *******************/ +#define ADC_IDATA0_IDATA_Pos (0U) +#define ADC_IDATA0_IDATA_Msk (0xFFFFU << ADC_IDATA0_IDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_IDATA0_IDATA ADC_IDATA0_IDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JSQR_JL_Pos (20U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ -#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ +/******************* Bit definition for ADC_IDATA1 register *******************/ +#define ADC_IDATA1_IDATA_Pos (0U) +#define ADC_IDATA1_IDATA_Msk (0xFFFFU << ADC_IDATA1_IDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_IDATA1_IDATA ADC_IDATA1_IDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +/******************* Bit definition for ADC_IDATA2 register *******************/ +#define ADC_IDATA2_IDATA_Pos (0U) +#define ADC_IDATA2_IDATA_Msk (0xFFFFU << ADC_IDATA2_IDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_IDATA2_IDATA ADC_IDATA2_IDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +/******************* Bit definition for ADC_IDATA3 register *******************/ +#define ADC_IDATA3_IDATA_Pos (0U) +#define ADC_IDATA3_IDATA_Msk (0xFFFFU << ADC_IDATA3_IDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_IDATA3_IDATA ADC_IDATA3_IDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA_Pos (0U) -#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ -#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_ADC2DATA_Pos (16U) -#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ -#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ +/******************** Bit definition for ADC_RDATA register ********************/ +#define ADC_RDATA_RDATA_Pos (0U) +#define ADC_RDATA_RDATA_Msk (0xFFFFU << ADC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_RDATA_RDATA ADC_RDATA_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_RDATA_ADC1RDTR_Pos (16U) +#define ADC_RDATA_ADC1RDTR_Msk (0xFFFFU << ADC_RDATA_ADC1RDTR_Pos) /*!< 0xFFFF0000 */ +#define ADC_RDATA_ADC1RDTR ADC_RDATA_ADC1RDTR_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ /******************************************************************************/ /* */ /* Digital to Analog Converter */