K60F improvements
This commit is contained in:
fauxpark
parent
9e4deb49e8
commit
4b24d2e9c0
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@ -229,7 +229,7 @@ typedef enum IRQn {
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PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
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PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
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PDB0_IRQn = 52, /**< PDB0 Interrupt */
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USB0_IRQn = 53, /**< USB0 interrupt */
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USB_OTG_IRQn = 53, /**< USB0 interrupt */
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USBDCD_IRQn = 54, /**< USBDCD Interrupt */
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Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
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DAC0_IRQn = 56, /**< DAC0 interrupt */
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@ -7495,9 +7495,9 @@ typedef struct {
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__IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
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uint8_t RESERVED_21[11];
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struct { /* offset: 0xC0, array step: 0x4 */
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__IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
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__IO uint8_t V; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
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uint8_t RESERVED_0[3];
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} ENDPOINT[16];
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} ENDPT[16];
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__IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
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uint8_t RESERVED_22[3];
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__I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
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@ -7525,202 +7525,203 @@ typedef struct {
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*/
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/*! @name PERID - Peripheral ID register */
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#define USB_PERID_ID_MASK (0x3FU)
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#define USB_PERID_ID_SHIFT (0U)
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#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
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#define USBx_PERID_ID_MASK (0x3FU)
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#define USBx_PERID_ID_SHIFT (0U)
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#define USBx_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USBx_PERID_ID_SHIFT)) & USBx_PERID_ID_MASK)
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/*! @name IDCOMP - Peripheral ID Complement register */
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#define USB_IDCOMP_NID_MASK (0x3FU)
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#define USB_IDCOMP_NID_SHIFT (0U)
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#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
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#define USBx_IDCOMP_NID_MASK (0x3FU)
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#define USBx_IDCOMP_NID_SHIFT (0U)
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#define USBx_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USBx_IDCOMP_NID_SHIFT)) & USBx_IDCOMP_NID_MASK)
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/*! @name REV - Peripheral Revision register */
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#define USB_REV_REV_MASK (0xFFU)
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#define USB_REV_REV_SHIFT (0U)
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#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
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#define USBx_REV_REV_MASK (0xFFU)
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#define USBx_REV_REV_SHIFT (0U)
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#define USBx_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USBx_REV_REV_SHIFT)) & USBx_REV_REV_MASK)
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/*! @name ADDINFO - Peripheral Additional Info register */
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#define USB_ADDINFO_IEHOST (0x1U)
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#define USB_ADDINFO_IRQNUM_MASK (0xF8U)
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#define USB_ADDINFO_IRQNUM_SHIFT (3U)
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#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
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#define USBx_ADDINFO_IEHOST (0x1U)
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#define USBx_ADDINFO_IRQNUM_MASK (0xF8U)
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#define USBx_ADDINFO_IRQNUM_SHIFT (3U)
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#define USBx_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USBx_ADDINFO_IRQNUM_SHIFT)) & USBx_ADDINFO_IRQNUM_MASK)
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/*! @name OTGISTAT - OTG Interrupt Status register */
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#define USB_OTGISTAT_AVBUSCHG (0x1U)
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#define USB_OTGISTAT_B_SESS_CHG (0x4U)
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#define USB_OTGISTAT_SESSVLDCHG (0x8U)
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#define USB_OTGISTAT_LINE_STATE_CHG (0x20U)
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#define USB_OTGISTAT_ONEMSEC (0x40U)
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#define USB_OTGISTAT_IDCHG (0x80U)
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#define USBx_OTGISTAT_AVBUSCHG (0x1U)
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#define USBx_OTGISTAT_B_SESS_CHG (0x4U)
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#define USBx_OTGISTAT_SESSVLDCHG (0x8U)
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#define USBx_OTGISTAT_LINE_STATE_CHG (0x20U)
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#define USBx_OTGISTAT_ONEMSEC (0x40U)
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#define USBx_OTGISTAT_IDCHG (0x80U)
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/*! @name OTGICR - OTG Interrupt Control register */
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#define USB_OTGICR_AVBUSEN (0x1U)
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#define USB_OTGICR_BSESSEN (0x4U)
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#define USB_OTGICR_SESSVLDEN (0x8U)
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#define USB_OTGICR_LINESTATEEN (0x20U)
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#define USB_OTGICR_ONEMSECEN (0x40U)
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#define USB_OTGICR_IDEN (0x80U)
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#define USBx_OTGICR_AVBUSEN (0x1U)
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#define USBx_OTGICR_BSESSEN (0x4U)
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#define USBx_OTGICR_SESSVLDEN (0x8U)
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#define USBx_OTGICR_LINESTATEEN (0x20U)
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#define USBx_OTGICR_ONEMSECEN (0x40U)
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#define USBx_OTGICR_IDEN (0x80U)
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/*! @name OTGSTAT - OTG Status register */
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#define USB_OTGSTAT_AVBUSVLD (0x1U)
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#define USB_OTGSTAT_BSESSEND (0x4U)
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#define USB_OTGSTAT_SESS_VLD (0x8U)
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#define USB_OTGSTAT_LINESTATESTABLE (0x20U)
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#define USB_OTGSTAT_ONEMSECEN (0x40U)
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#define USB_OTGSTAT_ID (0x80U)
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#define USBx_OTGSTAT_AVBUSVLD (0x1U)
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#define USBx_OTGSTAT_BSESSEND (0x4U)
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#define USBx_OTGSTAT_SESS_VLD (0x8U)
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#define USBx_OTGSTAT_LINESTATESTABLE (0x20U)
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#define USBx_OTGSTAT_ONEMSECEN (0x40U)
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#define USBx_OTGSTAT_ID (0x80U)
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/*! @name OTGCTL - OTG Control register */
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#define USB_OTGCTL_OTGEN (0x4U)
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#define USB_OTGCTL_DMLOW (0x10U)
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#define USB_OTGCTL_DPLOW (0x20U)
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#define USB_OTGCTL_DPHIGH (0x80U)
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#define USBx_OTGCTL_OTGEN (0x4U)
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#define USBx_OTGCTL_DMLOW (0x10U)
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#define USBx_OTGCTL_DPLOW (0x20U)
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#define USBx_OTGCTL_DPHIGH (0x80U)
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/*! @name ISTAT - Interrupt Status register */
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#define USB_ISTAT_USBRST (0x1U)
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#define USB_ISTAT_ERROR (0x2U)
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#define USB_ISTAT_SOFTOK (0x4U)
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#define USB_ISTAT_TOKDNE (0x8U)
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#define USB_ISTAT_SLEEP (0x10U)
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#define USB_ISTAT_RESUME (0x20U)
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#define USB_ISTAT_ATTACH (0x40U)
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#define USB_ISTAT_STALL (0x80U)
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#define USBx_ISTAT_USBRST (0x1U)
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#define USBx_ISTAT_ERROR (0x2U)
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#define USBx_ISTAT_SOFTOK (0x4U)
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#define USBx_ISTAT_TOKDNE (0x8U)
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#define USBx_ISTAT_SLEEP (0x10U)
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#define USBx_ISTAT_RESUME (0x20U)
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#define USBx_ISTAT_ATTACH (0x40U)
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#define USBx_ISTAT_STALL (0x80U)
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/*! @name INTEN - Interrupt Enable register */
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#define USB_INTEN_USBRSTEN (0x1U)
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#define USB_INTEN_ERROREN (0x2U)
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#define USB_INTEN_SOFTOKEN (0x4U)
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#define USB_INTEN_TOKDNEEN (0x8U)
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#define USB_INTEN_SLEEPEN (0x10U)
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#define USB_INTEN_RESUMEEN (0x20U)
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#define USB_INTEN_ATTACHEN (0x40U)
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#define USB_INTEN_STALLEN (0x80U)
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#define USBx_INTEN_USBRSTEN (0x1U)
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#define USBx_INTEN_ERROREN (0x2U)
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#define USBx_INTEN_SOFTOKEN (0x4U)
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#define USBx_INTEN_TOKDNEEN (0x8U)
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#define USBx_INTEN_SLEEPEN (0x10U)
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#define USBx_INTEN_RESUMEEN (0x20U)
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#define USBx_INTEN_ATTACHEN (0x40U)
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#define USBx_INTEN_STALLEN (0x80U)
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/*! @name ERRSTAT - Error Interrupt Status register */
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#define USB_ERRSTAT_PIDERR (0x1U)
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#define USB_ERRSTAT_CRC5EOF (0x2U)
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#define USB_ERRSTAT_CRC16 (0x4U)
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#define USB_ERRSTAT_DFN8 (0x8U)
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#define USB_ERRSTAT_BTOERR (0x10U)
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#define USB_ERRSTAT_DMAERR (0x20U)
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#define USB_ERRSTAT_BTSERR (0x80U)
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#define USBx_ERRSTAT_PIDERR (0x1U)
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#define USBx_ERRSTAT_CRC5EOF (0x2U)
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#define USBx_ERRSTAT_CRC16 (0x4U)
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#define USBx_ERRSTAT_DFN8 (0x8U)
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#define USBx_ERRSTAT_BTOERR (0x10U)
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#define USBx_ERRSTAT_DMAERR (0x20U)
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#define USBx_ERRSTAT_BTSERR (0x80U)
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/*! @name ERREN - Error Interrupt Enable register */
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#define USB_ERREN_PIDERREN (0x1U)
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#define USB_ERREN_CRC5EOFEN (0x2U)
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#define USB_ERREN_CRC16EN (0x4U)
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#define USB_ERREN_DFN8EN (0x8U)
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#define USB_ERREN_BTOERREN (0x10U)
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#define USB_ERREN_DMAERREN (0x20U)
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#define USB_ERREN_BTSERREN (0x80U)
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#define USBx_ERREN_PIDERREN (0x1U)
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#define USBx_ERREN_CRC5EOFEN (0x2U)
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#define USBx_ERREN_CRC16EN (0x4U)
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#define USBx_ERREN_DFN8EN (0x8U)
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#define USBx_ERREN_BTOERREN (0x10U)
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#define USBx_ERREN_DMAERREN (0x20U)
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#define USBx_ERREN_BTSERREN (0x80U)
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/*! @name STAT - Status register */
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#define USB_STAT_ODD (0x4U)
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#define USB_STAT_TX (0x8U)
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#define USB_STAT_ENDP_MASK (0xF0U)
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#define USB_STAT_ENDP_SHIFT (4U)
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#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
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#define USBx_STAT_ODD_MASK (0x4U)
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#define USBx_STAT_ODD_SHIFT (0x2U)
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#define USBx_STAT_TX_MASK (0x8U)
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#define USBx_STAT_TX_SHIFT (0x3U)
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#define USBx_STAT_ENDP_MASK (0xF0U)
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#define USBx_STAT_ENDP_SHIFT (4U)
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/*! @name CTL - Control register */
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#define USB_CTL_USBENSOFEN (0x1U)
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#define USB_CTL_ODDRST (0x2U)
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#define USB_CTL_RESUME (0x4U)
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#define USB_CTL_HOSTMODEEN (0x8U)
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#define USB_CTL_RESET (0x10U)
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#define USB_CTL_TXSUSPENDTOKENBUSY (0x20U)
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#define USB_CTL_SE0 (0x40U)
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#define USB_CTL_JSTATE (0x80U)
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#define USBx_CTL_USBENSOFEN (0x1U)
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#define USBx_CTL_ODDRST (0x2U)
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#define USBx_CTL_RESUME (0x4U)
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#define USBx_CTL_HOSTMODEEN (0x8U)
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#define USBx_CTL_RESET (0x10U)
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#define USBx_CTL_TXSUSPENDTOKENBUSY (0x20U)
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#define USBx_CTL_SE0 (0x40U)
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#define USBx_CTL_JSTATE (0x80U)
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/*! @name ADDR - Address register */
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#define USB_ADDR_ADDR_MASK (0x7FU)
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#define USB_ADDR_ADDR_SHIFT (0U)
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#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
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#define USB_ADDR_LSEN (0x80U)
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#define USBx_ADDR_ADDR_MASK (0x7FU)
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#define USBx_ADDR_ADDR_SHIFT (0U)
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#define USBx_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USBx_ADDR_ADDR_SHIFT)) & USBx_ADDR_ADDR_MASK)
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#define USBx_ADDR_LSEN (0x80U)
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/*! @name BDTPAGE1 - BDT Page register 1 */
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#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
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#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
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#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
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#define USBx_BDTPAGE1_BDTBA_MASK (0xFEU)
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#define USBx_BDTPAGE1_BDTBA_SHIFT (1U)
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#define USBx_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USBx_BDTPAGE1_BDTBA_SHIFT)) & USBx_BDTPAGE1_BDTBA_MASK)
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/*! @name FRMNUML - Frame Number register Low */
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#define USB_FRMNUML_FRM_MASK (0xFFU)
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#define USB_FRMNUML_FRM_SHIFT (0U)
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#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
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#define USBx_FRMNUML_FRM_MASK (0xFFU)
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#define USBx_FRMNUML_FRM_SHIFT (0U)
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#define USBx_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USBx_FRMNUML_FRM_SHIFT)) & USBx_FRMNUML_FRM_MASK)
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/*! @name FRMNUMH - Frame Number register High */
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#define USB_FRMNUMH_FRM_MASK (0x7U)
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#define USB_FRMNUMH_FRM_SHIFT (0U)
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#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
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#define USBx_FRMNUMH_FRM_MASK (0x7U)
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#define USBx_FRMNUMH_FRM_SHIFT (0U)
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#define USBx_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USBx_FRMNUMH_FRM_SHIFT)) & USBx_FRMNUMH_FRM_MASK)
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/*! @name TOKEN - Token register */
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#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
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#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
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#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
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#define USB_TOKEN_TOKENPID_MASK (0xF0U)
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#define USB_TOKEN_TOKENPID_SHIFT (4U)
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#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
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#define USBx_TOKEN_TOKENENDPT_MASK (0xFU)
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#define USBx_TOKEN_TOKENENDPT_SHIFT (0U)
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#define USBx_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USBx_TOKEN_TOKENENDPT_SHIFT)) & USBx_TOKEN_TOKENENDPT_MASK)
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#define USBx_TOKEN_TOKENPID_MASK (0xF0U)
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#define USBx_TOKEN_TOKENPID_SHIFT (4U)
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#define USBx_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USBx_TOKEN_TOKENPID_SHIFT)) & USBx_TOKEN_TOKENPID_MASK)
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/*! @name SOFTHLD - SOF Threshold register */
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#define USB_SOFTHLD_CNT_MASK (0xFFU)
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#define USB_SOFTHLD_CNT_SHIFT (0U)
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#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
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#define USBx_SOFTHLD_CNT_MASK (0xFFU)
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#define USBx_SOFTHLD_CNT_SHIFT (0U)
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#define USBx_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USBx_SOFTHLD_CNT_SHIFT)) & USBx_SOFTHLD_CNT_MASK)
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/*! @name BDTPAGE2 - BDT Page Register 2 */
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#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
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#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
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#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
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#define USBx_BDTPAGE2_BDTBA_MASK (0xFFU)
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#define USBx_BDTPAGE2_BDTBA_SHIFT (0U)
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#define USBx_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USBx_BDTPAGE2_BDTBA_SHIFT)) & USBx_BDTPAGE2_BDTBA_MASK)
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/*! @name BDTPAGE3 - BDT Page Register 3 */
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#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
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#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
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#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
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#define USBx_BDTPAGE3_BDTBA_MASK (0xFFU)
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#define USBx_BDTPAGE3_BDTBA_SHIFT (0U)
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#define USBx_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USBx_BDTPAGE3_BDTBA_SHIFT)) & USBx_BDTPAGE3_BDTBA_MASK)
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/*! @name ENDPT - Endpoint Control register */
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#define USB_ENDPT_EPHSHK (0x1U)
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#define USB_ENDPT_EPSTALL (0x2U)
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#define USB_ENDPT_EPTXEN (0x4U)
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#define USB_ENDPT_EPRXEN (0x8U)
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#define USB_ENDPT_EPCTLDIS (0x10U)
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#define USB_ENDPT_RETRYDIS (0x40U)
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#define USB_ENDPT_HOSTWOHUB (0x80U)
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#define USBx_ENDPTn_EPHSHK (0x1U)
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#define USBx_ENDPTn_EPSTALL (0x2U)
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#define USBx_ENDPTn_EPTXEN (0x4U)
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#define USBx_ENDPTn_EPRXEN (0x8U)
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#define USBx_ENDPTn_EPCTLDIS (0x10U)
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#define USBx_ENDPTn_RETRYDIS (0x40U)
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#define USBx_ENDPTn_HOSTWOHUB (0x80U)
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/* The count of USB_ENDPT */
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#define USB_ENDPT_COUNT (16U)
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/* The count of USBx_ENDPT */
|
||||
#define USBx_ENDPTn_COUNT (16U)
|
||||
|
||||
/*! @name USBCTRL - USB Control register */
|
||||
#define USB_USBCTRL_PDE (0x40U)
|
||||
#define USB_USBCTRL_SUSP (0x80U)
|
||||
#define USBx_USBCTRL_PDE (0x40U)
|
||||
#define USBx_USBCTRL_SUSP (0x80U)
|
||||
|
||||
/*! @name OBSERVE - USB OTG Observe register */
|
||||
#define USB_OBSERVE_DMPD (0x10U)
|
||||
#define USB_OBSERVE_DPPD (0x40U)
|
||||
#define USB_OBSERVE_DPPU (0x80U)
|
||||
#define USBx_OBSERVE_DMPD (0x10U)
|
||||
#define USBx_OBSERVE_DPPD (0x40U)
|
||||
#define USBx_OBSERVE_DPPU (0x80U)
|
||||
|
||||
/*! @name CONTROL - USB OTG Control register */
|
||||
#define USB_CONTROL_DPPULLUPNONOTG (0x10U)
|
||||
#define USBx_CONTROL_DPPULLUPNONOTG (0x10U)
|
||||
|
||||
/*! @name USBTRC0 - USB Transceiver Control register 0 */
|
||||
#define USB_USBTRC0_USB_RESUME_INT (0x1U)
|
||||
#define USB_USBTRC0_SYNC_DET (0x2U)
|
||||
#define USB_USBTRC0_USB_CLK_RECOVERY_INT (0x4U)
|
||||
#define USB_USBTRC0_USBRESMEN (0x20U)
|
||||
#define USB_USBTRC0_USBRESET (0x80U)
|
||||
#define USBx_USBTRC0_USB_RESUME_INT (0x1U)
|
||||
#define USBx_USBTRC0_SYNC_DET (0x2U)
|
||||
#define USBx_USBTRC0_USB_CLK_RECOVERY_INT (0x4U)
|
||||
#define USBx_USBTRC0_USBRESMEN (0x20U)
|
||||
#define USBx_USBTRC0_USBRESET (0x80U)
|
||||
|
||||
/*! @name USBFRMADJUST - Frame Adjust Register */
|
||||
#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
|
||||
#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
|
||||
#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
|
||||
#define USBx_USBFRMADJUST_ADJ_MASK (0xFFU)
|
||||
#define USBx_USBFRMADJUST_ADJ_SHIFT (0U)
|
||||
#define USBx_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USBx_USBFRMADJUST_ADJ_SHIFT)) & USBx_USBFRMADJUST_ADJ_MASK)
|
||||
|
||||
/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
|
||||
#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (0x20U)
|
||||
#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (0x40U)
|
||||
#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (0x80U)
|
||||
#define USBx_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN (0x20U)
|
||||
#define USBx_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN (0x40U)
|
||||
#define USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN (0x80U)
|
||||
|
||||
/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
|
||||
#define USB_CLK_RECOVER_IRC_EN_REG_EN (0x1U)
|
||||
#define USB_CLK_RECOVER_IRC_EN_IRC_EN (0x2U)
|
||||
#define USBx_CLK_RECOVER_IRC_EN_REG_EN (0x1U)
|
||||
#define USBx_CLK_RECOVER_IRC_EN_IRC_EN (0x2U)
|
||||
|
||||
/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
|
||||
#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR (0x10U)
|
||||
#define USBx_CLK_RECOVER_INT_STATUS_OVF_ERROR (0x10U)
|
||||
|
||||
|
||||
/*!
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
|
|||
STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \
|
||||
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K60x \
|
||||
$(CHIBIOS)/os/common/ext/CMSIS/include \
|
||||
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
|
||||
$(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
|
||||
|
||||
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/PITv1/driver.mk
|
|||
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/SDHCv1/driver.mk
|
||||
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/I2Cv1/driver.mk
|
||||
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/ADCv1/driver.mk
|
||||
include ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/USBHSv1/driver.mk
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(PLATFORMSRC_CONTRIB)
|
||||
|
|
|
|||
|
|
@ -398,7 +398,7 @@ void usb_lld_init(void) {
|
|||
/* Set USB clock source to MCGPLLCLK, MCGFLLCLK, USB1 PFD, or IRC48M */
|
||||
SIM->SOPT2 |= SIM_SOPT2_USBSRC;
|
||||
|
||||
#if defined(K20x5) || defined(K20x7) || defined(MK66F18)
|
||||
#if defined(K20x5) || defined(K20x7) || defined(K64F) || defined(MK66F18)
|
||||
|
||||
#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue