Renumber CAN peripherals to start from 0
This commit is contained in:
Stefan Kerkmann
parent
b047b96764
commit
4ec485fdab
|
|
@ -33,9 +33,9 @@
|
|||
/*
|
||||
* Addressing differences in the headers, they seem unable to agree on names.
|
||||
*/
|
||||
#if GD32_CAN_USE_CAN1
|
||||
#if !defined(CAN1)
|
||||
#define CAN1 CAN
|
||||
#if GD32_CAN_USE_CAN0
|
||||
#if !defined(CAN0)
|
||||
#define CAN0 CAN
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
@ -43,13 +43,13 @@
|
|||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/** @brief CAN1 driver identifier.*/
|
||||
#if GD32_CAN_USE_CAN1 || defined(__DOXYGEN__)
|
||||
/** @brief CAN0 driver identifier.*/
|
||||
#if GD32_CAN_USE_CAN0 || defined(__DOXYGEN__)
|
||||
CANDriver CAND1;
|
||||
#endif
|
||||
|
||||
/** @brief CAN2 driver identifier.*/
|
||||
#if GD32_CAN_USE_CAN2 || defined(__DOXYGEN__)
|
||||
/** @brief CAN1 driver identifier.*/
|
||||
#if GD32_CAN_USE_CAN1 || defined(__DOXYGEN__)
|
||||
CANDriver CAND2;
|
||||
#endif
|
||||
|
||||
|
|
@ -64,7 +64,7 @@ CANDriver CAND2;
|
|||
* @brief Programs the filters of CAN 1 and CAN 2.
|
||||
*
|
||||
* @param[in] canp pointer to the @p CANDriver object
|
||||
* @param[in] can2sb number of the first filter assigned to CAN2
|
||||
* @param[in] can2sb number of the first filter assigned to CAN1
|
||||
* @param[in] num number of entries in the filters array, if zero then
|
||||
* a default filter is programmed
|
||||
* @param[in] cfp pointer to the filters array, can be @p NULL if
|
||||
|
|
@ -77,17 +77,17 @@ static void can_lld_set_filters(CANDriver* canp,
|
|||
uint32_t num,
|
||||
const CANFilter *cfp) {
|
||||
|
||||
#if GD32_CAN_USE_CAN2
|
||||
#if GD32_CAN_USE_CAN1
|
||||
if (canp == &CAND2) {
|
||||
/* Set handle to CAN1, because CAN1 manages the filters of CAN2.*/
|
||||
/* Set handle to CAN0, because CAN0 manages the filters of CAN1.*/
|
||||
canp = &CAND1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Temporarily enabling CAN clock.*/
|
||||
#if GD32_CAN_USE_CAN1
|
||||
#if GD32_CAN_USE_CAN0
|
||||
if (canp == &CAND1) {
|
||||
rcuEnableCAN1(true);
|
||||
rcuEnableCAN0(true);
|
||||
/* Filters initialization.*/
|
||||
canp->can->FCTL = (canp->can->FCTL & 0xFFFF0000) | CAN_FCTL_FLD;
|
||||
canp->can->FCTL = (canp->can->FCTL & 0xFFFF0000) | (can2sb << 8) | CAN_FCTL_FLD;
|
||||
|
|
@ -103,7 +103,7 @@ static void can_lld_set_filters(CANDriver* canp,
|
|||
canp->can->FSCFG = 0;
|
||||
canp->can->FAFIFO = 0;
|
||||
|
||||
#if GD32_CAN_USE_CAN1
|
||||
#if GD32_CAN_USE_CAN0
|
||||
if (canp == &CAND1) {
|
||||
for (i = 0; i < GD32_CAN_MAX_FILTERS; i++) {
|
||||
canp->can->sFilterRegister[i].FR1 = 0;
|
||||
|
|
@ -132,7 +132,7 @@ static void can_lld_set_filters(CANDriver* canp,
|
|||
CANs.*/
|
||||
canp->can->sFilterRegister[0].FR1 = 0;
|
||||
canp->can->sFilterRegister[0].FR2 = 0;
|
||||
#if GD32_CAN_USE_CAN2
|
||||
#if GD32_CAN_USE_CAN1
|
||||
if (canp == &CAND1) {
|
||||
canp->can->sFilterRegister[can2sb].FR1 = 0;
|
||||
canp->can->sFilterRegister[can2sb].FR2 = 0;
|
||||
|
|
@ -142,7 +142,7 @@ static void can_lld_set_filters(CANDriver* canp,
|
|||
canp->can->FAFIFO = 0;
|
||||
canp->can->FSCFG = 1;
|
||||
canp->can->FW = 1;
|
||||
#if GD32_CAN_USE_CAN2
|
||||
#if GD32_CAN_USE_CAN1
|
||||
if (canp == &CAND1) {
|
||||
canp->can->FSCFG |= 1 << can2sb;
|
||||
canp->can->FW |= 1 << can2sb;
|
||||
|
|
@ -153,9 +153,9 @@ static void can_lld_set_filters(CANDriver* canp,
|
|||
|
||||
/* Clock disabled, it will be enabled again in can_lld_start().*/
|
||||
/* Temporarily enabling CAN clock.*/
|
||||
#if GD32_CAN_USE_CAN1
|
||||
#if GD32_CAN_USE_CAN0
|
||||
if (canp == &CAND1) {
|
||||
rcuDisableCAN1();
|
||||
rcuDisableCAN0();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
@ -303,10 +303,10 @@ static void can_lld_sce_handler(CANDriver *canp) {
|
|||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if GD32_CAN_USE_CAN1 || defined(__DOXYGEN__)
|
||||
#if GD32_CAN_USE_CAN0 || defined(__DOXYGEN__)
|
||||
#if defined(GD32_CAN0_UNIFIED_HANDLER)
|
||||
/**
|
||||
* @brief CAN1 unified interrupt handler.
|
||||
* @brief CAN0 unified interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
|
|
@ -337,7 +337,7 @@ OSAL_IRQ_HANDLER(GD32_CAN0_UNIFIED_HANDLER) {
|
|||
#endif
|
||||
|
||||
/**
|
||||
* @brief CAN1 TX interrupt handler.
|
||||
* @brief CAN0 TX interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
|
|
@ -351,7 +351,7 @@ OSAL_IRQ_HANDLER(GD32_CAN0_TX_HANDLER) {
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief CAN1 RX0 interrupt handler.
|
||||
* @brief CAN0 RX0 interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
|
|
@ -365,7 +365,7 @@ OSAL_IRQ_HANDLER(GD32_CAN0_RX0_HANDLER) {
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief CAN1 RX1 interrupt handler.
|
||||
* @brief CAN0 RX1 interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
|
|
@ -379,7 +379,7 @@ OSAL_IRQ_HANDLER(GD32_CAN0_RX1_HANDLER) {
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief CAN1 SCE interrupt handler.
|
||||
* @brief CAN0 SCE interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
|
|
@ -392,16 +392,16 @@ OSAL_IRQ_HANDLER(GD32_CAN0_EWMC_HANDLER) {
|
|||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* !defined(GD32_CAN0_UNIFIED_HANDLER) */
|
||||
#endif /* GD32_CAN_USE_CAN1 */
|
||||
#endif /* GD32_CAN_USE_CAN0 */
|
||||
|
||||
#if GD32_CAN_USE_CAN2 || defined(__DOXYGEN__)
|
||||
#if defined(GD32_CAN1_UNIFIED_HANDLER)
|
||||
#if GD32_CAN_USE_CAN1 || defined(__DOXYGEN__)
|
||||
#if defined(GD32_CAN0_UNIFIED_HANDLER)
|
||||
/**
|
||||
* @brief CAN1 unified interrupt handler.
|
||||
* @brief CAN0 unified interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(GD32_CAN1_UNIFIED_HANDLER) {
|
||||
OSAL_IRQ_HANDLER(GD32_CAN0_UNIFIED_HANDLER) {
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
|
|
@ -412,7 +412,7 @@ OSAL_IRQ_HANDLER(GD32_CAN1_UNIFIED_HANDLER) {
|
|||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#else /* !defined(GD32_CAN1_UNIFIED_HANDLER) */
|
||||
#else /* !defined(GD32_CAN0_UNIFIED_HANDLER) */
|
||||
|
||||
#if !defined(GD32_CAN0_TX_HANDLER)
|
||||
#error "GD32_CAN0_TX_HANDLER not defined"
|
||||
|
|
@ -428,11 +428,11 @@ OSAL_IRQ_HANDLER(GD32_CAN1_UNIFIED_HANDLER) {
|
|||
#endif
|
||||
|
||||
/**
|
||||
* @brief CAN2 TX interrupt handler.
|
||||
* @brief CAN1 TX interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(GD32_CAN1_TX_HANDLER) {
|
||||
OSAL_IRQ_HANDLER(GD32_CAN0_TX_HANDLER) {
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
|
|
@ -442,11 +442,11 @@ OSAL_IRQ_HANDLER(GD32_CAN1_TX_HANDLER) {
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief CAN2 RX0 interrupt handler.
|
||||
* @brief CAN1 RX0 interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(GD32_CAN1_RX0_HANDLER) {
|
||||
OSAL_IRQ_HANDLER(GD32_CAN0_RX0_HANDLER) {
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
|
|
@ -456,11 +456,11 @@ OSAL_IRQ_HANDLER(GD32_CAN1_RX0_HANDLER) {
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief CAN2 RX1 interrupt handler.
|
||||
* @brief CAN1 RX1 interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(GD32_CAN1_RX1_HANDLER) {
|
||||
OSAL_IRQ_HANDLER(GD32_CAN0_RX1_HANDLER) {
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
|
|
@ -470,11 +470,11 @@ OSAL_IRQ_HANDLER(GD32_CAN1_RX1_HANDLER) {
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief CAN2 SCE interrupt handler.
|
||||
* @brief CAN1 SCE interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(GD32_CAN1_EWMC_HANDLER) {
|
||||
OSAL_IRQ_HANDLER(GD32_CAN0_EWMC_HANDLER) {
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
|
|
@ -482,8 +482,8 @@ OSAL_IRQ_HANDLER(GD32_CAN1_EWMC_HANDLER) {
|
|||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* !defined(GD32_CAN1_UNIFIED_HANDLER) */
|
||||
#endif /* GD32_CAN_USE_CAN2 */
|
||||
#endif /* !defined(GD32_CAN0_UNIFIED_HANDLER) */
|
||||
#endif /* GD32_CAN_USE_CAN1 */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
|
|
@ -496,10 +496,24 @@ OSAL_IRQ_HANDLER(GD32_CAN1_EWMC_HANDLER) {
|
|||
*/
|
||||
void can_lld_init(void) {
|
||||
|
||||
#if GD32_CAN_USE_CAN1
|
||||
#if GD32_CAN_USE_CAN0
|
||||
/* Driver initialization.*/
|
||||
canObjectInit(&CAND1);
|
||||
CAND1.can = CAN1;
|
||||
CAND1.can = CAN0;
|
||||
#if defined(GD32_CAN0_UNIFIED_NUMBER)
|
||||
eclicEnableVector(GD32_CAN0_UNIFIED_NUMBER, GD32_CAN_CAN0_IRQ_PRIORITY, GD32_CAN_CAN0_IRQ_TRIGGER);
|
||||
#else
|
||||
eclicEnableVector(GD32_CAN0_TX_NUMBER, GD32_CAN_CAN0_IRQ_PRIORITY, GD32_CAN_CAN0_IRQ_TRIGGER);
|
||||
eclicEnableVector(GD32_CAN0_RX0_NUMBER, GD32_CAN_CAN0_IRQ_PRIORITY, GD32_CAN_CAN0_IRQ_TRIGGER);
|
||||
eclicEnableVector(GD32_CAN0_RX1_NUMBER, GD32_CAN_CAN0_IRQ_PRIORITY, GD32_CAN_CAN0_IRQ_TRIGGER);
|
||||
eclicEnableVector(GD32_CAN0_EWMC_NUMBER, GD32_CAN_CAN0_IRQ_PRIORITY, GD32_CAN_CAN0_IRQ_TRIGGER);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if GD32_CAN_USE_CAN1
|
||||
/* Driver initialization.*/
|
||||
canObjectInit(&CAND2);
|
||||
CAND2.can = CAN1;
|
||||
#if defined(GD32_CAN0_UNIFIED_NUMBER)
|
||||
eclicEnableVector(GD32_CAN0_UNIFIED_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
|
||||
#else
|
||||
|
|
@ -508,25 +522,11 @@ void can_lld_init(void) {
|
|||
eclicEnableVector(GD32_CAN0_RX1_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
|
||||
eclicEnableVector(GD32_CAN0_EWMC_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if GD32_CAN_USE_CAN2
|
||||
/* Driver initialization.*/
|
||||
canObjectInit(&CAND2);
|
||||
CAND2.can = CAN2;
|
||||
#if defined(GD32_CAN1_UNIFIED_NUMBER)
|
||||
eclicEnableVector(GD32_CAN1_UNIFIED_NUMBER, GD32_CAN_CAN2_IRQ_PRIORITY, GD32_CAN_CAN2_IRQ_TRIGGER);
|
||||
#else
|
||||
eclicEnableVector(GD32_CAN1_TX_NUMBER, GD32_CAN_CAN2_IRQ_PRIORITY, GD32_CAN_CAN2_IRQ_TRIGGER);
|
||||
eclicEnableVector(GD32_CAN1_RX0_NUMBER, GD32_CAN_CAN2_IRQ_PRIORITY, GD32_CAN_CAN2_IRQ_TRIGGER);
|
||||
eclicEnableVector(GD32_CAN1_RX1_NUMBER, GD32_CAN_CAN2_IRQ_PRIORITY, GD32_CAN_CAN2_IRQ_TRIGGER);
|
||||
eclicEnableVector(GD32_CAN1_EWMC_NUMBER, GD32_CAN_CAN2_IRQ_PRIORITY, GD32_CAN_CAN2_IRQ_TRIGGER);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Filters initialization.*/
|
||||
#if GD32_CAN_USE_CAN1
|
||||
#if GD32_HAS_CAN2
|
||||
#if GD32_CAN_USE_CAN0
|
||||
#if GD32_HAS_CAN1
|
||||
can_lld_set_filters(&CAND1, GD32_CAN_MAX_FILTERS / 2, 0, NULL);
|
||||
#else
|
||||
can_lld_set_filters(&CAND1, GD32_CAN_MAX_FILTERS, 0, NULL);
|
||||
|
|
@ -544,16 +544,16 @@ void can_lld_init(void) {
|
|||
void can_lld_start(CANDriver *canp) {
|
||||
|
||||
/* Clock activation.*/
|
||||
#if GD32_CAN_USE_CAN1
|
||||
#if GD32_CAN_USE_CAN0
|
||||
if (&CAND1 == canp) {
|
||||
rcuEnableCAN1(true);
|
||||
rcuEnableCAN0(true);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if GD32_CAN_USE_CAN2
|
||||
#if GD32_CAN_USE_CAN1
|
||||
if (&CAND2 == canp) {
|
||||
rcuEnableCAN1(true); /* CAN 2 requires CAN1, so enabling it first.*/
|
||||
rcuEnableCAN2(true);
|
||||
rcuEnableCAN0(true); /* CAN 2 requires CAN0, so enabling it first.*/
|
||||
rcuEnableCAN1(true);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -589,32 +589,32 @@ void can_lld_stop(CANDriver *canp) {
|
|||
|
||||
/* If in ready state then disables the CAN peripheral.*/
|
||||
if (canp->state == CAN_READY) {
|
||||
#if GD32_CAN_USE_CAN1
|
||||
#if GD32_CAN_USE_CAN0
|
||||
if (&CAND1 == canp) {
|
||||
CAN1->CTL = 0x00010002; /* Register reset value. */
|
||||
CAN1->INTEN = 0x00000000; /* All sources disabled. */
|
||||
#if GD32_CAN_USE_CAN2
|
||||
/* If CAND2 is stopped then CAN1 clock is stopped here.*/
|
||||
CAN0->CTL = 0x00010002; /* Register reset value. */
|
||||
CAN0->INTEN = 0x00000000; /* All sources disabled. */
|
||||
#if GD32_CAN_USE_CAN1
|
||||
/* If CAND2 is stopped then CAN0 clock is stopped here.*/
|
||||
if (CAND2.state == CAN_STOP)
|
||||
#endif
|
||||
{
|
||||
rcuDisableCAN1();
|
||||
rcuDisableCAN0();
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if GD32_CAN_USE_CAN2
|
||||
if (&CAND2 == canp) {
|
||||
CAN2->CTL = 0x00010002; /* Register reset value. */
|
||||
CAN2->INTEN = 0x00000000; /* All sources disabled. */
|
||||
#if GD32_CAN_USE_CAN1
|
||||
/* If CAND1 is stopped then CAN1 clock is stopped here.*/
|
||||
if (&CAND2 == canp) {
|
||||
CAN1->CTL = 0x00010002; /* Register reset value. */
|
||||
CAN1->INTEN = 0x00000000; /* All sources disabled. */
|
||||
#if GD32_CAN_USE_CAN0
|
||||
/* If CAND1 is stopped then CAN0 clock is stopped here.*/
|
||||
if (CAND1.state == CAN_STOP)
|
||||
#endif
|
||||
{
|
||||
rcuDisableCAN1();
|
||||
rcuDisableCAN0();
|
||||
}
|
||||
rcuDisableCAN2();
|
||||
rcuDisableCAN1();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
@ -837,7 +837,7 @@ void can_lld_wakeup(CANDriver *canp) {
|
|||
* @note This is an STM32-specific API.
|
||||
*
|
||||
* @param[in] canp pointer to the @p CANDriver object
|
||||
* @param[in] can2sb number of the first filter assigned to CAN2
|
||||
* @param[in] can2sb number of the first filter assigned to CAN1
|
||||
* @param[in] num number of entries in the filters array, if zero then
|
||||
* a default filter is programmed
|
||||
* @param[in] cfp pointer to the filters array, can be @p NULL if
|
||||
|
|
@ -848,19 +848,19 @@ void can_lld_wakeup(CANDriver *canp) {
|
|||
void canSTM32SetFilters(CANDriver *canp, uint32_t can2sb,
|
||||
uint32_t num, const CANFilter *cfp) {
|
||||
|
||||
#if GD32_CAN_USE_CAN2
|
||||
#if GD32_CAN_USE_CAN1
|
||||
osalDbgCheck((can2sb <= GD32_CAN_MAX_FILTERS) &&
|
||||
(num <= GD32_CAN_MAX_FILTERS));
|
||||
#endif
|
||||
|
||||
#if GD32_CAN_USE_CAN1
|
||||
#if GD32_CAN_USE_CAN0
|
||||
osalDbgAssert(CAND1.state == CAN_STOP, "invalid state");
|
||||
#endif
|
||||
#if GD32_CAN_USE_CAN2
|
||||
#if GD32_CAN_USE_CAN1
|
||||
osalDbgAssert(CAND2.state == CAN_STOP, "invalid state");
|
||||
#endif
|
||||
|
||||
#if GD32_CAN_USE_CAN1
|
||||
#if GD32_CAN_USE_CAN0
|
||||
if (canp == &CAND1) {
|
||||
can_lld_set_filters(canp, can2sb, num, cfp);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -88,6 +88,14 @@
|
|||
#define GD32_CAN_REPORT_ALL_ERRORS FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief CAN0 driver enable switch.
|
||||
* @details If set to @p TRUE the support for CAN0 is included.
|
||||
*/
|
||||
#if !defined(GD32_CAN_USE_CAN0) || defined(__DOXYGEN__)
|
||||
#define GD32_CAN_USE_CAN0 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief CAN1 driver enable switch.
|
||||
* @details If set to @p TRUE the support for CAN1 is included.
|
||||
|
|
@ -97,12 +105,12 @@
|
|||
#endif
|
||||
|
||||
/**
|
||||
* @brief CAN2 driver enable switch.
|
||||
* @details If set to @p TRUE the support for CAN2 is included.
|
||||
* @brief CAN0 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(GD32_CAN_USE_CAN2) || defined(__DOXYGEN__)
|
||||
#define GD32_CAN_USE_CAN2 FALSE
|
||||
#if !defined(GD32_CAN_CAN0_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define GD32_CAN_CAN0_IRQ_PRIORITY 11
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief CAN1 interrupt priority level setting.
|
||||
|
|
@ -112,44 +120,36 @@
|
|||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief CAN2 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(GD32_CAN_CAN2_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define GD32_CAN_CAN2_IRQ_PRIORITY 11
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(GD32_HAS_CAN0)
|
||||
#error "GD32_HAS_CAN0 not defined in registry"
|
||||
#endif
|
||||
|
||||
#if !defined(GD32_HAS_CAN1)
|
||||
#error "GD32_HAS_CAN1 not defined in registry"
|
||||
#endif
|
||||
|
||||
#if !defined(GD32_HAS_CAN2)
|
||||
#error "GD32_HAS_CAN2 not defined in registry"
|
||||
#if (GD32_HAS_CAN0 | GD32_HAS_CAN1) && !defined(GD32_CAN_MAX_FILTERS)
|
||||
#error "GD32_CAN_MAX_FILTERS not defined in registry"
|
||||
#endif
|
||||
|
||||
#if (GD32_HAS_CAN1 | GD32_HAS_CAN2) && !defined(GD32_CAN_MAX_FILTERS)
|
||||
#error "GD32_CAN_MAX_FILTERS not defined in registry"
|
||||
#if GD32_CAN_USE_CAN0 && !GD32_HAS_CAN0
|
||||
#error "CAN0 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if GD32_CAN_USE_CAN1 && !GD32_HAS_CAN1
|
||||
#error "CAN1 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if GD32_CAN_USE_CAN2 && !GD32_HAS_CAN2
|
||||
#error "CAN2 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if !GD32_CAN_USE_CAN1 && !GD32_CAN_USE_CAN2
|
||||
#if !GD32_CAN_USE_CAN0 && !GD32_CAN_USE_CAN1
|
||||
#error "CAN driver activated but no CAN peripheral assigned"
|
||||
#endif
|
||||
|
||||
#if !GD32_CAN_USE_CAN1 && GD32_CAN_USE_CAN2
|
||||
#error "CAN2 requires CAN1, it cannot operate independently"
|
||||
#if !GD32_CAN_USE_CAN0 && GD32_CAN_USE_CAN1
|
||||
#error "CAN1 requires CAN0, it cannot operate independently"
|
||||
#endif
|
||||
|
||||
#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP
|
||||
|
|
@ -398,11 +398,11 @@ struct CANDriver {
|
|||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if GD32_CAN_USE_CAN1 && !defined(__DOXYGEN__)
|
||||
#if GD32_CAN_USE_CAN0 && !defined(__DOXYGEN__)
|
||||
extern CANDriver CAND1;
|
||||
#endif
|
||||
|
||||
#if GD32_CAN_USE_CAN2 && !defined(__DOXYGEN__)
|
||||
#if GD32_CAN_USE_CAN1 && !defined(__DOXYGEN__)
|
||||
extern CANDriver CAND2;
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -177,9 +177,8 @@
|
|||
#define ECLIC_TRIGGER_DEFAULT ECLIC_POSTIVE_EDGE_TRIGGER
|
||||
#define ECLIC_DMA_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||
|
||||
#define GD32_CAN_CAN0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||
#define GD32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||
#define GD32_CAN_CAN2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||
#define GD32_CAN_CAN3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||
|
||||
#define GD32_I2C_I2C0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||
#define GD32_I2C_I2C1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
|
||||
|
|
|
|||
|
|
@ -299,13 +299,36 @@
|
|||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the CAN1 peripheral clock.
|
||||
* @brief Enables the CAN0 peripheral clock.
|
||||
* @note The @p lp parameter is ignored in this family.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rcuEnableCAN0(lp) rcuEnableAPB1(RCU_APB1ENR_CAN0EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the CAN0 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rcuDisableCAN0() rcuDisableAPB1(RCU_APB1ENR_CAN0EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the CAN0 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rcuResetCAN0() rcuResetAPB1(RCU_APB1RSTR_CAN0RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the CAN1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rcuEnableCAN1(lp) rcuEnableAPB1(RCU_APB1ENR_CAN1EN, lp)
|
||||
|
||||
/**
|
||||
|
|
@ -321,29 +344,6 @@
|
|||
* @api
|
||||
*/
|
||||
#define rcuResetCAN1() rcuResetAPB1(RCU_APB1RSTR_CAN1RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the CAN2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rcuEnableCAN2(lp) rcuEnableAPB1(RCU_APB1ENR_CAN2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the CAN2 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rcuDisableCAN2() rcuDisableAPB1(RCU_APB1ENR_CAN2EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the CAN2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rcuResetCAN2() rcuResetAPB1(RCU_APB1RSTR_CAN2RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -102,8 +102,8 @@
|
|||
#define GD32_HAS_ADC2 TRUE
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define GD32_HAS_CAN0 TRUE
|
||||
#define GD32_HAS_CAN1 TRUE
|
||||
#define GD32_HAS_CAN2 TRUE
|
||||
#define GD32_CAN_MAX_FILTERS 28
|
||||
|
||||
/* DAC attributes.*/
|
||||
|
|
|
|||
|
|
@ -664,8 +664,8 @@ typedef struct
|
|||
#define UART4_BASE (APB1PERIPH_BASE + 0x00005000U)
|
||||
#define I2C0_BASE (APB1PERIPH_BASE + 0x00005400U)
|
||||
#define I2C1_BASE (APB1PERIPH_BASE + 0x5800)
|
||||
#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
|
||||
#define CAN2_BASE (APB1PERIPH_BASE + 0x00006800U)
|
||||
#define CAN0_BASE (APB1PERIPH_BASE + 0x00006400U)
|
||||
#define CAN1_BASE (APB1PERIPH_BASE + 0x00006800U)
|
||||
//#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
|
||||
//#define PMU_BASE (APB1PERIPH_BASE + 0x00007000U)
|
||||
//#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
|
||||
|
|
@ -752,8 +752,8 @@ typedef struct
|
|||
#define UART4 ((USART_TypeDef *)UART4_BASE)
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
|
||||
#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
|
||||
#define CAN0 ((CAN_TypeDef *)CAN0_BASE)
|
||||
#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
|
||||
#define CAN2 ((CAN_TypeDef *)CAN2_BASE)
|
||||
#define BKP ((BKP_TypeDef *)BKP_BASE)
|
||||
#define PMU ((PMU_TypeDef *)PMU_BASE)
|
||||
#define DAC1 ((DAC_TypeDef *)DAC_BASE)
|
||||
|
|
@ -1499,9 +1499,9 @@ typedef struct
|
|||
#define RCU_APB1RSTR_I2C0RST_Msk (0x1U << RCU_APB1RSTR_I2C0RST_Pos) /*!< 0x00200000 */
|
||||
#define RCU_APB1RSTR_I2C0RST RCU_APB1RSTR_I2C0RST_Msk /*!< I2C 1 reset */
|
||||
|
||||
#define RCU_APB1RSTR_CAN1RST_Pos (25U)
|
||||
#define RCU_APB1RSTR_CAN1RST_Msk (0x1U << RCU_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
|
||||
#define RCU_APB1RSTR_CAN1RST RCU_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
|
||||
#define RCU_APB1RSTR_CAN0RST_Pos (25U)
|
||||
#define RCU_APB1RSTR_CAN0RST_Msk (0x1U << RCU_APB1RSTR_CAN0RST_Pos) /*!< 0x02000000 */
|
||||
#define RCU_APB1RSTR_CAN0RST RCU_APB1RSTR_CAN0RST_Msk /*!< CAN0 reset */
|
||||
|
||||
#define RCU_APB1RSTR_BKPRST_Pos (27U)
|
||||
#define RCU_APB1RSTR_BKPRST_Msk (0x1U << RCU_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
|
||||
|
|
@ -1545,9 +1545,9 @@ typedef struct
|
|||
|
||||
|
||||
|
||||
#define RCU_APB1RSTR_CAN2RST_Pos (26U)
|
||||
#define RCU_APB1RSTR_CAN2RST_Msk (0x1U << RCU_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
|
||||
#define RCU_APB1RSTR_CAN2RST RCU_APB1RSTR_CAN2RST_Msk /*!< CAN2 reset */
|
||||
#define RCU_APB1RSTR_CAN1RST_Pos (26U)
|
||||
#define RCU_APB1RSTR_CAN1RST_Msk (0x1U << RCU_APB1RSTR_CAN1RST_Pos) /*!< 0x04000000 */
|
||||
#define RCU_APB1RSTR_CAN1RST RCU_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
|
||||
|
||||
#define RCU_APB1RSTR_DACRST_Pos (29U)
|
||||
#define RCU_APB1RSTR_DACRST_Msk (0x1U << RCU_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
|
||||
|
|
@ -1635,9 +1635,9 @@ typedef struct
|
|||
#define RCU_APB1ENR_I2C0EN_Msk (0x1U << RCU_APB1ENR_I2C0EN_Pos) /*!< 0x00200000 */
|
||||
#define RCU_APB1ENR_I2C0EN RCU_APB1ENR_I2C0EN_Msk /*!< I2C 1 clock enable */
|
||||
|
||||
#define RCU_APB1ENR_CAN1EN_Pos (25U)
|
||||
#define RCU_APB1ENR_CAN1EN_Msk (0x1U << RCU_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
|
||||
#define RCU_APB1ENR_CAN1EN RCU_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
|
||||
#define RCU_APB1ENR_CAN0EN_Pos (25U)
|
||||
#define RCU_APB1ENR_CAN0EN_Msk (0x1U << RCU_APB1ENR_CAN0EN_Pos) /*!< 0x02000000 */
|
||||
#define RCU_APB1ENR_CAN0EN RCU_APB1ENR_CAN0EN_Msk /*!< CAN0 clock enable */
|
||||
|
||||
#define RCU_APB1ENR_BKPEN_Pos (27U)
|
||||
#define RCU_APB1ENR_BKPEN_Msk (0x1U << RCU_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
|
||||
|
|
@ -1681,9 +1681,9 @@ typedef struct
|
|||
|
||||
|
||||
|
||||
#define RCU_APB1ENR_CAN2EN_Pos (26U)
|
||||
#define RCU_APB1ENR_CAN2EN_Msk (0x1U << RCU_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
|
||||
#define RCU_APB1ENR_CAN2EN RCU_APB1ENR_CAN2EN_Msk /*!< CAN2 clock enable */
|
||||
#define RCU_APB1ENR_CAN1EN_Pos (26U)
|
||||
#define RCU_APB1ENR_CAN1EN_Msk (0x1U << RCU_APB1ENR_CAN1EN_Pos) /*!< 0x04000000 */
|
||||
#define RCU_APB1ENR_CAN1EN RCU_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
|
||||
|
||||
#define RCU_APB1ENR_DACEN_Pos (29U)
|
||||
#define RCU_APB1ENR_DACEN_Msk (0x1U << RCU_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
|
||||
|
|
@ -5781,7 +5781,7 @@ typedef struct
|
|||
#define CAN_FCTL_FLD CAN_FCTL_FLD_Msk /*!< Filter Init Mode */
|
||||
#define CAN_FCTL_HBC1F_Pos (8U)
|
||||
#define CAN_FCTL_HBC1F_Msk (0x3FU << CAN_FCTL_HBC1F_Pos) /*!< 0x00003F00 */
|
||||
#define CAN_FCTL_HBC1F CAN_FCTL_HBC1F_Msk /*!< CAN2 start bank */
|
||||
#define CAN_FCTL_HBC1F CAN_FCTL_HBC1F_Msk /*!< CAN1 start bank */
|
||||
|
||||
/******************* Bit definition for CAN_FMCFG register *******************/
|
||||
#define CAN_FMCFG_FMOD_Pos (0U)
|
||||
|
|
|
|||
Loading…
Reference in New Issue