rusefi
/
ChibiOS-Contrib
mirror of https://github.com/rusefi/ChibiOS-Contrib.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Rename RCU registers

This commit is contained in:
Stefan Kerkmann 2021-03-31 11:34:30 +02:00
parent 66e83a4685
commit 4eef25ac2a
3 changed files with 71 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
os/hal/ports/GD/GD32VF103/gd32_rcu.h
View File

@ -61,8 +61,8 @@
* @api * @api
*/ */
#define rcuEnableAPB1(mask, lp) { \ #define rcuEnableAPB1(mask, lp) { \
RCU->APB1ENR |= (mask); \ RCU->APB1EN |= (mask); \
(void)RCU->APB1ENR; \ (void)RCU->APB1EN; \
} }
/** /**
@ -74,8 +74,8 @@
* @api * @api
*/ */
#define rcuDisableAPB1(mask) { \ #define rcuDisableAPB1(mask) { \
RCU->APB1ENR &= ~(mask); \ RCU->APB1EN &= ~(mask); \
(void)RCU->APB1ENR; \ (void)RCU->APB1EN; \
} }
/** /**
@ -86,9 +86,9 @@
* @api * @api
*/ */
#define rcuResetAPB1(mask) { \ #define rcuResetAPB1(mask) { \
RCU->APB1RSTR |= (mask); \ RCU->APB1RST |= (mask); \
RCU->APB1RSTR &= ~(mask); \ RCU->APB1RST &= ~(mask); \
(void)RCU->APB1RSTR; \ (void)RCU->APB1RST; \
} }
/** /**
@ -101,8 +101,8 @@
* @api * @api
*/ */
#define rcuEnableAPB2(mask, lp) { \ #define rcuEnableAPB2(mask, lp) { \
RCU->APB2ENR |= (mask); \ RCU->APB2EN |= (mask); \
(void)RCU->APB2ENR; \ (void)RCU->APB2EN; \
} }
/** /**
@ -114,8 +114,8 @@
* @api * @api
*/ */
#define rcuDisableAPB2(mask) { \ #define rcuDisableAPB2(mask) { \
RCU->APB2ENR &= ~(mask); \ RCU->APB2EN &= ~(mask); \
(void)RCU->APB2ENR; \ (void)RCU->APB2EN; \
} }
/** /**
@ -126,9 +126,9 @@
* @api * @api
*/ */
#define rcuResetAPB2(mask) { \ #define rcuResetAPB2(mask) { \
RCU->APB2RSTR |= (mask); \ RCU->APB2RST |= (mask); \
RCU->APB2RSTR &= ~(mask); \ RCU->APB2RST &= ~(mask); \
(void)RCU->APB2RSTR; \ (void)RCU->APB2RST; \
} }
/** /**
@ -141,8 +141,8 @@
* @api * @api
*/ */
#define rcuEnableAHB(mask, lp) { \ #define rcuEnableAHB(mask, lp) { \
RCU->AHBENR |= (mask); \ RCU->AHBEN |= (mask); \
(void)RCU->AHBENR; \ (void)RCU->AHBEN; \
} }
/** /**
@ -154,8 +154,8 @@
* @api * @api
*/ */
#define rcuDisableAHB(mask) { \ #define rcuDisableAHB(mask) { \
RCU->AHBENR &= ~(mask); \ RCU->AHBEN &= ~(mask); \
(void)RCU->AHBENR; \ (void)RCU->AHBEN; \
} }
/** /**
@ -166,9 +166,9 @@
* @api * @api
*/ */
#define rcuResetAHB(mask) { \ #define rcuResetAHB(mask) { \
RCU->AHBRSTR |= (mask); \ RCU->AHBRST |= (mask); \
RCU->AHBRSTR &= ~(mask); \ RCU->AHBRST &= ~(mask); \
(void)RCU->AHBRSTR; \ (void)RCU->AHBRST; \
} }
/** @} */ /** @} */
@ -262,7 +262,7 @@
* *
* @api * @api
*/ */
#define rcuResetBKP() (RCU->BDCR |= RCU_BDCR_BDRST) #define rcuResetBKP() (RCU->BDCTL |= RCU_BDCR_BDRST)
/** @} */ /** @} */
/** /**

70
os/hal/ports/GD/GD32VF103/hal_lld.c
View File

@ -54,41 +54,41 @@ uint32_t SystemCoreClock = GD32_HCLK;
static void hal_lld_backup_domain_init(void) { static void hal_lld_backup_domain_init(void) {
/* Backup domain access enabled and left open.*/ /* Backup domain access enabled and left open.*/
PWR->CR |= PWR_CR_DBP; PWR->CTL |= PWR_CR_DBP;
#if HAL_USE_RTC #if HAL_USE_RTC
/* Reset BKP domain if different clock source selected.*/ /* Reset BKP domain if different clock source selected.*/
if ((RCU->BDCR & GD32_RTCSEL_MASK) != GD32_RTCSEL) { if ((RCU->BDCTL & GD32_RTCSEL_MASK) != GD32_RTCSEL) {
/* Backup domain reset.*/ /* Backup domain reset.*/
RCU->BDCR = RCU_BDCR_BDRST; RCU->BDCTL = RCU_BDCR_BDRST;
RCU->BDCR = 0; RCU->BDCTL = 0;
} }
/* If enabled then the LSE is started.*/ /* If enabled then the LSE is started.*/
#if GD32_LSE_ENABLED #if GD32_LSE_ENABLED
#if defined(GD32_LSE_BYPASS) #if defined(GD32_LSE_BYPASS)
/* LSE Bypass.*/ /* LSE Bypass.*/
RCU->BDCR |= RCU_BDCR_LSEON | RCU_BDCR_LSEBYP; RCU->BDCTL |= RCU_BDCR_LSEON | RCU_BDCR_LSEBYP;
#else #else
/* No LSE Bypass.*/ /* No LSE Bypass.*/
RCU->BDCR |= RCU_BDCR_LSEON; RCU->BDCTL |= RCU_BDCR_LSEON;
#endif #endif
while ((RCU->BDCR & RCU_BDCR_LSERDY) == 0) while ((RCU->BDCTL & RCU_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */ ; /* Waits until LSE is stable. */
#endif /* GD32_LSE_ENABLED */ #endif /* GD32_LSE_ENABLED */
#if GD32_RTCSEL != GD32_RTCSEL_NOCLOCK #if GD32_RTCSEL != GD32_RTCSEL_NOCLOCK
/* If the backup domain hasn't been initialized yet then proceed with /* If the backup domain hasn't been initialized yet then proceed with
initialization.*/ initialization.*/
if ((RCU->BDCR & RCU_BDCR_RTCEN) == 0) { if ((RCU->BDCTL & RCU_BDCR_RTCEN) == 0) {
/* Selects clock source.*/ /* Selects clock source.*/
RCU->BDCR |= GD32_RTCSEL; RCU->BDCTL |= GD32_RTCSEL;
/* Prescaler value loaded in registers.*/ /* Prescaler value loaded in registers.*/
rtc_lld_set_prescaler(); rtc_lld_set_prescaler();
/* RTC clock enabled.*/ /* RTC clock enabled.*/
RCU->BDCR |= RCU_BDCR_RTCEN; RCU->BDCTL |= RCU_BDCR_RTCEN;
} }
#endif /* GD32_RTCSEL != GD32_RTCSEL_NOCLOCK */ #endif /* GD32_RTCSEL != GD32_RTCSEL_NOCLOCK */
#endif /* HAL_USE_RTC */ #endif /* HAL_USE_RTC */
@ -152,7 +152,7 @@ void hal_lld_init(void) {
/* Programmable voltage detector enable.*/ /* Programmable voltage detector enable.*/
#if GD32_PVD_ENABLE #if GD32_PVD_ENABLE
PWR->CR |= PWR_CR_PVDE | (GD32_PLS & GD32_PLS_MASK); PWR->CTL |= PWR_CR_PVDE | (GD32_PLS & GD32_PLS_MASK);
#endif /* GD32_PVD_ENABLE */ #endif /* GD32_PVD_ENABLE */
} }
@ -173,72 +173,72 @@ void gd32_clock_init(void) {
#if !GD32_NO_INIT #if !GD32_NO_INIT
/* HSI setup, it enforces the reset situation in order to handle possible /* HSI setup, it enforces the reset situation in order to handle possible
problems with JTAG probes and re-initializations.*/ problems with JTAG probes and re-initializations.*/
RCU->CR |= RCU_CR_HSION; /* Make sure HSI is ON. */ RCU->CTL |= RCU_CR_HSION; /* Make sure HSI is ON. */
while (!(RCU->CR & RCU_CR_HSIRDY)) while (!(RCU->CTL & RCU_CR_HSIRDY))
; /* Wait until HSI is stable. */ ; /* Wait until HSI is stable. */
/* HSI is selected as new source without touching the other fields in /* HSI is selected as new source without touching the other fields in
CFGR. Clearing the register has to be postponed after HSI is the CFGR. Clearing the register has to be postponed after HSI is the
new source.*/ new source.*/
RCU->CFGR &= ~RCU_CFGR_SW; /* Reset SW, selecting HSI. */ RCU->CFG0 &= ~RCU_CFGR_SW; /* Reset SW, selecting HSI. */
while ((RCU->CFGR & RCU_CFGR_SWS) != RCU_CFGR_SWS_HSI) while ((RCU->CFG0 & RCU_CFGR_SWS) != RCU_CFGR_SWS_HSI)
; /* Wait until HSI is selected. */ ; /* Wait until HSI is selected. */
/* Registers finally cleared to reset values.*/ /* Registers finally cleared to reset values.*/
RCU->CR &= RCU_CR_HSITRIM | RCU_CR_HSION; /* CR Reset value. */ RCU->CTL &= RCU_CR_HSITRIM | RCU_CR_HSION; /* CR Reset value. */
RCU->CFGR = 0; /* CFGR reset value. */ RCU->CFG0 = 0; /* CFGR reset value. */
#if GD32_HSE_ENABLED #if GD32_HSE_ENABLED
#if defined(GD32_HSE_BYPASS) #if defined(GD32_HSE_BYPASS)
/* HSE Bypass.*/ /* HSE Bypass.*/
RCU->CR |= RCU_CR_HSEBYP; RCU->CTL |= RCU_CR_HSEBYP;
#endif #endif
/* HSE activation.*/ /* HSE activation.*/
RCU->CR |= RCU_CR_HSEON; RCU->CTL |= RCU_CR_HSEON;
while (!(RCU->CR & RCU_CR_HSERDY)) while (!(RCU->CTL & RCU_CR_HSERDY))
; /* Waits until HSE is stable. */ ; /* Waits until HSE is stable. */
#endif #endif
#if GD32_LSI_ENABLED #if GD32_LSI_ENABLED
/* LSI activation.*/ /* LSI activation.*/
RCU->CSR |= RCU_CSR_LSION; RCU->RSTSCK |= RCU_CSR_LSION;
while ((RCU->CSR & RCU_CSR_LSIRDY) == 0) while ((RCU->RSTSCK & RCU_CSR_LSIRDY) == 0)
; /* Waits until LSI is stable. */ ; /* Waits until LSI is stable. */
#endif #endif
/* Settings of various dividers and multipliers in CFGR2.*/ /* Settings of various dividers and multipliers in CFGR2.*/
/*RCU->CFGR2 = GD32_PLL3MUL | GD32_PLL2MUL | GD32_PREDIV2 | /*RCU->CFG02 = GD32_PLL3MUL | GD32_PLL2MUL | GD32_PREDIV2 |
GD32_PREDIV1 | GD32_PREDIV1SRC;*/ GD32_PREDIV1 | GD32_PREDIV1SRC;*/
/* PLL2 setup, if activated.*/ /* PLL2 setup, if activated.*/
#if GD32_ACTIVATE_PLL2 #if GD32_ACTIVATE_PLL2
RCU->CR |= RCU_CR_PLL2ON; RCU->CTL |= RCU_CR_PLL2ON;
while (!(RCU->CR & RCU_CR_PLL2RDY)) while (!(RCU->CTL & RCU_CR_PLL2RDY))
; /* Waits until PLL2 is stable. */ ; /* Waits until PLL2 is stable. */
#endif #endif
/* PLL3 setup, if activated.*/ /* PLL3 setup, if activated.*/
#if GD32_ACTIVATE_PLL3 #if GD32_ACTIVATE_PLL3
RCU->CR |= RCU_CR_PLL3ON; RCU->CTL |= RCU_CR_PLL3ON;
while (!(RCU->CR & RCU_CR_PLL3RDY)) while (!(RCU->CTL & RCU_CR_PLL3RDY))
; /* Waits until PLL3 is stable. */ ; /* Waits until PLL3 is stable. */
#endif #endif
/* PLL1 setup, if activated.*/ /* PLL1 setup, if activated.*/
//#if GD32_ACTIVATE_PLL1 //#if GD32_ACTIVATE_PLL1
#if GD32_ACTIVATE_PLL #if GD32_ACTIVATE_PLL
RCU->CFGR |= GD32_PLLMUL | GD32_PLLSRC; RCU->CFG0 |= GD32_PLLMUL | GD32_PLLSRC;
RCU->CR |= RCU_CR_PLLON; RCU->CTL |= RCU_CR_PLLON;
while (!(RCU->CR & RCU_CR_PLLRDY)) while (!(RCU->CTL & RCU_CR_PLLRDY))
; /* Waits until PLL1 is stable. */ ; /* Waits until PLL1 is stable. */
#endif #endif
/* Clock settings.*/ /* Clock settings.*/
#if GD32_HAS_USBFS #if GD32_HAS_USBFS
RCU->CFGR = GD32_MCOSEL | GD32_USBPRE | GD32_PLLMUL | GD32_PLLSRC | RCU->CFG0 = GD32_MCOSEL | GD32_USBPRE | GD32_PLLMUL | GD32_PLLSRC |
GD32_ADCPRE | GD32_PPRE2 | GD32_PPRE1 | GD32_HPRE; GD32_ADCPRE | GD32_PPRE2 | GD32_PPRE1 | GD32_HPRE;
#else #else
RCU->CFGR = GD32_MCO | GD32_PLLMUL | GD32_PLLSRC | RCU->CFG0 = GD32_MCO | GD32_PLLMUL | GD32_PLLSRC |
GD32_ADCPRE | GD32_PPRE2 | GD32_PPRE1 | GD32_HPRE; GD32_ADCPRE | GD32_PPRE2 | GD32_PPRE1 | GD32_HPRE;
#endif #endif
@ -250,13 +250,13 @@ void gd32_clock_init(void) {
/* Switching to the configured clock source if it is different from HSI.*/ /* Switching to the configured clock source if it is different from HSI.*/
#if (GD32_SW != GD32_SW_HSI) #if (GD32_SW != GD32_SW_HSI)
RCU->CFGR |= GD32_SW; /* Switches on the selected clock source. */ RCU->CFG0 |= GD32_SW; /* Switches on the selected clock source. */
while ((RCU->CFGR & RCU_CFGR_SWS) != (GD32_SW << 2)) while ((RCU->CFG0 & RCU_CFGR_SWS) != (GD32_SW << 2))
; ;
#endif #endif
#if !GD32_HSI_ENABLED #if !GD32_HSI_ENABLED
RCU->CR &= ~RCU_CR_HSION; RCU->CTL &= ~RCU_CR_HSION;
#endif #endif
#endif /* !GD32_NO_INIT */ #endif /* !GD32_NO_INIT */
} }

28
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -430,20 +430,20 @@ typedef struct
typedef struct typedef struct
{ {
__IO uint32_t CR; __IO uint32_t CTL;
__IO uint32_t CFGR; __IO uint32_t CFG0;
__IO uint32_t CIR; __IO uint32_t INT;
__IO uint32_t APB2RSTR; __IO uint32_t APB2RST;
__IO uint32_t APB1RSTR; __IO uint32_t APB1RST;
__IO uint32_t AHBENR; __IO uint32_t AHBEN;
__IO uint32_t APB2ENR; __IO uint32_t APB2EN;
__IO uint32_t APB1ENR; __IO uint32_t APB1EN;
__IO uint32_t BDCR; __IO uint32_t BDCTL;
__IO uint32_t CSR; __IO uint32_t RSTSCK;
__IO uint32_t AHBRST;
__IO uint32_t AHBRSTR; __IO uint32_t CFG1;
__IO uint32_t CFGR2; uint32_t RESERVED;
__IO uint32_t DSV;
} RCU_TypeDef; } RCU_TypeDef;
/** /**