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Renumber SPI to begin at 0

This commit is contained in:
Stefan Kerkmann 2021-03-29 20:22:44 +02:00
parent c384a54401
commit 4f93d001a4
6 changed files with 242 additions and 239 deletions
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160
os/hal/ports/GD/GD32VF103/SPI/hal_i2s_lld.c
View File

@ -31,72 +31,72 @@
/*===========================================================================*/
#define I2S2_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_I2S_SPI1_RX_DMA_STREAM, \
GD32_SPI1_RX_DMA_CHN)
#define I2S2_TX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_I2S_SPI1_TX_DMA_STREAM, \
GD32_SPI1_TX_DMA_CHN)
#define I2S3_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_I2S_SPI2_RX_DMA_STREAM, \
GD32_SPI2_RX_DMA_CHN)
#define I2S2_TX_DMA_CHANNEL \
#define I2S3_TX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_I2S_SPI2_TX_DMA_STREAM, \
GD32_SPI2_TX_DMA_CHN)
#define I2S3_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_I2S_SPI3_RX_DMA_STREAM, \
GD32_SPI3_RX_DMA_CHN)
#define I2S3_TX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_I2S_SPI3_TX_DMA_STREAM, \
GD32_SPI3_TX_DMA_CHN)
/*
* Static I2S settings for I2S2.
*/
#if !GD32_I2S_IS_MASTER(GD32_I2S_SPI2_MODE)
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE)
#if !GD32_I2S_IS_MASTER(GD32_I2S_SPI1_MODE)
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI1_MODE)
#define GD32_I2S2_CFGR_CFG 0
#endif
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE)
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI1_MODE)
#define GD32_I2S2_CFGR_CFG SPI_I2SCTL_I2SOPMOD_0
#endif
#else /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI2_MODE) */
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE)
#else /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI1_MODE) */
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI1_MODE)
#define GD32_I2S2_CFGR_CFG SPI_I2SCTL_I2SOPMOD_1
#endif
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE)
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI1_MODE)
#define GD32_I2S2_CFGR_CFG (SPI_I2SCTL_I2SOPMOD_1 | \
SPI_I2SCTL_I2SOPMOD_0)
#endif
#endif /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI2_MODE) */
#endif /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI1_MODE) */
/*
* Static I2S settings for I2S3.
*/
#if !GD32_I2S_IS_MASTER(GD32_I2S_SPI3_MODE)
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI3_MODE)
#if !GD32_I2S_IS_MASTER(GD32_I2S_SPI2_MODE)
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE)
#define GD32_I2S3_CFGR_CFG 0
#endif
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI3_MODE)
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE)
#define GD32_I2S3_CFGR_CFG SPI_I2SCTL_I2SOPMOD_0
#endif
#else /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI3_MODE) */
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI3_MODE)
#else /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI2_MODE) */
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE)
#define GD32_I2S3_CFGR_CFG SPI_I2SCTL_I2SOPMOD_1
#endif
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI3_MODE)
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE)
#define GD32_I2S3_CFGR_CFG (SPI_I2SCTL_I2SOPMOD_1 | \
SPI_I2SCTL_I2SOPMOD_0)
#endif
#endif /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI3_MODE) */
#endif /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI2_MODE) */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/** @brief I2S2 driver identifier.*/
#if GD32_I2S_USE_SPI2 || defined(__DOXYGEN__)
#if GD32_I2S_USE_SPI1 || defined(__DOXYGEN__)
I2SDriver I2SD2;
#endif
/** @brief I2S3 driver identifier.*/
#if GD32_I2S_USE_SPI3 || defined(__DOXYGEN__)
#if GD32_I2S_USE_SPI2 || defined(__DOXYGEN__)
I2SDriver I2SD3;
#endif
@ -108,8 +108,8 @@ I2SDriver I2SD3;
/* Driver local functions. */
/*===========================================================================*/
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE) || \
GD32_I2S_RX_ENABLED(GD32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI1_MODE) || \
GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE) || defined(__DOXYGEN__)
/**
* @brief Shared end-of-rx service routine.
*
@ -140,9 +140,9 @@ static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) {
}
#endif
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI1_MODE) || \
GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE) || \
GD32_I2S_TX_ENABLED(GD32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI0_MODE) || \
GD32_I2S_TX_ENABLED(GD32_I2S_SPI1_MODE) || \
GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE) || defined(__DOXYGEN__)
/**
* @brief Shared end-of-tx service routine.
*
@ -188,15 +188,15 @@ static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) {
*/
void i2s_lld_init(void) {
#if GD32_I2S_USE_SPI2
#if GD32_I2S_USE_SPI1
i2sObjectInit(&I2SD2);
I2SD2.spi = SPI2;
I2SD2.spi = SPI1;
I2SD2.ctl = GD32_I2S2_CFGR_CFG;
I2SD2.dmarx = NULL;
I2SD2.dmatx = NULL;
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE)
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI1_MODE)
I2SD2.rxdmamode = GD32_DMA_CTL_CHSEL(I2S2_RX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_I2S_SPI2_DMA_PRIORITY) |
GD32_DMA_CTL_PRIO(GD32_I2S_SPI1_DMA_PRIORITY) |
GD32_DMA_CTL_PWIDTH_HWORD |
GD32_DMA_CTL_MWIDTH_HWORD |
GD32_DMA_CTL_DIR_P2M |
@ -209,9 +209,9 @@ void i2s_lld_init(void) {
#else
I2SD2.rxdmamode = 0;
#endif
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE)
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI1_MODE)
I2SD2.txdmamode = GD32_DMA_CTL_CHSEL(I2S2_TX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_I2S_SPI2_DMA_PRIORITY) |
GD32_DMA_CTL_PRIO(GD32_I2S_SPI1_DMA_PRIORITY) |
GD32_DMA_CTL_PWIDTH_HWORD |
GD32_DMA_CTL_MWIDTH_HWORD |
GD32_DMA_CTL_DIR_M2P |
@ -226,15 +226,15 @@ void i2s_lld_init(void) {
#endif
#endif
#if GD32_I2S_USE_SPI3
#if GD32_I2S_USE_SPI2
i2sObjectInit(&I2SD3);
I2SD3.spi = SPI3;
I2SD3.spi = SPI2;
I2SD3.ctl = GD32_I2S3_CFGR_CFG;
I2SD3.dmarx = NULL;
I2SD3.dmatx = NULL;
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI3_MODE)
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE)
I2SD3.rxdmamode = GD32_DMA_CTL_CHSEL(I2S3_RX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_I2S_SPI3_DMA_PRIORITY) |
GD32_DMA_CTL_PRIO(GD32_I2S_SPI2_DMA_PRIORITY) |
GD32_DMA_CTL_PWIDTH_HWORD |
GD32_DMA_CTL_MWIDTH_HWORD |
GD32_DMA_CTL_DIR_P2M |
@ -247,9 +247,9 @@ void i2s_lld_init(void) {
#else
I2SD3.rxdmamode = 0;
#endif
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI3_MODE)
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE)
I2SD3.txdmamode = GD32_DMA_CTL_CHSEL(I2S3_TX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_I2S_SPI3_DMA_PRIORITY) |
GD32_DMA_CTL_PRIO(GD32_I2S_SPI2_DMA_PRIORITY) |
GD32_DMA_CTL_PWIDTH_HWORD |
GD32_DMA_CTL_MWIDTH_HWORD |
GD32_DMA_CTL_DIR_M2P |
@ -277,9 +277,42 @@ void i2s_lld_start(I2SDriver *i2sp) {
/* If in stopped state then enables the SPI and DMA clocks.*/
if (i2sp->state == I2S_STOP) {
#if GD32_I2S_USE_SPI2
#if GD32_I2S_USE_SPI1
if (&I2SD2 == i2sp) {
/* Enabling I2S unit clock.*/
rccEnableSPI1(true);
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI1_MODE)
i2sp->dmarx = dmaStreamAllocI(GD32_I2S_SPI1_RX_DMA_STREAM,
GD32_I2S_SPI1_IRQ_PRIORITY,
(gd32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(i2sp->dmarx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CTL0 = 0;
i2sp->spi->CTL1 = SPI_CTL1_DMAREN;
#endif
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI1_MODE)
i2sp->dmatx = dmaStreamAllocI(GD32_I2S_SPI1_TX_DMA_STREAM,
GD32_I2S_SPI1_IRQ_PRIORITY,
(gd32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(i2sp->dmatx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CTL0 = 0;
i2sp->spi->CTL1 = SPI_CTL1_DMATEN;
#endif
}
#endif
#if GD32_I2S_USE_SPI2
if (&I2SD3 == i2sp) {
/* Enabling I2S unit clock.*/
rccEnableSPI2(true);
@ -309,39 +342,6 @@ void i2s_lld_start(I2SDriver *i2sp) {
#endif
}
#endif
#if GD32_I2S_USE_SPI3
if (&I2SD3 == i2sp) {
/* Enabling I2S unit clock.*/
rccEnableSPI3(true);
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI3_MODE)
i2sp->dmarx = dmaStreamAllocI(GD32_I2S_SPI3_RX_DMA_STREAM,
GD32_I2S_SPI3_IRQ_PRIORITY,
(gd32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(i2sp->dmarx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CTL0 = 0;
i2sp->spi->CTL1 = SPI_CTL1_DMAREN;
#endif
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI3_MODE)
i2sp->dmatx = dmaStreamAllocI(GD32_I2S_SPI3_TX_DMA_STREAM,
GD32_I2S_SPI3_IRQ_PRIORITY,
(gd32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(i2sp->dmatx != NULL, "unable to allocate stream");
/* CRs settings are done here because those never changes until
the driver is stopped.*/
i2sp->spi->CTL0 = 0;
i2sp->spi->CTL1 = SPI_CTL1_DMATEN;
#endif
}
#endif
}
/* I2S (re)configuration.*/
@ -372,14 +372,14 @@ void i2s_lld_stop(I2SDriver *i2sp) {
i2sp->dmatx = NULL;
}
#if GD32_I2S_USE_SPI2
#if GD32_I2S_USE_SPI1
if (&I2SD2 == i2sp)
rccDisableSPI2();
rccDisableSPI1();
#endif
#if GD32_I2S_USE_SPI3
#if GD32_I2S_USE_SPI2
if (&I2SD3 == i2sp)
rccDisableSPI3();
rccDisableSPI2();
#endif
}
}

86
os/hal/ports/GD/GD32VF103/SPI/hal_i2s_lld.h
View File

@ -65,8 +65,8 @@
* @details If set to @p TRUE the support for I2S1 is included.
* @note The default is @p TRUE.
*/
#if !defined(GD32_I2S_USE_SPI1) || defined(__DOXYGEN__)
#define GD32_I2S_USE_SPI1 FALSE
#if !defined(GD32_I2S_USE_SPI0) || defined(__DOXYGEN__)
#define GD32_I2S_USE_SPI0 FALSE
#endif
/**
@ -74,8 +74,8 @@
* @details If set to @p TRUE the support for I2S2 is included.
* @note The default is @p TRUE.
*/
#if !defined(GD32_I2S_USE_SPI2) || defined(__DOXYGEN__)
#define GD32_I2S_USE_SPI2 FALSE
#if !defined(GD32_I2S_USE_SPI1) || defined(__DOXYGEN__)
#define GD32_I2S_USE_SPI1 FALSE
#endif
/**
@ -83,52 +83,52 @@
* @details If set to @p TRUE the support for I2S3 is included.
* @note The default is @p TRUE.
*/
#if !defined(GD32_I2S_USE_SPI3) || defined(__DOXYGEN__)
#define GD32_I2S_USE_SPI3 FALSE
#if !defined(GD32_I2S_USE_SPI2) || defined(__DOXYGEN__)
#define GD32_I2S_USE_SPI2 FALSE
#endif
/**
* @brief I2S2 mode.
*/
#if !defined(GD32_I2S_SPI1_MODE) || defined(__DOXYGEN__)
#define GD32_I2S_SPI1_MODE (GD32_I2S_MODE_MASTER | \
GD32_I2S_MODE_RX)
#endif
/**
* @brief I2S3 mode.
*/
#if !defined(GD32_I2S_SPI2_MODE) || defined(__DOXYGEN__)
#define GD32_I2S_SPI2_MODE (GD32_I2S_MODE_MASTER | \
GD32_I2S_MODE_RX)
#endif
/**
* @brief I2S3 mode.
* @brief I2S2 interrupt priority level setting.
*/
#if !defined(GD32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
#define GD32_I2S_SPI3_MODE (GD32_I2S_MODE_MASTER | \
GD32_I2S_MODE_RX)
#if !defined(GD32_I2S_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2S_SPI1_IRQ_PRIORITY 10
#endif
/**
* @brief I2S2 interrupt priority level setting.
* @brief I2S3 interrupt priority level setting.
*/
#if !defined(GD32_I2S_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2S_SPI2_IRQ_PRIORITY 10
#endif
/**
* @brief I2S3 interrupt priority level setting.
*/
#if !defined(GD32_I2S_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2S_SPI3_IRQ_PRIORITY 10
#endif
/**
* @brief I2S2 DMA priority (0..3|lowest..highest).
*/
#if !defined(GD32_I2S_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2S_SPI2_DMA_PRIORITY 1
#if !defined(GD32_I2S_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2S_SPI1_DMA_PRIORITY 1
#endif
/**
* @brief I2S3 DMA priority (0..3|lowest..highest).
*/
#if !defined(GD32_I2S_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2S_SPI3_DMA_PRIORITY 1
#if !defined(GD32_I2S_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2S_SPI2_DMA_PRIORITY 1
#endif
/**
@ -143,7 +143,11 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if GD32_I2S_USE_SPI1
#if GD32_I2S_USE_SPI0
#error "SPI0 does not support I2S mode"
#endif
#if GD32_I2S_USE_SPI1 && !GD32_SPI1_SUPPORTS_I2S
#error "SPI1 does not support I2S mode"
#endif
@ -151,30 +155,31 @@
#error "SPI2 does not support I2S mode"
#endif
#if GD32_I2S_USE_SPI3 && !GD32_SPI3_SUPPORTS_I2S
#error "SPI3 does not support I2S mode"
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI1_MODE) && \
GD32_I2S_TX_ENABLED(GD32_I2S_SPI1_MODE)
#error "I2S2 RX and TX mode not supported in this driver implementation"
#endif
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE) && \
GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE)
#error "I2S2 RX and TX mode not supported in this driver implementation"
#error "I2S3 RX and TX mode not supported in this driver implementation"
#endif
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI3_MODE) && \
GD32_I2S_TX_ENABLED(GD32_I2S_SPI3_MODE)
#error "I2S3 RX and TX mode not supported in this driver implementation"
#if GD32_I2S_USE_SPI1 && !GD32_HAS_SPI1
#error "SPI1 not present in the selected device"
#endif
#if GD32_I2S_USE_SPI2 && !GD32_HAS_SPI2
#error "SPI2 not present in the selected device"
#endif
#if GD32_I2S_USE_SPI3 && !GD32_HAS_SPI3
#error "SPI3 not present in the selected device"
#if !GD32_I2S_USE_SPI1 && !GD32_I2S_USE_SPI2
#error "I2S driver activated but no SPI peripheral assigned"
#endif
#if !GD32_I2S_USE_SPI2 && !GD32_I2S_USE_SPI3
#error "I2S driver activated but no SPI peripheral assigned"
#if GD32_I2S_USE_SPI1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_I2S_SPI1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI1"
#endif
#if GD32_I2S_USE_SPI2 && \
@ -182,9 +187,9 @@
#error "Invalid IRQ priority assigned to SPI2"
#endif
#if GD32_I2S_USE_SPI3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_I2S_SPI3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI3"
#if GD32_I2S_USE_SPI1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_I2S_SPI1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI1"
#endif
#if GD32_I2S_USE_SPI2 && \
@ -192,11 +197,6 @@
#error "Invalid DMA priority assigned to SPI2"
#endif
#if GD32_I2S_USE_SPI3 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_I2S_SPI3_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI3"
#endif
#if !defined(GD32_DMA_REQUIRED)
#define GD32_DMA_REQUIRED
#endif
@ -248,11 +248,11 @@
/* External declarations. */
/*===========================================================================*/
#if GD32_I2S_USE_SPI2 && !defined(__DOXYGEN__)
#if GD32_I2S_USE_SPI1 && !defined(__DOXYGEN__)
extern I2SDriver I2SD2;
#endif
#if GD32_I2S_USE_SPI3 && !defined(__DOXYGEN__)
#if GD32_I2S_USE_SPI2 && !defined(__DOXYGEN__)
extern I2SDriver I2SD3;
#endif

128
os/hal/ports/GD/GD32VF103/SPI/hal_spi_lld.c
View File

@ -30,6 +30,14 @@
/* Driver local definitions. */
/*===========================================================================*/
#define SPI0_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_SPI_SPI0_RX_DMA_STREAM, \
GD32_SPI0_RX_DMA_CHN)
#define SPI0_TX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_SPI_SPI0_TX_DMA_STREAM, \
GD32_SPI0_TX_DMA_CHN)
#define SPI1_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_SPI_SPI1_RX_DMA_STREAM, \
GD32_SPI1_RX_DMA_CHN)
@ -46,30 +54,22 @@
GD32_DMA_GETCHANNEL(GD32_SPI_SPI2_TX_DMA_STREAM, \
GD32_SPI2_TX_DMA_CHN)
#define SPI3_RX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_SPI_SPI3_RX_DMA_STREAM, \
GD32_SPI3_RX_DMA_CHN)
#define SPI3_TX_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_SPI_SPI3_TX_DMA_STREAM, \
GD32_SPI3_TX_DMA_CHN)
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/** @brief SPI0 driver identifier.*/
#if GD32_SPI_USE_SPI0 || defined(__DOXYGEN__)
SPIDriver SPID1;
#endif
/** @brief SPI1 driver identifier.*/
#if GD32_SPI_USE_SPI1 || defined(__DOXYGEN__)
SPIDriver SPID1;
SPIDriver SPID2;
#endif
/** @brief SPI2 driver identifier.*/
#if GD32_SPI_USE_SPI2 || defined(__DOXYGEN__)
SPIDriver SPID2;
#endif
/** @brief SPI3 driver identifier.*/
#if GD32_SPI_USE_SPI3 || defined(__DOXYGEN__)
SPIDriver SPID3;
#endif
@ -157,18 +157,36 @@ static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
*/
void spi_lld_init(void) {
#if GD32_SPI_USE_SPI1
#if GD32_SPI_USE_SPI0
spiObjectInit(&SPID1);
SPID1.spi = SPI1;
SPID1.spi = SPI0;
SPID1.dmarx = NULL;
SPID1.dmatx = NULL;
SPID1.rxdmamode = GD32_DMA_CTL_CHSEL(SPI1_RX_DMA_CHANNEL) |
SPID1.rxdmamode = GD32_DMA_CTL_CHSEL(SPI0_RX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_SPI_SPI0_DMA_PRIORITY) |
GD32_DMA_CTL_DIR_P2M |
GD32_DMA_CTL_FTFIE |
GD32_DMA_CTL_ERRIE;
SPID1.txdmamode = GD32_DMA_CTL_CHSEL(SPI0_TX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_SPI_SPI0_DMA_PRIORITY) |
GD32_DMA_CTL_DIR_M2P |
GD32_DMA_CTL_ERRIE;
#endif
#if GD32_SPI_USE_SPI1
spiObjectInit(&SPID2);
SPID2.spi = SPI1;
SPID2.dmarx = NULL;
SPID2.dmatx = NULL;
SPID2.rxdmamode = GD32_DMA_CTL_CHSEL(SPI1_RX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_SPI_SPI1_DMA_PRIORITY) |
GD32_DMA_CTL_DIR_P2M |
GD32_DMA_CTL_FTFIE |
GD32_DMA_CTL_ERRIE;
SPID1.txdmamode = GD32_DMA_CTL_CHSEL(SPI1_TX_DMA_CHANNEL) |
SPID2.txdmamode = GD32_DMA_CTL_CHSEL(SPI1_TX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_SPI_SPI1_DMA_PRIORITY) |
GD32_DMA_CTL_DIR_M2P |
@ -176,36 +194,18 @@ void spi_lld_init(void) {
#endif
#if GD32_SPI_USE_SPI2
spiObjectInit(&SPID2);
SPID2.spi = SPI2;
SPID2.dmarx = NULL;
SPID2.dmatx = NULL;
SPID2.rxdmamode = GD32_DMA_CTL_CHSEL(SPI2_RX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_SPI_SPI2_DMA_PRIORITY) |
GD32_DMA_CTL_DIR_P2M |
GD32_DMA_CTL_FTFIE |
GD32_DMA_CTL_ERRIE;
SPID2.txdmamode = GD32_DMA_CTL_CHSEL(SPI2_TX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_SPI_SPI2_DMA_PRIORITY) |
GD32_DMA_CTL_DIR_M2P |
GD32_DMA_CTL_ERRIE;
#endif
#if GD32_SPI_USE_SPI3
spiObjectInit(&SPID3);
SPID3.spi = SPI3;
SPID3.spi = SPI2;
SPID3.dmarx = NULL;
SPID3.dmatx = NULL;
SPID3.rxdmamode = GD32_DMA_CTL_CHSEL(SPI3_RX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_SPI_SPI3_DMA_PRIORITY) |
SPID3.rxdmamode = GD32_DMA_CTL_CHSEL(SPI2_RX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_SPI_SPI2_DMA_PRIORITY) |
GD32_DMA_CTL_DIR_P2M |
GD32_DMA_CTL_FTFIE |
GD32_DMA_CTL_ERRIE;
SPID3.txdmamode = GD32_DMA_CTL_CHSEL(SPI3_TX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_SPI_SPI3_DMA_PRIORITY) |
SPID3.txdmamode = GD32_DMA_CTL_CHSEL(SPI2_TX_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_SPI_SPI2_DMA_PRIORITY) |
GD32_DMA_CTL_DIR_M2P |
GD32_DMA_CTL_ERRIE;
@ -223,8 +223,23 @@ void spi_lld_start(SPIDriver *spip) {
/* If in stopped state then enables the SPI and DMA clocks.*/
if (spip->state == SPI_STOP) {
#if GD32_SPI_USE_SPI1
#if GD32_SPI_USE_SPI0
if (&SPID1 == spip) {
spip->dmarx = dmaStreamAllocI(GD32_SPI_SPI0_RX_DMA_STREAM,
GD32_SPI_SPI0_IRQ_PRIORITY,
(gd32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(GD32_SPI_SPI0_TX_DMA_STREAM,
GD32_SPI_SPI0_IRQ_PRIORITY,
(gd32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI0(true);
}
#endif
#if GD32_SPI_USE_SPI1
if (&SPID2 == spip) {
spip->dmarx = dmaStreamAllocI(GD32_SPI_SPI1_RX_DMA_STREAM,
GD32_SPI_SPI1_IRQ_PRIORITY,
(gd32_dmaisr_t)spi_lld_serve_rx_interrupt,
@ -239,7 +254,7 @@ void spi_lld_start(SPIDriver *spip) {
}
#endif
#if GD32_SPI_USE_SPI2
if (&SPID2 == spip) {
if (&SPID3 == spip) {
spip->dmarx = dmaStreamAllocI(GD32_SPI_SPI2_RX_DMA_STREAM,
GD32_SPI_SPI2_IRQ_PRIORITY,
(gd32_dmaisr_t)spi_lld_serve_rx_interrupt,
@ -252,21 +267,6 @@ void spi_lld_start(SPIDriver *spip) {
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI2(true);
}
#endif
#if GD32_SPI_USE_SPI3
if (&SPID3 == spip) {
spip->dmarx = dmaStreamAllocI(GD32_SPI_SPI3_RX_DMA_STREAM,
GD32_SPI_SPI3_IRQ_PRIORITY,
(gd32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(GD32_SPI_SPI3_TX_DMA_STREAM,
GD32_SPI_SPI3_IRQ_PRIORITY,
(gd32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI3(true);
}
#endif
/* DMA setup.*/
dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DATA);
@ -328,17 +328,17 @@ void spi_lld_stop(SPIDriver *spip) {
spip->dmarx = NULL;
spip->dmatx = NULL;
#if GD32_SPI_USE_SPI1
#if GD32_SPI_USE_SPI0
if (&SPID1 == spip)
rccDisableSPI0();
#endif
#if GD32_SPI_USE_SPI1
if (&SPID2 == spip)
rccDisableSPI1();
#endif
#if GD32_SPI_USE_SPI2
if (&SPID2 == spip)
rccDisableSPI2();
#endif
#if GD32_SPI_USE_SPI3
if (&SPID3 == spip)
rccDisableSPI3();
rccDisableSPI2();
#endif
}
}

66
os/hal/ports/GD/GD32VF103/SPI/hal_spi_lld.h
View File

@ -44,6 +44,15 @@
* @name Configuration options
* @{
*/
/**
* @brief SPI0 driver enable switch.
* @details If set to @p TRUE the support for SPI0 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_SPI_USE_SPI0) || defined(__DOXYGEN__)
#define GD32_SPI_USE_SPI0 FALSE
#endif
/**
* @brief SPI1 driver enable switch.
* @details If set to @p TRUE the support for SPI1 is included.
@ -63,12 +72,10 @@
#endif
/**
* @brief SPI3 driver enable switch.
* @details If set to @p TRUE the support for SPI3 is included.
* @note The default is @p FALSE.
* @brief SPI0 interrupt priority level setting.
*/
#if !defined(GD32_SPI_USE_SPI3) || defined(__DOXYGEN__)
#define GD32_SPI_USE_SPI3 FALSE
#if !defined(GD32_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI0_IRQ_PRIORITY 10
#endif
/**
@ -86,10 +93,13 @@
#endif
/**
* @brief SPI3 interrupt priority level setting.
* @brief SPI0 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA streams but
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(GD32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI3_IRQ_PRIORITY 10
#if !defined(GD32_SPI_SPI0_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI0_DMA_PRIORITY 1
#endif
/**
@ -112,16 +122,6 @@
#define GD32_SPI_SPI2_DMA_PRIORITY 1
#endif
/**
* @brief SPI3 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA streams but
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(GD32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI3_DMA_PRIORITY 1
#endif
/**
* @brief SPI DMA error hook.
*/
@ -134,6 +134,10 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if GD32_SPI_USE_SPI0 && !GD32_HAS_SPI0
#error "SPI0 not present in the selected device"
#endif
#if GD32_SPI_USE_SPI1 && !GD32_HAS_SPI1
#error "SPI1 not present in the selected device"
#endif
@ -142,12 +146,13 @@
#error "SPI2 not present in the selected device"
#endif
#if GD32_SPI_USE_SPI3 && !GD32_HAS_SPI3
#error "SPI3 not present in the selected device"
#if !GD32_SPI_USE_SPI0 && !GD32_SPI_USE_SPI1 && !GD32_SPI_USE_SPI2
#error "SPI driver activated but no SPI peripheral assigned"
#endif
#if !GD32_SPI_USE_SPI1 && !GD32_SPI_USE_SPI2 && !GD32_SPI_USE_SPI3
#error "SPI driver activated but no SPI peripheral assigned"
#if GD32_SPI_USE_SPI0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SPI_SPI0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI0"
#endif
#if GD32_SPI_USE_SPI1 && \
@ -160,9 +165,9 @@
#error "Invalid IRQ priority assigned to SPI2"
#endif
#if GD32_SPI_USE_SPI3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SPI_SPI3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI3"
#if GD32_SPI_USE_SPI0 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_SPI_SPI0_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI0"
#endif
#if GD32_SPI_USE_SPI1 && \
@ -175,11 +180,6 @@
#error "Invalid DMA priority assigned to SPI2"
#endif
#if GD32_SPI_USE_SPI3 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_SPI_SPI3_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI3"
#endif
#if !defined(GD32_DMA_REQUIRED)
#define GD32_DMA_REQUIRED
#endif
@ -224,15 +224,15 @@
/* External declarations. */
/*===========================================================================*/
#if GD32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI0 && !defined(__DOXYGEN__)
extern SPIDriver SPID1;
#endif
#if GD32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
extern SPIDriver SPID2;
#endif
#if GD32_SPI_USE_SPI3 && !defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
extern SPIDriver SPID3;
#endif

31
os/hal/ports/GD/GD32VF103/gd32_registry.h
View File

@ -200,29 +200,32 @@
/* SPI attributes.*/
#if GD32_HAS_SPI_0 || GD32_HAS_SPI_012
#define GD32_HAS_SPI1 TRUE
#define GD32_SPI1_SUPPORTS_I2S FALSE
#define GD32_SPI_SPI1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 1)
#define GD32_SPI_SPI1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 2)
#define GD32_HAS_SPI0 TRUE
#define GD32_SPI0_SUPPORTS_I2S FALSE
#define GD32_SPI_SPI0_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 1)
#define GD32_SPI_SPI0_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 2)
#else
#define GD32_HAS_SPI1 FALSE
#define GD32_HAS_SPI0 FALSE
#endif
#if GD32_HAS_SPI_012
#define GD32_HAS_SPI1 TRUE
#define GD32_SPI1_SUPPORTS_I2S TRUE
#define GD32_SPI1_I2S_FULLDUPLEX FALSE
#define GD32_SPI_SPI1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
#define GD32_SPI_SPI1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
#define GD32_I2S_SPI1_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
#define GD32_I2S_SPI1_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
#define GD32_HAS_SPI2 TRUE
#define GD32_SPI2_SUPPORTS_I2S TRUE
#define GD32_SPI2_I2S_FULLDUPLEX FALSE
#define GD32_SPI_SPI2_RX_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
#define GD32_SPI_SPI2_TX_DMA_STREAM GD32_DMA_STREAM_ID(0, 4)
#define GD32_HAS_SPI3 TRUE
#define GD32_SPI3_SUPPORTS_I2S TRUE
#define GD32_SPI3_I2S_FULLDUPLEX FALSE
#define GD32_SPI_SPI3_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 0)
#define GD32_SPI_SPI3_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 1)
#define GD32_SPI_SPI2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 0)
#define GD32_SPI_SPI2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 1)
#define GD32_I2S_SPI2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 0)
#define GD32_I2S_SPI2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 1)
#else
#define GD32_HAS_SPI1 FALSE
#define GD32_HAS_SPI2 FALSE
#define GD32_HAS_SPI3 FALSE
#endif
/* TIM attributes.*/

10
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -680,8 +680,8 @@ typedef struct
//#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
#define SPI1_BASE (APB1PERIPH_BASE + 0x00003800U)
#define SPI2_BASE (APB1PERIPH_BASE + 0x00003C00U)
#define USART1_BASE (APB1PERIPH_BASE + 0x00004400U)
#define USART2_BASE (APB1PERIPH_BASE + 0x00004800U)
#define UART3_BASE (APB1PERIPH_BASE + 0x00004C00U)
@ -703,7 +703,7 @@ typedef struct
#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
#define SPI0_BASE (APB2PERIPH_BASE + 0x00003000U)
#define USART0_BASE (APB2PERIPH_BASE + 0x00003800U)
#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
@ -768,8 +768,8 @@ typedef struct
#define RTC ((RTC_TypeDef *)RTC_BASE)
#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
#define SPI3 ((SPI_TypeDef *)SPI3_BASE)
#define USART1 ((USART_TypeDef *)USART1_BASE)
#define USART2 ((USART_TypeDef *)USART2_BASE)
#define UART3 ((USART_TypeDef *)UART3_BASE)
@ -793,7 +793,7 @@ typedef struct
#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
#define SPI0 ((SPI_TypeDef *)SPI0_BASE)
#define USART0 ((USART_TypeDef *)USART0_BASE)
#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
#define DMA0 ((DMA_TypeDef *)DMA0_BASE)