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renamed NRF51_* to NRF5_*

This commit is contained in:
Stephane D'Alu 2016-07-10 10:48:04 +02:00
parent ba393d3ae1
commit 5259158d17
37 changed files with 428 additions and 415 deletions
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12
demos/NRF51/OSHCHIP_V1.0/mcuconf.h
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@ -17,15 +17,15 @@
#ifndef _MCUCONF_H_
#define _MCUCONF_H_
/* Possible value for NRF51_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth */
#define NRF51_LFCLK_SOURCE 0
/* Possible value for NRF5_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth */
#define NRF5_LFCLK_SOURCE 0
/*
* HAL driver system settings.
*/
#define NRF51_SERIAL_USE_UART0 TRUE
#define NRF51_ST_USE_RTC0 TRUE
#define NRF51_ST_USE_RTC1 FALSE
#define NRF51_ST_USE_TIMER0 FALSE
#define NRF5_SERIAL_USE_UART0 TRUE
#define NRF5_ST_USE_RTC0 TRUE
#define NRF5_ST_USE_RTC1 FALSE
#define NRF5_ST_USE_TIMER0 FALSE
#endif /* _MCUCONF_H_ */

8
demos/NRF51/RT-WVSHARE_BLE400/mcuconf.h
View File

@ -20,9 +20,9 @@
/*
* HAL driver system settings.
*/
#define NRF51_SERIAL_USE_UART0 TRUE
#define NRF51_ST_USE_RTC0 TRUE
#define NRF51_ST_USE_RTC1 FALSE
#define NRF51_ST_USE_TIMER0 FALSE
#define NRF5_SERIAL_USE_UART0 TRUE
#define NRF5_ST_USE_RTC0 TRUE
#define NRF5_ST_USE_RTC1 FALSE
#define NRF5_ST_USE_TIMER0 FALSE
#endif /* _MCUCONF_H_ */

2
demos/NRF52/Classic/main.c
View File

@ -24,7 +24,7 @@ static SerialConfig serial_config = {
.speed = 115200,
.tx_pad = UART_TX,
.rx_pad = UART_RX,
#if NRF51_SERIAL_USE_HWFLOWCTRL == TRUE
#if NRF5_SERIAL_USE_HWFLOWCTRL == TRUE
.rts_pad = UART_RTS,
.cts_pad = UART_CTS,
#endif

4
os/hal/boards/NRF52-DK/board.h
View File

@ -22,8 +22,8 @@
#define BOARD_NAME "nRF52 DK"
/* Board oscillators-related settings. */
#define NRF52_XTAL_VALUE 64000000
#define NRF52_LFCLK_SOURCE 1
#define NRF5_XTAL_VALUE 32000000
#define NRF5_LFCLK_SOURCE 1
/*
* GPIO pins.

4
os/hal/ports/NRF5/LLD/hal_pal_lld.c
View File

@ -15,7 +15,7 @@
*/
/**
* @file pal_lld.c
* @file NRF5/LLD/hal_pal_lld.c
* @brief NRF5 PAL subsystem low level driver source.
*
* @addtogroup PAL
@ -46,7 +46,7 @@
void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
{
(void)port;
osalDbgAssert(pad <= 31, "pal_lld_setpadmode() - invalid pad");
osalDbgAssert(pad < PAL_IOPORTS_WIDTH, "pal_lld_setpadmode() - invalid pad");
switch (mode) {
case PAL_MODE_RESET:

4
os/hal/ports/NRF5/LLD/hal_pal_lld.h
View File

@ -15,7 +15,7 @@
*/
/**
* @file pal_lld.h
* @file NRF5/LLD/hal_pal_lld.h
* @brief NRF5 PAL subsystem low level driver header.
*
* @addtogroup PAL
@ -132,6 +132,8 @@ typedef NRF_GPIO_Type *ioportid_t;
#define IOPORT1 NRF_GPIO
#elif NRF_SERIES == 52
#define IOPORT1 NRF_P0
#else
#error "Unknown NRF_SERIES"
#endif
/*===========================================================================*/

56
os/hal/ports/NRF5/LLD/hal_serial_lld.c
View File

@ -15,8 +15,8 @@
*/
/**
* @file serial_lld.c
* @brief NRF51822 serial subsystem low level driver source.
* @file NRF5/LLD/hal_serial_lld.c
* @brief NRF5 serial subsystem low level driver source.
*
* @addtogroup SERIAL
* @{
@ -43,7 +43,7 @@
/*===========================================================================*/
/** @brief USART1 serial driver identifier.*/
#if (NRF51_SERIAL_USE_UART0 == TRUE) || defined(__DOXYGEN__)
#if (NRF5_SERIAL_USE_UART0 == TRUE) || defined(__DOXYGEN__)
SerialDriver SD1;
#endif
@ -56,11 +56,11 @@ SerialDriver SD1;
*/
static const SerialConfig default_config = {
.speed = 38400,
.tx_pad = NRF51_SERIAL_PAD_DISCONNECTED,
.rx_pad = NRF51_SERIAL_PAD_DISCONNECTED,
#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
.rts_pad = NRF51_SERIAL_PAD_DISCONNECTED,
.cts_pad = NRF51_SERIAL_PAD_DISCONNECTED,
.tx_pad = NRF5_SERIAL_PAD_DISCONNECTED,
.rx_pad = NRF5_SERIAL_PAD_DISCONNECTED,
#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)
.rts_pad = NRF5_SERIAL_PAD_DISCONNECTED,
.cts_pad = NRF5_SERIAL_PAD_DISCONNECTED,
#endif
};
@ -101,17 +101,17 @@ static void configure_uart(const SerialConfig *config)
};
/* Configure PINs mode */
if (config->tx_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
if (config->tx_pad != NRF5_SERIAL_PAD_DISCONNECTED) {
palSetPadMode(IOPORT1, config->tx_pad, PAL_MODE_OUTPUT_PUSHPULL);
}
if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
if (config->rx_pad != NRF5_SERIAL_PAD_DISCONNECTED) {
palSetPadMode(IOPORT1, config->rx_pad, PAL_MODE_INPUT);
}
#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
if (config->rts_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)
if (config->rts_pad != NRF5_SERIAL_PAD_DISCONNECTED) {
palSetPadMode(IOPORT1, config->rts_pad, PAL_MODE_OUTPUT_PUSHPULL);
}
if (config->cts_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
if (config->cts_pad != NRF5_SERIAL_PAD_DISCONNECTED) {
palSetPadMode(IOPORT1, config->cts_pad, PAL_MODE_INPUT);
}
#endif
@ -119,12 +119,12 @@ static void configure_uart(const SerialConfig *config)
/* Select PINs used by UART */
NRF_UART0->PSELTXD = config->tx_pad;
NRF_UART0->PSELRXD = config->rx_pad;
#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)
NRF_UART0->PSELRTS = config->rts_pad;
NRF_UART0->PSELCTS = config->cts_pad;
#else
NRF_UART0->PSELRTS = NRF51_SERIAL_PAD_DISCONNECTED;
NRF_UART0->PSELCTS = NRF51_SERIAL_PAD_DISCONNECTED;
NRF_UART0->PSELRTS = NRF5_SERIAL_PAD_DISCONNECTED;
NRF_UART0->PSELCTS = NRF5_SERIAL_PAD_DISCONNECTED;
#endif
/* Set baud rate */
@ -134,7 +134,7 @@ static void configure_uart(const SerialConfig *config)
NRF_UART0->CONFIG = (UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos);
/* Adjust flow control */
#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)
if ((config->rts_pad < TOTAL_GPIO_PADS) ||
(config->cts_pad < TOTAL_GPIO_PADS)) {
NRF_UART0->CONFIG |= UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos;
@ -152,7 +152,7 @@ static void configure_uart(const SerialConfig *config)
NRF_UART0->EVENTS_TXDRDY = 0;
(void)NRF_UART0->EVENTS_TXDRDY;
if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
if (config->rx_pad != NRF5_SERIAL_PAD_DISCONNECTED) {
while (NRF_UART0->EVENTS_RXDRDY != 0) {
(void)NRF_UART0->RXD;
}
@ -163,14 +163,14 @@ static void configure_uart(const SerialConfig *config)
/**
* @brief Driver output notification.
*/
#if NRF51_SERIAL_USE_UART0 || defined(__DOXYGEN__)
#if NRF5_SERIAL_USE_UART0 || defined(__DOXYGEN__)
static void notify1(io_queue_t *qp)
{
SerialDriver *sdp = &SD1;
(void)qp;
if (NRF_UART0->PSELTXD == NRF51_SERIAL_PAD_DISCONNECTED)
if (NRF_UART0->PSELTXD == NRF5_SERIAL_PAD_DISCONNECTED)
return;
if (!sdp->tx_busy) {
@ -193,7 +193,7 @@ static void notify1(io_queue_t *qp)
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_SERIAL_USE_UART0 || defined(__DOXYGEN__)
#if NRF5_SERIAL_USE_UART0 || defined(__DOXYGEN__)
OSAL_IRQ_HANDLER(Vector48) {
OSAL_IRQ_PROLOGUE();
@ -260,7 +260,7 @@ OSAL_IRQ_HANDLER(Vector48) {
*/
void sd_lld_init(void) {
#if NRF51_SERIAL_USE_UART0 == TRUE
#if NRF5_SERIAL_USE_UART0 == TRUE
sdObjectInit(&SD1, NULL, notify1);
#endif
}
@ -286,21 +286,21 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
if (sdp->state == SD_STOP) {
#if NRF51_SERIAL_USE_UART0 == TRUE
#if NRF5_SERIAL_USE_UART0 == TRUE
if (sdp == &SD1) {
configure_uart(config);
// Enable UART interrupt
NRF_UART0->INTENCLR = (uint32_t)-1;
NRF_UART0->INTENSET = UART_INTENSET_ERROR_Msk;
if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED)
if (config->rx_pad != NRF5_SERIAL_PAD_DISCONNECTED)
NRF_UART0->INTENSET |= UART_INTENSET_RXDRDY_Msk;
if (config->tx_pad != NRF51_SERIAL_PAD_DISCONNECTED)
if (config->tx_pad != NRF5_SERIAL_PAD_DISCONNECTED)
NRF_UART0->INTENSET |= UART_INTENSET_TXDRDY_Msk;
nvicEnableVector(UART0_IRQn, NRF51_SERIAL_UART0_PRIORITY);
nvicEnableVector(UART0_IRQn, NRF5_SERIAL_UART0_PRIORITY);
if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED)
if (config->rx_pad != NRF5_SERIAL_PAD_DISCONNECTED)
NRF_UART0->TASKS_STARTRX = 1;
}
#endif
@ -321,7 +321,7 @@ void sd_lld_stop(SerialDriver *sdp) {
if (sdp->state == SD_READY) {
#if NRF51_SERIAL_USE_UART0 == TRUE
#if NRF5_SERIAL_USE_UART0 == TRUE
if (&SD1 == sdp) {
nvicDisableVector(UART0_IRQn);
NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Disabled;

28
os/hal/ports/NRF5/LLD/hal_serial_lld.h
View File

@ -15,8 +15,8 @@
*/
/**
* @file serial_lld.h
* @brief NRF51822 serial subsystem low level driver header.
* @file NRF5/LLD/hal_serial_lld.h
* @brief NRF5 serial subsystem low level driver header.
*
* @addtogroup SERIAL
* @{
@ -45,8 +45,8 @@
* is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_SERIAL_USE_HWFLOWCTRL) || defined(__DOXYGEN__)
#define NRF51_SERIAL_USE_HWFLOWCTRL FALSE
#if !defined(NRF5_SERIAL_USE_HWFLOWCTRL) || defined(__DOXYGEN__)
#define NRF5_SERIAL_USE_HWFLOWCTRL FALSE
#endif
/**
@ -54,20 +54,20 @@
* @details If set to @p TRUE the support for SD1 is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_SERIAL_USE_UART0) || defined(__DOXYGEN__)
#define NRF51_SERIAL_USE_UART0 FALSE
#if !defined(NRF5_SERIAL_USE_UART0) || defined(__DOXYGEN__)
#define NRF5_SERIAL_USE_UART0 FALSE
#endif
/**
* @brief UART0 interrupt priority level setting.
*/
#if !defined(NRF51_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_SERIAL_UART0_PRIORITY 3
#if !defined(NRF5_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_SERIAL_UART0_PRIORITY 3
#endif
/* Value indicating that no pad is connected to this UART register. */
#define NRF51_SERIAL_PAD_DISCONNECTED 0xFFFFFFFFU
#define NRF51_SERIAL_INVALID_BAUDRATE 0xFFFFFFFFU
#define NRF5_SERIAL_PAD_DISCONNECTED 0xFFFFFFFFU
#define NRF5_SERIAL_INVALID_BAUDRATE 0xFFFFFFFFU
/** @} */
@ -75,8 +75,8 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if NRF51_SERIAL_USE_UART0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SERIAL_UART0_PRIORITY)
#if NRF5_SERIAL_USE_UART0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_SERIAL_UART0_PRIORITY)
#error "Invalid IRQ priority assigned to UART0"
#endif
@ -100,7 +100,7 @@ typedef struct {
/* End of the mandatory fields.*/
uint32_t tx_pad;
uint32_t rx_pad;
#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)
uint32_t rts_pad;
uint32_t cts_pad;
#endif
@ -134,7 +134,7 @@ typedef struct {
/* External declarations. */
/*===========================================================================*/
#if (NRF51_SERIAL_USE_UART0 == TRUE) && !defined(__DOXYGEN__)
#if (NRF5_SERIAL_USE_UART0 == TRUE) && !defined(__DOXYGEN__)
extern SerialDriver SD1;
#endif

62
os/hal/ports/NRF5/LLD/hal_st_lld.c
View File

@ -16,8 +16,8 @@
*/
/**
* @file st_lld.c
* @brief NRF51822 ST subsystem low level driver source.
* @file NRF5/LLD/hal_st_lld.c
* @brief NRF5 ST subsystem low level driver source.
*
* @addtogroup ST
* @{
@ -52,11 +52,11 @@
/*===========================================================================*/
#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
/**
* @brief System Timer vector (RTC0)
* @details This interrupt is used for system tick in periodic mode
* if selected with NRF51_ST_USE_RTC0
* if selected with NRF5_ST_USE_RTC0
*
* @isr
*/
@ -75,11 +75,11 @@ OSAL_IRQ_HANDLER(Vector6C) {
}
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
/**
* @brief System Timer vector (RTC1)
* @details This interrupt is used for system tick in periodic mode
* if selected with NRF51_ST_USE_RTC1
* if selected with NRF5_ST_USE_RTC1
*
* @isr
*/
@ -98,11 +98,11 @@ OSAL_IRQ_HANDLER(Vector84) {
}
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
/**
* @brief System Timer vector. (TIMER0)
* @details This interrupt is used for system tick in periodic mode
* if selected with NRF51_ST_USE_TIMER0
* if selected with NRF5_ST_USE_TIMER0
*
* @isr
*/
@ -126,11 +126,11 @@ OSAL_IRQ_HANDLER(Vector60) {
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
/**
* @brief System Timer vector (RTC0)
* @details This interrupt is used for freerunning mode (tick-less)
* if selected with NRF51_ST_USE_RTC0
* if selected with NRF5_ST_USE_RTC0
*
* @isr
*/
@ -159,11 +159,11 @@ OSAL_IRQ_HANDLER(Vector6C) {
}
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
/**
* @brief System Timer vector (RTC1)
* @details This interrupt is used for freerunning mode (tick-less)
* if selected with NRF51_ST_USE_RTC1
* if selected with NRF5_ST_USE_RTC1
*
* @isr
*/
@ -205,10 +205,10 @@ OSAL_IRQ_HANDLER(Vector84) {
void st_lld_init(void) {
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
/* Using RTC with prescaler */
NRF_RTC0->TASKS_STOP = 1;
NRF_RTC0->PRESCALER = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC0->PRESCALER = (NRF5_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC0->EVTENCLR = RTC_EVTENSET_COMPARE0_Msk;
NRF_RTC0->EVENTS_COMPARE[0] = 0;
NRF_RTC0->INTENSET = RTC_INTENSET_COMPARE0_Msk;
@ -221,14 +221,14 @@ void st_lld_init(void) {
NRF_RTC0->TASKS_CLEAR = 1;
/* Start timer */
nvicEnableVector(RTC0_IRQn, NRF51_ST_PRIORITY);
nvicEnableVector(RTC0_IRQn, NRF5_ST_PRIORITY);
NRF_RTC0->TASKS_START = 1;
#endif /* NRF51_ST_USE_RTC0 == TRUE */
#endif /* NRF5_ST_USE_RTC0 == TRUE */
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
/* Using RTC with prescaler */
NRF_RTC1->TASKS_STOP = 1;
NRF_RTC1->PRESCALER = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC1->PRESCALER = (NRF5_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC1->EVTENCLR = RTC_EVTENSET_COMPARE0_Msk;
NRF_RTC1->EVENTS_COMPARE[0] = 0;
NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE0_Msk;
@ -241,37 +241,37 @@ void st_lld_init(void) {
NRF_RTC1->TASKS_CLEAR = 1;
/* Start timer */
nvicEnableVector(RTC1_IRQn, NRF51_ST_PRIORITY);
nvicEnableVector(RTC1_IRQn, NRF5_ST_PRIORITY);
NRF_RTC1->TASKS_START = 1;
#endif /* NRF51_ST_USE_RTC1 == TRUE */
#endif /* NRF5_ST_USE_RTC1 == TRUE */
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
/* Using RTC with prescaler */
NRF_RTC0->TASKS_STOP = 1;
NRF_RTC0->PRESCALER = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC0->PRESCALER = (NRF5_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC0->INTENSET = RTC_INTENSET_TICK_Msk;
/* Start timer */
nvicEnableVector(RTC0_IRQn, NRF51_ST_PRIORITY);
nvicEnableVector(RTC0_IRQn, NRF5_ST_PRIORITY);
NRF_RTC0->TASKS_START = 1;
#endif /* NRF51_ST_USE_RTC0 == TRUE */
#endif /* NRF5_ST_USE_RTC0 == TRUE */
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
/* Using RTC with prescaler */
NRF_RTC1->TASKS_STOP = 1;
NRF_RTC1->PRESCALER = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC1->PRESCALER = (NRF5_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC1->INTENSET = RTC_INTENSET_TICK_Msk;
/* Start timer */
nvicEnableVector(RTC1_IRQn, NRF51_ST_PRIORITY);
nvicEnableVector(RTC1_IRQn, NRF5_ST_PRIORITY);
NRF_RTC1->TASKS_START = 1;
#endif /* NRF51_ST_USE_RTC1 == TRUE */
#endif /* NRF5_ST_USE_RTC1 == TRUE */
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
NRF_TIMER0->TASKS_CLEAR = 1;
/*
@ -290,9 +290,9 @@ void st_lld_init(void) {
NRF_TIMER0->INTENSET = TIMER_INTENSET_COMPARE0_Msk;
/* Start timer */
nvicEnableVector(TIMER0_IRQn, NRF51_ST_PRIORITY);
nvicEnableVector(TIMER0_IRQn, NRF5_ST_PRIORITY);
NRF_TIMER0->TASKS_START = 1;
#endif /* NRF51_ST_USE_TIMER0 == TRUE */
#endif /* NRF5_ST_USE_TIMER0 == TRUE */
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
}

80
os/hal/ports/NRF5/LLD/hal_st_lld.h
View File

@ -40,40 +40,40 @@
/**
* @brief Use RTC0 to generates system ticks
*/
#if !defined(NRF51_ST_USE_RTC0) || defined(__DOXYGEN__)
#if !defined(NRF5_ST_USE_RTC0) || defined(__DOXYGEN__)
#if !defined(SOFTDEVICE_PRESENT)
#define NRF51_ST_USE_RTC0 TRUE
#define NRF5_ST_USE_RTC0 TRUE
#else
#define NRF51_ST_USE_RTC0 FALSE
#define NRF5_ST_USE_RTC0 FALSE
#endif
#endif
/**
* @brief Use RTC1 to generates system ticks
*/
#if !defined(NRF51_ST_USE_RTC1) || defined(__DOXYGEN__)
#if !defined(NRF5_ST_USE_RTC1) || defined(__DOXYGEN__)
#if !defined(SOFTDEVICE_PRESENT)
#define NRF51_ST_USE_RTC1 FALSE
#define NRF5_ST_USE_RTC1 FALSE
#else
#define NRF51_ST_USE_RTC1 TRUE
#define NRF5_ST_USE_RTC1 TRUE
#endif
#endif
/**
* @brief Use TIMER0 to generates system ticks
*/
#if !defined(NRF51_ST_USE_TIMER0) || defined(__DOXYGEN__)
#define NRF51_ST_USE_TIMER0 FALSE
#if !defined(NRF5_ST_USE_TIMER0) || defined(__DOXYGEN__)
#define NRF5_ST_USE_TIMER0 FALSE
#endif
/**
* @brief ST interrupt priority level setting.
*/
#if !defined(NRF51_ST_PRIORITY) || defined(__DOXYGEN__)
#if !defined(NRF5_ST_PRIORITY) || defined(__DOXYGEN__)
#if !defined(SOFTDEVICE_PRESENT)
#define NRF51_ST_PRIORITY CORTEX_MAX_KERNEL_PRIORITY
#define NRF5_ST_PRIORITY CORTEX_MAX_KERNEL_PRIORITY
#else
#define NRF51_ST_PRIORITY 1
#define NRF5_ST_PRIORITY 1
#endif
#endif
@ -82,32 +82,32 @@
/*===========================================================================*/
#if OSAL_ST_MODE != OSAL_ST_MODE_NONE
#if (NRF51_ST_USE_TIMER0 == TRUE) && (NRF51_GPT_USE_TIMER0 == TRUE)
#if (NRF5_ST_USE_TIMER0 == TRUE) && (NRF5_GPT_USE_TIMER0 == TRUE)
#error "TIMER0 already used by GPT driver"
#endif
#if (NRF51_ST_USE_RTC0 == FALSE) && \
(NRF51_ST_USE_RTC1 == FALSE) && \
(NRF51_ST_USE_TIMER0 == FALSE)
#if (NRF5_ST_USE_RTC0 == FALSE) && \
(NRF5_ST_USE_RTC1 == FALSE) && \
(NRF5_ST_USE_TIMER0 == FALSE)
#error "One clock source is needed, enable one (RTC0, RTC1, or TIMER0)"
#endif
#if ((NRF51_ST_USE_RTC0 == TRUE ? 1 : 0) + \
(NRF51_ST_USE_RTC1 == TRUE ? 1 : 0) + \
(NRF51_ST_USE_TIMER0 == TRUE ? 1 : 0)) > 1
#if ((NRF5_ST_USE_RTC0 == TRUE ? 1 : 0) + \
(NRF5_ST_USE_RTC1 == TRUE ? 1 : 0) + \
(NRF5_ST_USE_TIMER0 == TRUE ? 1 : 0)) > 1
#error "Only one clock source can be used (RTC0, RTC1, or TIMER0)"
#endif
#if defined(SOFTDEVICE_PRESENT)
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
#error "RTC0 cannot be used for system ticks when SOFTDEVICE present"
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
#error "TIMER0 cannot be used for system ticks when SOFTDEVICE present"
#endif
#if NRF51_ST_PRIORITY != 1
#if NRF5_ST_PRIORITY != 1
#error "ST priority must be 1 when SOFTDEVICE present"
#endif
@ -118,12 +118,12 @@
#if defined(CH_CFG_ST_TIMEDELTA) && (CH_CFG_ST_TIMEDELTA < 5)
#error "CH_CFG_ST_TIMEDELTA is too low"
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
#error "Freeruning (tick-less) mode not supported with TIMER, use RTC"
#endif
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
#if !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_ST_PRIORITY)
#if !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_ST_PRIORITY)
#error "Invalid IRQ priority assigned to ST driver"
#endif
@ -159,13 +159,13 @@ extern "C" {
* @notapi
*/
static inline systime_t st_lld_get_counter(void) {
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
return (systime_t)NRF_RTC0->COUNTER;
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
return (systime_t)NRF_RTC1->COUNTER;
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
return (systime_t)0;
#endif
}
@ -180,17 +180,17 @@ static inline systime_t st_lld_get_counter(void) {
* @notapi
*/
static inline void st_lld_start_alarm(systime_t abstime) {
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
NRF_RTC0->CC[0] = abstime;
NRF_RTC0->EVENTS_COMPARE[0] = 0;
NRF_RTC0->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
NRF_RTC1->CC[0] = abstime;
NRF_RTC1->EVENTS_COMPARE[0] = 0;
NRF_RTC1->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
(void)abstime;
#endif
}
@ -201,11 +201,11 @@ static inline void st_lld_start_alarm(systime_t abstime) {
* @notapi
*/
static inline void st_lld_stop_alarm(void) {
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
NRF_RTC0->EVTENCLR = RTC_EVTENCLR_COMPARE0_Msk;
NRF_RTC0->EVENTS_COMPARE[0] = 0;
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
NRF_RTC1->EVTENCLR = RTC_EVTENCLR_COMPARE0_Msk;
NRF_RTC1->EVENTS_COMPARE[0] = 0;
#endif
@ -219,13 +219,13 @@ static inline void st_lld_stop_alarm(void) {
* @notapi
*/
static inline void st_lld_set_alarm(systime_t abstime) {
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
NRF_RTC0->CC[0] = abstime;
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
NRF_RTC1->CC[0] = abstime;
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
(void)abstime;
#endif
}
@ -238,13 +238,13 @@ static inline void st_lld_set_alarm(systime_t abstime) {
* @notapi
*/
static inline systime_t st_lld_get_alarm(void) {
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
return (systime_t)NRF_RTC0->CC[0];
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
return (systime_t)NRF_RTC1->CC[0];
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
return (systime_t)0;
#endif
}
@ -259,13 +259,13 @@ static inline systime_t st_lld_get_alarm(void) {
* @notapi
*/
static inline bool st_lld_is_alarm_active(void) {
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
return NRF_RTC0->EVTEN & RTC_EVTEN_COMPARE0_Msk;
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
return NRF_RTC1->EVTEN & RTC_EVTEN_COMPARE0_Msk;
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
return false;
#endif
}

14
os/hal/ports/NRF5/NRF51822/hal_adc_lld.c
View File

@ -36,7 +36,7 @@
/*===========================================================================*/
/** @brief ADC1 driver identifier.*/
#if NRF51_ADC_USE_ADC1 || defined(__DOXYGEN__)
#if NRF5_ADC_USE_ADC1 || defined(__DOXYGEN__)
ADCDriver ADCD1;
#endif
@ -68,7 +68,7 @@ static void adc_lld_config_next_channel(ADCDriver *adcp, uint32_t config) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_ADC_USE_ADC1 || defined(__DOXYGEN__)
#if NRF5_ADC_USE_ADC1 || defined(__DOXYGEN__)
/**
* @brief ADC interrupt handler.
*
@ -130,7 +130,7 @@ OSAL_IRQ_HANDLER(Vector5C) {
*/
void adc_lld_init(void) {
#if NRF51_ADC_USE_ADC1
#if NRF5_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = NRF_ADC;
@ -148,13 +148,13 @@ void adc_lld_start(ADCDriver *adcp) {
/* If in stopped state then configures and enables the ADC. */
if (adcp->state == ADC_STOP) {
#if NRF51_ADC_USE_ADC1
#if NRF5_ADC_USE_ADC1
if (&ADCD1 == adcp) {
adcp->adc->INTENSET = ADC_INTENSET_END_Enabled << ADC_INTENSET_END_Pos;
nvicEnableVector(ADC_IRQn, NRF51_ADC_IRQ_PRIORITY);
nvicEnableVector(ADC_IRQn, NRF5_ADC_IRQ_PRIORITY);
}
#endif /* NRF51_ADC_USE_ADC1 */
#endif /* NRF5_ADC_USE_ADC1 */
}
}
@ -170,7 +170,7 @@ void adc_lld_stop(ADCDriver *adcp) {
/* If in ready state then disables the ADC clock and analog part.*/
if (adcp->state == ADC_READY) {
#if NRF51_ADC_USE_ADC1
#if NRF5_ADC_USE_ADC1
if (&ADCD1 == adcp) {
nvicDisableVector(ADC_IRQn);

16
os/hal/ports/NRF5/NRF51822/hal_adc_lld.h
View File

@ -44,15 +44,15 @@
* @details If set to @p TRUE the support for ADC1 is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_ADC_USE_ADC1) || defined(__DOXYGEN__)
#define NRF51_ADC_USE_ADC1 FALSE
#if !defined(NRF5_ADC_USE_ADC1) || defined(__DOXYGEN__)
#define NRF5_ADC_USE_ADC1 FALSE
#endif
/**
* @brief ADC interrupt priority level setting.
*/
#if !defined(NRF51_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_ADC_IRQ_PRIORITY 2
#if !defined(NRF5_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_ADC_IRQ_PRIORITY 2
#endif
/** @} */
@ -61,12 +61,12 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !NRF51_ADC_USE_ADC1
#if !NRF5_ADC_USE_ADC1
#error "ADC driver activated but no ADC peripheral assigned"
#endif
#if NRF51_ADC_USE_ADC1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_ADC_IRQ_PRIORITY)
#if NRF5_ADC_USE_ADC1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_ADC_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to ADC1"
#endif
@ -206,7 +206,7 @@ struct ADCDriver {
/* External declarations. */
/*===========================================================================*/
#if NRF51_ADC_USE_ADC1 && !defined(__DOXYGEN__)
#if NRF5_ADC_USE_ADC1 && !defined(__DOXYGEN__)
extern ADCDriver ADCD1;
#endif

2
os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c
View File

@ -92,7 +92,7 @@ OSAL_IRQ_HANDLER(Vector58) {
*/
void ext_lld_exti_irq_enable(void) {
nvicEnableVector(GPIOTE_IRQn, NRF51_EXT_GPIOTE_IRQ_PRIORITY);
nvicEnableVector(GPIOTE_IRQn, NRF5_EXT_GPIOTE_IRQ_PRIORITY);
}
/**

4
os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.h
View File

@ -42,8 +42,8 @@
/**
* @brief GPIOTE interrupt priority level setting.
*/
#if !defined(NRF51_EXT_GPIOTE_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_EXT_GPIOTE_IRQ_PRIORITY 3
#if !defined(NRF5_EXT_GPIOTE_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_EXT_GPIOTE_IRQ_PRIORITY 3
#endif
/** @} */

72
os/hal/ports/NRF5/NRF51822/hal_gpt_lld.c
View File

@ -30,8 +30,8 @@
/* Driver local definitions. */
/*===========================================================================*/
#define NRF51_TIMER_PRESCALER_NUM 10
#define NRF51_TIMER_COMPARE_NUM 4
#define NRF5_TIMER_PRESCALER_NUM 10
#define NRF5_TIMER_COMPARE_NUM 4
/*===========================================================================*/
/* Driver exported variables. */
@ -41,7 +41,7 @@
* @brief GPTD1 driver identifier.
* @note The driver GPTD1 allocates the complex timer TIM1 when enabled.
*/
#if NRF51_GPT_USE_TIMER0 || defined(__DOXYGEN__)
#if NRF5_GPT_USE_TIMER0 || defined(__DOXYGEN__)
GPTDriver GPTD1;
#endif
@ -49,7 +49,7 @@ GPTDriver GPTD1;
* @brief GPTD2 driver identifier.
* @note The driver GPTD2 allocates the timer TIM2 when enabled.
*/
#if NRF51_GPT_USE_TIMER1 || defined(__DOXYGEN__)
#if NRF5_GPT_USE_TIMER1 || defined(__DOXYGEN__)
GPTDriver GPTD2;
#endif
@ -57,7 +57,7 @@ GPTDriver GPTD2;
* @brief GPTD3 driver identifier.
* @note The driver GPTD3 allocates the timer TIM3 when enabled.
*/
#if NRF51_GPT_USE_TIMER2 || defined(__DOXYGEN__)
#if NRF5_GPT_USE_TIMER2 || defined(__DOXYGEN__)
GPTDriver GPTD3;
#endif
@ -73,19 +73,19 @@ static uint8_t prescaler(uint16_t freq)
{
uint8_t i;
static const gptfreq_t frequencies[] = {
NRF51_GPT_FREQ_16MHZ,
NRF51_GPT_FREQ_8MHZ,
NRF51_GPT_FREQ_4MHZ,
NRF51_GPT_FREQ_2MHZ,
NRF51_GPT_FREQ_1MHZ,
NRF51_GPT_FREQ_500KHZ,
NRF51_GPT_FREQ_250KHZ,
NRF51_GPT_FREQ_125KHZ,
NRF51_GPT_FREQ_62500HZ,
NRF51_GPT_FREQ_31250HZ,
NRF5_GPT_FREQ_16MHZ,
NRF5_GPT_FREQ_8MHZ,
NRF5_GPT_FREQ_4MHZ,
NRF5_GPT_FREQ_2MHZ,
NRF5_GPT_FREQ_1MHZ,
NRF5_GPT_FREQ_500KHZ,
NRF5_GPT_FREQ_250KHZ,
NRF5_GPT_FREQ_125KHZ,
NRF5_GPT_FREQ_62500HZ,
NRF5_GPT_FREQ_31250HZ,
};
for (i = 0; i < NRF51_TIMER_PRESCALER_NUM; i++)
for (i = 0; i < NRF5_TIMER_PRESCALER_NUM; i++)
if (freq == frequencies[i])
return i;
@ -111,7 +111,7 @@ static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_GPT_USE_TIMER0
#if NRF5_GPT_USE_TIMER0
/**
* @brief TIMER0 interrupt handler.
*
@ -125,9 +125,9 @@ OSAL_IRQ_HANDLER(Vector60) {
OSAL_IRQ_EPILOGUE();
}
#endif /* NRF51_GPT_USE_TIMER0 */
#endif /* NRF5_GPT_USE_TIMER0 */
#if NRF51_GPT_USE_TIMER1
#if NRF5_GPT_USE_TIMER1
/**
* @brief TIMER1 interrupt handler.
*
@ -141,9 +141,9 @@ OSAL_IRQ_HANDLER(Vector64) {
OSAL_IRQ_EPILOGUE();
}
#endif /* NRF51_GPT_USE_TIMER1 */
#endif /* NRF5_GPT_USE_TIMER1 */
#if NRF51_GPT_USE_TIMER2
#if NRF5_GPT_USE_TIMER2
/**
* @brief TIMER2 interrupt handler.
*
@ -157,7 +157,7 @@ OSAL_IRQ_HANDLER(Vector68) {
OSAL_IRQ_EPILOGUE();
}
#endif /* NRF51_GPT_USE_TIMER2 */
#endif /* NRF5_GPT_USE_TIMER2 */
/*===========================================================================*/
/* Driver exported functions. */
@ -170,19 +170,19 @@ OSAL_IRQ_HANDLER(Vector68) {
*/
void gpt_lld_init(void) {
#if NRF51_GPT_USE_TIMER0
#if NRF5_GPT_USE_TIMER0
/* Driver initialization.*/
GPTD1.tim = NRF_TIMER0;
gptObjectInit(&GPTD1);
#endif
#if NRF51_GPT_USE_TIMER1
#if NRF5_GPT_USE_TIMER1
/* Driver initialization.*/
GPTD2.tim = NRF_TIMER1;
gptObjectInit(&GPTD2);
#endif
#if NRF51_GPT_USE_TIMER2
#if NRF5_GPT_USE_TIMER2
/* Driver initialization.*/
GPTD3.tim = NRF_TIMER2;
gptObjectInit(&GPTD3);
@ -201,21 +201,21 @@ void gpt_lld_start(GPTDriver *gptp) {
NRF_TIMER_Type *tim = gptp->tim;
if (gptp->state == GPT_STOP) {
osalDbgAssert(gptp->cc_int < NRF51_TIMER_COMPARE_NUM,
osalDbgAssert(gptp->cc_int < NRF5_TIMER_COMPARE_NUM,
"invalid capture/compare index");
tim->INTENSET = TIMER_INTENSET_COMPARE0_Msk << gptp->cc_int;
#if NRF51_GPT_USE_TIMER0
#if NRF5_GPT_USE_TIMER0
if (&GPTD1 == gptp)
nvicEnableVector(TIMER0_IRQn, NRF51_GPT_TIMER0_IRQ_PRIORITY);
nvicEnableVector(TIMER0_IRQn, NRF5_GPT_TIMER0_IRQ_PRIORITY);
#endif
#if NRF51_GPT_USE_TIMER1
#if NRF5_GPT_USE_TIMER1
if (&GPTD2 == gptp)
nvicEnableVector(TIMER1_IRQn, NRF51_GPT_TIMER1_IRQ_PRIORITY);
nvicEnableVector(TIMER1_IRQn, NRF5_GPT_TIMER1_IRQ_PRIORITY);
#endif
#if NRF51_GPT_USE_TIMER2
#if NRF5_GPT_USE_TIMER2
if (&GPTD3 == gptp)
nvicEnableVector(TIMER2_IRQn, NRF51_GPT_TIMER2_IRQ_PRIORITY);
nvicEnableVector(TIMER2_IRQn, NRF5_GPT_TIMER2_IRQ_PRIORITY);
#endif
}
@ -235,7 +235,7 @@ void gpt_lld_start(GPTDriver *gptp) {
tim->BITMODE = TIMER_BITMODE_BITMODE_16Bit << TIMER_BITMODE_BITMODE_Pos;
break;
#if NRF51_GPT_USE_TIMER0
#if NRF5_GPT_USE_TIMER0
case 24:
tim->BITMODE = TIMER_BITMODE_BITMODE_24Bit << TIMER_BITMODE_BITMODE_Pos;
break;
@ -263,15 +263,15 @@ void gpt_lld_stop(GPTDriver *gptp) {
if (gptp->state == GPT_READY) {
gptp->tim->TASKS_SHUTDOWN = 1;
#if NRF51_GPT_USE_TIMER0
#if NRF5_GPT_USE_TIMER0
if (&GPTD1 == gptp)
nvicDisableVector(TIMER0_IRQn);
#endif
#if NRF51_GPT_USE_TIMER1
#if NRF5_GPT_USE_TIMER1
if (&GPTD2 == gptp)
nvicDisableVector(TIMER1_IRQn);
#endif
#if NRF51_GPT_USE_TIMER2
#if NRF5_GPT_USE_TIMER2
if (&GPTD3 == gptp)
nvicDisableVector(TIMER2_IRQn);
#endif

66
os/hal/ports/NRF5/NRF51822/hal_gpt_lld.h
View File

@ -44,8 +44,8 @@
* @details If set to @p TRUE the support for GPTD1 is included.
* @note The default is @p TRUE.
*/
#if !defined(NRF51_GPT_USE_TIMER0) || defined(__DOXYGEN__)
#define NRF51_GPT_USE_TIMER0 FALSE
#if !defined(NRF5_GPT_USE_TIMER0) || defined(__DOXYGEN__)
#define NRF5_GPT_USE_TIMER0 FALSE
#endif
/**
@ -53,8 +53,8 @@
* @details If set to @p TRUE the support for GPTD2 is included.
* @note The default is @p TRUE.
*/
#if !defined(NRF51_GPT_USE_TIMER1) || defined(__DOXYGEN__)
#define NRF51_GPT_USE_TIMER1 FALSE
#if !defined(NRF5_GPT_USE_TIMER1) || defined(__DOXYGEN__)
#define NRF5_GPT_USE_TIMER1 FALSE
#endif
/**
@ -62,29 +62,29 @@
* @details If set to @p TRUE the support for GPTD3 is included.
* @note The default is @p TRUE.
*/
#if !defined(NRF51_GPT_USE_TIMER2) || defined(__DOXYGEN__)
#define NRF51_GPT_USE_TIMER2 FALSE
#if !defined(NRF5_GPT_USE_TIMER2) || defined(__DOXYGEN__)
#define NRF5_GPT_USE_TIMER2 FALSE
#endif
/**
* @brief GPTD1 interrupt priority level setting.
*/
#if !defined(NRF51_GPT_TIMER0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_GPT_TIMER0_IRQ_PRIORITY 3
#if !defined(NRF5_GPT_TIMER0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_GPT_TIMER0_IRQ_PRIORITY 3
#endif
/**
* @brief GPTD2 interrupt priority level setting.
*/
#if !defined(NRF51_GPT_TIMER1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_GPT_TIMER1_IRQ_PRIORITY 3
#if !defined(NRF5_GPT_TIMER1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_GPT_TIMER1_IRQ_PRIORITY 3
#endif
/**
* @brief GPTD3 interrupt priority level setting.
*/
#if !defined(NRF51_GPT_TIMER2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_GPT_TIMER2_IRQ_PRIORITY 3
#if !defined(NRF5_GPT_TIMER2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_GPT_TIMER2_IRQ_PRIORITY 3
#endif
/** @} */
@ -92,23 +92,23 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !NRF51_GPT_USE_TIMER0 && !NRF51_GPT_USE_TIMER1 && \
!NRF51_GPT_USE_TIMER2
#if !NRF5_GPT_USE_TIMER0 && !NRF5_GPT_USE_TIMER1 && \
!NRF5_GPT_USE_TIMER2
#error "GPT driver activated but no TIMER peripheral assigned"
#endif
#if NRF51_GPT_USE_TIMER0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER0_IRQ_PRIORITY)
#if NRF5_GPT_USE_TIMER0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_GPT_TIMER0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER0"
#endif
#if NRF51_GPT_USE_TIMER1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER1_IRQ_PRIORITY)
#if NRF5_GPT_USE_TIMER1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_GPT_TIMER1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER1"
#endif
#if NRF51_GPT_USE_TIMER2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER2_IRQ_PRIORITY)
#if NRF5_GPT_USE_TIMER2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_GPT_TIMER2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER2"
#endif
@ -120,16 +120,16 @@
* @brief GPT frequency type.
*/
typedef enum {
NRF51_GPT_FREQ_31250HZ = 31250,
NRF51_GPT_FREQ_62500HZ = 62500,
NRF51_GPT_FREQ_125KHZ = 125000,
NRF51_GPT_FREQ_250KHZ = 250000,
NRF51_GPT_FREQ_500KHZ = 500000,
NRF51_GPT_FREQ_1MHZ = 1000000,
NRF51_GPT_FREQ_2MHZ = 2000000,
NRF51_GPT_FREQ_4MHZ = 4000000,
NRF51_GPT_FREQ_8MHZ = 8000000,
NRF51_GPT_FREQ_16MHZ = 16000000,
NRF5_GPT_FREQ_31250HZ = 31250,
NRF5_GPT_FREQ_62500HZ = 62500,
NRF5_GPT_FREQ_125KHZ = 125000,
NRF5_GPT_FREQ_250KHZ = 250000,
NRF5_GPT_FREQ_500KHZ = 500000,
NRF5_GPT_FREQ_1MHZ = 1000000,
NRF5_GPT_FREQ_2MHZ = 2000000,
NRF5_GPT_FREQ_4MHZ = 4000000,
NRF5_GPT_FREQ_8MHZ = 8000000,
NRF5_GPT_FREQ_16MHZ = 16000000,
} gptfreq_t;
/**
@ -231,15 +231,15 @@ struct GPTDriver {
/* External declarations. */
/*===========================================================================*/
#if NRF51_GPT_USE_TIMER0 && !defined(__DOXYGEN__)
#if NRF5_GPT_USE_TIMER0 && !defined(__DOXYGEN__)
extern GPTDriver GPTD1;
#endif
#if NRF51_GPT_USE_TIMER1 && !defined(__DOXYGEN__)
#if NRF5_GPT_USE_TIMER1 && !defined(__DOXYGEN__)
extern GPTDriver GPTD2;
#endif
#if NRF51_GPT_USE_TIMER2 && !defined(__DOXYGEN__)
#if NRF5_GPT_USE_TIMER2 && !defined(__DOXYGEN__)
extern GPTDriver GPTD3;
#endif

20
os/hal/ports/NRF5/NRF51822/hal_i2c_lld.c
View File

@ -52,12 +52,12 @@
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos))
#if NRF51_I2C_USE_I2C0
#if NRF5_I2C_USE_I2C0
#define I2C_IRQ_NUM SPI0_TWI0_IRQn
#define I2C_IRQ_PRI NRF51_I2C_I2C0_IRQ_PRIORITY
#elif NRF51_I2C_USE_I2C1
#define I2C_IRQ_PRI NRF5_I2C_I2C0_IRQ_PRIORITY
#elif NRF5_I2C_USE_I2C1
#define I2C_IRQ_NUM SPI1_TWI1_IRQn
#define I2C_IRQ_PRI NRF51_I2C_I2C1_IRQ_PRIORITY
#define I2C_IRQ_PRI NRF5_I2C_I2C1_IRQ_PRIORITY
#endif
/*===========================================================================*/
@ -67,14 +67,14 @@
/**
* @brief I2C0 driver identifier.
*/
#if NRF51_I2C_USE_I2C0 || defined(__DOXYGEN__)
#if NRF5_I2C_USE_I2C0 || defined(__DOXYGEN__)
I2CDriver I2CD1;
#endif
/**
* @brief I2C1 driver identifier.
*/
#if NRF51_I2C_USE_I2C1 || defined(__DOXYGEN__)
#if NRF5_I2C_USE_I2C1 || defined(__DOXYGEN__)
I2CDriver I2CD2;
#endif
@ -214,7 +214,7 @@ static void serve_interrupt(I2CDriver *i2cp) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_I2C_USE_I2C0 || defined(__DOXYGEN__)
#if NRF5_I2C_USE_I2C0 || defined(__DOXYGEN__)
OSAL_IRQ_HANDLER(Vector4C) {
@ -225,7 +225,7 @@ OSAL_IRQ_HANDLER(Vector4C) {
#endif
#if NRF51_I2C_USE_I2C1 || defined(__DOXYGEN__)
#if NRF5_I2C_USE_I2C1 || defined(__DOXYGEN__)
OSAL_IRQ_HANDLER(Vector50) {
@ -247,13 +247,13 @@ OSAL_IRQ_HANDLER(Vector50) {
*/
void i2c_lld_init(void) {
#if NRF51_I2C_USE_I2C0
#if NRF5_I2C_USE_I2C0
i2cObjectInit(&I2CD1);
I2CD1.thread = NULL;
I2CD1.i2c = NRF_TWI0;
#endif
#if NRF51_I2C_USE_I2C1
#if NRF5_I2C_USE_I2C1
i2cObjectInit(&I2CD2);
I2CD2.thread = NULL;
I2CD2.i2c = NRF_TWI1;

28
os/hal/ports/NRF5/NRF51822/hal_i2c_lld.h
View File

@ -49,8 +49,8 @@
* @details If set to @p TRUE the support for I2C0 is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_I2C_USE_I2C0) || defined(__DOXYGEN__)
#define NRF51_I2C_USE_I2C0 FALSE
#if !defined(NRF5_I2C_USE_I2C0) || defined(__DOXYGEN__)
#define NRF5_I2C_USE_I2C0 FALSE
#endif
/**
@ -58,22 +58,22 @@
* @details If set to @p TRUE the support for I2C1 is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_I2C_USE_I2C1) || defined(__DOXYGEN__)
#define NRF51_I2C_USE_I2C1 FALSE
#if !defined(NRF5_I2C_USE_I2C1) || defined(__DOXYGEN__)
#define NRF5_I2C_USE_I2C1 FALSE
#endif
/**
* @brief I2C0 interrupt priority level setting.
*/
#if !defined(NRF51_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_I2C_I2C0_IRQ_PRIORITY 3
#if !defined(NRF5_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_I2C_I2C0_IRQ_PRIORITY 3
#endif
/**
* @brief I2C1 interrupt priority level setting.
*/
#if !defined(NRF51_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_I2C_I2C1_IRQ_PRIORITY 3
#if !defined(NRF5_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_I2C_I2C1_IRQ_PRIORITY 3
#endif
/** @} */
@ -81,13 +81,13 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if NRF51_I2C_USE_I2C0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_I2C_I2C0_IRQ_PRIORITY)
#if NRF5_I2C_USE_I2C0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_I2C_I2C0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to I2C0"
#endif
#if NRF51_I2C_USE_I2C1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_I2C_I2C1_IRQ_PRIORITY)
#if NRF5_I2C_USE_I2C1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_I2C_I2C1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to I2C1"
#endif
@ -198,11 +198,11 @@ struct I2CDriver {
#if !defined(__DOXYGEN__)
#if NRF51_I2C_USE_I2C0
#if NRF5_I2C_USE_I2C0
extern I2CDriver I2CD1;
#endif
#if NRF51_I2C_USE_I2C1
#if NRF5_I2C_USE_I2C1
extern I2CDriver I2CD2;
#endif

14
os/hal/ports/NRF5/NRF51822/hal_lld.c
View File

@ -56,14 +56,16 @@
void hal_lld_init(void)
{
/* High frequency clock initialisation
* (If NRF51_XTAL_VALUE is not defined assume its an RC oscillator)
* (If NRF5_XTAL_VALUE is not defined assume its an 16Mhz RC oscillator)
*/
NRF_CLOCK->TASKS_HFCLKSTOP = 1;
#if defined(NRF51_XTAL_VALUE)
#if NRF51_XTAL_VALUE == 16000000
#if defined(NRF5_XTAL_VALUE)
#if NRF5_XTAL_VALUE == 16000000
NRF_CLOCK->XTALFREQ = 0xFF;
#elif NRF51_XTAL_VALUE == 32000000
#elif NRF5_XTAL_VALUE == 32000000
NRF_CLOCK->XTALFREQ = 0x00;
#else
#error "Unsupported XTAL value"
#endif
#endif
@ -72,10 +74,10 @@ void hal_lld_init(void)
* Clock is only started if st driver requires it
*/
NRF_CLOCK->TASKS_LFCLKSTOP = 1;
NRF_CLOCK->LFCLKSRC = NRF51_LFCLK_SOURCE;
NRF_CLOCK->LFCLKSRC = NRF5_LFCLK_SOURCE;
#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) && \
(NRF51_SYSTEM_TICKS == NRF51_SYSTEM_TICKS_AS_RTC)
(NRF5_SYSTEM_TICKS == NRF5_SYSTEM_TICKS_AS_RTC)
NRF_CLOCK->TASKS_LFCLKSTART = 1;
#endif
}

37
os/hal/ports/NRF5/NRF51822/hal_lld.h
View File

@ -15,7 +15,7 @@
*/
/**
* @file NRF51/NRF51822/hal_lld.h
* @file NRF5/NRF51822/hal_lld.h
* @brief NRF51822 HAL subsystem low level driver header.
*
* @addtogroup HAL
@ -29,25 +29,32 @@
/* Driver constants. */
/*===========================================================================*/
/**
* @name Chip series
*/
#define NRF_SERIES 51
/**
* @name Platform identification
* @{
*/
#define PLATFORM_NAME "Nordic Semiconductor nRF51822"
/**
* @name Chip series
*/
#define NRF_SERIES 51
/**
* @brief Frequency value for the Low Frequency Clock
*/
#define NRF5_LFCLK_FREQUENCY 32768
/**
* @brief Frequency value for the High Frequency Clock
*/
#define NRF5_HFCLK_FREQUENCY 16000000
/**
* @}
*/
/**
* @brief Frequency valuefor the Low Frequency Clock
*/
#define NRF51_LFCLK_FREQUENCY 32768
/*===========================================================================*/
/* Driver pre-compile time settings. */
@ -62,16 +69,16 @@
* When cristal is not available it's preferable to use the
* internal RC oscillator that synthezing the clock.
*/
#if !defined(NRF51_LFCLK_SOURCE) || defined(__DOXYGEN__)
#define NRF51_LFCLK_SOURCE 0
#if !defined(NRF5_LFCLK_SOURCE) || defined(__DOXYGEN__)
#define NRF5_LFCLK_SOURCE 0
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if (NRF51_LFCLK_SOURCE < 0) || (NRF51_LFCLK_SOURCE > 2)
#error "Possible value for NRF51_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth"
#if (NRF5_LFCLK_SOURCE < 0) || (NRF5_LFCLK_SOURCE > 2)
#error "Possible value for NRF5_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth"
#endif
/*===========================================================================*/
@ -88,8 +95,6 @@
#include "nvic.h"
#define NRF51_LFCLK_FREQUENCY 32768
#define NRF51_HFCLK_FREQUENCY 16000000
#ifdef __cplusplus
extern "C" {

48
os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c
View File

@ -39,7 +39,7 @@
* @brief PWMD1 driver identifier.
* @note The driver PWMD1 allocates the timer TIMER0 when enabled.
*/
#if NRF51_PWM_USE_TIMER0 || defined(__DOXYGEN__)
#if NRF5_PWM_USE_TIMER0 || defined(__DOXYGEN__)
PWMDriver PWMD1;
#endif
@ -47,7 +47,7 @@ PWMDriver PWMD1;
* @brief PWMD2 driver identifier.
* @note The driver PWMD2 allocates the timer TIMER1 when enabled.
*/
#if NRF51_PWM_USE_TIMER1 || defined(__DOXYGEN__)
#if NRF5_PWM_USE_TIMER1 || defined(__DOXYGEN__)
PWMDriver PWMD2;
#endif
@ -55,7 +55,7 @@ PWMDriver PWMD2;
* @brief PWMD3 driver identifier.
* @note The driver PWMD3 allocates the timer TIMER2 when enabled.
*/
#if NRF51_PWM_USE_TIMER2 || defined(__DOXYGEN__)
#if NRF5_PWM_USE_TIMER2 || defined(__DOXYGEN__)
PWMDriver PWMD3;
#endif
@ -95,7 +95,7 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_PWM_USE_TIMER0
#if NRF5_PWM_USE_TIMER0
/**
* @brief TIMER0 interrupt handler.
*
@ -106,9 +106,9 @@ OSAL_IRQ_HANDLER(Vector60) {
pwm_lld_serve_interrupt(&PWMD1);
OSAL_IRQ_EPILOGUE();
}
#endif /* NRF51_PWM_USE_TIMER0 */
#endif /* NRF5_PWM_USE_TIMER0 */
#if NRF51_PWM_USE_TIMER1
#if NRF5_PWM_USE_TIMER1
/**
* @brief TIMER1 interrupt handler.
*
@ -119,9 +119,9 @@ OSAL_IRQ_HANDLER(Vector64) {
pwm_lld_serve_interrupt(&PWMD2);
OSAL_IRQ_EPILOGUE();
}
#endif /* NRF51_PWM_USE_TIMER1 */
#endif /* NRF5_PWM_USE_TIMER1 */
#if NRF51_PWM_USE_TIMER2
#if NRF5_PWM_USE_TIMER2
/**
* @brief TIMER2 interrupt handler.
*
@ -132,7 +132,7 @@ OSAL_IRQ_HANDLER(Vector68) {
pwm_lld_serve_interrupt(&PWMD3);
OSAL_IRQ_EPILOGUE();
}
#endif /* NRF51_PWM_USE_TIMER2 */
#endif /* NRF5_PWM_USE_TIMER2 */
/*===========================================================================*/
/* Driver exported functions. */
@ -145,19 +145,19 @@ OSAL_IRQ_HANDLER(Vector68) {
*/
void pwm_lld_init(void) {
#if NRF51_PWM_USE_TIMER0
#if NRF5_PWM_USE_TIMER0
pwmObjectInit(&PWMD1);
PWMD1.channels = PWM_CHANNELS;
PWMD1.timer = NRF_TIMER0;
#endif
#if NRF51_PWM_USE_TIMER1
#if NRF5_PWM_USE_TIMER1
pwmObjectInit(&PWMD2);
PWMD2.channels = PWM_CHANNELS;
PWMD2.timer = NRF_TIMER1;
#endif
#if NRF51_PWM_USE_TIMER2
#if NRF5_PWM_USE_TIMER2
pwmObjectInit(&PWMD3);
PWMD3.channels = PWM_CHANNELS;
PWMD3.timer = NRF_TIMER2;
@ -175,7 +175,7 @@ void pwm_lld_init(void) {
*/
void pwm_lld_start(PWMDriver *pwmp) {
// Prescaler value calculation: ftimer = 16MHz / 2^PRESCALER
uint16_t psc_ratio = NRF51_HFCLK_FREQUENCY / pwmp->config->frequency;
uint16_t psc_ratio = NRF5_HFCLK_FREQUENCY / pwmp->config->frequency;
// Prescaler ratio must be between 1 and 512, and a power of two.
osalDbgAssert(psc_ratio <= 512 && !(psc_ratio & (psc_ratio - 1)),
"invalid frequency");
@ -215,21 +215,21 @@ void pwm_lld_start(PWMDriver *pwmp) {
// Enable interrupt
#if NRF51_PWM_USE_TIMER0
#if NRF5_PWM_USE_TIMER0
if (&PWMD1 == pwmp) {
nvicEnableVector(TIMER0_IRQn, NRF51_PWM_TIMER0_PRIORITY);
nvicEnableVector(TIMER0_IRQn, NRF5_PWM_TIMER0_PRIORITY);
}
#endif
#if NRF51_PWM_USE_TIMER1
#if NRF5_PWM_USE_TIMER1
if (&PWMD2 == pwmp) {
nvicEnableVector(TIMER1_IRQn, NRF51_PWM_TIMER1_PRIORITY);
nvicEnableVector(TIMER1_IRQn, NRF5_PWM_TIMER1_PRIORITY);
}
#endif
#if NRF51_PWM_USE_TIMER2
#if NRF5_PWM_USE_TIMER2
if (&PWMD3 == pwmp) {
nvicEnableVector(TIMER2_IRQn, NRF51_PWM_TIMER2_PRIORITY);
nvicEnableVector(TIMER2_IRQn, NRF5_PWM_TIMER2_PRIORITY);
}
#endif
@ -247,19 +247,19 @@ void pwm_lld_start(PWMDriver *pwmp) {
void pwm_lld_stop(PWMDriver *pwmp) {
pwmp->timer->TASKS_STOP = 1;
#if NRF51_PWM_USE_TIMER0
#if NRF5_PWM_USE_TIMER0
if (&PWMD1 == pwmp) {
nvicDisableVector(TIMER0_IRQn);
}
#endif
#if NRF51_PWM_USE_TIMER1
#if NRF5_PWM_USE_TIMER1
if (&PWMD2 == pwmp) {
nvicDisableVector(TIMER1_IRQn);
}
#endif
#if NRF51_PWM_USE_TIMER2
#if NRF5_PWM_USE_TIMER2
if (&PWMD3 == pwmp) {
nvicDisableVector(TIMER2_IRQn);
}
@ -282,7 +282,7 @@ void pwm_lld_stop(PWMDriver *pwmp) {
void pwm_lld_enable_channel(PWMDriver *pwmp,
pwmchannel_t channel,
pwmcnt_t width) {
#if NRF51_PWM_USE_GPIOTE_PPI
#if NRF5_PWM_USE_GPIOTE_PPI
const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];
uint32_t outinit;
@ -340,7 +340,7 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
*/
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
pwmp->timer->CC[channel] = 0;
#if NRF51_PWM_USE_GPIOTE_PPI
#if NRF5_PWM_USE_GPIOTE_PPI
const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];
switch(cfg_channel->mode & PWM_OUTPUT_MASK) {
case PWM_OUTPUT_ACTIVE_LOW:

54
os/hal/ports/NRF5/NRF51822/hal_pwm_lld.h
View File

@ -60,50 +60,50 @@
/**
* @brief TIMER0 as driver implementation
*/
#if !defined(NRF51_PWM_USE_TIMER0)
#define NRF51_PWM_USE_TIMER0 FALSE
#if !defined(NRF5_PWM_USE_TIMER0)
#define NRF5_PWM_USE_TIMER0 FALSE
#endif
/**
* @brief TIMER1 as driver implementation
*/
#if !defined(NRF51_PWM_USE_TIMER1)
#define NRF51_PWM_USE_TIMER1 FALSE
#if !defined(NRF5_PWM_USE_TIMER1)
#define NRF5_PWM_USE_TIMER1 FALSE
#endif
/**
* @brief TIMER2 as driver implementation
*/
#if !defined(NRF51_PWM_USE_TIMER2)
#define NRF51_PWM_USE_TIMER2 FALSE
#if !defined(NRF5_PWM_USE_TIMER2)
#define NRF5_PWM_USE_TIMER2 FALSE
#endif
/**
* @brief TIMER0 interrupt priority level setting.
*/
#if !defined(NRF51_PWM_TIMER0_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_PWM_TIMER0_PRIORITY 3
#if !defined(NRF5_PWM_TIMER0_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_PWM_TIMER0_PRIORITY 3
#endif
/**
* @brief TIMER1 interrupt priority level setting.
*/
#if !defined(NRF51_PWM_TIMER1_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_PWM_TIMER1_PRIORITY 3
#if !defined(NRF5_PWM_TIMER1_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_PWM_TIMER1_PRIORITY 3
#endif
/**
* @brief TIMER2 interrupt priority level setting.
*/
#if !defined(NRF51_PWM_TIMER2_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_PWM_TIMER2_PRIORITY 3
#if !defined(NRF5_PWM_TIMER2_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_PWM_TIMER2_PRIORITY 3
#endif
/**
* @brief Allow driver to use GPIOTE/PPI to control PAL line
*/
#if !defined(NRF51_PWM_USE_GPIOTE_PPI)
#define NRF51_PWM_USE_GPIOTE_PPI FALSE
#if !defined(NRF5_PWM_USE_GPIOTE_PPI)
#define NRF5_PWM_USE_GPIOTE_PPI FALSE
#endif
/** @} */
@ -112,26 +112,26 @@
/* Configuration checks. */
/*===========================================================================*/
#if !NRF51_PWM_USE_TIMER0 && !NRF51_PWM_USE_TIMER1 && !NRF51_PWM_USE_TIMER2
#if !NRF5_PWM_USE_TIMER0 && !NRF5_PWM_USE_TIMER1 && !NRF5_PWM_USE_TIMER2
#error "PWM driver activated but no TIMER peripheral assigned"
#endif
#if (NRF51_ST_USE_TIMER0 == TRUE) && (NRF51_PWM_USE_TIMER0 == TRUE)
#if (NRF5_ST_USE_TIMER0 == TRUE) && (NRF5_PWM_USE_TIMER0 == TRUE)
#error "TIMER0 used for ST and PWM"
#endif
#if NRF51_PWM_USE_TIMER0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER0_PRIORITY)
#if NRF5_PWM_USE_TIMER0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_PWM_TIMER0_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER0"
#endif
#if NRF51_PWM_USE_TIMER1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER1_PRIORITY)
#if NRF5_PWM_USE_TIMER1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_PWM_TIMER1_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER1"
#endif
#if NRF51_PWM_USE_TIMER2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER2_PRIORITY)
#if NRF5_PWM_USE_TIMER2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_PWM_TIMER2_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER2"
#endif
@ -180,13 +180,13 @@ typedef struct {
/**
* @brief PAL line to toggle.
* @note Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.
* @note When NRF51_PWM_USE_GPIOTE_PPI is used and channel enabled,
* @note When NRF5_PWM_USE_GPIOTE_PPI is used and channel enabled,
* it wont be possible to access this PAL line using the PAL
* driver.
*/
ioline_t ioline;
#if NRF51_PWM_USE_GPIOTE_PPI || defined(__DOXYGEN__)
#if NRF5_PWM_USE_GPIOTE_PPI || defined(__DOXYGEN__)
/**
* @brief Unique GPIOTE channel to use. (1 channel)
* @note Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.
@ -296,13 +296,13 @@ struct PWMDriver {
/* External declarations. */
/*===========================================================================*/
#if NRF51_PWM_USE_TIMER0 || defined(__DOXYGEN__)
#if NRF5_PWM_USE_TIMER0 || defined(__DOXYGEN__)
extern PWMDriver PWMD1;
#endif
#if NRF51_PWM_USE_TIMER1 || defined(__DOXYGEN__)
#if NRF5_PWM_USE_TIMER1 || defined(__DOXYGEN__)
extern PWMDriver PWMD2;
#endif
#if NRF51_PWM_USE_TIMER2 || defined(__DOXYGEN__)
#if NRF5_PWM_USE_TIMER2 || defined(__DOXYGEN__)
extern PWMDriver PWMD3;
#endif

26
os/hal/ports/NRF5/NRF51822/hal_qei_lld.c
View File

@ -38,7 +38,7 @@
/**
* @brief QEID1 driver identifier.
*/
#if NRF51_QEI_USE_QDEC0 || defined(__DOXYGEN__)
#if NRF5_QEI_USE_QDEC0 || defined(__DOXYGEN__)
QEIDriver QEID1;
#endif
@ -59,7 +59,7 @@ QEIDriver QEID1;
static void serve_interrupt(QEIDriver *qeip) {
NRF_QDEC_Type *qdec = qeip->qdec;
#if NRF51_QEI_USE_ACC_OVERFLOWED_CB == TRUE
#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE
/* Accumulator overflowed
*/
if (qdec->EVENTS_ACCOF) {
@ -93,7 +93,7 @@ static void serve_interrupt(QEIDriver *qeip) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_QEI_USE_QDEC0 == TRUE
#if NRF5_QEI_USE_QDEC0 == TRUE
/**
* @brief Quadrature decoder vector (QDEC)
*
@ -118,7 +118,7 @@ OSAL_IRQ_HANDLER(Vector88) {
*/
void qei_lld_init(void) {
#if NRF51_QEI_USE_QDEC0 == TRUE
#if NRF5_QEI_USE_QDEC0 == TRUE
/* Driver initialization.*/
qeiObjectInit(&QEID1);
QEID1.qdec = NRF_QDEC;
@ -140,22 +140,22 @@ void qei_lld_start(QEIDriver *qeip) {
/* Set Pins */
palSetLineMode(cfg->phase_a, PAL_MODE_INPUT);
palSetLineMode(cfg->phase_b, PAL_MODE_INPUT);
#if NRF51_QEI_USE_LED == TRUE
#if NRF5_QEI_USE_LED == TRUE
if (cfg->led != PAL_NOLINE) {
palSetLineMode(cfg->led, PAL_MODE_INPUT);
}
#endif
/* Set interrupt masks and enable interrupt */
#if NRF51_QEI_USE_ACC_OVERFLOWED_CB == TRUE
#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE
qdec->INTENSET = QDEC_INTENSET_REPORTRDY_Msk |
QDEC_INTENSET_ACCOF_Msk;
#else
qdec->INTENSET = QDEC_INTENSET_REPORTRDY_Msk;
#endif
#if NRF51_QEI_USE_QDEC0 == TRUE
#if NRF5_QEI_USE_QDEC0 == TRUE
if (&QEID1 == qeip) {
nvicEnableVector(QDEC_IRQn, NRF51_QEI_QDEC0_IRQ_PRIORITY);
nvicEnableVector(QDEC_IRQn, NRF5_QEI_QDEC0_IRQ_PRIORITY);
}
#endif
@ -164,7 +164,7 @@ void qei_lld_start(QEIDriver *qeip) {
qdec->PSELB = PAL_PAD(cfg->phase_b);
/* Select (optional) pin for LED, and configure it */
#if NRF51_QEI_USE_LED == TRUE
#if NRF5_QEI_USE_LED == TRUE
qdec->PSELLED = PAL_PAD(cfg->led);
qdec->LEDPOL = ((cfg->led_polarity == QEI_LED_POLARITY_LOW)
? QDEC_LEDPOL_LEDPOL_ActiveLow
@ -214,12 +214,12 @@ void qei_lld_stop(QEIDriver *qeip) {
qdec->ENABLE = 0;
/* Unset interrupt masks and disable interrupt */
#if NRF51_QEI_USE_QDEC0 == TRUE
#if NRF5_QEI_USE_QDEC0 == TRUE
if (&QEID1 == qeip) {
nvicDisableVector(QDEC_IRQn);
}
#endif
#if NRF51_QEI_USE_ACC_OVERFLOWED_CB == TRUE
#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE
qdec->INTENCLR = QDEC_INTENCLR_REPORTRDY_Msk |
QDEC_INTENCLR_ACCOF_Msk;
#else
@ -229,7 +229,7 @@ void qei_lld_stop(QEIDriver *qeip) {
/* Return pins to reset state */
palSetLineMode(cfg->phase_a, PAL_MODE_RESET);
palSetLineMode(cfg->phase_b, PAL_MODE_RESET);
#if NRF51_QEI_USE_LED == TRUE
#if NRF5_QEI_USE_LED == TRUE
if (cfg->led != PAL_NOLINE) {
palSetLineMode(cfg->led, PAL_MODE_RESET);
}
@ -245,7 +245,7 @@ void qei_lld_stop(QEIDriver *qeip) {
* @notapi
*/
void qei_lld_enable(QEIDriver *qeip) {
#if NRF51_QEI_USE_ACC_OVERFLOWED_CB == TRUE
#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE
qeip->overflowed = 0;
#endif

30
os/hal/ports/NRF5/NRF51822/hal_qei_lld.h
View File

@ -71,8 +71,8 @@
* is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_QEI_USE_LED) || defined(__DOXYGEN__)
#define NRF51_QEI_USE_LED FALSE
#if !defined(NRF5_QEI_USE_LED) || defined(__DOXYGEN__)
#define NRF5_QEI_USE_LED FALSE
#endif
/**
@ -81,8 +81,8 @@
* is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_QEI_USE_ACC_OVERFLOWED_CB) || defined(__DOXYGEN__)
#define NRF51_QEI_USE_ACC_OVERFLOWED_CB FALSE
#if !defined(NRF5_QEI_USE_ACC_OVERFLOWED_CB) || defined(__DOXYGEN__)
#define NRF5_QEI_USE_ACC_OVERFLOWED_CB FALSE
#endif
/**
@ -90,15 +90,15 @@
* @details If set to @p TRUE the support for QEID1 is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_QEI_USE_QDEC0) || defined(__DOXYGEN__)
#define NRF51_QEI_USE_QDEC0 FALSE
#if !defined(NRF5_QEI_USE_QDEC0) || defined(__DOXYGEN__)
#define NRF5_QEI_USE_QDEC0 FALSE
#endif
/**
* @brief QEID interrupt priority level setting for QDEC0.
*/
#if !defined(NRF51_QEI_QDEC0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_QEI_QDEC0_IRQ_PRIORITY 2
#if !defined(NRF5_QEI_QDEC0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_QEI_QDEC0_IRQ_PRIORITY 2
#endif
/** @} */
@ -106,12 +106,12 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if NRF51_QEI_USE_QDEC0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_QEI_QDEC0_IRQ_PRIORITY)
#if NRF5_QEI_USE_QDEC0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_QEI_QDEC0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to QDEC0"
#endif
#if NRF51_QEI_USE_QDEC0 == FALSE
#if NRF5_QEI_USE_QDEC0 == FALSE
#error "Requesting QEI driver, but no QDEC peripheric attached"
#endif
@ -238,7 +238,7 @@ typedef struct {
* @brief Line for reading Phase B
*/
ioline_t phase_b;
#if (NRF51_QEI_USE_LED == TRUE) || defined(__DOXYGEN__)
#if (NRF5_QEI_USE_LED == TRUE) || defined(__DOXYGEN__)
/**
* @brief Line used to control LED
*
@ -276,7 +276,7 @@ typedef struct {
* @details Default to QEI_REPORT_10
*/
qeireport_t report;
#if NRF51_QEI_USE_ACC_OVERFLOWED_CB == TRUE
#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE
/**
* @brief Notify of internal accumulator overflowed
* (ie: MCU discarding samples)
@ -311,7 +311,7 @@ struct QEIDriver {
* @brief Counter
*/
qeicnt_t count;
#if NRF51_QEI_USE_ACC_OVERFLOWED_CB == TRUE
#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE
/**
* @brief Number of time the MCU discarded updates due to
* accumulator overflow
@ -359,7 +359,7 @@ struct QEIDriver {
/* External declarations. */
/*===========================================================================*/
#if NRF51_QEI_USE_QDEC0 && !defined(__DOXYGEN__)
#if NRF5_QEI_USE_QDEC0 && !defined(__DOXYGEN__)
extern QEIDriver QEID1;
#endif

2
os/hal/ports/NRF5/NRF51822/hal_rng_lld.c
View File

@ -42,7 +42,7 @@ static const RNGConfig default_config = {
/*===========================================================================*/
/** @brief RNG1 driver identifier.*/
#if NRF51_RNG_USE_RNG1 || defined(__DOXYGEN__)
#if NRF5_RNG_USE_RNG1 || defined(__DOXYGEN__)
RNGDriver RNGD1;
#endif

20
os/hal/ports/NRF5/NRF51822/hal_rng_lld.h
View File

@ -44,8 +44,8 @@
* @details If set to @p TRUE the support for RNG1 is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_RNG_USE_RNG1) || defined(__DOXYGEN__)
#define NRF51_RNG_USE_RNG1 FALSE
#if !defined(NRF5_RNG_USE_RNG1) || defined(__DOXYGEN__)
#define NRF5_RNG_USE_RNG1 FALSE
#endif
/**
@ -53,15 +53,15 @@
* @details If set to @p TRUE the support for RNG1 is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_RNG_USE_RNG1) || defined(__DOXYGEN__)
#define NRF51_RNG_USE_POWER_ON_WRITE FALSE
#if !defined(NRF5_RNG_USE_RNG1) || defined(__DOXYGEN__)
#define NRF5_RNG_USE_POWER_ON_WRITE FALSE
#endif
/**
* @brief RNG1 interrupt priority level setting.
*/
#if !defined(NRF51_RNG_RNG1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_RNG_RNG1_IRQ_PRIORITY 3
#if !defined(NRF5_RNG_RNG1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_RNG_RNG1_IRQ_PRIORITY 3
#endif
@ -69,8 +69,8 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if NRF51_RNG_USE_RNG1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_RNG_RNG1_IRQ_PRIORITY)
#if NRF5_RNG_USE_RNG1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_RNG_RNG1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to RNG1"
#endif
@ -148,9 +148,9 @@ struct RNGDriver {
/* External declarations. */
/*===========================================================================*/
#if NRF51_RNG_USE_RNG1 && !defined(__DOXYGEN__)
#if NRF5_RNG_USE_RNG1 && !defined(__DOXYGEN__)
extern RNGDriver RNGD1;
#endif /* NRF51_RNG_USE_RNG1 */
#endif /* NRF5_RNG_USE_RNG1 */
#ifdef __cplusplus
extern "C" {

24
os/hal/ports/NRF5/NRF51822/hal_spi_lld.c
View File

@ -30,12 +30,12 @@
/* Driver exported variables. */
/*===========================================================================*/
#if NRF51_SPI_USE_SPI0 || defined(__DOXYGEN__)
#if NRF5_SPI_USE_SPI0 || defined(__DOXYGEN__)
/** @brief SPI1 driver identifier.*/
SPIDriver SPID1;
#endif
#if NRF51_SPI_USE_SPI1 || defined(__DOXYGEN__)
#if NRF5_SPI_USE_SPI1 || defined(__DOXYGEN__)
/** @brief SPI2 driver identifier.*/
SPIDriver SPID2;
#endif
@ -107,7 +107,7 @@ static void serve_interrupt(SPIDriver *spip) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_SPI_USE_SPI0 || defined(__DOXYGEN__)
#if NRF5_SPI_USE_SPI0 || defined(__DOXYGEN__)
/**
* @brief SPI0 interrupt handler.
*
@ -120,7 +120,7 @@ CH_IRQ_HANDLER(Vector4C) {
CH_IRQ_EPILOGUE();
}
#endif
#if NRF51_SPI_USE_SPI1 || defined(__DOXYGEN__)
#if NRF5_SPI_USE_SPI1 || defined(__DOXYGEN__)
/**
* @brief SPI1 interrupt handler.
*
@ -145,11 +145,11 @@ CH_IRQ_HANDLER(Vector50) {
*/
void spi_lld_init(void) {
#if NRF51_SPI_USE_SPI0
#if NRF5_SPI_USE_SPI0
spiObjectInit(&SPID1);
SPID1.port = NRF_SPI0;
#endif
#if NRF51_SPI_USE_SPI1
#if NRF5_SPI_USE_SPI1
spiObjectInit(&SPID2);
SPID2.port = NRF_SPI1;
#endif
@ -166,13 +166,13 @@ void spi_lld_start(SPIDriver *spip) {
uint32_t config;
if (spip->state == SPI_STOP) {
#if NRF51_SPI_USE_SPI0
#if NRF5_SPI_USE_SPI0
if (&SPID1 == spip)
nvicEnableVector(SPI0_TWI0_IRQn, NRF51_SPI_SPI0_IRQ_PRIORITY);
nvicEnableVector(SPI0_TWI0_IRQn, NRF5_SPI_SPI0_IRQ_PRIORITY);
#endif
#if NRF51_SPI_USE_SPI1
#if NRF5_SPI_USE_SPI1
if (&SPID2 == spip)
nvicEnableVector(SPI1_TWI1_IRQn, NRF51_SPI_SPI1_IRQ_PRIORITY);
nvicEnableVector(SPI1_TWI1_IRQn, NRF5_SPI_SPI1_IRQ_PRIORITY);
#endif
}
@ -223,11 +223,11 @@ void spi_lld_stop(SPIDriver *spip) {
if (spip->state != SPI_STOP) {
spip->port->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
spip->port->INTENCLR = (SPI_INTENCLR_READY_Clear << SPI_INTENCLR_READY_Pos);
#if NRF51_SPI_USE_SPI0
#if NRF5_SPI_USE_SPI0
if (&SPID1 == spip)
nvicDisableVector(SPI0_TWI0_IRQn);
#endif
#if NRF51_SPI_USE_SPI1
#if NRF5_SPI_USE_SPI1
if (&SPID2 == spip)
nvicDisableVector(SPI1_TWI1_IRQn);
#endif

40
os/hal/ports/NRF5/NRF51822/hal_spi_lld.h
View File

@ -38,40 +38,40 @@
/**
* @brief SPI0 interrupt priority level setting.
*/
#if !defined(NRF51_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_SPI_SPI0_IRQ_PRIORITY 3
#if !defined(NRF5_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_SPI_SPI0_IRQ_PRIORITY 3
#endif
/**
* @brief SPI1 interrupt priority level setting.
*/
#if !defined(NRF51_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_SPI_SPI1_IRQ_PRIORITY 3
#if !defined(NRF5_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_SPI_SPI1_IRQ_PRIORITY 3
#endif
/**
* @brief Overflow error hook.
* @details The default action is to stop the system.
*/
#if !defined(NRF51_SPI_SPI_ERROR_HOOK) || defined(__DOXYGEN__)
#define NRF51_SPI_SPI_ERROR_HOOK() chSysHalt()
#if !defined(NRF5_SPI_SPI_ERROR_HOOK) || defined(__DOXYGEN__)
#define NRF5_SPI_SPI_ERROR_HOOK() chSysHalt()
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if !NRF51_SPI_USE_SPI0 && !NRF51_SPI_USE_SPI1
#if !NRF5_SPI_USE_SPI0 && !NRF5_SPI_USE_SPI1
#error "SPI driver activated but no SPI peripheral assigned"
#endif
#if NRF51_SPI_USE_SPI0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SPI_SPI0_IRQ_PRIORITY)
#if NRF5_SPI_USE_SPI0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_SPI_SPI0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI0"
#endif
#if NRF51_SPI_USE_SPI1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SPI_SPI1_IRQ_PRIORITY)
#if NRF5_SPI_USE_SPI1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_SPI_SPI1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI1"
#endif
@ -96,13 +96,13 @@ typedef void (*spicallback_t)(SPIDriver *spip);
* @brief SPI frequency
*/
typedef enum {
NRF51_SPI_FREQ_125KBPS = (SPI_FREQUENCY_FREQUENCY_K125 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF51_SPI_FREQ_250KBPS = (SPI_FREQUENCY_FREQUENCY_K250 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF51_SPI_FREQ_500KBPS = (SPI_FREQUENCY_FREQUENCY_K500 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF51_SPI_FREQ_1MBPS = (SPI_FREQUENCY_FREQUENCY_M1 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF51_SPI_FREQ_2MBPS = (SPI_FREQUENCY_FREQUENCY_M2 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF51_SPI_FREQ_4MBPS = (SPI_FREQUENCY_FREQUENCY_M4 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF51_SPI_FREQ_8MBPS = (SPI_FREQUENCY_FREQUENCY_M8 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_125KBPS = (SPI_FREQUENCY_FREQUENCY_K125 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_250KBPS = (SPI_FREQUENCY_FREQUENCY_K250 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_500KBPS = (SPI_FREQUENCY_FREQUENCY_K500 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_1MBPS = (SPI_FREQUENCY_FREQUENCY_M1 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_2MBPS = (SPI_FREQUENCY_FREQUENCY_M2 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_4MBPS = (SPI_FREQUENCY_FREQUENCY_M4 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_8MBPS = (SPI_FREQUENCY_FREQUENCY_M8 << SPI_FREQUENCY_FREQUENCY_Pos),
} spifreq_t;
/**
@ -206,10 +206,10 @@ struct SPIDriver {
/* External declarations. */
/*===========================================================================*/
#if NRF51_SPI_USE_SPI0 && !defined(__DOXYGEN__)
#if NRF5_SPI_USE_SPI0 && !defined(__DOXYGEN__)
extern SPIDriver SPID1;
#endif
#if NRF51_SPI_USE_SPI1 && !defined(__DOXYGEN__)
#if NRF5_SPI_USE_SPI1 && !defined(__DOXYGEN__)
extern SPIDriver SPID2;
#endif

4
os/hal/ports/NRF5/NRF51822/hal_wdg_lld.c
View File

@ -55,7 +55,7 @@ WDGDriver WDGD1;
* @brief Watchdog vector.
* @details This interrupt is used when watchdog timeout.
*
* @note Only 2 cycles at NRF51_LFCLK_FREQUENCY are available
* @note Only 2 cycles at NRF5_LFCLK_FREQUENCY are available
* to they good bye.
*
* @isr
@ -111,7 +111,7 @@ void wdg_lld_start(WDGDriver *wdgp) {
(wdgp->config->flags.pause_on_halt * WDT_CONFIG_HALT_Msk );
/* Timeout in milli-seconds */
uint64_t tout = (NRF51_LFCLK_FREQUENCY * wdgp->config->timeout_ms / 1000) - 1;
uint64_t tout = (NRF5_LFCLK_FREQUENCY * wdgp->config->timeout_ms / 1000) - 1;
osalDbgAssert(tout <= 0xFFFFFFFF, "watchdog timout value exceeded");
wdgp->wdt->CRV = (uint32_t)tout;

2
os/hal/ports/NRF5/NRF51822/hal_wdg_lld.h
View File

@ -32,7 +32,7 @@
/*===========================================================================*/
#define WDG_MAX_TIMEOUT_MS \
((uint32_t)(0xFFFFFFFFu * 1000 / NRF51_LFCLK_FREQUENCY))
((uint32_t)(0xFFFFFFFFu * 1000 / NRF5_LFCLK_FREQUENCY))
/*===========================================================================*/
/* Driver pre-compile time settings. */

34
os/hal/ports/NRF5/NRF52832/hal_lld.h
View File

@ -29,25 +29,31 @@
/* Driver constants. */
/*===========================================================================*/
/**
* @name Chip series
*/
#define NRF_SERIES 52
/**
* @name Platform identification
* @{
*/
#define PLATFORM_NAME "Nordic Semiconductor nRF52832"
/**
* @name Chip series
*/
#define NRF_SERIES 52
/**
* @brief Frequency value for the Low Frequency Clock
*/
#define NRF5_LFCLK_FREQUENCY 32768
/**
* @brief Frequency value for the High Frequency Clock
*/
#define NRF5_HFCLK_FREQUENCY 64000000
/**
* @}
*/
/**
* @brief Frequency valuefor the Low Frequency Clock
*/
#define NRF51_LFCLK_FREQUENCY 32768
/*===========================================================================*/
/* Driver pre-compile time settings. */
@ -62,16 +68,16 @@
* When cristal is not available it's preferable to use the
* internal RC oscillator that synthezing the clock.
*/
#if !defined(NRF51_LFCLK_SOURCE) || defined(__DOXYGEN__)
#define NRF51_LFCLK_SOURCE 0
#if !defined(NRF5_LFCLK_SOURCE) || defined(__DOXYGEN__)
#define NRF5_LFCLK_SOURCE 0
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if (NRF51_LFCLK_SOURCE < 0) || (NRF51_LFCLK_SOURCE > 2)
#error "Possible value for NRF51_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth"
#if (NRF5_LFCLK_SOURCE < 0) || (NRF5_LFCLK_SOURCE > 2)
#error "Possible value for NRF5_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth"
#endif
/*===========================================================================*/
@ -88,8 +94,6 @@
#include "nvic.h"
#define NRF51_LFCLK_FREQUENCY 32768
#define NRF51_HFCLK_FREQUENCY 16000000
#ifdef __cplusplus
extern "C" {

2
testhal/NRF51/NRF51822/ADC/mcuconf.h
View File

@ -20,6 +20,6 @@
/*
* NRF51 driver system settings.
*/
#define NRF51_ADC_USE_ADC1 TRUE
#define NRF5_ADC_USE_ADC1 TRUE
#endif /* _MCUCONF_H_ */

4
testhal/NRF51/NRF51822/GPT/mcuconf.h
View File

@ -20,7 +20,7 @@
/*
* NRF51 driver system settings.
*/
#define NRF51_GPT_USE_TIMER1 TRUE
#define NRF51_GPT_USE_TIMER2 TRUE
#define NRF5_GPT_USE_TIMER1 TRUE
#define NRF5_GPT_USE_TIMER2 TRUE
#endif /* _MCUCONF_H_ */

2
testhal/NRF51/NRF51822/I2C/mcuconf.h
View File

@ -20,6 +20,6 @@
/*
* HAL driver system settings.
*/
#define NRF51_I2C_USE_I2C0 TRUE
#define NRF5_I2C_USE_I2C0 TRUE
#endif /* _MCUCONF_H_ */

12
testhal/NRF51/NRF51822/PWM/mcuconf.h
View File

@ -20,11 +20,11 @@
/*
* HAL driver system settings.
*/
#define NRF51_SERIAL_USE_UART0 TRUE
#define NRF51_ST_USE_RTC0 TRUE
#define NRF51_ST_USE_RTC1 FALSE
#define NRF51_ST_USE_TIMER0 FALSE
#define NRF51_PWM_USE_TIMER0 TRUE
#define NRF51_PWM_USE_GPIOTE_PPI TRUE
#define NRF5_SERIAL_USE_UART0 TRUE
#define NRF5_ST_USE_RTC0 TRUE
#define NRF5_ST_USE_RTC1 FALSE
#define NRF5_ST_USE_TIMER0 FALSE
#define NRF5_PWM_USE_TIMER0 TRUE
#define NRF5_PWM_USE_GPIOTE_PPI TRUE
#endif /* _MCUCONF_H_ */

4
testhal/NRF51/NRF51822/RNG/mcuconf.h
View File

@ -17,8 +17,8 @@
#ifndef _MCUCONF_H_
#define _MCUCONF_H_
#define NRF51_RNG_USE_RNG1 TRUE
#define NRF51_SERIAL_USE_UART0 TRUE
#define NRF5_RNG_USE_RNG1 TRUE
#define NRF5_SERIAL_USE_UART0 TRUE
#endif /* _MCUCONF_H_ */

2
testhal/NRF51/NRF51822/SPI/mcuconf.h
View File

@ -20,6 +20,6 @@
/*
* HAL driver system settings.
*/
#define NRF51_SPI_USE_SPI0 TRUE
#define NRF5_SPI_USE_SPI0 TRUE
#endif /* _MCUCONF_H_ */