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FSMC. Sync mode improvements. 

1) Control registers writes reordered in init sequence to eliminate
incorrect output clock frequnency in short period after CCLKEN bit
set and B(W)TR registers set.
2) Added reset of CCLEN bit in stop procedure.
This commit is contained in:
barthess 2016-12-09 18:00:28 +03:00
parent 319c9f9ee2
commit 53d3fd07f3
1 changed files with 8 additions and 2 deletions
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10
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c
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@ -128,9 +128,9 @@ void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) {
"invalid state");
if (sramp->state == SRAM_STOP) {
sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN;
sramp->sram->BTR = cfgp->btr;
sramp->sram->BWTR = cfgp->bwtr;
sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN;
sramp->state = SRAM_READY;
}
}
@ -145,7 +145,13 @@ void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) {
void fsmcSramStop(SRAMDriver *sramp) {
if (sramp->state == SRAM_READY) {
sramp->sram->BCR &= ~FSMC_BCR_MBKEN;
uint32_t mask = FSMC_BCR_MBKEN;
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F7))
mask |= FSMC_BCR_CCLKEN;
#endif
sramp->sram->BCR &= ~mask;
sramp->state = SRAM_STOP;
}
}