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Rename PMU register defines

This commit is contained in:
Stefan Kerkmann 2021-03-31 11:52:05 +02:00
parent fcb2d49c25
commit 53ddaa399b
3 changed files with 76 additions and 89 deletions
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8
os/hal/ports/GD/GD32VF103/hal_lld.c
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@ -15,8 +15,8 @@
*/
/**
* @file STM32F1xx/hal_lld.c
* @brief STM32F1xx HAL subsystem low level driver source.
* @file GD32VF103/hal_lld.c
* @brief GD32VF103 HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
@ -54,7 +54,7 @@ uint32_t SystemCoreClock = GD32_HCLK;
static void hal_lld_backup_domain_init(void) {
/* Backup domain access enabled and left open.*/
PMU->CTL |= PMU_CR_DBP;
PMU->CTL |= PMU_CTL_BKPWEN;
#if HAL_USE_RTC
/* Reset BKP domain if different clock source selected.*/
@ -152,7 +152,7 @@ void hal_lld_init(void) {
/* Programmable voltage detector enable.*/
#if GD32_PVD_ENABLE
PMU->CTL |= PMU_CR_PVDE | (GD32_PLS & GD32_PLS_MASK);
PMU->CTL |= PMU_CTL_LVDEN | (GD32_LVDT & GD32_LVDT_MASK);
#endif /* GD32_PVD_ENABLE */
}

43
os/hal/ports/GD/GD32VF103/hal_lld.h
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@ -16,26 +16,14 @@
*/
/**
* @file STM32F1xx/hal_lld.h
* @brief STM32F1xx HAL subsystem low level driver header.
* @file GD32VF103/hal_lld.h
* @brief GD32VF103 HAL subsystem low level driver header.
* @pre This module requires the following macros to be defined in the
* @p board.h file:
* - GD32_LSECLK.
* - GD32_LSE_BYPASS (optionally).
* - GD32_HSECLK.
* - GD32_HSE_BYPASS (optionally).
* .
* One of the following macros must also be defined:
* - STM32F100xB for Value Line Medium Density devices.
* - STM32F100xE for Value Line High Density devices.
* - STM32F101x6, STM32F102x6, STM32F103x6 for Performance
* Low Density devices.
* - STM32F101xB, STM32F102xB, STM32F103xB for Performance
* Medium Density devices.
* - STM32F101xE, STM32F103xE for Performance High Density devices.
* - STM32F101xG, STM32F103xG for Performance eXtra Density devices.
* - STM32F105xC, STM32F107xC for Connectivity Line devices.
* .
*
* @addtogroup HAL
* @{
@ -66,8 +54,7 @@
/**
* @brief Sub-family identifier.
*/
#if !defined(STM32F1XX) || !defined(GD32VF103) || defined(__DOXYGEN__)
#define STM32F1XX
#if !defined(GD32VF103) || defined(__DOXYGEN__)
#define GD32VF103
#endif
/** @} */
@ -81,18 +68,18 @@
/** @} */
/**
* @name PMU_CR register bits definitions
* @name PMU_CTL register bits definitions
* @{
*/
#define GD32_PLS_MASK (7 << 5) /**< PLS bits mask. */
#define GD32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
#define GD32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
#define GD32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
#define GD32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
#define GD32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
#define GD32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
#define GD32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
#define GD32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
#define GD32_LVDT_MASK (7 << 5) /**< LVDT bits mask. */
#define GD32_LVDT_LEV0 (0 << 5) /**< LVDT level 0. */
#define GD32_LVDT_LEV1 (1 << 5) /**< LVDT level 1. */
#define GD32_LVDT_LEV2 (2 << 5) /**< LVDT level 2. */
#define GD32_LVDT_LEV3 (3 << 5) /**< LVDT level 3. */
#define GD32_LVDT_LEV4 (4 << 5) /**< LVDT level 4. */
#define GD32_LVDT_LEV5 (5 << 5) /**< LVDT level 5. */
#define GD32_LVDT_LEV6 (6 << 5) /**< LVDT level 6. */
#define GD32_LVDT_LEV7 (7 << 5) /**< LVDT level 7. */
/** @} */
/*===========================================================================*/
@ -124,8 +111,8 @@
/**
* @brief Sets voltage level for programmable voltage detector.
*/
#if !defined(GD32_PLS) || defined(__DOXYGEN__)
#define GD32_PLS GD32_PLS_LEV0
#if !defined(GD32_LVDT) || defined(__DOXYGEN__)
#define GD32_LVDT GD32_LVDT_LEV0
#endif
/**

114
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -6,7 +6,7 @@
* @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
* definitions and memory mapping for GD32VF103 devices.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
@ -667,7 +667,7 @@ typedef struct
#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
#define CAN2_BASE (APB1PERIPH_BASE + 0x00006800U)
//#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
#define PMU_BASE (APB1PERIPH_BASE + 0x00007000U)
//#define PMU_BASE (APB1PERIPH_BASE + 0x00007000U)
//#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
//#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
//#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
@ -837,68 +837,68 @@ typedef struct
/* */
/******************************************************************************/
/******************** Bit definition for PMU_CR register ********************/
#define PMU_CR_LPDS_Pos (0U)
#define PMU_CR_LPDS_Msk (0x1U << PMU_CR_LPDS_Pos) /*!< 0x00000001 */
#define PMU_CR_LPDS PMU_CR_LPDS_Msk /*!< Low-Power Deepsleep */
#define PMU_CR_PDDS_Pos (1U)
#define PMU_CR_PDDS_Msk (0x1U << PMU_CR_PDDS_Pos) /*!< 0x00000002 */
#define PMU_CR_PDDS PMU_CR_PDDS_Msk /*!< Power Down Deepsleep */
#define PMU_CR_CWUF_Pos (2U)
#define PMU_CR_CWUF_Msk (0x1U << PMU_CR_CWUF_Pos) /*!< 0x00000004 */
#define PMU_CR_CWUF PMU_CR_CWUF_Msk /*!< Clear Wakeup Flag */
#define PMU_CR_CSBF_Pos (3U)
#define PMU_CR_CSBF_Msk (0x1U << PMU_CR_CSBF_Pos) /*!< 0x00000008 */
#define PMU_CR_CSBF PMU_CR_CSBF_Msk /*!< Clear Standby Flag */
#define PMU_CR_PVDE_Pos (4U)
#define PMU_CR_PVDE_Msk (0x1U << PMU_CR_PVDE_Pos) /*!< 0x00000010 */
#define PMU_CR_PVDE PMU_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
/******************** Bit definition for PMU_CTL register ********************/
#define PMU_CTL_LDOLP_Pos (0U)
#define PMU_CTL_LDOLP_Msk (0x1U << PMU_CTL_LDOLP_Pos) /*!< 0x00000001 */
#define PMU_CTL_LDOLP PMU_CTL_LDOLP_Msk /*!< Low-Power Deepsleep */
#define PMU_CTL_STBMOD_Pos (1U)
#define PMU_CTL_STBMOD_Msk (0x1U << PMU_CTL_STBMOD_Pos) /*!< 0x00000002 */
#define PMU_CTL_STBMOD PMU_CTL_STBMOD_Msk /*!< Power Down Deepsleep */
#define PMU_CTL_WURST_Pos (2U)
#define PMU_CTL_WURST_Msk (0x1U << PMU_CTL_WURST_Pos) /*!< 0x00000004 */
#define PMU_CTL_WURST PMU_CTL_WURST_Msk /*!< Clear Wakeup Flag */
#define PMU_CTL_STBRST_Pos (3U)
#define PMU_CTL_STBRST_Msk (0x1U << PMU_CTL_STBRST_Pos) /*!< 0x00000008 */
#define PMU_CTL_STBRST PMU_CTL_STBRST_Msk /*!< Clear Standby Flag */
#define PMU_CTL_LVDEN_Pos (4U)
#define PMU_CTL_LVDEN_Msk (0x1U << PMU_CTL_LVDEN_Pos) /*!< 0x00000010 */
#define PMU_CTL_LVDEN PMU_CTL_LVDEN_Msk /*!< Power Voltage Detector Enable */
#define PMU_CR_PLS_Pos (5U)
#define PMU_CR_PLS_Msk (0x7U << PMU_CR_PLS_Pos) /*!< 0x000000E0 */
#define PMU_CR_PLS PMU_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
#define PMU_CR_PLS_0 (0x1U << PMU_CR_PLS_Pos) /*!< 0x00000020 */
#define PMU_CR_PLS_1 (0x2U << PMU_CR_PLS_Pos) /*!< 0x00000040 */
#define PMU_CR_PLS_2 (0x4U << PMU_CR_PLS_Pos) /*!< 0x00000080 */
#define PMU_CTL_LVDT_Pos (5U)
#define PMU_CTL_LVDT_Msk (0x7U << PMU_CTL_LVDT_Pos) /*!< 0x000000E0 */
#define PMU_CTL_LVDT PMU_CTL_LVDT_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
#define PMU_CTL_LVDT_0 (0x1U << PMU_CTL_LVDT_Pos) /*!< 0x00000020 */
#define PMU_CTL_LVDT_1 (0x2U << PMU_CTL_LVDT_Pos) /*!< 0x00000040 */
#define PMU_CTL_LVDT_2 (0x4U << PMU_CTL_LVDT_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
#define PMU_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
#define PMU_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
#define PMU_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
#define PMU_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
#define PMU_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
#define PMU_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
#define PMU_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
#define PMU_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
#define PMU_CTL_LVDT_LEV0 0x00000000U /*!< PVD level 2.2V */
#define PMU_CTL_LVDT_LEV1 0x00000020U /*!< PVD level 2.3V */
#define PMU_CTL_LVDT_LEV2 0x00000040U /*!< PVD level 2.4V */
#define PMU_CTL_LVDT_LEV3 0x00000060U /*!< PVD level 2.5V */
#define PMU_CTL_LVDT_LEV4 0x00000080U /*!< PVD level 2.6V */
#define PMU_CTL_LVDT_LEV5 0x000000A0U /*!< PVD level 2.7V */
#define PMU_CTL_LVDT_LEV6 0x000000C0U /*!< PVD level 2.8V */
#define PMU_CTL_LVDT_LEV7 0x000000E0U /*!< PVD level 2.9V */
/* Legacy defines */
#define PMU_CR_PLS_2V2 PMU_CR_PLS_LEV0
#define PMU_CR_PLS_2V3 PMU_CR_PLS_LEV1
#define PMU_CR_PLS_2V4 PMU_CR_PLS_LEV2
#define PMU_CR_PLS_2V5 PMU_CR_PLS_LEV3
#define PMU_CR_PLS_2V6 PMU_CR_PLS_LEV4
#define PMU_CR_PLS_2V7 PMU_CR_PLS_LEV5
#define PMU_CR_PLS_2V8 PMU_CR_PLS_LEV6
#define PMU_CR_PLS_2V9 PMU_CR_PLS_LEV7
#define PMU_CTL_LVDT_2V2 PMU_CTL_LVDT_LEV0
#define PMU_CTL_LVDT_2V3 PMU_CTL_LVDT_LEV1
#define PMU_CTL_LVDT_2V4 PMU_CTL_LVDT_LEV2
#define PMU_CTL_LVDT_2V5 PMU_CTL_LVDT_LEV3
#define PMU_CTL_LVDT_2V6 PMU_CTL_LVDT_LEV4
#define PMU_CTL_LVDT_2V7 PMU_CTL_LVDT_LEV5
#define PMU_CTL_LVDT_2V8 PMU_CTL_LVDT_LEV6
#define PMU_CTL_LVDT_2V9 PMU_CTL_LVDT_LEV7
#define PMU_CR_DBP_Pos (8U)
#define PMU_CR_DBP_Msk (0x1U << PMU_CR_DBP_Pos) /*!< 0x00000100 */
#define PMU_CR_DBP PMU_CR_DBP_Msk /*!< Disable Backup Domain write protection */
#define PMU_CTL_BKPWEN_Pos (8U)
#define PMU_CTL_BKPWEN_Msk (0x1U << PMU_CTL_BKPWEN_Pos) /*!< 0x00000100 */
#define PMU_CTL_BKPWEN PMU_CTL_BKPWEN_Msk /*!< Disable Backup Domain write protection */
/******************* Bit definition for PMU_CSR register ********************/
#define PMU_CSR_WUF_Pos (0U)
#define PMU_CSR_WUF_Msk (0x1U << PMU_CSR_WUF_Pos) /*!< 0x00000001 */
#define PMU_CSR_WUF PMU_CSR_WUF_Msk /*!< Wakeup Flag */
#define PMU_CSR_SBF_Pos (1U)
#define PMU_CSR_SBF_Msk (0x1U << PMU_CSR_SBF_Pos) /*!< 0x00000002 */
#define PMU_CSR_SBF PMU_CSR_SBF_Msk /*!< Standby Flag */
#define PMU_CSR_PVDO_Pos (2U)
#define PMU_CSR_PVDO_Msk (0x1U << PMU_CSR_PVDO_Pos) /*!< 0x00000004 */
#define PMU_CSR_PVDO PMU_CSR_PVDO_Msk /*!< PVD Output */
#define PMU_CSR_EWUP_Pos (8U)
#define PMU_CSR_EWUP_Msk (0x1U << PMU_CSR_EWUP_Pos) /*!< 0x00000100 */
#define PMU_CSR_EWUP PMU_CSR_EWUP_Msk /*!< Enable WKUP pin */
/******************* Bit definition for PMU_CS register ********************/
#define PMU_CS_WUF_Pos (0U)
#define PMU_CS_WUF_Msk (0x1U << PMU_CS_WUF_Pos) /*!< 0x00000001 */
#define PMU_CS_WUF PMU_CS_WUF_Msk /*!< Wakeup Flag */
#define PMU_CS_STBF_Pos (1U)
#define PMU_CS_STBF_Msk (0x1U << PMU_CS_STBF_Pos) /*!< 0x00000002 */
#define PMU_CS_STBF PMU_CS_STBF_Msk /*!< Standby Flag */
#define PMU_CS_LVDF_Pos (2U)
#define PMU_CS_LVDF_Msk (0x1U << PMU_CS_LVDF_Pos) /*!< 0x00000004 */
#define PMU_CS_LVDF PMU_CS_LVDF_Msk /*!< PVD Output */
#define PMU_CS_WUPEN_Pos (8U)
#define PMU_CS_WUPEN_Msk (0x1U << PMU_CS_WUPEN_Pos) /*!< 0x00000100 */
#define PMU_CS_WUPEN PMU_CS_WUPEN_Msk /*!< Enable WKUP pin */
/******************************************************************************/
/* */
@ -12855,7 +12855,7 @@ typedef struct
* @}
*/
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* For a painless codes migration between the GD32VF103 device product */
/* lines, the aliases defined below are put in place to overcome the */
/* differences in the interrupt handlers and IRQn definitions. */
/* No need to update developed interrupt code when moving across */