rusefi
/
ChibiOS-Contrib
mirror of https://github.com/rusefi/ChibiOS-Contrib.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

LTDC and DMA2D ported to ChibiOS/RT 3 

+ LTDC and DMA2D peripheral drivers
+ LTDC and DMA2D demo project
This commit is contained in:
TexZK 2015-06-24 21:24:45 +02:00
parent 57d8d8f549
commit 542d79ef90
33 changed files with 19546 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
AUTHORS.txt
View File

@ -1,18 +1,21 @@
Joel Bodenmann aka Tectu
https://github.com/Tectu
Git repository maintainer
Uladzimir Pylinsky aka barthess
https://github.com/barthess
Git repository maintainer
Marco Veeneman aka Marco
https://github.com/marcoveeneman
Maintainer of the ChibiOS port for the Texas Instruments
Tiva C Series Microcontrollers
Fabien Poussin aka fpoussin
https://github.com/fpoussin
Matthias Blaicher aka mabl
https://github.com/mabl
Joel Bodenmann aka Tectu
https://github.com/Tectu
Git repository maintainer
Uladzimir Pylinsky aka barthess
https://github.com/barthess
Git repository maintainer
Marco Veeneman aka Marco
https://github.com/marcoveeneman
Maintainer of the ChibiOS port for the Texas Instruments
Tiva C Series Microcontrollers
Fabien Poussin aka fpoussin
https://github.com/fpoussin
Matthias Blaicher aka mabl
https://github.com/mabl
Andrea Zoppi aka TexZK
https://github.com/TexZK

58
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject Normal file
View File

@ -0,0 +1,58 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="0.114656749">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.114656749" moduleId="org.eclipse.cdt.core.settings" name="Default">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactName="${ProjName}" buildProperties="" description="" id="0.114656749" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
<folderInfo id="0.114656749." name="/" resourcePath="">
<toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.1182750861" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
<targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.1182750861.169007201" name=""/>
<builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.579570726" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
<tool id="org.eclipse.cdt.build.core.settings.holder.libs.2143276802" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
<tool id="org.eclipse.cdt.build.core.settings.holder.1873650595" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
<option id="org.eclipse.cdt.build.core.settings.holder.incpaths.1821379090" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1337802279" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
<tool id="org.eclipse.cdt.build.core.settings.holder.1707090075" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
<option id="org.eclipse.cdt.build.core.settings.holder.incpaths.586544031" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.338985256" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
<tool id="org.eclipse.cdt.build.core.settings.holder.1165165914" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
<option id="org.eclipse.cdt.build.core.settings.holder.incpaths.1379525985" name="Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.incpaths" valueType="includePath"/>
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
</tool>
</toolChain>
</folderInfo>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="RT-STM32F429-DISCOVERY-DMA2D.null.1703860681" name="RT-STM32F429-DISCOVERY-DMA2D"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="0.114656749">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="Default">
<resource resourceType="PROJECT" workspacePath="/RT-STM32F429-DISCOVERY-DMA2D"/>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
</cproject>

2
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.gitignore vendored Normal file
View File

@ -0,0 +1,2 @@
build/
.dep/

90
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.project Normal file
View File

@ -0,0 +1,90 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>RT-STM32F429-DISCOVERY-DMA2D</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
<dictionary>
<key>?name?</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildArguments</key>
<value>-j1</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildCommand</key>
<value>make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.contents</key>
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
</dictionary>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>os</name>
<type>2</type>
<locationURI>CHIBIOS/os</locationURI>
</link>
<link>
<name>test</name>
<type>2</type>
<locationURI>CHIBIOS/test</locationURI>
</link>
</linkedResources>
</projectDescription>

11
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.settings/language.settings.xml Normal file
View File

@ -0,0 +1,11 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="0.114656749" name="Default">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
</extension>
</configuration>
</project>

229
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile Normal file
View File

@ -0,0 +1,229 @@
##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# Linker extra options here.
ifeq ($(USE_LDOPT),)
USE_LDOPT =
endif
# Enable this if you want link time optimizations (LTO)
ifeq ($(USE_LTO),)
USE_LTO = yes
endif
# If enabled, this option allows to compile the application in THUMB mode.
ifeq ($(USE_THUMB),)
USE_THUMB = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
# If enabled, this option makes the build process faster by not compiling
# modules not used in the current configuration.
ifeq ($(USE_SMART_BUILD),)
USE_SMART_BUILD = yes
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Stack size to be allocated to the Cortex-M process stack. This stack is
# the stack used by the main() thread.
ifeq ($(USE_PROCESS_STACKSIZE),)
USE_PROCESS_STACKSIZE = 0x400
endif
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
# stack is used for processing interrupts and exceptions.
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
USE_EXCEPTIONS_STACKSIZE = 0x400
endif
# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
ifeq ($(USE_FPU),)
USE_FPU = no
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, sources and paths
#
# Define project name here
PROJECT = ch
# Imported source files and paths
CHIBIOS = ../../../..
# Startup files.
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/community/os/hal/ports/STM32/STM32F4xx/platform.mk
include $(CHIBIOS)/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
# Other files (optional).
include $(CHIBIOS)/test/rt/test.mk
# Define linker script file here
LDSCRIPT = $(CHIBIOS)/community/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(STARTUPSRC) \
$(KERNSRC) \
$(PORTSRC) \
$(OSALSRC) \
$(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
$(TESTSRC) \
$(CHIBIOS)/os/various/shell.c \
$(CHIBIOS)/os/hal/lib/streams/memstreams.c \
$(CHIBIOS)/os/hal/lib/streams/chprintf.c \
./main.c \
./ili9341.c \
./wolf3d_palette.c \
./res/wolf3d_vgagraph_chunk87.c \
./stmdrivers/stm32f4xx_fmc.c \
./stmdrivers/stm32f429i_discovery_sdram.c \
# eol
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC =
# C sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACSRC =
# C++ sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACPPSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCPPSRC =
# List ASM source files here
ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
$(CHIBIOS)/os/various \
$(CHIBIOS)/os/hal/lib/streams \
./res \
./stmdrivers \
# eol
#
# Project, sources and paths
##############################################################################
##############################################################################
# Compiler settings
#
MCU = cortex-m4
#TRGT = arm-elf-
TRGT = arm-none-eabi-
CC = $(TRGT)gcc
CPPC = $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
AR = $(TRGT)ar
OD = $(TRGT)objdump
SZ = $(TRGT)size
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
# ARM-specific options here
AOPT =
# THUMB-specific options here
TOPT = -mthumb -DTHUMB
# Define C warning options here
CWARN = -Wall -Wextra -Wstrict-prototypes
# Define C++ warning options here
CPPWARN = -Wall -Wextra
#
# Compiler settings
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user defines
##############################################################################
RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
include $(RULESPATH)/rules.mk

499
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/chconf.h Normal file
View File

@ -0,0 +1,499 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name System timers settings
* @{
*/
/*===========================================================================*/
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
*/
#define CH_CFG_ST_RESOLUTION 32
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#define CH_CFG_ST_FREQUENCY 1000
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#define CH_CFG_ST_TIMEDELTA 0
/** @} */
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
* @note The round robin preemption is not supported in tickless mode and
* must be set to zero in that case.
*/
#define CH_CFG_TIME_QUANTUM 0
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#define CH_CFG_MEMCORE_SIZE 0
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread. The application @p main()
* function becomes the idle thread and must implement an
* infinite loop.
*/
#define CH_CFG_NO_IDLE_THREAD FALSE
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#define CH_CFG_OPTIMIZE_SPEED TRUE
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Time Measurement APIs.
* @details If enabled then the time measurement APIs are included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_TM TRUE
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_REGISTRY TRUE
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_WAITEXIT TRUE
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_SEMAPHORES TRUE
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_MUTEXES TRUE
/**
* @brief Enables recursive behavior on mutexes.
* @note Recursive mutexes are heavier and have an increased
* memory footprint.
*
* @note The default is @p FALSE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
#define CH_CFG_USE_CONDVARS TRUE
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_CONDVARS.
*/
#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_EVENTS TRUE
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_EVENTS.
*/
#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_MESSAGES TRUE
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_MESSAGES.
*/
#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#define CH_CFG_USE_MAILBOXES TRUE
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_QUEUES TRUE
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_MEMCORE TRUE
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
* @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#define CH_CFG_USE_HEAP TRUE
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_MEMPOOLS TRUE
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
#define CH_CFG_USE_DYNAMIC TRUE
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_STATISTICS TRUE
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_SYSTEM_STATE_CHECK TRUE
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_ENABLE_CHECKS TRUE
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_ENABLE_ASSERTS TRUE
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_ENABLE_TRACE TRUE
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#define CH_DBG_ENABLE_STACK_CHECK TRUE
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_FILL_THREADS TRUE
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p FALSE.
* @note This debug option is not currently compatible with the
* tickless mode.
*/
#define CH_DBG_THREADS_PROFILING TRUE
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure.
*/
#define CH_CFG_THREAD_EXTRA_FIELDS \
/* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* Context switch code here.*/ \
}
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() { \
}
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() { \
}
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#define CH_CFG_IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#define CH_CFG_SYSTEM_TICK_HOOK() { \
/* System tick event code here.*/ \
}
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \
}
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

52
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (OpenOCD, Flash and Run).launch Normal file
View File

@ -0,0 +1,52 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
<stringAttribute key="bad_container_name" value="\RT-STM32F429-DISCOVERY-DMA2D\debug"/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 20&#13;&#10;monitor reset init&#13;&#10;monitor sleep 50&#13;&#10;"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-STM32F429-DISCOVERY-DMA2D"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.114656749"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/RT-STM32F429-DISCOVERY-DMA2D"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
</listAttribute>
</launchConfiguration>

52
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (Run Only).launch Normal file
View File

@ -0,0 +1,52 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
<stringAttribute key="bad_container_name" value="\RT-STM32F429-DISCOVERY-DMA2D\debug"/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 20&#13;&#10;monitor reset init&#13;&#10;monitor sleep 50&#13;&#10;"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-STM32F429-DISCOVERY-DMA2D"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.114656749"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/RT-STM32F429-DISCOVERY-DMA2D"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
</listAttribute>
</launchConfiguration>

334
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h Normal file
View File

@ -0,0 +1,334 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the DAC subsystem.
*/
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
#define HAL_USE_DAC FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI TRUE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

418
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/ili9341.c Normal file
View File

@ -0,0 +1,418 @@
/*
Copyright (C) 2013-2015 Andrea Zoppi
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file ili9341.c
* @brief ILI9341 TFT LCD diaplay controller driver.
* @note Does not support multiple calling threads natively.
*/
#include "ch.h"
#include "hal.h"
#include "ili9341.h"
/**
* @addtogroup ili9341
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#if !ILI9341_USE_CHECKS && !defined(__DOXYGEN__)
/* Disable checks as needed.*/
#ifdef osalDbgCheck
#undef osalDbgCheck
#endif
#define osalDbgCheck(c, func) { \
(void)(c), (void)__QUOTE_THIS(func)"()"; \
}
#ifdef osalDbgAssert
#undef osalDbgAssert
#endif
#define osalDbgAssert(c, m, r) { \
(void)(c); \
}
#ifdef osalDbgCheckClassS
#undef osalDbgCheckClassS
#endif
#define osalDbgCheckClassS() {}
#ifdef osalDbgCheckClassS
#undef osalDbgCheckClassS
#endif
#define osalDbgCheckClassI() {}
#endif /* ILI9341_USE_CHECKS */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/** @brief ILI9341D1 driver identifier.*/
ILI9341Driver ILI9341D1;
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Initializes the standard part of a @p ILI9341Driver structure.
*
* @param[out] driverp pointer to the @p ILI9341Driver object
*
* @init
*/
void ili9341ObjectInit(ILI9341Driver *driverp) {
osalDbgCheck(driverp != NULL);
driverp->state = ILI9341_STOP;
driverp->config = NULL;
#if (TRUE == ILI9341_USE_MUTUAL_EXCLUSION)
#if (TRUE == CH_CFG_USE_MUTEXES)
chMtxObjectInit(&driverp->lock);
#else
chSemObjectInit(&driverp->lock, 1);
#endif
#endif /* (TRUE == ILI9341_USE_MUTUAL_EXCLUSION) */
}
/**
* @brief Configures and activates the ILI9341 peripheral.
* @pre ILI9341 is stopped.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
* @param[in] configp pointer to the @p ILI9341Config object
*
* @api
*/
void ili9341Start(ILI9341Driver *driverp, const ILI9341Config *configp) {
chSysLock();
osalDbgCheck(driverp != NULL);
osalDbgCheck(configp != NULL);
osalDbgCheck(configp->spi != NULL);
osalDbgAssert(driverp->state == ILI9341_STOP, "invalid state");
spiSelectI(configp->spi);
spiUnselectI(configp->spi);
driverp->config = configp;
driverp->state = ILI9341_READY;
chSysUnlock();
}
/**
* @brief Deactivates the ILI9341 peripheral.
* @pre ILI9341 is ready.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
*
* @api
*/
void ili9341Stop(ILI9341Driver *driverp) {
chSysLock();
osalDbgCheck(driverp != NULL);
osalDbgAssert(driverp->state == ILI9341_READY, "invalid state");
driverp->state = ILI9341_STOP;
chSysUnlock();
}
#if ILI9341_USE_MUTUAL_EXCLUSION
/**
* @brief Gains exclusive access to the ILI9341 module.
* @details This function tries to gain ownership to the ILI9341 module, if the
* module is already being used then the invoking thread is queued.
* @pre In order to use this function the option
* @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled.
* @pre ILI9341 is ready.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
*
* @sclass
*/
void ili9341AcquireBusS(ILI9341Driver *driverp) {
osalDbgCheckClassS();
osalDbgCheck(driverp == &ILI9341D1);
osalDbgAssert(driverp->state == ILI9341_READY, "not ready");
#if (TRUE == CH_CFG_USE_MUTEXES)
chMtxLockS(&driverp->lock);
#else
chSemWaitS(&driverp->lock);
#endif
}
/**
* @brief Gains exclusive access to the ILI9341 module.
* @details This function tries to gain ownership to the ILI9341 module, if the
* module is already being used then the invoking thread is queued.
* @pre In order to use this function the option
* @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled.
* @pre ILI9341 is ready.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
*
* @api
*/
void ili9341AcquireBus(ILI9341Driver *driverp) {
chSysLock();
ili9341AcquireBusS(driverp);
chSysUnlock();
}
/**
* @brief Releases exclusive access to the ILI9341 module.
* @pre In order to use this function the option
* @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled.
* @pre ILI9341 is ready.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
*
* @sclass
*/
void ili9341ReleaseBusS(ILI9341Driver *driverp) {
osalDbgCheckClassS();
osalDbgCheck(driverp == &ILI9341D1);
osalDbgAssert(driverp->state == ILI9341_READY, "not ready");
#if (TRUE == CH_CFG_USE_MUTEXES)
chMtxUnlockS(&driverp->lock);
#else
chSemSignalI(&driverp->lock);
#endif
}
/**
* @brief Releases exclusive access to the ILI9341 module.
* @pre In order to use this function the option
* @p ILI9341_USE_MUTUAL_EXCLUSION must be enabled.
* @pre ILI9341 is ready.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
*
* @api
*/
void ili9341ReleaseBus(ILI9341Driver *driverp) {
chSysLock();
ili9341ReleaseBusS(driverp);
chSysUnlock();
}
#endif /* ILI9341_USE_MUTUAL_EXCLUSION */
#if ILI9341_IM == ILI9341_IM_4LSI_1 /* 4-wire, half-duplex */
/**
* @brief Asserts the slave select signal and prepares for transfers.
* @pre ILI9341 is ready.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
*
* @iclass
*/
void ili9341SelectI(ILI9341Driver *driverp) {
osalDbgCheckClassI();
osalDbgCheck(driverp != NULL);
osalDbgAssert(driverp->state == ILI9341_READY, "invalid state");
driverp->state = ILI9341_ACTIVE;
spiSelectI(driverp->config->spi);
}
/**
* @brief Asserts the slave select signal and prepares for transfers.
* @pre ILI9341 is ready.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
*
* @api
*/
void ili9341Select(ILI9341Driver *driverp) {
chSysLock();
ili9341SelectI(driverp);
chSysUnlock();
}
/**
* @brief Deasserts the slave select signal.
* @details The previously selected peripheral is unselected.
* @pre ILI9341 is active.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
*
* @iclass
*/
void ili9341UnselectI(ILI9341Driver *driverp) {
osalDbgCheckClassI();
osalDbgCheck(driverp != NULL);
osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state");
spiUnselectI(driverp->config->spi);
driverp->state = ILI9341_READY;
}
/**
* @brief Deasserts the slave select signal.
* @details The previously selected peripheral is unselected.
* @pre ILI9341 is active.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
*
* @iclass
*/
void ili9341Unselect(ILI9341Driver *driverp) {
chSysLock();
ili9341UnselectI(driverp);
chSysUnlock();
}
/**
* @brief Write command byte.
* @details Sends a command byte via SPI.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
* @param[in] cmd command byte
*
* @api
*/
void ili9341WriteCommand(ILI9341Driver *driverp, uint8_t cmd) {
osalDbgCheck(driverp != NULL);
osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state");
driverp->value = cmd;
palClearPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* !Cmd */
spiSend(driverp->config->spi, 1, &driverp->value);
}
/**
* @brief Write data byte.
* @details Sends a data byte via SPI.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
* @param[in] value data byte
*
* @api
*/
void ili9341WriteByte(ILI9341Driver *driverp, uint8_t value) {
osalDbgCheck(driverp != NULL);
osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state");
driverp->value = value;
palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */
spiSend(driverp->config->spi, 1, &driverp->value);
}
/**
* @brief Read data byte.
* @details Receives a data byte via SPI.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
*
* @return data byte
*
* @api
*/
uint8_t ili9341ReadByte(ILI9341Driver *driverp) {
osalDbgAssert(FALSE, "should not be used");
osalDbgCheck(driverp != NULL);
osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state");
palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */
spiReceive(driverp->config->spi, 1, &driverp->value);
return driverp->value;
}
/**
* @brief Write data chunk.
* @details Sends a data chunk via SPI.
* @pre The chunk must be accessed by DMA.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
* @param[in] chunk chunk bytes
* @param[in] length chunk length
*
* @api
*/
void ili9341WriteChunk(ILI9341Driver *driverp, const uint8_t chunk[],
size_t length) {
osalDbgCheck(driverp != NULL);
osalDbgCheck(chunk != NULL);
osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state");
if (length != 0) {
palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */
spiSend(driverp->config->spi, length, chunk);
}
}
/**
* @brief Read data chunk.
* @details Receives a data chunk via SPI.
* @pre The chunk must be accessed by DMA.
*
* @param[in] driverp pointer to the @p ILI9341Driver object
* @param[out] chunk chunk bytes
* @param[in] length chunk length
*
* @api
*/
void ili9341ReadChunk(ILI9341Driver *driverp, uint8_t chunk[],
size_t length) {
osalDbgCheck(driverp != NULL);
osalDbgCheck(chunk != NULL);
osalDbgAssert(driverp->state == ILI9341_ACTIVE, "invalid state");
if (length != 0) {
palSetPad(driverp->config->dcx_port, driverp->config->dcx_pad); /* Data */
spiReceive(driverp->config->spi, length, chunk);
}
}
#else /* ILI9341_IM == * */
#error "Only the ILI9341_IM_4LSI_1 interface mode is currently supported"
#endif /* ILI9341_IM == * */
/** @} */

593
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/ili9341.h Normal file
View File

@ -0,0 +1,593 @@
/*
Copyright (C) 2013-2015 Andrea Zoppi
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file ili9341.h
* @brief ILI9341 TFT LCD diaplay controller driver.
*/
#ifndef _ILI9341_H_
#define _ILI9341_H_
/**
* @addtogroup ili9341
* @{
*/
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ILI9341 regulative commands
* @{
*/
#define ILI9341_CMD_NOP (0x00) /**< No operation.*/
#define ILI9341_CMD_RESET (0x01) /**< Software reset.*/
#define ILI9341_GET_ID_INFO (0x04) /**< Get ID information.*/
#define ILI9341_GET_STATUS (0x09) /**< Get status.*/
#define ILI9341_GET_PWR_MODE (0x0A) /**< Get power mode.*/
#define ILI9341_GET_MADCTL (0x0B) /**< Get MADCTL.*/
#define ILI9341_GET_PIX_FMT (0x0C) /**< Get pixel format.*/
#define ILI9341_GET_IMG_FMT (0x0D) /**< Get image format.*/
#define ILI9341_GET_SIG_MODE (0x0E) /**< Get signal mode.*/
#define ILI9341_GET_SELF_DIAG (0x0F) /**< Get self-diagnostics.*/
#define ILI9341_CMD_SLEEP_ON (0x10) /**< Enter sleep mode.*/
#define ILI9341_CMD_SLEEP_OFF (0x11) /**< Exist sleep mode.*/
#define ILI9341_CMD_PARTIAL_ON (0x12) /**< Enter partial mode.*/
#define ILI9341_CMD_PARTIAL_OFF (0x13) /**< Exit partial mode.*/
#define ILI9341_CMD_INVERT_ON (0x20) /**< Enter inverted mode.*/
#define ILI9341_CMD_INVERT_OFF (0x21) /**< Exit inverted mode.*/
#define ILI9341_SET_GAMMA (0x26) /**< Set gamma params.*/
#define ILI9341_CMD_DISPLAY_OFF (0x28) /**< Disable display.*/
#define ILI9341_CMD_DISPLAY_ON (0x29) /**< Enable display.*/
#define ILI9341_SET_COL_ADDR (0x2A) /**< Set column address.*/
#define ILI9341_SET_PAGE_ADDR (0x2B) /**< Set page address.*/
#define ILI9341_SET_MEM (0x2C) /**< Set memory.*/
#define ILI9341_SET_COLOR (0x2D) /**< Set color.*/
#define ILI9341_GET_MEM (0x2E) /**< Get memory.*/
#define ILI9341_SET_PARTIAL_AREA (0x30) /**< Set partial area.*/
#define ILI9341_SET_VSCROLL (0x33) /**< Set vertical scroll def.*/
#define ILI9341_CMD_TEARING_ON (0x34) /**< Tearing line enabled.*/
#define ILI9341_CMD_TEARING_OFF (0x35) /**< Tearing line disabled.*/
#define ILI9341_SET_MEM_ACS_CTL (0x36) /**< Set mem access ctl.*/
#define ILI9341_SET_VSCROLL_ADDR (0x37) /**< Set vscroll start addr.*/
#define ILI9341_CMD_IDLE_OFF (0x38) /**< Exit idle mode.*/
#define ILI9341_CMD_IDLE_ON (0x39) /**< Enter idle mode.*/
#define ILI9341_SET_PIX_FMT (0x3A) /**< Set pixel format.*/
#define ILI9341_SET_MEM_CONT (0x3C) /**< Set memory continue.*/
#define ILI9341_GET_MEM_CONT (0x3E) /**< Get memory continue.*/
#define ILI9341_SET_TEAR_SCANLINE (0x44) /**< Set tearing scanline.*/
#define ILI9341_GET_TEAR_SCANLINE (0x45) /**< Get tearing scanline.*/
#define ILI9341_SET_BRIGHTNESS (0x51) /**< Set brightness.*/
#define ILI9341_GET_BRIGHTNESS (0x52) /**< Get brightness.*/
#define ILI9341_SET_DISPLAY_CTL (0x53) /**< Set display ctl.*/
#define ILI9341_GET_DISPLAY_CTL (0x54) /**< Get display ctl.*/
#define ILI9341_SET_CABC (0x55) /**< Set CABC.*/
#define ILI9341_GET_CABC (0x56) /**< Get CABC.*/
#define ILI9341_SET_CABC_MIN (0x5E) /**< Set CABC min.*/
#define ILI9341_GET_CABC_MIN (0x5F) /**< Set CABC max.*/
#define ILI9341_GET_ID1 (0xDA) /**< Get ID1.*/
#define ILI9341_GET_ID2 (0xDB) /**< Get ID2.*/
#define ILI9341_GET_ID3 (0xDC) /**< Get ID3.*/
/** @} */
/**
* @name ILI9341 extended commands
* @{
*/
#define ILI9341_SET_RGB_IF_SIG_CTL (0xB0) /**< RGB IF signal ctl.*/
#define ILI9341_SET_FRAME_CTL_NORMAL (0xB1) /**< Set frame ctl (normal).*/
#define ILI9341_SET_FRAME_CTL_IDLE (0xB2) /**< Set frame ctl (idle).*/
#define ILI9341_SET_FRAME_CTL_PARTIAL (0xB3) /**< Set frame ctl (partial).*/
#define ILI9341_SET_INVERSION_CTL (0xB4) /**< Set inversion ctl.*/
#define ILI9341_SET_BLANKING_PORCH_CTL (0xB5) /**< Set blanking porch ctl.*/
#define ILI9341_SET_FUNCTION_CTL (0xB6) /**< Set function ctl.*/
#define ILI9341_SET_ENTRY_MODE (0xB7) /**< Set entry mode.*/
#define ILI9341_SET_LIGHT_CTL_1 (0xB8) /**< Set backlight ctl 1.*/
#define ILI9341_SET_LIGHT_CTL_2 (0xB9) /**< Set backlight ctl 2.*/
#define ILI9341_SET_LIGHT_CTL_3 (0xBA) /**< Set backlight ctl 3.*/
#define ILI9341_SET_LIGHT_CTL_4 (0xBB) /**< Set backlight ctl 4.*/
#define ILI9341_SET_LIGHT_CTL_5 (0xBC) /**< Set backlight ctl 5.*/
#define ILI9341_SET_LIGHT_CTL_7 (0xBE) /**< Set backlight ctl 7.*/
#define ILI9341_SET_LIGHT_CTL_8 (0xBF) /**< Set backlight ctl 8.*/
#define ILI9341_SET_POWER_CTL_1 (0xC0) /**< Set power ctl 1.*/
#define ILI9341_SET_POWER_CTL_2 (0xC1) /**< Set power ctl 2.*/
#define ILI9341_SET_VCOM_CTL_1 (0xC5) /**< Set VCOM ctl 1.*/
#define ILI9341_SET_VCOM_CTL_2 (0xC6) /**< Set VCOM ctl 2.*/
#define ILI9341_SET_NVMEM (0xD0) /**< Set NVMEM data.*/
#define ILI9341_GET_NVMEM_KEY (0xD1) /**< Get NVMEM protect key.*/
#define ILI9341_GET_NVMEM_STATUS (0xD2) /**< Get NVMEM status.*/
#define ILI9341_GET_ID4 (0xD3) /**< Get ID4.*/
#define ILI9341_SET_PGAMMA (0xE0) /**< Set positive gamma.*/
#define ILI9341_SET_NGAMMA (0xE1) /**< Set negative gamma.*/
#define ILI9341_SET_DGAMMA_CTL_1 (0xE2) /**< Set digital gamma ctl 1.*/
#define ILI9341_SET_DGAMMA_CTL_2 (0xE3) /**< Set digital gamma ctl 2.*/
#define ILI9341_SET_IF_CTL (0xF6) /**< Set interface control.*/
/** @} */
/**
* @name ILI9341 interface modes
* @{
*/
#define ILI9341_IM_3LSI_1 (0x5) /**< 3-line serial, mode 1.*/
#define ILI9341_IM_3LSI_2 (0xD) /**< 3-line serial, mode 2.*/
#define ILI9341_IM_4LSI_1 (0x6) /**< 4-line serial, mode 1.*/
#define ILI9341_IM_4LSI_2 (0xE) /**< 4-line serial, mode 2.*/
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name ILI9341 configuration options
* @{
*/
/**
* @brief Enables the @p ili9341AcquireBus() and @p ili9341ReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ILI9341_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ILI9341_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief ILI9341 Interface Mode.
*/
#if !defined(ILI9341_IM) || defined(__DOXYGEN__)
#define ILI9341_IM (ILI9341_IM_4LSI_1)
#endif
/**
* @brief Enables checks for ILI9341 functions.
* @note Disabling this option saves both code and data space.
* @note Disabling checks by ChibiOS will automatically disable ILI9341
* checks.
*/
#if !defined(ILI9341_USE_CHECKS) || defined(__DOXYGEN__)
#define ILI9341_USE_CHECKS TRUE
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if ((TRUE == ILI9341_USE_MUTUAL_EXCLUSION) && \
(TRUE != CH_CFG_USE_MUTEXES) && \
(TRUE != CH_CFG_USE_SEMAPHORES))
#error "ILI9341_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES"
#endif
/* TODO: Add the remaining modes.*/
#if (ILI9341_IM != ILI9341_IM_4LSI_1)
#error "Only ILI9341_IM_4LSI_1 interface mode is supported currently"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/* Complex types forwarding.*/
typedef struct ILI9341Config ILI9341Config;
typedef enum ili9341state_t ili9341state_t;
typedef struct ILI9341Driver ILI9341Driver;
/**
* @brief ILI9341 driver configuration.
*/
typedef struct ILI9341Config {
SPIDriver *spi; /**< SPI driver used by ILI9341.*/
#if (ILI9341_IM == ILI9341_IM_4LSI_1)
ioportid_t dcx_port; /**< <tt>D/!C</tt> signal port.*/
uint16_t dcx_pad; /**< <tt>D/!C</tt> signal pad.*/
#endif /* ILI9341_IM == * */ /* TODO: Add all modes.*/
} ILI9341Config;
/**
* @brief ILI9341 driver state.
*/
typedef enum ili9341state_t {
ILI9341_UNINIT = (0), /**< Not initialized.*/
ILI9341_STOP = (1), /**< Stopped.*/
ILI9341_READY = (2), /**< Ready.*/
ILI9341_ACTIVE = (3), /**< Exchanging data.*/
} ili9341state_t;
/**
* @brief ILI9341 driver.
*/
typedef struct ILI9341Driver {
ili9341state_t state; /**< Driver state.*/
const ILI9341Config *config; /**< Driver configuration.*/
/* Multithreading stuff.*/
#if (TRUE == ILI9341_USE_MUTUAL_EXCLUSION)
#if (TRUE == CH_CFG_USE_MUTEXES)
mutex_t lock; /**< Multithreading lock.*/
#elif (TRUE == CH_CFG_USE_SEMAPHORES)
semaphore_t lock; /**< Multithreading lock.*/
#endif
#endif /* (TRUE == ILI9341_USE_MUTUAL_EXCLUSION) */
/* Temporary variables.*/
uint8_t value; /**< Non-stacked value, for SPI with CCM.*/
} ILI9341Driver;
/**
* @name ILI9341 command params (little endian)
* @{
*/
#pragma pack(push, 1)
typedef union {
struct ILI9341ParamBits_GET_ID_INFO {
uint8_t reserved_;
uint8_t ID1;
uint8_t ID2;
uint8_t ID3;
} bits;
uint8_t bytes[4];
} ILI9341Params_GET_ID_INFO;
typedef union {
struct ILI9341ParamBits_GET_STATUS {
unsigned _reserved_1 : 5; /* D[ 4: 0] */
unsigned tearing_mode : 1; /* D[ 5] */
unsigned gamma_curve : 3; /* D[ 8: 6] */
unsigned tearing : 1; /* D[ 9] */
unsigned display : 1; /* D[10] */
unsigned all_on : 1; /* D[11] */
unsigned all_off : 1; /* D[12] */
unsigned invert : 1; /* D[13] */
unsigned _reserved_2 : 1; /* D[14] */
unsigned vscroll : 1; /* D[15] */
unsigned normal : 1; /* D[16] */
unsigned sleep : 1; /* D[17] */
unsigned partial : 1; /* D[18] */
unsigned idle : 1; /* D[19] */
unsigned pixel_format : 3; /* D[22:20] */
unsigned _reserved_3 : 2; /* D[24:23] */
unsigned hrefr_rtl_nltr : 1; /* D[25] */
unsigned bgr_nrgb : 1; /* D[26] */
unsigned vrefr_btt_nttb : 1; /* D[27] */
unsigned transpose : 1; /* D[28] */
unsigned coladr_rtl_nltr : 1; /* D[29] */
unsigned rowadr_btt_nttb : 1; /* D[30] */
unsigned booster : 1; /* D[31] */
} bits;
uint8_t bytes[4];
} ILI9341Params_GET_STATUS;
typedef union {
struct ILI9341ParamBits_GET_PWR_MODE {
unsigned _reserved_1 : 2; /* D[1:0] */
unsigned display : 1; /* D[2] */
unsigned normal : 1; /* D[3] */
unsigned sleep : 1; /* D[4] */
unsigned partial : 1; /* D[5] */
unsigned idle : 1; /* D[6] */
unsigned booster : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_PWR_MODE;
typedef union {
struct ILI9341ParamBits_GET_MADCTL {
unsigned _reserved_1 : 2; /* D[1:0] */
unsigned refr_rtl_nltr : 1; /* D[2] */
unsigned bgr_nrgb : 1; /* D[3] */
unsigned refr_btt_nttb : 1; /* D[4] */
unsigned invert : 1; /* D[5] */
unsigned rtl_nltr : 1; /* D[6] */
unsigned btt_nttb : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_MADCTL;
typedef union {
struct ILI9341ParamBits_GET_PIX_FMT {
unsigned DBI : 3; /* D[2:0] */
unsigned _reserved_1 : 1; /* D[3] */
unsigned DPI : 3; /* D[6:4] */
unsigned RIM : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_PIX_FMT;
typedef union {
struct ILI9341ParamBits_GET_IMG_FMT {
unsigned gamma_curve : 3; /* D[2:0] */
unsigned _reserved_1 : 5; /* D[7:3] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_IMG_FMT;
typedef union {
struct ILI9341ParamBits_GET_SIG_MODE {
unsigned _reserved_1 : 2; /* D[1:0] */
unsigned data_enable : 1; /* D[2] */
unsigned pixel_clock : 1; /* D[3] */
unsigned vsync : 1; /* D[4] */
unsigned hsync : 1; /* D[5] */
unsigned tearing_mode : 1; /* D[6] */
unsigned tearing : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_SIG_MODE;
typedef union {
struct ILI9341ParamBits_GET_SELF_DIAG {
unsigned _reserved_1 : 6; /* D[5:0] */
unsigned func_err : 1; /* D[6] */
unsigned reg_err : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_SELF_DIAG;
typedef union {
struct ILI9341ParamBits_SET_GAMMA {
uint8_t gamma_curve; /* D[7:0] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_GAMMA;
typedef union {
struct ILI9341ParamBits_SET_COL_ADDR {
uint8_t SC_15_8; /* D[ 7: 0] */
uint8_t SC_7_0; /* D[15: 8] */
uint8_t EC_15_8; /* D[23:16] */
uint8_t EC_7_0; /* D[31:24] */
} bits;
uint8_t bytes[4];
} ILI9341Params_SET_COL_ADDR;
typedef union {
struct ILI9341ParamBits_SET_PAGE_ADDR {
uint8_t SP_15_8; /* D[ 7: 0] */
uint8_t SP_7_0; /* D[15: 8] */
uint8_t EP_15_8; /* D[23:16] */
uint8_t EP_7_0; /* D[31:24] */
} bits;
uint8_t bytes[4];
} ILI9341Params_SET_PAGE_ADDR;
typedef union {
struct ILI9341ParamBits_SET_PARTIAL_AREA {
uint8_t SR_15_8; /* D[ 7: 0] */
uint8_t SR_7_0; /* D[15: 8] */
uint8_t ER_15_8; /* D[23:16] */
uint8_t ER_7_0; /* D[31:24] */
} bits;
uint8_t bytes[4];
} ILI9341Params_SET_PARTIAL_AREA;
typedef union {
struct ILI9341ParamBits_SET_VSCROLL {
uint8_t TFA_15_8; /* D[ 7: 0] */
uint8_t TFA_7_0; /* D[15: 8] */
uint8_t VSA_15_8; /* D[23:16] */
uint8_t VSA_7_0; /* D[31:24] */
uint8_t BFA_15_8; /* D[39:32] */
uint8_t BFA_7_0; /* D[47:40] */
} bits;
uint8_t bytes[6];
} ILI9341Params_SET_VSCROLL;
typedef union {
struct ILI9341ParamBits_CMD_TEARING_ON {
unsigned M : 1; /* D[0] */
unsigned _reserved_1 : 7; /* D[7:1] */
} bits;
uint8_t bytes[1];
} ILI9341Params_CMD_TEARING_ON;
typedef union {
struct ILI9341ParamBits_SET_MEM_ACS_CTL {
unsigned _reserved_1 : 2; /* D[1:0] */
unsigned MH : 1; /* D[2] */
unsigned BGR : 1; /* D[3] */
unsigned ML : 1; /* D[4] */
unsigned MV : 1; /* D[5] */
unsigned MX : 1; /* D[6] */
unsigned MY : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_MEM_ACS_CTL;
typedef union {
struct ILI9341ParamBits_SET_VSCROLL_ADDR {
uint8_t VSP_15_8; /* D[ 7: 0] */
uint8_t VSP_7_0; /* D[15: 8] */
} bits;
uint8_t bytes[2];
} ILI9341Params_SET_VSCROLL_ADDR;
typedef union {
struct ILI9341ParamBits_SET_PIX_FMT {
unsigned DBI : 3; /* D[2:0] */
unsigned _reserved_1 : 1; /* D[3] */
unsigned DPI : 3; /* D[4:6] */
unsigned _reserved_2 : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_PIX_FMT;
typedef union {
struct ILI9341ParamBits_SET_TEAR_SCANLINE {
uint8_t STS_8; /* D[ 7: 0] */
uint8_t STS_7_0; /* D[15: 8] */
} bits;
uint8_t bytes[4];
} ILI9341Params_SET_TEAR_SCANLINE;
typedef union {
struct ILI9341ParamBits_GET_TEAR_SCANLINE {
uint8_t GTS_9_8; /* D[ 7: 0] */
uint8_t GTS_7_0; /* D[15: 8] */
} bits;
uint8_t bytes[2];
} ILI9341Params_GET_TEAR_SCANLINE;
typedef union {
struct ILI9341ParamBits_SET_BRIGHTNESS {
uint8_t DBV; /* D[7:0] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_BRIGHTNESS;
typedef union {
struct ILI9341ParamBits_GET_BRIGHTNESS {
uint8_t DBV; /* D[7:0] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_BRIGHTNESS;
typedef union {
struct ILI9341ParamBits_SET_DISPLAY_CTL {
unsigned _reserved_1 : 2; /* D[1:0] */
unsigned BL : 1; /* D[2] */
unsigned DD : 1; /* D[3] */
unsigned _reserved_2 : 1; /* D[4] */
unsigned BCTRL : 1; /* D[5] */
unsigned _reserved_3 : 1; /* D[7:6] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_DISPLAY_CTL;
typedef union {
struct ILI9341ParamBits_GET_DISPLAY_CTL {
unsigned _reserved_1 : 2; /* D[1:0] */
unsigned BL : 1; /* D[2] */
unsigned DD : 1; /* D[3] */
unsigned _reserved_2 : 1; /* D[4] */
unsigned BCTRL : 1; /* D[5] */
unsigned _reserved_3 : 1; /* D[7:6] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_DISPLAY_CTL;
typedef union {
struct ILI9341ParamBits_SET_CABC {
unsigned C : 2; /* D[1:0] */
unsigned _reserved_1 : 6; /* D[7:2] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_CABC;
typedef union {
struct ILI9341ParamBits_GET_CABC {
unsigned C : 2; /* D[1:0] */
unsigned _reserved_1 : 6; /* D[7:2] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_CABC;
typedef union {
struct ILI9341ParamBits_SET_CABC_MIN {
uint8_t CMB; /* D[7:0] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_CABC_MIN;
typedef union {
struct ILI9341ParamBits_GET_CABC_MIN {
uint8_t CMB; /* D[7:0] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_CABC_MIN;
#if 0 /* TODO: Extended command structs.*/
typedef union {
struct ILI9341ParamBits {
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
} bits;
uint8_t bytes[1];
} ILI9341Params_;
typedef union {
struct ILI9341ParamBits {
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
} bits;
uint8_t bytes[1];
} ILI9341Params_;
#endif /*0*/
#pragma pack(pop)
/** @} */
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
extern ILI9341Driver ILI9341D1;
#ifdef __cplusplus
extern "C" {
#endif
void ili9341ObjectInit(ILI9341Driver *driverp);
void ili9341Start(ILI9341Driver *driverp, const ILI9341Config *configp);
void ili9341Stop(ILI9341Driver *driverp);
#if (ILI9341_USE_MUTUAL_EXCLUSION == TRUE)
void ili9341AcquireBusS(ILI9341Driver *driverp);
void ili9341AcquireBus(ILI9341Driver *driverp);
void ili9341ReleaseBusS(ILI9341Driver *driverp);
void ili9341ReleaseBus(ILI9341Driver *driverp);
#endif /* (ILI9341_USE_MUTUAL_EXCLUSION == TRUE) */
void ili9341SelectI(ILI9341Driver *driverp);
void ili9341Select(ILI9341Driver *driverp);
void ili9341UnselectI(ILI9341Driver *driverp);
void ili9341Unselect(ILI9341Driver *driverp);
void ili9341WriteCommand(ILI9341Driver *driverp, uint8_t cmd);
void ili9341WriteByte(ILI9341Driver *driverp, uint8_t value);
uint8_t ili9341ReadByte(ILI9341Driver *driverp);
void ili9341WriteChunk(ILI9341Driver *driverp, const uint8_t chunk[],
size_t length);
void ili9341ReadChunk(ILI9341Driver *driverp, uint8_t chunk[],
size_t length);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* _ILI9341_H_ */

785
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c Normal file
View File

@ -0,0 +1,785 @@
/*
Copyright (C) 2013-2015 Andrea Zoppi
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
#include "test.h"
#include "chprintf.h"
#include "shell.h"
#if HAL_USE_SERIAL_USB
#include "usbcfg.h"
#endif
#include "stmdrivers/stm32f429i_discovery_sdram.h"
#include "stmdrivers/stm32f4xx_fmc.h"
#include "ili9341.h"
#include "stm32_ltdc.h"
#include "stm32_dma2d.h"
#include "res/wolf3d_vgagraph_chunk87.h"
#define IS42S16400J_SIZE (8 * 1024 * 1024)
/*
* Erases the whole SDRAM bank.
*/
static void sdram_bulk_erase(void) {
volatile uint8_t *p = (volatile uint8_t *)SDRAM_BANK_ADDR;
volatile uint8_t *end = p + IS42S16400J_SIZE;
while (p < end)
*p++ = 0;
}
/*
* Red LED blinker thread, times are in milliseconds.
*/
static THD_WORKING_AREA(waThread1, 128);
static THD_FUNCTION(Thread1, arg) {
(void)arg;
chRegSetThreadName("blinker1");
while (true) {
palClearPad(GPIOG, GPIOG_LED4_RED);
chThdSleepMilliseconds(500);
palSetPad(GPIOG, GPIOG_LED4_RED);
chThdSleepMilliseconds(500);
}
}
/*
* Green LED blinker thread, times are in milliseconds.
*/
static THD_WORKING_AREA(waThread2, 128);
static THD_FUNCTION(Thread2, arg) {
(void)arg;
chRegSetThreadName("blinker2");
while (true) {
palClearPad(GPIOG, GPIOG_LED3_GREEN);
chThdSleepMilliseconds(250);
palSetPad(GPIOG, GPIOG_LED3_GREEN);
chThdSleepMilliseconds(250);
}
}
/*===========================================================================*/
/* LTDC related. */
/*===========================================================================*/
static uint8_t frame_buffer[240 * 320 * 3] __attribute__((section(".ram7")));
static uint8_t view_buffer[240 * 320];
extern const ltdc_color_t wolf3d_palette[256];
static const ltdc_window_t ltdc_fullscreen_wincfg = {
0,
240 - 1,
0,
320 - 1
};
static const ltdc_frame_t ltdc_view_frmcfg1 = {
view_buffer,
240,
320,
240 * sizeof(uint8_t),
LTDC_FMT_L8
};
static const ltdc_laycfg_t ltdc_view_laycfg1 = {
&ltdc_view_frmcfg1,
&ltdc_fullscreen_wincfg,
LTDC_COLOR_FUCHSIA,
0xFF,
0x980088,
wolf3d_palette,
256,
LTDC_BLEND_FIX1_FIX2,
LTDC_LEF_ENABLE | LTDC_LEF_PALETTE
};
static const ltdc_frame_t ltdc_screen_frmcfg1 = {
frame_buffer,
240,
320,
240 * 3,
LTDC_FMT_RGB888
};
static const ltdc_laycfg_t ltdc_screen_laycfg1 = {
&ltdc_screen_frmcfg1,
&ltdc_fullscreen_wincfg,
LTDC_COLOR_FUCHSIA,
0xFF,
0x980088,
NULL,
0,
LTDC_BLEND_FIX1_FIX2,
LTDC_LEF_ENABLE
};
static const LTDCConfig ltdc_cfg = {
/* Display specifications.*/
240, /**< Screen pixel width.*/
320, /**< Screen pixel height.*/
10, /**< Horizontal sync pixel width.*/
2, /**< Vertical sync pixel height.*/
20, /**< Horizontal back porch pixel width.*/
2, /**< Vertical back porch pixel height.*/
10, /**< Horizontal front porch pixel width.*/
4, /**< Vertical front porch pixel height.*/
0, /**< Driver configuration flags.*/
/* ISR callbacks.*/
NULL, /**< Line Interrupt ISR, or @p NULL.*/
NULL, /**< Register Reload ISR, or @p NULL.*/
NULL, /**< FIFO Underrun ISR, or @p NULL.*/
NULL, /**< Transfer Error ISR, or @p NULL.*/
/* Color and layer settings.*/
LTDC_COLOR_TEAL,
&ltdc_view_laycfg1,
NULL
};
extern LTDCDriver LTDCD1;
const SPIConfig spi_cfg5 = {
NULL,
GPIOC,
GPIOC_SPI5_LCD_CS,
((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR
};
extern SPIDriver SPID5;
const ILI9341Config ili9341_cfg = {
&SPID5,
GPIOD,
GPIOD_LCD_WRX
};
static void initialize_lcd(void) {
static const uint8_t pgamma[15] = {
0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78,
0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00
};
static const uint8_t ngamma[15] = {
0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33,
0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F
};
ILI9341Driver *const lcdp = &ILI9341D1;
/* XOR-checkerboard texture.*/
unsigned x, y;
for (y = 0; y < 320; ++y)
for (x = 0; x < 240; ++x)
view_buffer[y * 240 + x] = (uint8_t)(x ^ y);
ili9341AcquireBus(lcdp);
ili9341Select(lcdp);
ili9341WriteCommand(lcdp, ILI9341_SET_FRAME_CTL_NORMAL);
ili9341WriteByte(lcdp, 0x00);
ili9341WriteByte(lcdp, 0x1B);
ili9341WriteCommand(lcdp, ILI9341_SET_FUNCTION_CTL);
ili9341WriteByte(lcdp, 0x0A);
ili9341WriteByte(lcdp, 0xA2);
ili9341WriteCommand(lcdp, ILI9341_SET_POWER_CTL_1);
ili9341WriteByte(lcdp, 0x10);
ili9341WriteCommand(lcdp, ILI9341_SET_POWER_CTL_2);
ili9341WriteByte(lcdp, 0x10);
ili9341WriteCommand(lcdp, ILI9341_SET_VCOM_CTL_1);
ili9341WriteByte(lcdp, 0x45);
ili9341WriteByte(lcdp, 0x15);
ili9341WriteCommand(lcdp, ILI9341_SET_VCOM_CTL_2);
ili9341WriteByte(lcdp, 0x90);
ili9341WriteCommand(lcdp, ILI9341_SET_MEM_ACS_CTL);
ili9341WriteByte(lcdp, 0xC8);
ili9341WriteCommand(lcdp, ILI9341_SET_RGB_IF_SIG_CTL);
ili9341WriteByte(lcdp, 0xC2);
ili9341WriteCommand(lcdp, ILI9341_SET_FUNCTION_CTL);
ili9341WriteByte(lcdp, 0x0A);
ili9341WriteByte(lcdp, 0xA7);
ili9341WriteByte(lcdp, 0x27);
ili9341WriteByte(lcdp, 0x04);
ili9341WriteCommand(lcdp, ILI9341_SET_COL_ADDR);
ili9341WriteByte(lcdp, 0x00);
ili9341WriteByte(lcdp, 0x00);
ili9341WriteByte(lcdp, 0x00);
ili9341WriteByte(lcdp, 0xEF);
ili9341WriteCommand(lcdp, ILI9341_SET_PAGE_ADDR);
ili9341WriteByte(lcdp, 0x00);
ili9341WriteByte(lcdp, 0x00);
ili9341WriteByte(lcdp, 0x01);
ili9341WriteByte(lcdp, 0x3F);
ili9341WriteCommand(lcdp, ILI9341_SET_IF_CTL);
ili9341WriteByte(lcdp, 0x01);
ili9341WriteByte(lcdp, 0x00);
ili9341WriteByte(lcdp, 0x06);
ili9341WriteCommand(lcdp, ILI9341_SET_GAMMA);
ili9341WriteByte(lcdp, 0x01);
ili9341WriteCommand(lcdp, ILI9341_SET_PGAMMA);
ili9341WriteChunk(lcdp, pgamma, 15);
ili9341WriteCommand(lcdp, ILI9341_SET_NGAMMA);
ili9341WriteChunk(lcdp, ngamma, 15);
ili9341WriteCommand(lcdp, ILI9341_CMD_SLEEP_OFF);
chThdSleepMilliseconds(10);
ili9341WriteCommand(lcdp, ILI9341_CMD_DISPLAY_ON);
ili9341WriteCommand(lcdp, ILI9341_SET_MEM);
chThdSleepMilliseconds(10);
ili9341Unselect(lcdp);
ili9341ReleaseBus(lcdp);
}
static const DMA2DConfig dma2d_cfg = {
/* ISR callbacks.*/
NULL, /**< Configuration error, or @p NULL.*/
NULL, /**< Palette transfer done, or @p NULL.*/
NULL, /**< Palette access error, or @p NULL.*/
NULL, /**< Transfer watermark, or @p NULL.*/
NULL, /**< Transfer complete, or @p NULL.*/
NULL /**< Transfer error, or @p NULL.*/
};
static const dma2d_palcfg_t dma2d_palcfg = {
wolf3d_palette,
256,
DMA2D_FMT_ARGB8888
};
static const dma2d_laycfg_t dma2d_bg_laycfg = {
view_buffer,
0,
DMA2D_FMT_L8,
DMA2D_COLOR_RED,
0xFF,
&dma2d_palcfg
};
static const dma2d_laycfg_t dma2d_fg_laycfg = {
(void *)wolf3d_vgagraph_chunk87,
0,
DMA2D_FMT_L8,
DMA2D_COLOR_LIME,
0xFF,
&dma2d_palcfg
};
static const dma2d_laycfg_t dma2d_frame_laycfg = {
frame_buffer,
0,
DMA2D_FMT_RGB888,
DMA2D_COLOR_BLUE,
0xFF,
NULL
};
static void dma2d_test(void) {
DMA2DDriver *const dma2dp = &DMA2DD1;
LTDCDriver *const ltdcp = &LTDCD1;
chThdSleepSeconds(1);
ltdcBgSetConfig(ltdcp, &ltdc_screen_laycfg1);
ltdcReload(ltdcp, TRUE);
dma2dAcquireBus(dma2dp);
/* Target the frame buffer by default.*/
dma2dBgSetConfig(dma2dp, &dma2d_frame_laycfg);
dma2dFgSetConfig(dma2dp, &dma2d_frame_laycfg);
dma2dOutSetConfig(dma2dp, &dma2d_frame_laycfg);
/* Copy the background.*/
dma2dFgSetConfig(dma2dp, &dma2d_bg_laycfg);
dma2dJobSetMode(dma2dp, DMA2D_JOB_CONVERT);
dma2dJobSetSize(dma2dp, 240, 320);
dma2dJobExecute(dma2dp);
/* Draw the splashscren picture at (8, 0).*/
dma2dFgSetConfig(dma2dp, &dma2d_fg_laycfg);
dma2dOutSetAddress(dma2dp, dma2dComputeAddress(
frame_buffer, ltdc_screen_frmcfg1.pitch, DMA2D_FMT_RGB888, 8, 0
));
dma2dOutSetWrapOffset(dma2dp, ltdc_screen_frmcfg1.width - 200);
dma2dJobSetMode(dma2dp, DMA2D_JOB_CONVERT);
dma2dJobSetSize(dma2dp, 200, 320);
dma2dJobExecute(dma2dp);
dma2dReleaseBus(dma2dp);
}
/*===========================================================================*/
/* Command line related. */
/*===========================================================================*/
#define RTT2MS(ticks) ((ticks) / (STM32_HCLK / 1000UL))
#if HAL_USE_SERIAL_USB
/* Virtual serial port over USB.*/
SerialUSBDriver SDU1;
#endif
#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
#define TEST_WA_SIZE THD_WORKING_AREA_SIZE(256)
static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) {
size_t n, size;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: mem\r\n");
return;
}
n = chHeapStatus(NULL, &size);
chprintf(chp, "core free memory : %u bytes\r\n", chCoreGetStatusX());
chprintf(chp, "heap fragments : %u\r\n", n);
chprintf(chp, "heap free total : %u bytes\r\n", size);
}
static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) {
static const char *states[] = {CH_STATE_NAMES};
thread_t *tp;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: threads\r\n");
return;
}
chprintf(chp, " addr stack prio refs state time\r\n");
tp = chRegFirstThread();
do {
chprintf(chp, "%08lx %08lx %4lu %4lu %9s\r\n",
(uint32_t)tp, (uint32_t)tp->p_ctx.r13,
(uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1),
states[tp->p_state]);
tp = chRegNextThread(tp);
} while (tp != NULL);
}
static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) {
thread_t *tp;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: test\r\n");
return;
}
tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriorityX(),
TestThread, chp);
if (tp == NULL) {
chprintf(chp, "out of memory\r\n");
return;
}
chThdWait(tp);
}
static void cmd_reset(BaseSequentialStream *chp, int argc, char *argv[]) {
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: reset\r\n");
return;
}
chprintf(chp, "Will reset in 200ms\r\n");
chThdSleepMilliseconds(200);
NVIC_SystemReset();
}
static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) {
uint32_t counter = 0;
uint8_t ubWritedata_8b = 0x3C;
uint32_t uwReadwritestatus = 0;
time_measurement_t tm;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: write\r\n");
return;
}
chTMObjectInit(&tm);
chTMStartMeasurementX(&tm);
/* Write data value to all SDRAM memory */
for (counter = 0; counter < IS42S16400J_SIZE; counter++)
{
*(__IO uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)(ubWritedata_8b + counter);
}
chTMStopMeasurementX(&tm);
uint32_t write_ms = RTT2MS(tm.last);
if (!uwReadwritestatus) {
chprintf(chp, "SDRAM written in %dms.\r\n", write_ms);
}
}
static void cmd_erase(BaseSequentialStream *chp, int argc, char *argv[]) {
uint32_t counter = 0;
uint32_t uwReadwritestatus = 0;
time_measurement_t tm;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: erase\r\n");
return;
}
chTMObjectInit(&tm);
//XXX chTMStartMeasurement(&tm);
/* Write data value to all SDRAM memory */
/* Erase SDRAM memory */
for (counter = 0; counter < IS42S16400J_SIZE; counter++)
{
*(__IO uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)0x0;
}
//XXX chTMStopMeasurement(&tm);
uint32_t write_ms = 0;//XXX RTT2MS(tm.last);
if (!uwReadwritestatus) {
chprintf(chp, "SDRAM erased in %dms.\r\n", write_ms);
}
}
static void cmd_selfrefresh(BaseSequentialStream *chp, int argc, char *argv[]) {
(void)argv;
FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
if (argc > 0) {
chprintf(chp, "Usage: selfrefresh\r\n");
return;
}
/* Program a self-refresh mode command */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_Selfrefresh;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
/* Send the command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) {
}
/* Check the bank mode status */
if(FMC_GetModeStatus(FMC_Bank2_SDRAM) != FMC_SelfRefreshMode_Status) {
chprintf(chp, "SDRAM is not in self refresh mode, command FAILED.\r\n");
} else {
chprintf(chp, "SDRAM is in self refresh mode.\r\n");
}
}
static void cmd_normal(BaseSequentialStream *chp, int argc, char *argv[]) {
(void)argv;
FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
if (argc > 0) {
chprintf(chp, "Usage: normal\r\n");
return;
}
/* Program a self-refresh mode command */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_normal;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
/* Send the command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) {
}
/* Check the bank mode status */
if(FMC_GetModeStatus(FMC_Bank2_SDRAM) != FMC_NormalMode_Status) {
chprintf(chp, "SDRAM is not in normal mode, command FAILED.\r\n");
} else {
chprintf(chp, "SDRAM is in normal mode.\r\n");
}
}
static void cmd_check(BaseSequentialStream *chp, int argc, char *argv[]) {
uint32_t counter = 0;
uint8_t ubWritedata_8b = 0x3C, ubReaddata_8b = 0;
uint32_t uwReadwritestatus = 0;
time_measurement_t tm;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: check\r\n");
return;
}
chTMObjectInit(&tm);
chTMStartMeasurementX(&tm);
/* Read back SDRAM memory and check content correctness*/
counter = 0;
uwReadwritestatus = 0;
while ((counter < IS42S16400J_SIZE) && (uwReadwritestatus == 0))
{
ubReaddata_8b = *(__IO uint8_t*)(SDRAM_BANK_ADDR + counter);
if ( ubReaddata_8b != (uint8_t)(ubWritedata_8b + counter))
{
uwReadwritestatus = 1;
chprintf(chp, "Error at %d, expected %d but read %d.\r\n", counter, ubWritedata_8b + counter, ubReaddata_8b);
}
counter++;
}
chTMStopMeasurementX(&tm);
uint32_t check_ms = RTT2MS(tm.last);
//FIXME time this
if (!uwReadwritestatus) {
chprintf(chp, "SDRAM read and check completed successfully in %dms.\r\n", check_ms);
}
}
static void cmd_sdram(BaseSequentialStream *chp, int argc, char *argv[]) {
uint32_t counter = 0;
uint8_t ubWritedata_8b = 0x3C, ubReaddata_8b = 0;
uint32_t uwReadwritestatus = 0;
time_measurement_t tm;
(void)argv;
if (argc > 0) {
chprintf(chp, "Usage: sdram\r\n");
return;
}
chTMObjectInit(&tm);
chTMStartMeasurementX(&tm);
// /* Erase SDRAM memory */
// for (counter = 0; counter < IS42S16400J_SIZE; counter++)
// {
// *(__IO uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)0x0;
// }
/* Write data value to all SDRAM memory */
for (counter = 0; counter < IS42S16400J_SIZE; counter++)
{
*(__IO uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)(ubWritedata_8b + counter);
}
chTMStopMeasurementX(&tm);
uint32_t write_ms = RTT2MS(tm.last);
chTMStartMeasurementX(&tm);
/* Read back SDRAM memory */
counter = 0;
while ((counter < IS42S16400J_SIZE))
{
ubReaddata_8b = *(__IO uint8_t*)(SDRAM_BANK_ADDR + counter);
counter++;
}
chTMStopMeasurementX(&tm);
uint32_t read_ms = RTT2MS(tm.last);
/* Read back SDRAM memory and check content correctness*/
counter = 0;
uwReadwritestatus = 0;
while ((counter < IS42S16400J_SIZE) && (uwReadwritestatus == 0))
{
ubReaddata_8b = *(__IO uint8_t*)(SDRAM_BANK_ADDR + counter);
if ( ubReaddata_8b != (uint8_t)(ubWritedata_8b + counter))
{
uwReadwritestatus = 1;
chprintf(chp, "Error at %d, expected %d but read %d.\r\n", counter, ubWritedata_8b + counter, ubReaddata_8b);
}
counter++;
}
if (!uwReadwritestatus) {
chprintf(chp, "SDRAM test completed successfully, writing entire memory took %dms, reading it took %dms.\r\n", write_ms, read_ms);
}
}
static const ShellCommand commands[] = {
{"mem", cmd_mem},
{"threads", cmd_threads},
{"test", cmd_test},
{"sdram", cmd_sdram},
{"reset", cmd_reset},
{"write", cmd_write},
{"check", cmd_check},
{"erase", cmd_erase},
{"selfrefresh", cmd_selfrefresh},
{"normal", cmd_normal},
{NULL, NULL}
};
static const ShellConfig shell_cfg1 = {
#if HAL_USE_SERIAL_USB
(BaseSequentialStream *)&SDU1,
#else
(BaseSequentialStream *)&SD1,
#endif
commands
};
/*===========================================================================*/
/* Initialization and main thread. */
/*===========================================================================*/
/*
* Application entry point.
*/
int main(void) {
thread_t *shelltp = NULL;
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/*
* Shell manager initialization.
*/
shellInit();
#if HAL_USE_SERIAL_USB
/*
* Initializes a serial-over-USB CDC driver.
*/
sduObjectInit(&SDU1);
sduStart(&SDU1, &serusbcfg);
/*
* Activates the USB driver and then the USB bus pull-up on D+.
* Note, a delay is inserted in order to not have to disconnect the cable
* after a reset.
*/
usbDisconnectBus(serusbcfg.usbp);
chThdSleepMilliseconds(1000);
usbStart(serusbcfg.usbp, &usbcfg);
usbConnectBus(serusbcfg.usbp);
#else
/*
* Initializes serial port.
*/
sdStart(&SD1, NULL);
#endif /* HAL_USE_SERIAL_USB */
/*
* Initialise SDRAM, board.h has already configured GPIO correctly (except that ST example uses 50MHz not 100MHz?)
*/
SDRAM_Init();
sdram_bulk_erase();
/*
* Activates the LCD-related drivers.
*/
spiStart(&SPID5, &spi_cfg5);
ili9341Start(&ILI9341D1, &ili9341_cfg);
initialize_lcd();
ltdcStart(&LTDCD1, &ltdc_cfg);
/*
* Activates the DMA2D-related drivers.
*/
dma2dStart(&DMA2DD1, &dma2d_cfg);
dma2d_test();
/*
* Creating the blinker threads.
*/
chThdCreateStatic(waThread1, sizeof(waThread1),
NORMALPRIO + 10, Thread1, NULL);
chThdCreateStatic(waThread2, sizeof(waThread2),
NORMALPRIO + 10, Thread2, NULL);
/*
* Normal main() thread activity, in this demo it just performs
* a shell respawn upon its termination.
*/
while (true) {
if (!shelltp) {
#if HAL_USE_SERIAL_USB
if (SDU1.config->usbp->state == USB_ACTIVE) {
/* Spawns a new shell.*/
shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
}
#else
shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
#endif
}
else {
/* If the previous shell exited.*/
if (chThdTerminatedX(shelltp)) {
/* Recovers memory of the previous shell.*/
chThdRelease(shelltp);
shelltp = NULL;
}
}
chThdSleepMilliseconds(500);
}
}

355
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h Normal file
View File

@ -0,0 +1,355 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _MCUCONF_H_
#define _MCUCONF_H_
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 8
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_SAISRC STM32_SAISRC_PLL
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIQ_VALUE 7
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
/*
* SDC driver system settings.
*/
#define STM32_SDC_SDIO_DMA_PRIORITY 3
#define STM32_SDC_SDIO_IRQ_PRIORITY 9
#define STM32_SDC_WRITE_TIMEOUT_MS 250
#define STM32_SDC_READ_TIMEOUT_MS 25
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 TRUE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_USE_SPI5 TRUE
#define STM32_SPI_USE_SPI6 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI5_DMA_PRIORITY 1
#define STM32_SPI_SPI6_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 FALSE
#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
/*
* LTDC driver system settings.
*/
#define STM32_LTDC_USE_LTDC TRUE
#define STM32_LTDC_EV_IRQ_PRIORITY 11
#define STM32_LTDC_ER_IRQ_PRIORITY 11
/*
* DMA2D driver system settings.
*/
#define STM32_DMA2D_USE_DMA2D TRUE
#define STM32_DMA2D_IRQ_PRIORITY 11
#endif /* _MCUCONF_H_ */

29
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/readme.txt Normal file
View File

@ -0,0 +1,29 @@
*****************************************************************************
** ChibiOS/RT port for ARM-Cortex-M4 STM32F429. **
*****************************************************************************
** TARGET **
The demo runs on an ST STM32F429I-Discovery board.
** The Demo **
A simple command shell is activated on virtual serial port SD1.
The demo makes use of FMC, LTDC, and DMA2D peripherals to show graphical
contents on the display of the board, composed both on the on-chip SRAM
and the on-board SDRAM.
** Build Procedure **
The demo has been tested by using the free Codesourcery GCC-based toolchain
and YAGARTO. just modify the TRGT line in the makefile in order to use
different GCC toolchains.
** Notes **
Some files used by the demo are not part of ChibiOS/RT but are copyright of
ST Microelectronics and are licensed under a different license.
Also note that not all the files present in the ST library are distributed
with ChibiOS/RT, you can find the whole library on the ST web site:
http://www.st.com

BIN
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bin Normal file
View File

Binary file not shown.

BIN
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/chunk87.bmp Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 64 KiB

BIN
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_palette.gif Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 22 KiB

4005
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.c Normal file
View File

File diff suppressed because it is too large Load Diff

9
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/res/wolf3d_vgagraph_chunk87.h Normal file
View File

@ -0,0 +1,9 @@
/* Generated by bin2c, do not edit manually */
#ifndef __wolf3d_vgagraph_chunk87_h_included
#define __wolf3d_vgagraph_chunk87_h_included
/* Contents of file chunk87.bin */
#define wolf3d_vgagraph_chunk87_size 64000
extern const unsigned char wolf3d_vgagraph_chunk87[64000];
#endif /* __wolf3d_vgagraph_chunk87_h_included */

332
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.c Normal file
View File

@ -0,0 +1,332 @@
#include "ch.h"
#include "hal.h"
#include "stm32f429i_discovery_sdram.h"
#include "stm32f4xx_fmc.h"
/**
* @brief Configures the FMC and GPIOs to interface with the SDRAM memory.
* This function must be called before any read/write operation
* on the SDRAM.
* @param None
* @retval None
*/
void SDRAM_Init(void)
{
FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure;
FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure;
/* Enable FMC clock */
rccEnableAHB3(RCC_AHB3ENR_FMCEN, FALSE);
/* FMC Configuration ---------------------------------------------------------*/
/* FMC SDRAM Bank configuration */
/* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */
/* TMRD: 2 Clock cycles */
FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
/* TXSR: min=70ns (6x11.90ns) */
FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7;
/* TRAS: min=42ns (4x11.90ns) max=120k (ns) */
FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
/* TRC: min=63 (6x11.90ns) */
FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7;
/* TWR: 2 Clock cycles */
FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
/* TRP: 15ns => 2x11.90ns */
FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
/* TRCD: 15ns => 2x11.90ns */
FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
/* FMC SDRAM control configuration */
FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM;
/* Row addressing: [7:0] */
FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
/* Column addressing: [11:0] */
FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;
FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH;
FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY;
FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD;
FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST;
FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
/* FMC SDRAM bank initialization */
FMC_SDRAMInit(&FMC_SDRAMInitStructure);
/* FMC SDRAM device initialization sequence */
SDRAM_InitSequence();
}
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+--------------------+--------------------+
+ SDRAM pins assignment +
+-------------------+--------------------+--------------------+--------------------+
| PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
| PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
| PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK |
| PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS |
| PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+
| PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 |
| PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS |
+-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 |
| PE13 <-> FMC_D10 | PF13 <-> FMC_A7 |
| PE14 <-> FMC_D11 | PF14 <-> FMC_A8 |
| PE15 <-> FMC_D12 | PF15 <-> FMC_A9 |
+-------------------+--------------------+--------------------+
| PB5 <-> FMC_SDCKE1|
| PB6 <-> FMC_SDNE1 |
| PC0 <-> FMC_SDNWE |
+-------------------+
*/
// /* Common GPIO configuration */
// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
// GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
//
// /* GPIOB configuration */
// GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOB, GPIO_PinSource6 , GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6;
//
// GPIO_Init(GPIOB, &GPIO_InitStructure);
//
// /* GPIOC configuration */
// GPIO_PinAFConfig(GPIOC, GPIO_PinSource0 , GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
//
// GPIO_Init(GPIOC, &GPIO_InitStructure);
//
// /* GPIOD configuration */
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 |
// GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
// GPIO_Pin_15;
//
// GPIO_Init(GPIOD, &GPIO_InitStructure);
//
// /* GPIOE configuration */
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 |
// GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
// GPIO_Pin_14 | GPIO_Pin_15;
//
// GPIO_Init(GPIOE, &GPIO_InitStructure);
//
// /* GPIOF configuration */
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
// GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 |
// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
// GPIO_Pin_14 | GPIO_Pin_15;
//
// GPIO_Init(GPIOF, &GPIO_InitStructure);
//
// /* GPIOG configuration */
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC);
//
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 |
// GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15;
//
// GPIO_Init(GPIOG, &GPIO_InitStructure);
/**
* @brief Executes the SDRAM memory initialization sequence.
* @param None.
* @retval None.
*/
void SDRAM_InitSequence(void)
{
FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
uint32_t tmpr = 0;
/* Step 3 --------------------------------------------------------------------*/
/* Configure a clock configuration enable command */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
//In the ST example, this is 100ms, but the 429 RM says 100us is typical, and
//the ISSI datasheet confirms this. 1ms seems plenty, and is much shorter than
//refresh interval, meaning we won't risk losing contents if the SDRAM is in self-refresh
//mode
/* Step 4 --------------------------------------------------------------------*/
/* Insert 1 ms delay */
chThdSleepMilliseconds(1);
/* Step 5 --------------------------------------------------------------------*/
/* Configure a PALL (precharge all) command */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Step 6 --------------------------------------------------------------------*/
/* Configure a Auto-Refresh command */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the first command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the second command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Step 7 --------------------------------------------------------------------*/
/* Program the external memory mode register */
tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
SDRAM_MODEREG_CAS_LATENCY_3 |
SDRAM_MODEREG_OPERATING_MODE_STANDARD |
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
/* Configure a load Mode register command*/
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Step 8 --------------------------------------------------------------------*/
/* Set the refresh rate counter */
/* (7.81 us x Freq) - 20 */
/* Set the device refresh counter */
FMC_SetRefreshCount(683);
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
}
/**
* @brief Writes a Entire-word buffer to the SDRAM memory.
* @param pBuffer: pointer to buffer.
* @param uwWriteAddress: SDRAM memory internal address from which the data will be
* written.
* @param uwBufferSize: number of words to write.
* @retval None.
*/
void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize)
{
__IO uint32_t write_pointer = (uint32_t)uwWriteAddress;
/* Disable write protection */
FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE);
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* While there is data to write */
for (; uwBufferSize != 0; uwBufferSize--)
{
/* Transfer data to the memory */
*(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;
/* Increment the address*/
write_pointer += 4;
}
}
/**
* @brief Reads data buffer from the SDRAM memory.
* @param pBuffer: pointer to buffer.
* @param ReadAddress: SDRAM memory internal address from which the data will be
* read.
* @param uwBufferSize: number of words to write.
* @retval None.
*/
void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize)
{
__IO uint32_t write_pointer = (uint32_t)uwReadAddress;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Read data */
for(; uwBufferSize != 0x00; uwBufferSize--)
{
*pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer );
/* Increment the address*/
write_pointer += 4;
}
}

96
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.h Normal file
View File

@ -0,0 +1,96 @@
/**
******************************************************************************
* @file stm32f429i_discovery_sdram.h
* @author MCD Application Team
* @version V1.0.0
* @date 20-September-2013
* @brief This file contains all the functions prototypes for the
* stm324x9i_disco_sdram.c driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32429I_DISCO_SDRAM_H
#define __STM32429I_DISCO_SDRAM_H
#ifdef __cplusplus
extern "C" {
#endif
//FIXME this should not be needed
#define STM32F429_439xx
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/**
* @brief FMC SDRAM Bank address
*/
#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
/**
* @brief FMC SDRAM Memory Width
*/
/* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */
#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b
/**
* @brief FMC SDRAM CAS Latency
*/
/* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */
#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3
/**
* @brief FMC SDRAM Memory clock period
*/
#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */
/* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */
/**
* @brief FMC SDRAM Memory Read Burst feature
*/
#define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */
/* #define SDRAM_READBURST FMC_Read_Burst_Enable */
/**
* @brief FMC SDRAM Mode definition register defines
*/
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
void SDRAM_Init(void);
void SDRAM_InitSequence(void);
void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize);
void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize);
#ifdef __cplusplus
}
#endif
#endif

1379
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.c Normal file
View File

File diff suppressed because it is too large Load Diff

1144
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.h Normal file
View File

File diff suppressed because it is too large Load Diff

314
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.c Normal file
View File

@ -0,0 +1,314 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
/*
* Endpoints to be used for USBD2.
*/
#define USBD2_DATA_REQUEST_EP 1
#define USBD2_DATA_AVAILABLE_EP 1
#define USBD2_INTERRUPT_REQUEST_EP 2
/*
* USB Device Descriptor.
*/
static const uint8_t vcom_device_descriptor_data[18] = {
USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */
0x02, /* bDeviceClass (CDC). */
0x00, /* bDeviceSubClass. */
0x00, /* bDeviceProtocol. */
0x40, /* bMaxPacketSize. */
0x0483, /* idVendor (ST). */
0x5740, /* idProduct. */
0x0200, /* bcdDevice. */
1, /* iManufacturer. */
2, /* iProduct. */
3, /* iSerialNumber. */
1) /* bNumConfigurations. */
};
/*
* Device Descriptor wrapper.
*/
static const USBDescriptor vcom_device_descriptor = {
sizeof vcom_device_descriptor_data,
vcom_device_descriptor_data
};
/* Configuration Descriptor tree for a CDC.*/
static const uint8_t vcom_configuration_descriptor_data[67] = {
/* Configuration Descriptor.*/
USB_DESC_CONFIGURATION(67, /* wTotalLength. */
0x02, /* bNumInterfaces. */
0x01, /* bConfigurationValue. */
0, /* iConfiguration. */
0xC0, /* bmAttributes (self powered). */
50), /* bMaxPower (100mA). */
/* Interface Descriptor.*/
USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */
0x00, /* bAlternateSetting. */
0x01, /* bNumEndpoints. */
0x02, /* bInterfaceClass (Communications
Interface Class, CDC section
4.2). */
0x02, /* bInterfaceSubClass (Abstract
Control Model, CDC section 4.3). */
0x01, /* bInterfaceProtocol (AT commands,
CDC section 4.4). */
0), /* iInterface. */
/* Header Functional Descriptor (CDC section 5.2.3).*/
USB_DESC_BYTE (5), /* bLength. */
USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header
Functional Descriptor. */
USB_DESC_BCD (0x0110), /* bcdCDC. */
/* Call Management Functional Descriptor. */
USB_DESC_BYTE (5), /* bFunctionLength. */
USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management
Functional Descriptor). */
USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */
USB_DESC_BYTE (0x01), /* bDataInterface. */
/* ACM Functional Descriptor.*/
USB_DESC_BYTE (4), /* bFunctionLength. */
USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract
Control Management Descriptor). */
USB_DESC_BYTE (0x02), /* bmCapabilities. */
/* Union Functional Descriptor.*/
USB_DESC_BYTE (5), /* bFunctionLength. */
USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union
Functional Descriptor). */
USB_DESC_BYTE (0x00), /* bMasterInterface (Communication
Class Interface). */
USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class
Interface). */
/* Endpoint 2 Descriptor.*/
USB_DESC_ENDPOINT (USBD2_INTERRUPT_REQUEST_EP|0x80,
0x03, /* bmAttributes (Interrupt). */
0x0008, /* wMaxPacketSize. */
0xFF), /* bInterval. */
/* Interface Descriptor.*/
USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */
0x00, /* bAlternateSetting. */
0x02, /* bNumEndpoints. */
0x0A, /* bInterfaceClass (Data Class
Interface, CDC section 4.5). */
0x00, /* bInterfaceSubClass (CDC section
4.6). */
0x00, /* bInterfaceProtocol (CDC section
4.7). */
0x00), /* iInterface. */
/* Endpoint 3 Descriptor.*/
USB_DESC_ENDPOINT (USBD2_DATA_AVAILABLE_EP, /* bEndpointAddress.*/
0x02, /* bmAttributes (Bulk). */
0x0040, /* wMaxPacketSize. */
0x00), /* bInterval. */
/* Endpoint 1 Descriptor.*/
USB_DESC_ENDPOINT (USBD2_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/
0x02, /* bmAttributes (Bulk). */
0x0040, /* wMaxPacketSize. */
0x00) /* bInterval. */
};
/*
* Configuration Descriptor wrapper.
*/
static const USBDescriptor vcom_configuration_descriptor = {
sizeof vcom_configuration_descriptor_data,
vcom_configuration_descriptor_data
};
/*
* U.S. English language identifier.
*/
static const uint8_t vcom_string0[] = {
USB_DESC_BYTE(4), /* bLength. */
USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */
};
/*
* Vendor string.
*/
static const uint8_t vcom_string1[] = {
USB_DESC_BYTE(38), /* bLength. */
USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
'c', 0, 's', 0
};
/*
* Device Description string.
*/
static const uint8_t vcom_string2[] = {
USB_DESC_BYTE(56), /* bLength. */
USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0,
'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0,
'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0,
'o', 0, 'r', 0, 't', 0
};
/*
* Serial Number string.
*/
static const uint8_t vcom_string3[] = {
USB_DESC_BYTE(8), /* bLength. */
USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
'0' + CH_KERNEL_MAJOR, 0,
'0' + CH_KERNEL_MINOR, 0,
'0' + CH_KERNEL_PATCH, 0
};
/*
* Strings wrappers array.
*/
static const USBDescriptor vcom_strings[] = {
{sizeof vcom_string0, vcom_string0},
{sizeof vcom_string1, vcom_string1},
{sizeof vcom_string2, vcom_string2},
{sizeof vcom_string3, vcom_string3}
};
/*
* Handles the GET_DESCRIPTOR callback. All required descriptors must be
* handled here.
*/
static const USBDescriptor *get_descriptor(USBDriver *usbp,
uint8_t dtype,
uint8_t dindex,
uint16_t lang) {
(void)usbp;
(void)lang;
switch (dtype) {
case USB_DESCRIPTOR_DEVICE:
return &vcom_device_descriptor;
case USB_DESCRIPTOR_CONFIGURATION:
return &vcom_configuration_descriptor;
case USB_DESCRIPTOR_STRING:
if (dindex < 4)
return &vcom_strings[dindex];
}
return NULL;
}
/**
* @brief IN EP1 state.
*/
static USBInEndpointState ep1instate;
/**
* @brief OUT EP1 state.
*/
static USBOutEndpointState ep1outstate;
/**
* @brief EP1 initialization structure (both IN and OUT).
*/
static const USBEndpointConfig ep1config = {
USB_EP_MODE_TYPE_BULK,
NULL,
sduDataTransmitted,
sduDataReceived,
0x0040,
0x0040,
&ep1instate,
&ep1outstate,
2,
NULL
};
/**
* @brief IN EP2 state.
*/
static USBInEndpointState ep2instate;
/**
* @brief EP2 initialization structure (IN only).
*/
static const USBEndpointConfig ep2config = {
USB_EP_MODE_TYPE_INTR,
NULL,
sduInterruptTransmitted,
NULL,
0x0010,
0x0000,
&ep2instate,
NULL,
1,
NULL
};
/*
* Handles the USB driver global events.
*/
static void usb_event(USBDriver *usbp, usbevent_t event) {
extern SerialUSBDriver SDU1;
switch (event) {
case USB_EVENT_RESET:
return;
case USB_EVENT_ADDRESS:
return;
case USB_EVENT_CONFIGURED:
chSysLockFromISR();
/* Enables the endpoints specified into the configuration.
Note, this callback is invoked from an ISR so I-Class functions
must be used.*/
usbInitEndpointI(usbp, USBD2_DATA_REQUEST_EP, &ep1config);
usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config);
/* Resetting the state of the CDC subsystem.*/
sduConfigureHookI(&SDU1);
chSysUnlockFromISR();
return;
case USB_EVENT_SUSPEND:
return;
case USB_EVENT_WAKEUP:
return;
case USB_EVENT_STALLED:
return;
}
return;
}
/*
* USB driver configuration.
*/
const USBConfig usbcfg = {
usb_event,
get_descriptor,
sduRequestsHook,
NULL
};
/*
* Serial over USB driver configuration.
*/
const SerialUSBConfig serusbcfg = {
&USBD2,
USBD2_DATA_REQUEST_EP,
USBD2_DATA_AVAILABLE_EP,
USBD2_INTERRUPT_REQUEST_EP
};

25
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.h Normal file
View File

@ -0,0 +1,25 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _USBCFG_H_
#define _USBCFG_H_
extern const USBConfig usbcfg;
extern SerialUSBConfig serusbcfg;
#endif /* _USBCFG_H_ */
/** @} */

277
demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/wolf3d_palette.c Normal file
View File

@ -0,0 +1,277 @@
#include <ch.h>
#include <hal.h>
#include <stm32_ltdc.h>
const ltdc_color_t wolf3d_palette[256] __attribute__((aligned(4))) = {
0xFF000000, /* 0x00 */
0xFF0000A8, /* 0x01 */
0xFF00A800, /* 0x02 */
0xFF00A8A8, /* 0x03 */
0xFFA80000, /* 0x04 */
0xFFA800A8, /* 0x05 */
0xFFA85400, /* 0x06 */
0xFFA8A8A8, /* 0x07 */
0xFF545454, /* 0x08 */
0xFF5454FC, /* 0x09 */
0xFF54FC54, /* 0x0A */
0xFF54FCFC, /* 0x0B */
0xFFFC5454, /* 0x0C */
0xFFFC54FC, /* 0x0D */
0xFFFCFC54, /* 0x0E */
0xFFFCFCFC, /* 0x0F */
0xFFECECEC, /* 0x10 */
0xFFDCDCDC, /* 0x11 */
0xFFD0D0D0, /* 0x12 */
0xFFC0C0C0, /* 0x13 */
0xFFB4B4B4, /* 0x14 */
0xFFA8A8A8, /* 0x15 */
0xFF989898, /* 0x16 */
0xFF8C8C8C, /* 0x17 */
0xFF7C7C7C, /* 0x18 */
0xFF707070, /* 0x19 */
0xFF646464, /* 0x1A */
0xFF545454, /* 0x1B */
0xFF484848, /* 0x1C */
0xFF383838, /* 0x1D */
0xFF2C2C2C, /* 0x1E */
0xFF202020, /* 0x1F */
0xFFFC0000, /* 0x20 */
0xFFEC0000, /* 0x21 */
0xFFE00000, /* 0x22 */
0xFFD40000, /* 0x23 */
0xFFC80000, /* 0x24 */
0xFFBC0000, /* 0x25 */
0xFFB00000, /* 0x26 */
0xFFA40000, /* 0x27 */
0xFF980000, /* 0x28 */
0xFF880000, /* 0x29 */
0xFF7C0000, /* 0x2A */
0xFF700000, /* 0x2B */
0xFF640000, /* 0x2C */
0xFF580000, /* 0x2D */
0xFF4C0000, /* 0x2E */
0xFF400000, /* 0x2F */
0xFFFCD8D8, /* 0x30 */
0xFFFCB8B8, /* 0x31 */
0xFFFC9C9C, /* 0x32 */
0xFFFC7C7C, /* 0x33 */
0xFFFC5C5C, /* 0x34 */
0xFFFC4040, /* 0x35 */
0xFFFC2020, /* 0x36 */
0xFFFC0000, /* 0x37 */
0xFFFCA85C, /* 0x38 */
0xFFFC9840, /* 0x39 */
0xFFFC8820, /* 0x3A */
0xFFFC7800, /* 0x3B */
0xFFE46C00, /* 0x3C */
0xFFCC6000, /* 0x3D */
0xFFB45400, /* 0x3E */
0xFF9C4C00, /* 0x3F */
0xFFFCFCD8, /* 0x40 */
0xFFFCFCB8, /* 0x41 */
0xFFFCFC9C, /* 0x42 */
0xFFFCFC7C, /* 0x43 */
0xFFFCF85C, /* 0x44 */
0xFFFCF440, /* 0x45 */
0xFFFCF420, /* 0x46 */
0xFFFCF400, /* 0x47 */
0xFFE4D800, /* 0x48 */
0xFFCCC400, /* 0x49 */
0xFFB4AC00, /* 0x4A */
0xFF9C9C00, /* 0x4B */
0xFF848400, /* 0x4C */
0xFF706C00, /* 0x4D */
0xFF585400, /* 0x4E */
0xFF404000, /* 0x4F */
0xFFD0FC5C, /* 0x50 */
0xFFC4FC40, /* 0x51 */
0xFFB4FC20, /* 0x52 */
0xFFA0FC00, /* 0x53 */
0xFF90E400, /* 0x54 */
0xFF80CC00, /* 0x55 */
0xFF74B400, /* 0x56 */
0xFF609C00, /* 0x57 */
0xFFD8FCD8, /* 0x58 */
0xFFBCFCB8, /* 0x59 */
0xFF9CFC9C, /* 0x5A */
0xFF80FC7C, /* 0x5B */
0xFF60FC5C, /* 0x5C */
0xFF40FC40, /* 0x5D */
0xFF20FC20, /* 0x5E */
0xFF00FC00, /* 0x5F */
0xFF00FC00, /* 0x60 */
0xFF00EC00, /* 0x61 */
0xFF00E000, /* 0x62 */
0xFF00D400, /* 0x63 */
0xFF04C800, /* 0x64 */
0xFF04BC00, /* 0x65 */
0xFF04B000, /* 0x66 */
0xFF04A400, /* 0x67 */
0xFF049800, /* 0x68 */
0xFF048800, /* 0x69 */
0xFF047C00, /* 0x6A */
0xFF047000, /* 0x6B */
0xFF046400, /* 0x6C */
0xFF045800, /* 0x6D */
0xFF044C00, /* 0x6E */
0xFF044000, /* 0x6F */
0xFFD8FCFC, /* 0x70 */
0xFFB8FCFC, /* 0x71 */
0xFF9CFCFC, /* 0x72 */
0xFF7CFCF8, /* 0x73 */
0xFF5CFCFC, /* 0x74 */
0xFF40FCFC, /* 0x75 */
0xFF20FCFC, /* 0x76 */
0xFF00FCFC, /* 0x77 */
0xFF00E4E4, /* 0x78 */
0xFF00CCCC, /* 0x79 */
0xFF00B4B4, /* 0x7A */
0xFF009C9C, /* 0x7B */
0xFF008484, /* 0x7C */
0xFF007070, /* 0x7D */
0xFF005858, /* 0x7E */
0xFF004040, /* 0x7F */
0xFF5CBCFC, /* 0x80 */
0xFF40B0FC, /* 0x81 */
0xFF20A8FC, /* 0x82 */
0xFF009CFC, /* 0x83 */
0xFF008CE4, /* 0x84 */
0xFF007CCC, /* 0x85 */
0xFF006CB4, /* 0x86 */
0xFF005C9C, /* 0x87 */
0xFFD8D8FC, /* 0x88 */
0xFFB8BCFC, /* 0x89 */
0xFF9C9CFC, /* 0x8A */
0xFF7C80FC, /* 0x8B */
0xFF5C60FC, /* 0x8C */
0xFF4040FC, /* 0x8D */
0xFF2024FC, /* 0x8E */
0xFF0004FC, /* 0x8F */
0xFF0000FC, /* 0x90 */
0xFF0000EC, /* 0x91 */
0xFF0000E0, /* 0x92 */
0xFF0000D4, /* 0x93 */
0xFF0000C8, /* 0x94 */
0xFF0000BC, /* 0x95 */
0xFF0000B0, /* 0x96 */
0xFF0000A4, /* 0x97 */
0xFF000098, /* 0x98 */
0xFF000088, /* 0x99 */
0xFF00007C, /* 0x9A */
0xFF000070, /* 0x9B */
0xFF000064, /* 0x9C */
0xFF000058, /* 0x9D */
0xFF00004C, /* 0x9E */
0xFF000040, /* 0x9F */
0xFF282828, /* 0xA0 */
0xFFFCE034, /* 0xA1 */
0xFFFCD424, /* 0xA2 */
0xFFFCCC18, /* 0xA3 */
0xFFFCC008, /* 0xA4 */
0xFFFCB400, /* 0xA5 */
0xFFB420FC, /* 0xA6 */
0xFFA800FC, /* 0xA7 */
0xFF9800E4, /* 0xA8 */
0xFF8000CC, /* 0xA9 */
0xFF7400B4, /* 0xAA */
0xFF60009C, /* 0xAB */
0xFF500084, /* 0xAC */
0xFF440070, /* 0xAD */
0xFF340058, /* 0xAE */
0xFF280040, /* 0xAF */
0xFFFCD8FC, /* 0xB0 */
0xFFFCB8FC, /* 0xB1 */
0xFFFC9CFC, /* 0xB2 */
0xFFFC7CFC, /* 0xB3 */
0xFFFC5CFC, /* 0xB4 */
0xFFFC40FC, /* 0xB5 */
0xFFFC20FC, /* 0xB6 */
0xFFFC00FC, /* 0xB7 */
0xFFE000E4, /* 0xB8 */
0xFFC800CC, /* 0xB9 */
0xFFB400B4, /* 0xBA */
0xFF9C009C, /* 0xBB */
0xFF840084, /* 0xBC */
0xFF6C0070, /* 0xBD */
0xFF580058, /* 0xBE */
0xFF400040, /* 0xBF */
0xFFFCE8DC, /* 0xC0 */
0xFFFCE0D0, /* 0xC1 */
0xFFFCD8C4, /* 0xC2 */
0xFFFCD4BC, /* 0xC3 */
0xFFFCCCB0, /* 0xC4 */
0xFFFCC4A4, /* 0xC5 */
0xFFFCBC9C, /* 0xC6 */
0xFFFCB890, /* 0xC7 */
0xFFFCB080, /* 0xC8 */
0xFFFCA470, /* 0xC9 */
0xFFFC9C60, /* 0xCA */
0xFFF0945C, /* 0xCB */
0xFFE88C58, /* 0xCC */
0xFFDC8854, /* 0xCD */
0xFFD08050, /* 0xCE */
0xFFC87C4C, /* 0xCF */
0xFFBC7848, /* 0xD0 */
0xFFB47044, /* 0xD1 */
0xFFA86840, /* 0xD2 */
0xFFA0643C, /* 0xD3 */
0xFF9C6038, /* 0xD4 */
0xFF905C34, /* 0xD5 */
0xFF885830, /* 0xD6 */
0xFF80502C, /* 0xD7 */
0xFF744C28, /* 0xD8 */
0xFF6C4824, /* 0xD9 */
0xFF5C4020, /* 0xDA */
0xFF543C1C, /* 0xDB */
0xFF483818, /* 0xDC */
0xFF403018, /* 0xDD */
0xFF382C14, /* 0xDE */
0xFF28200C, /* 0xDF */
0xFF600064, /* 0xE0 */
0xFF006464, /* 0xE1 */
0xFF006060, /* 0xE2 */
0xFF00001C, /* 0xE3 */
0xFF00002C, /* 0xE4 */
0xFF302410, /* 0xE5 */
0xFF480048, /* 0xE6 */
0xFF500050, /* 0xE7 */
0xFF000034, /* 0xE8 */
0xFF1C1C1C, /* 0xE9 */
0xFF4C4C4C, /* 0xEA */
0xFF5C5C5C, /* 0xEB */
0xFF404040, /* 0xEC */
0xFF303030, /* 0xED */
0xFF343434, /* 0xEE */
0xFFD8F4F4, /* 0xEF */
0xFFB8E8E8, /* 0xF0 */
0xFF9CDCDC, /* 0xF1 */
0xFF74C8C8, /* 0xF2 */
0xFF48C0C0, /* 0xF3 */
0xFF20B4B4, /* 0xF4 */
0xFF20B0B0, /* 0xF5 */
0xFF00A4A4, /* 0xF6 */
0xFF009898, /* 0xF7 */
0xFF008C8C, /* 0xF8 */
0xFF008484, /* 0xF9 */
0xFF007C7C, /* 0xFA */
0xFF007878, /* 0xFB */
0xFF007474, /* 0xFC */
0xFF007070, /* 0xFD */
0xFF006C6C, /* 0xFE */
0xFF980088, /* 0xFF */
};

54
os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld Normal file
View File

@ -0,0 +1,54 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
This file is part of ChibiOS.
ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* ST32F429xI memory setup.
* Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0.
*/
MEMORY
{
flash : org = 0x08000000, len = 2M
ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */
ram1 : org = 0x20000000, len = 112k /* SRAM1 */
ram2 : org = 0x2001C000, len = 16k /* SRAM2 */
ram3 : org = 0x20020000, len = 64k /* SRAM3 */
ram4 : org = 0x10000000, len = 64k /* CCM SRAM */
ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
ram6 : org = 0x00000000, len = 0
ram7 : org = 0xD0000000, len = 8M /* SDRAM */
}
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for SDRAM segment.*/
REGION_ALIAS("SDRAM_RAM", ram7);
INCLUDE rules.ld

3125
os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.c Normal file
View File

File diff suppressed because it is too large Load Diff

690
os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.h Normal file
View File

@ -0,0 +1,690 @@
/*
Copyright (C) 2013-2015 Andrea Zoppi
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file stm32_dma2d.h
* @brief DMA2D/Chrom-ART driver.
*
* @addtogroup dma2d
* @{
*/
#ifndef _STM32_DMA2D_H_
#define _STM32_DMA2D_H_
/**
* @brief Using the DMA2D driver.
*/
#if !defined(STM32_DMA2D_USE_DMA2D) || defined(__DOXYGEN__)
#define STM32_DMA2D_USE_DMA2D FALSE
#endif
#if (TRUE == STM32_DMA2D_USE_DMA2D) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name DMA2D job modes
* @{
*/
#define DMA2D_JOB_COPY (0 << 16) /**< Copy, replace(FG only).*/
#define DMA2D_JOB_CONVERT (1 << 16) /**< Copy, convert (FG + PFC).*/
#define DMA2D_JOB_BLEND (2 << 16) /**< Copy, blend (FG + BG + PFC).*/
#define DMA2D_JOB_CONST (3 << 16) /**< Default color only (FG REG).*/
/** @} */
/**
* @name DMA2D enable flag
* @{
*/
#define DMA2D_EF_ENABLE (1 << 0) /**< DMA2D enabled.*/
#define DMA2D_EF_DITHER (1 << 16) /**< Dithering enabled.*/
#define DMA2D_EF_PIXCLK_INVERT (1 << 28) /**< Inverted pixel clock.*/
#define DMA2D_EF_DATAEN_HIGH (1 << 29) /**< Active-high data enable.*/
#define DMA2D_EF_VSYNC_HIGH (1 << 30) /**< Active-high vsync.*/
#define DMA2D_EF_HSYNC_HIGH (1 << 31) /**< Active-high hsync.*/
/** Enable flags mask. */
#define DMA2D_EF_MASK \
(DMA2D_EF_ENABLE | DMA2D_EF_DITHER | DMA2D_EF_PIXCLK_INVERT | \
DMA2D_EF_DATAEN_HIGH | DMA2D_EF_VSYNC_HIGH | DMA2D_EF_HSYNC_HIGH)
/** @} */
/**
* @name DMA2D layer enable flags
* @{
*/
#define DMA2D_LEF_ENABLE (1 << 0) /**< Layer enabled*/
#define DMA2D_LEF_KEYING (1 << 1) /**< Color keying enabled.*/
#define DMA2D_LEF_PALETTE (1 << 4) /**< Palette enabled.*/
/** Layer enable flag masks. */
#define DMA2D_LEF_MASK \
(DMA2D_LEF_ENABLE | DMA2D_LEF_KEYING | DMA2D_LEF_PALETTE)
/** @} */
/**
* @name DMA2D pixel formats
* @{
*/
#define DMA2D_FMT_ARGB8888 (0) /**< ARGB-8888 format.*/
#define DMA2D_FMT_RGB888 (1) /**< RGB-888 format.*/
#define DMA2D_FMT_RGB565 (2) /**< RGB-565 format.*/
#define DMA2D_FMT_ARGB1555 (3) /**< ARGB-1555 format.*/
#define DMA2D_FMT_ARGB4444 (4) /**< ARGB-4444 format.*/
#define DMA2D_FMT_L8 (5) /**< L-8 format.*/
#define DMA2D_FMT_AL44 (6) /**< AL-44 format.*/
#define DMA2D_FMT_AL88 (7) /**< AL-88 format.*/
#define DMA2D_FMT_L4 (8) /**< L-4 format.*/
#define DMA2D_FMT_A8 (9) /**< A-8 format.*/
#define DMA2D_FMT_A4 (10) /**< A-4 format.*/
/** @} */
/**
* @name DMA2D pixel format aliased raw masks
* @{
*/
#define DMA2D_XMASK_ARGB8888 (0xFFFFFFFF) /**< ARGB-8888 aliased mask.*/
#define DMA2D_XMASK_RGB888 (0x00FFFFFF) /**< RGB-888 aliased mask.*/
#define DMA2D_XMASK_RGB565 (0x00F8FCF8) /**< RGB-565 aliased mask.*/
#define DMA2D_XMASK_ARGB1555 (0x80F8F8F8) /**< ARGB-1555 aliased mask.*/
#define DMA2D_XMASK_ARGB4444 (0xF0F0F0F0) /**< ARGB-4444 aliased mask.*/
#define DMA2D_XMASK_L8 (0x000000FF) /**< L-8 aliased mask.*/
#define DMA2D_XMASK_AL44 (0xF00000F0) /**< AL-44 aliased mask.*/
#define DMA2D_XMASK_AL88 (0xFF0000FF) /**< AL-88 aliased mask.*/
#define DMA2D_XMASK_L4 (0x0000000F) /**< L-4 aliased mask.*/
#define DMA2D_XMASK_A8 (0xFF000000) /**< A-8 aliased mask.*/
#define DMA2D_XMASK_A4 (0xF0000000) /**< A-4 aliased mask.*/
/** @} */
/**
* @name DMA2D alpha modes
* @{
*/
#define DMA2D_ALPHA_KEEP (0x00000000) /**< Original alpha channel.*/
#define DMA2D_ALPHA_REPLACE (0x00010000) /**< Replace with constant.*/
#define DMA2D_ALPHA_MODULATE (0x00020000) /**< Modulate with constant.*/
/** @} */
/**
* @name DMA2D parameter bounds
* @{
*/
#define DMA2D_MIN_PIXFMT_ID (0) /**< Minimum pixel format ID.*/
#define DMA2D_MAX_PIXFMT_ID (11) /**< Maximum pixel format ID.*/
#define DMA2D_MIN_OUTPIXFMT_ID (0) /**< Minimum output pixel format ID.*/
#define DMA2D_MAX_OUTPIXFMT_ID (4) /**< Maximum output pixel format ID.*/
#define DMA2D_MAX_OFFSET ((1 << 14) - 1)
#define DMA2D_MAX_PALETTE_LENGTH (256) /***/
#define DMA2D_MAX_WIDTH ((1 << 14) - 1)
#define DMA2D_MAX_HEIGHT ((1 << 16) - 1)
#define DMA2D_MAX_WATERMARK_POS ((1 << 16) - 1)
#define DMA2D_MAX_DEADTIME_CYCLES ((1 << 8) - 1)
/** @} */
/**
* @name DMA2D basic ARGB-8888 colors.
* @{
*/
/* Microsoft Windows default 16-color palette.*/
#define DMA2D_COLOR_BLACK (0xFF000000)
#define DMA2D_COLOR_MAROON (0xFF800000)
#define DMA2D_COLOR_GREEN (0xFF008000)
#define DMA2D_COLOR_OLIVE (0xFF808000)
#define DMA2D_COLOR_NAVY (0xFF000080)
#define DMA2D_COLOR_PURPLE (0xFF800080)
#define DMA2D_COLOR_TEAL (0xFF008080)
#define DMA2D_COLOR_SILVER (0xFFC0C0C0)
#define DMA2D_COLOR_GRAY (0xFF808080)
#define DMA2D_COLOR_RED (0xFFFF0000)
#define DMA2D_COLOR_LIME (0xFF00FF00)
#define DMA2D_COLOR_YELLOW (0xFFFFFF00)
#define DMA2D_COLOR_BLUE (0xFF0000FF)
#define DMA2D_COLOR_FUCHSIA (0xFFFF00FF)
#define DMA2D_COLOR_AQUA (0xFF00FFFF)
#define DMA2D_COLOR_WHITE (0xFFFFFFFF)
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*
* These definitions should already be defined by stm32_isr.h
*/
#if !defined(STM32_DMA2D_NUMBER) && !defined(__DOXYGEN__)
#define STM32_DMA2D_NUMBER (DMA2D_IRQn)
#endif
/*
* These definitions should already be defined by hal_lld.h
*/
#if !defined(DMA2D_IRQHandler) && !defined(__DOXYGEN__)
#define DMA2D_IRQHandler Vector1A8
#endif
#if !defined(STM32_HAS_DMA2D) && !defined(__DOXYGEN__)
#ifdef STM32F429_439xx
#define STM32_HAS_DMA2D (TRUE)
#else
#define STM32_HAS_DMA2D (FALSE)
#endif
#endif
/**
* @name DMA2D configuration options
* @{
*/
/**
* @brief DMA2D event interrupt priority level setting.
*/
#if !defined(STM32_DMA2D_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DMA2D_IRQ_PRIORITY (11)
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DMA2D_USE_WAIT) || defined(__DOXYGEN__)
#define DMA2D_USE_WAIT (TRUE)
#endif
/**
* @brief Enables the @p dma2dAcquireBus() and @p dma2dReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DMA2D_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define DMA2D_USE_MUTUAL_EXCLUSION (TRUE)
#endif
/**
* @brief Provides software color conversion functions.
* @note Disabling this option saves both code and data space.
*/
#if !defined(DMA2D_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__)
#define DMA2D_USE_SOFTWARE_CONVERSIONS (TRUE)
#endif
/**
* @brief Enables checks for DMA2D functions.
* @note Disabling this option saves both code and data space.
* @note Disabling checks by ChibiOS will automatically disable DMA2D checks.
*/
#if !defined(DMA2D_USE_CHECKS) || defined(__DOXYGEN__)
#define DMA2D_USE_CHECKS (TRUE)
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#ifndef STM32F429_439xx
#error "Currently only STM32F429xx and STM32F439xx are supported"
#endif
#if (TRUE != STM32_HAS_DMA2D)
#error "DMA2D must be present when using the DMA2D subsystem"
#endif
#if (TRUE != STM32_DMA2D_USE_DMA2D) && (TRUE != STM32_HAS_DMA2D)
#error "DMA2D not present in the selected device"
#endif
#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION)
#if (TRUE != CH_CFG_USE_MUTEXES) && (TRUE != CH_CFG_USE_SEMAPHORES)
#error "DMA2D_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES"
#endif
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/* Complex types forwarding.*/
typedef union dma2d_coloralias_t dma2d_coloralias_t;
typedef struct dma2d_palcfg_t dma2d_palcfg_t;
typedef struct dma2d_laycfg_t dma2d_layercfg_t;
typedef struct DMA2DConfig DMA2DConfig;
typedef enum dma2d_state_t dma2d_state_t;
typedef struct DMA2DDriver DMA2DDriver;
/**
* @name DMA2D Data types
* @{
*/
/**
* @brief DMA2D generic color.
*/
typedef uint32_t dma2d_color_t;
/**
* @brief DMA2D color aliases.
* @detail Mapped with ARGB-8888, except for luminance (L mapped onto B).
* Padding fields prefixed with <tt>'x'</tt>, which should be clear
* (all 0) before compression and set (all 1) after expansion.
*/
typedef union dma2d_coloralias_t {
struct {
unsigned b : 8;
unsigned g : 8;
unsigned r : 8;
unsigned a : 8;
} argb8888; /**< Mapped ARGB-8888 bits.*/
struct {
unsigned b : 8;
unsigned g : 8;
unsigned r : 8;
unsigned xa : 8;
} rgb888; /**< Mapped RGB-888 bits.*/
struct {
unsigned xb : 3;
unsigned b : 5;
unsigned xg : 2;
unsigned g : 6;
unsigned xr : 3;
unsigned r : 5;
unsigned xa : 8;
} rgb565; /**< Mapped RGB-565 bits.*/
struct {
unsigned xb : 3;
unsigned b : 5;
unsigned xg : 3;
unsigned g : 5;
unsigned xr : 3;
unsigned r : 5;
unsigned xa : 7;
unsigned a : 1;
} argb1555; /**< Mapped ARGB-1555 values.*/
struct {
unsigned xb : 4;
unsigned b : 4;
unsigned xg : 4;
unsigned g : 4;
unsigned xr : 4;
unsigned r : 4;
unsigned xa : 4;
unsigned a : 4;
} argb4444; /**< Mapped ARGB-4444 values.*/
struct {
unsigned l : 8;
unsigned x : 16;
unsigned xa : 8;
} l8; /**< Mapped L-8 bits.*/
struct {
unsigned xl : 4;
unsigned l : 4;
unsigned x : 16;
unsigned xa : 4;
unsigned a : 4;
} al44; /**< Mapped AL-44 bits.*/
struct {
unsigned l : 8;
unsigned x : 16;
unsigned a : 8;
} al88; /**< Mapped AL-88 bits.*/
struct {
unsigned l : 4;
unsigned xl : 4;
unsigned x : 16;
unsigned xa : 8;
} l4; /**< Mapped L-4 bits.*/
struct {
unsigned x : 24;
unsigned a : 8;
} a8; /**< Mapped A-8 bits.*/
struct {
unsigned x : 24;
unsigned xa : 4;
unsigned a : 4;
} a4; /**< Mapped A-4 bits.*/
dma2d_color_t aliased; /**< Aliased raw bits.*/
} dma2d_coloralias_t;
/**
* @brief DMA2D job (transfer) mode.
*/
typedef uint32_t dma2d_jobmode_t;
/**
* @brief DMA2D pixel format.
*/
typedef uint32_t dma2d_pixfmt_t;
/**
* @brief DMA2D alpha mode.
*/
typedef uint32_t dma2d_amode_t;
/**
* @brief DMA2D ISR callback.
*/
typedef void (*dma2d_isrcb_t)(DMA2DDriver *dma2dp);
/**
* @brief DMA2D palette specifications.
*/
typedef struct dma2d_palcfg_t {
const void *colorsp; /**< Pointer to color entries.*/
uint16_t length; /**< Number of color entries.*/
dma2d_pixfmt_t fmt; /**< Format, RGB-888 or ARGB-8888.*/
} dma2d_palcfg_t;
/**
* @brief DMA2D layer specifications.
*/
typedef struct dma2d_layercfg_t {
void *bufferp; /**< Frame buffer address.*/
size_t wrap_offset; /**< Offset between lines, in pixels.*/
dma2d_pixfmt_t fmt; /**< Pixel format.*/
dma2d_color_t def_color; /**< Default color, RGB-888.*/
uint8_t const_alpha; /**< Constant alpha factor.*/
const dma2d_palcfg_t *palettep; /**< Palette specs, or @p NULL.*/
} dma2d_laycfg_t;
/**
* @brief DMA2D driver configuration.
*/
typedef struct DMA2DConfig {
/* ISR callbacks.*/
dma2d_isrcb_t cfgerr_isr; /**< Configuration error, or @p NULL.*/
dma2d_isrcb_t paltrfdone_isr; /**< Palette transfer done, or @p NULL.*/
dma2d_isrcb_t palacserr_isr; /**< Palette access error, or @p NULL.*/
dma2d_isrcb_t trfwmark_isr; /**< Transfer watermark, or @p NULL.*/
dma2d_isrcb_t trfdone_isr; /**< Transfer complete, or @p NULL.*/
dma2d_isrcb_t trferr_isr; /**< Transfer error, or @p NULL.*/
} DMA2DConfig;
/**
* @brief DMA2D driver state.
*/
typedef enum dma2d_state_t {
DMA2D_UNINIT = (0), /**< Not initialized.*/
DMA2D_STOP = (1), /**< Stopped.*/
DMA2D_READY = (2), /**< Ready.*/
DMA2D_ACTIVE = (3), /**< Executing commands.*/
DMA2D_PAUSED = (4), /**< Transfer suspended.*/
} dma2d_state_t;
/**
* @brief DMA2D driver.
*/
typedef struct DMA2DDriver {
dma2d_state_t state; /**< Driver state.*/
const DMA2DConfig *config; /**< Driver configuration.*/
/* Multithreading stuff.*/
#if (TRUE == DMA2D_USE_WAIT) || defined(__DOXYGEN__)
thread_t *thread; /**< Waiting thread.*/
#endif /* DMA2D_USE_WAIT */
#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION)
#if (TRUE == CH_CFG_USE_MUTEXES)
mutex_t lock; /**< Multithreading lock.*/
#elif (TRUE == CH_CFG_USE_SEMAPHORES)
semaphore_t lock; /**< Multithreading lock.*/
#endif
#endif /* DMA2D_USE_MUTUAL_EXCLUSION */
} DMA2DDriver;
/** @} */
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Makes an ARGB-8888 value from byte components.
*
* @param[in] a alpha byte component
* @param[in] r red byte component
* @param[in] g green byte component
* @param[in] b blue byte component
*
* @return color in ARGB-8888 format
*
* @api
*/
#define dma2dMakeARGB8888(a, r, g, b) \
((((dma2d_color_t)(a) & 0xFF) << 24) | \
(((dma2d_color_t)(r) & 0xFF) << 16) | \
(((dma2d_color_t)(g) & 0xFF) << 8) | \
(((dma2d_color_t)(b) & 0xFF) << 0))
/**
* @brief Compute bytes per pixel.
* @details Computes the bytes per pixel for the specified pixel format.
* Rounds to the ceiling.
*
* @param[in] fmt pixel format
*
* @return bytes per pixel
*
* @api
*/
#define dma2dBytesPerPixel(fmt) \
((dma2dBitsPerPixel(fmt) + 7) >> 3)
/**
* @brief Compute pixel address.
* @details Computes the buffer address of a pixel, given the buffer
* specifications.
*
* @param[in] originp buffer origin address
* @param[in] pitch buffer pitch, in bytes
* @param[in] fmt buffer pixel format
* @param[in] x horizontal pixel coordinate
* @param[in] y vertical pixel coordinate
*
* @return pixel address
*
* @api
*/
#define dma2dComputeAddress(originp, pitch, fmt, x, y) \
((void *)dma2dComputeAddressConst(originp, pitch, fmt, x, y))
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
extern DMA2DDriver DMA2DD1;
#ifdef __cplusplus
extern "C" {
#endif
/* Driver methods.*/
void dma2dInit(void);
void dma2dObjectInit(DMA2DDriver *dma2dp);
dma2d_state_t dma2dGetStateI(DMA2DDriver *dma2dp);
dma2d_state_t dma2dGetState(DMA2DDriver *dma2dp);
void dma2dStart(DMA2DDriver *dma2dp, const DMA2DConfig *configp);
void dma2dStop(DMA2DDriver *dma2dp);
#if (TRUE == DMA2D_USE_MUTUAL_EXCLUSION)
void dma2dAcquireBusS(DMA2DDriver *dma2dp);
void dma2dAcquireBus(DMA2DDriver *dma2dp);
void dma2dReleaseBusS(DMA2DDriver *dma2dp);
void dma2dReleaseBus(DMA2DDriver *dma2dp);
#endif /* DMA2D_USE_MUTUAL_EXCLUSION */
/* Global methods.*/
uint16_t dma2dGetWatermarkPosI(DMA2DDriver *dma2dp);
uint16_t dma2dGetWatermarkPos(DMA2DDriver *dma2dp);
void dma2dSetWatermarkPosI(DMA2DDriver *dma2dp, uint16_t line);
void dma2dSetWatermarkPos(DMA2DDriver *dma2dp, uint16_t line);
bool dma2dIsWatermarkEnabledI(DMA2DDriver *dma2dp);
bool dma2dIsWatermarkEnabled(DMA2DDriver *dma2dp);
void dma2dEnableWatermarkI(DMA2DDriver *dma2dp);
void dma2dEnableWatermark(DMA2DDriver *dma2dp);
void dma2dDisableWatermarkI(DMA2DDriver *dma2dp);
void dma2dDisableWatermark(DMA2DDriver *dma2dp);
uint32_t dma2dGetDeadTimeI(DMA2DDriver *dma2dp);
uint32_t dma2dGetDeadTime(DMA2DDriver *dma2dp);
void dma2dSetDeadTimeI(DMA2DDriver *dma2dp, uint32_t cycles);
void dma2dSetDeadTime(DMA2DDriver *dma2dp, uint32_t cycles);
bool dma2dIsDeadTimeEnabledI(DMA2DDriver *dma2dp);
bool dma2dIsDeadTimeEnabled(DMA2DDriver *dma2dp);
void dma2dEnableDeadTimeI(DMA2DDriver *dma2dp);
void dma2dEnableDeadTime(DMA2DDriver *dma2dp);
void dma2dDisableDeadTimeI(DMA2DDriver *dma2dp);
void dma2dDisableDeadTime(DMA2DDriver *dma2dp);
/* Job methods.*/
dma2d_jobmode_t dma2dJobGetModeI(DMA2DDriver *dma2dp);
dma2d_jobmode_t dma2dJobGetMode(DMA2DDriver *dma2dp);
void dma2dJobSetModeI(DMA2DDriver *dma2dp, dma2d_jobmode_t mode);
void dma2dJobSetMode(DMA2DDriver *dma2dp, dma2d_jobmode_t mode);
void dma2dJobGetSizeI(DMA2DDriver *dma2dp,
uint16_t *widthp, uint16_t *heightp);
void dma2dJobGetSize(DMA2DDriver *dma2dp,
uint16_t *widthp, uint16_t *heightp);
void dma2dJobSetSizeI(DMA2DDriver *dma2dp, uint16_t width, uint16_t height);
void dma2dJobSetSize(DMA2DDriver *dma2dp, uint16_t width, uint16_t height);
bool dma2dJobIsExecutingI(DMA2DDriver *dma2dp);
bool dma2dJobIsExecuting(DMA2DDriver *dma2dp);
void dma2dJobStartI(DMA2DDriver *dma2dp);
void dma2dJobStart(DMA2DDriver *dma2dp);
void dma2dJobExecuteS(DMA2DDriver *dma2dp);
void dma2dJobExecute(DMA2DDriver *dma2dp);
void dma2dJobSuspendI(DMA2DDriver *dma2dp);
void dma2dJobSuspend(DMA2DDriver *dma2dp);
void dma2dJobResumeI(DMA2DDriver *dma2dp);
void dma2dJobResume(DMA2DDriver *dma2dp);
void dma2dJobAbortI(DMA2DDriver *dma2dp);
void dma2dJobAbort(DMA2DDriver *dma2dp);
/* Background layer methods.*/
void *dma2dBgGetAddressI(DMA2DDriver *dma2dp);
void *dma2dBgGetAddress(DMA2DDriver *dma2dp);
void dma2dBgSetAddressI(DMA2DDriver *dma2dp, void *bufferp);
void dma2dBgSetAddress(DMA2DDriver *dma2dp, void *bufferp);
size_t dma2dBgGetWrapOffsetI(DMA2DDriver *dma2dp);
size_t dma2dBgGetWrapOffset(DMA2DDriver *dma2dp);
void dma2dBgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset);
void dma2dBgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset);
uint8_t dma2dBgGetConstantAlphaI(DMA2DDriver *dma2dp);
uint8_t dma2dBgGetConstantAlpha(DMA2DDriver *dma2dp);
void dma2dBgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a);
void dma2dBgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a);
dma2d_amode_t dma2dBgGetAlphaModeI(DMA2DDriver *dma2dp);
dma2d_amode_t dma2dBgGetAlphaMode(DMA2DDriver *dma2dp);
void dma2dBgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode);
void dma2dBgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode);
dma2d_pixfmt_t dma2dBgGetPixelFormatI(DMA2DDriver *dma2dp);
dma2d_pixfmt_t dma2dBgGetPixelFormat(DMA2DDriver *dma2dp);
void dma2dBgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt);
void dma2dBgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt);
dma2d_color_t dma2dBgGetDefaultColorI(DMA2DDriver *dma2dp);
dma2d_color_t dma2dBgGetDefaultColor(DMA2DDriver *dma2dp);
void dma2dBgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c);
void dma2dBgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c);
void dma2dBgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep);
void dma2dBgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep);
void dma2dBgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep);
void dma2dBgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep);
void dma2dBgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp);
void dma2dBgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp);
void dma2dBgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp);
void dma2dBgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp);
/* Foreground layer methods.*/
void *dma2dFgGetAddressI(DMA2DDriver *dma2dp);
void *dma2dFgGetAddress(DMA2DDriver *dma2dp);
void dma2dFgSetAddressI(DMA2DDriver *dma2dp, void *bufferp);
void dma2dFgSetAddress(DMA2DDriver *dma2dp, void *bufferp);
size_t dma2dFgGetWrapOffsetI(DMA2DDriver *dma2dp);
size_t dma2dFgGetWrapOffset(DMA2DDriver *dma2dp);
void dma2dFgSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset);
void dma2dFgSetWrapOffset(DMA2DDriver *dma2dp, size_t offset);
uint8_t dma2dFgGetConstantAlphaI(DMA2DDriver *dma2dp);
uint8_t dma2dFgGetConstantAlpha(DMA2DDriver *dma2dp);
void dma2dFgSetConstantAlphaI(DMA2DDriver *dma2dp, uint8_t a);
void dma2dFgSetConstantAlpha(DMA2DDriver *dma2dp, uint8_t a);
dma2d_amode_t dma2dFgGetAlphaModeI(DMA2DDriver *dma2dp);
dma2d_amode_t dma2dFgGetAlphaMode(DMA2DDriver *dma2dp);
void dma2dFgSetAlphaModeI(DMA2DDriver *dma2dp, dma2d_amode_t mode);
void dma2dFgSetAlphaMode(DMA2DDriver *dma2dp, dma2d_amode_t mode);
dma2d_pixfmt_t dma2dFgGetPixelFormatI(DMA2DDriver *dma2dp);
dma2d_pixfmt_t dma2dFgGetPixelFormat(DMA2DDriver *dma2dp);
void dma2dFgSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt);
void dma2dFgSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt);
dma2d_color_t dma2dFgGetDefaultColorI(DMA2DDriver *dma2dp);
dma2d_color_t dma2dFgGetDefaultColor(DMA2DDriver *dma2dp);
void dma2dFgSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c);
void dma2dFgSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c);
void dma2dFgGetPaletteI(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep);
void dma2dFgGetPalette(DMA2DDriver *dma2dp, dma2d_palcfg_t *palettep);
void dma2dFgSetPaletteS(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep);
void dma2dFgSetPalette(DMA2DDriver *dma2dp, const dma2d_palcfg_t *palettep);
void dma2dFgGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp);
void dma2dFgGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp);
void dma2dFgSetConfigS(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp);
void dma2dFgSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp);
/* Output layer methods.*/
void *dma2dOutGetAddressI(DMA2DDriver *dma2dp);
void *dma2dOutGetAddress(DMA2DDriver *dma2dp);
void dma2dOutSetAddressI(DMA2DDriver *dma2dp, void *bufferp);
void dma2dOutSetAddress(DMA2DDriver *dma2dp, void *bufferp);
size_t dma2dOutGetWrapOffsetI(DMA2DDriver *dma2dp);
size_t dma2dOutGetWrapOffset(DMA2DDriver *dma2dp);
void dma2dOutSetWrapOffsetI(DMA2DDriver *dma2dp, size_t offset);
void dma2dOutSetWrapOffset(DMA2DDriver *dma2dp, size_t offset);
dma2d_pixfmt_t dma2dOutGetPixelFormatI(DMA2DDriver *dma2dp);
dma2d_pixfmt_t dma2dOutGetPixelFormat(DMA2DDriver *dma2dp);
void dma2dOutSetPixelFormatI(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt);
void dma2dOutSetPixelFormat(DMA2DDriver *dma2dp, dma2d_pixfmt_t fmt);
dma2d_color_t dma2dOutGetDefaultColorI(DMA2DDriver *dma2dp);
dma2d_color_t dma2dOutGetDefaultColor(DMA2DDriver *dma2dp);
void dma2dOutSetDefaultColorI(DMA2DDriver *dma2dp, dma2d_color_t c);
void dma2dOutSetDefaultColor(DMA2DDriver *dma2dp, dma2d_color_t c);
void dma2dOutGetLayerI(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp);
void dma2dOutGetLayer(DMA2DDriver *dma2dp, dma2d_laycfg_t *cfgp);
void dma2dOutSetConfigI(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp);
void dma2dOutSetConfig(DMA2DDriver *dma2dp, const dma2d_laycfg_t *cfgp);
/* Helper functions.*/
const void *dma2dComputeAddressConst(const void *originp, size_t pitch,
dma2d_pixfmt_t fmt,
uint16_t x, uint16_t y);
bool dma2dIsAligned(const void *bufferp, dma2d_pixfmt_t fmt);
size_t dma2dBitsPerPixel(dma2d_pixfmt_t fmt);
#if (TRUE == DMA2D_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__)
dma2d_color_t dma2dFromARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt);
dma2d_color_t dma2dToARGB8888(dma2d_color_t c, dma2d_pixfmt_t fmt);
#endif /* DMA2D_USE_SOFTWARE_CONVERSIONS */
#ifdef __cplusplus
}
#endif
#endif /* STM32_DMA2D_USE_DMA2D */
#endif /* _STM32_DMA2D_H_ */
/** @} */

3792
os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.c Normal file
View File

File diff suppressed because it is too large Load Diff

770
os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.h Normal file
View File

@ -0,0 +1,770 @@
/*
Copyright (C) 2013-2015 Andrea Zoppi
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file stm32_ltdc.h
* @brief LCD-TFT Controller Driver.
*
* @addtogroup ltdc
* @{
*/
#ifndef _STM32_LTDC_H_
#define _STM32_LTDC_H_
/**
* @brief Using the LTDC driver.
*/
#if !defined(STM32_LTDC_USE_LTDC) || defined(__DOXYGEN__)
#define STM32_LTDC_USE_LTDC FALSE
#endif
#if (TRUE == STM32_LTDC_USE_LTDC) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name LTDC enable flags
* @{
*/
#define LTDC_EF_ENABLE (1 << 0) /**< LTDC enabled.*/
#define LTDC_EF_DITHER (1 << 16) /**< Dithering enabled.*/
#define LTDC_EF_PIXCLK_INVERT (1 << 28) /**< Inverted pixel clock.*/
#define LTDC_EF_DATAEN_HIGH (1 << 29) /**< Active-high data enable.*/
#define LTDC_EF_VSYNC_HIGH (1 << 30) /**< Active-high vsync.*/
#define LTDC_EF_HSYNC_HIGH (1 << 31) /**< Active-high hsync.*/
#define LTDC_EF_MASK \
(LTDC_EF_ENABLE | LTDC_EF_DITHER | LTDC_EF_PIXCLK_INVERT | \
LTDC_EF_DATAEN_HIGH | LTDC_EF_VSYNC_HIGH | LTDC_EF_HSYNC_HIGH)
/** @} */
/**
* @name LTDC layer enable flags
* @{
*/
#define LTDC_LEF_ENABLE (1 << 0) /**< Layer enabled*/
#define LTDC_LEF_KEYING (1 << 1) /**< Color keying enabled.*/
#define LTDC_LEF_PALETTE (1 << 4) /**< Palette enabled.*/
#define LTDC_LEF_MASK \
(LTDC_LEF_ENABLE | LTDC_LEF_KEYING | LTDC_LEF_PALETTE)
/** @} */
/**
* @name LTDC pixel formats
* @{
*/
#define LTDC_FMT_ARGB8888 0 /**< ARGB-8888 format.*/
#define LTDC_FMT_RGB888 1 /**< RGB-888 format.*/
#define LTDC_FMT_RGB565 2 /**< RGB-565 format.*/
#define LTDC_FMT_ARGB1555 3 /**< ARGB-1555 format.*/
#define LTDC_FMT_ARGB4444 4 /**< ARGB-4444 format.*/
#define LTDC_FMT_L8 5 /**< L-8 format.*/
#define LTDC_FMT_AL44 6 /**< AL-44 format.*/
#define LTDC_FMT_AL88 7 /**< AL-88 format.*/
/** @} */
/**
* @name LTDC pixel format aliased raw masks
* @{
*/
#define LTDC_XMASK_ARGB8888 0xFFFFFFFF /**< ARGB-8888 aliased mask.*/
#define LTDC_XMASK_RGB888 0x00FFFFFF /**< RGB-888 aliased mask.*/
#define LTDC_XMASK_RGB565 0x00F8FCF8 /**< RGB-565 aliased mask.*/
#define LTDC_XMASK_ARGB1555 0x80F8F8F8 /**< ARGB-1555 aliased mask.*/
#define LTDC_XMASK_ARGB4444 0xF0F0F0F0 /**< ARGB-4444 aliased mask.*/
#define LTDC_XMASK_L8 0x000000FF /**< L-8 aliased mask.*/
#define LTDC_XMASK_AL44 0xF00000F0 /**< AL-44 aliased mask.*/
#define LTDC_XMASK_AL88 0xFF0000FF /**< AL-88 aliased mask.*/
/** @} */
/**
* @name LTDC blending factors
* @{
*/
#define LTDC_BLEND_FIX1_FIX2 0x0405 /**< cnst1; 1 - cnst2 */
#define LTDC_BLEND_FIX1_MOD2 0x0407 /**< cnst1; 1 - a2 * cnst2 */
#define LTDC_BLEND_MOD1_FIX2 0x0605 /**< a1 * cnst1; 1 - cnst2 */
#define LTDC_BLEND_MOD1_MOD2 0x0607 /**< a1 * cnst1; 1 - a2 * cnst2 */
/** @} */
/**
* @name LTDC parameter bounds
* @{
*/
#define LTDC_MIN_SCREEN_WIDTH 1
#define LTDC_MIN_SCREEN_HEIGHT 1
#define LTDC_MAX_SCREEN_WIDTH 800
#define LTDC_MAX_SCREEN_HEIGHT 600
#define LTDC_MIN_HSYNC_WIDTH 1
#define LTDC_MIN_VSYNC_HEIGHT 1
#define LTDC_MAX_HSYNC_WIDTH (1 << 12)
#define LTDC_MAX_VSYNC_HEIGHT (1 << 11)
#define LTDC_MIN_HBP_WIDTH 0
#define LTDC_MIN_VBP_HEIGHT 0
#define LTDC_MAX_HBP_WIDTH (1 << 12)
#define LTDC_MAX_VBP_HEIGHT (1 << 11)
#define LTDC_MIN_ACC_HBP_WIDTH 1
#define LTDC_MIN_ACC_VBP_HEIGHT 1
#define LTDC_MAX_ACC_HBP_WIDTH (1 << 12)
#define LTDC_MAX_ACC_VBP_HEIGHT (1 << 11)
#define LTDC_MIN_HFP_WIDTH 0
#define LTDC_MIN_VFP_HEIGHT 0
#define LTDC_MAX_HFP_WIDTH (1 << 12)
#define LTDC_MAX_VFP_HEIGHT (1 << 11)
#define LTDC_MIN_ACTIVE_WIDTH 0
#define LTDC_MIN_ACTIVE_HEIGHT 0
#define LTDC_MAX_ACTIVE_WIDTH (1 << 12)
#define LTDC_MAX_ACTIVE_HEIGHT (1 << 11)
#define LTDC_MIN_ACC_ACTIVE_WIDTH 1
#define LTDC_MIN_ACC_ACTIVE_HEIGHT 1
#define LTDC_MAX_ACC_ACTIVE_WIDTH (1 << 12)
#define LTDC_MAX_ACC_ACTIVE_HEIGHT (1 << 11)
#define LTDC_MIN_ACC_TOTAL_WIDTH 1
#define LTDC_MIN_ACC_TOTAL_HEIGHT 1
#define LTDC_MAX_ACC_TOTAL_WIDTH (1 << 12)
#define LTDC_MAX_ACC_TOTAL_HEIGHT (1 << 11)
#define LTDC_MIN_LINE_INTERRUPT_POS 0
#define LTDC_MAX_LINE_INTERRUPT_POS ((1 << 11) - 1)
#define LTDC_MIN_WINDOW_HSTART 0
#define LTDC_MIN_WINDOW_HSTART 0
#define LTDC_MAX_WINDOW_HSTOP ((1 << 12) - 1)
#define LTDC_MAX_WINDOW_HSTOP ((1 << 12) - 1)
#define LTDC_MIN_WINDOW_VSTART 0
#define LTDC_MIN_WINDOW_VSTART 0
#define LTDC_MAX_WINDOW_VSTOP ((1 << 11) - 1)
#define LTDC_MAX_WINDOW_VSTOP ((1 << 11) - 1)
#define LTDC_MIN_FRAME_WIDTH_BYTES 0
#define LTDC_MIN_FRAME_HEIGHT_LINES 0
#define LTDC_MIN_FRAME_PITCH_BYTES 0
#define LTDC_MAX_FRAME_WIDTH_BYTES ((1 << 13) - 1 - 3)
#define LTDC_MAX_FRAME_HEIGHT_LINES ((1 << 11) - 1)
#define LTDC_MAX_FRAME_PITCH_BYTES ((1 << 13) - 1)
#define LTDC_MIN_PIXFMT_ID 0
#define LTDC_MAX_PIXFMT_ID 7
#define LTDC_MAX_PALETTE_LENGTH 256
/** @} */
/**
* @name LTDC basic ARGB-8888 colors.
* @{
*/
/* Microsoft Windows default 16-color palette.*/
#define LTDC_COLOR_BLACK 0xFF000000
#define LTDC_COLOR_MAROON 0xFF800000
#define LTDC_COLOR_GREEN 0xFF008000
#define LTDC_COLOR_OLIVE 0xFF808000
#define LTDC_COLOR_NAVY 0xFF000080
#define LTDC_COLOR_PURPLE 0xFF800080
#define LTDC_COLOR_TEAL 0xFF008080
#define LTDC_COLOR_SILVER 0xFFC0C0C0
#define LTDC_COLOR_GRAY 0xFF808080
#define LTDC_COLOR_RED 0xFFFF0000
#define LTDC_COLOR_LIME 0xFF00FF00
#define LTDC_COLOR_YELLOW 0xFFFFFF00
#define LTDC_COLOR_BLUE 0xFF0000FF
#define LTDC_COLOR_FUCHSIA 0xFFFF00FF
#define LTDC_COLOR_AQUA 0xFF00FFFF
#define LTDC_COLOR_WHITE 0xFFFFFFFF
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*
* These definitions should already be defined by stm32_isr.h
*/
#if !defined(STM32_LTDC_EV_NUMBER) && !defined(__DOXYGEN__)
#define STM32_LTDC_EV_NUMBER LTDC_IRQn
#endif
#if !defined(STM32_LTDC_ER_NUMBER) && !defined(__DOXYGEN__)
#define STM32_LTDC_ER_NUMBER LTDC_ER_IRQn
#endif
/*
* These definitions should already be defined by hal_lld.h
*/
#if !defined(STM32_LTDC_EV_HANDLER) && !defined(__DOXYGEN__)
#define STM32_LTDC_EV_HANDLER Vector1A0
#endif
#if !defined(STM32_LTDC_ER_HANDLER) && !defined(__DOXYGEN__)
#define STM32_LTDC_ER_HANDLER Vector1A4
#endif
#if !defined(STM32_HAS_LTDC) && !defined(__DOXYGEN__)
#ifdef STM32F429_439xx
#define STM32_HAS_LTDC TRUE
#else
#define STM32_HAS_LTDC FALSE
#endif
#endif
/**
* @name LTDC configuration options
* @{
*/
/**
* @brief LTDC event interrupt priority level setting.
*/
#if !defined(STM32_LTDC_EV_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_LTDC_EV_IRQ_PRIORITY 11
#endif
/**
* @brief LTDC error interrupt priority level setting.
*/
#if !defined(STM32_LTDC_ER_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_LTDC_ER_IRQ_PRIORITY 11
#endif
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(LTDC_USE_WAIT) || defined(__DOXYGEN__)
#define LTDC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p ltdcAcquireBus() and @p ltdcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(LTDC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define LTDC_USE_MUTUAL_EXCLUSION TRUE
#endif
/**
* @brief Provides software color conversion functions.
* @note Disabling this option saves both code and data space.
*/
#if !defined(LTDC_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__)
#define LTDC_USE_SOFTWARE_CONVERSIONS TRUE
#endif
/**
* @brief Enables checks for LTDC functions.
* @note Disabling this option saves both code and data space.
* @note Disabling checks by ChibiOS will automatically disable LTDC checks.
*/
#if !defined(LTDC_USE_CHECKS) || defined(__DOXYGEN__)
#define LTDC_USE_CHECKS TRUE
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#ifndef STM32F429_439xx
#error "Currently only STM32F429xx and STM32F439xx are supported"
#endif
#if (TRUE != STM32_HAS_LTDC)
#error "LTDC must be present when using the LTDC subsystem"
#endif
#if (TRUE == STM32_LTDC_USE_LTDC) && (TRUE != STM32_HAS_LTDC)
#error "LTDC not present in the selected device"
#endif
#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION)
#if (TRUE != CH_CFG_USE_MUTEXES) && (TRUE != CH_CFG_USE_SEMAPHORES)
#error "LTDC_USE_MUTUAL_EXCLUSION requires CH_CFG_USE_MUTEXES and/or CH_CFG_USE_SEMAPHORES"
#endif
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/* Complex types forwarding.*/
typedef union ltdc_coloralias_t ltdc_coloralias_t;
typedef struct ltdc_window_t ltdc_window_t;
typedef struct ltdc_frame_t ltdc_frame_t;
typedef struct ltdc_laycfg_t ltdc_laycfg_t;
typedef struct LTDCConfig LTDCConfig;
typedef enum ltdc_state_t ltdc_state_t;
typedef struct LTDCDriver LTDCDriver;
/**
* @name LTDC Data types
* @{
*/
/**
* @brief LTDC generic color.
*/
typedef uint32_t ltdc_color_t;
/**
* @brief LTDC color aliases.
* @detail Mapped with ARGB-8888, except for luminance (L mapped onto B).
* Padding fields prefixed with <tt>'x'</tt>, which should be clear
* (all 0) before compression and set (all 1) after expansion.
*/
typedef union ltdc_coloralias_t {
struct {
unsigned b : 8;
unsigned g : 8;
unsigned r : 8;
unsigned a : 8;
} argb8888; /**< Mapped ARGB-8888 bits.*/
struct {
unsigned b : 8;
unsigned g : 8;
unsigned r : 8;
unsigned xa : 8;
} rgb888; /**< Mapped RGB-888 bits.*/
struct {
unsigned xb : 3;
unsigned b : 5;
unsigned xg : 2;
unsigned g : 6;
unsigned xr : 3;
unsigned r : 5;
unsigned xa : 8;
} rgb565; /**< Mapped RGB-565 bits.*/
struct {
unsigned xb : 3;
unsigned b : 5;
unsigned xg : 3;
unsigned g : 5;
unsigned xr : 3;
unsigned r : 5;
unsigned xa : 7;
unsigned a : 1;
} argb1555; /**< Mapped ARGB-1555 values.*/
struct {
unsigned xb : 4;
unsigned b : 4;
unsigned xg : 4;
unsigned g : 4;
unsigned xr : 4;
unsigned r : 4;
unsigned xa : 4;
unsigned a : 4;
} argb4444; /**< Mapped ARGB-4444 values.*/
struct {
unsigned l : 8;
unsigned x : 16;
unsigned xa : 8;
} l8; /**< Mapped L-8 bits.*/
struct {
unsigned xl : 4;
unsigned l : 4;
unsigned x : 16;
unsigned xa : 4;
unsigned a : 4;
} al44; /**< Mapped AL-44 bits.*/
struct {
unsigned l : 8;
unsigned x : 16;
unsigned a : 8;
} al88; /**< Mapped AL-88 bits.*/
ltdc_color_t aliased; /**< Aliased raw bits.*/
} ltdc_coloralias_t;
/**
* @brief LTDC layer identifier.
*/
typedef uint32_t ltdc_layerid_t;
/**
* @brief LTDC pixel format.
*/
typedef uint32_t ltdc_pixfmt_t;
/**
* @brief LTDC blending factor.
*/
typedef uint32_t ltdc_blendf_t;
/**
* @brief LTDC ISR callback.
*/
typedef void (*ltdc_isrcb_t)(LTDCDriver *ltdcp);
/**
* @brief LTDC window specifications.
*/
typedef struct ltdc_window_t {
uint16_t hstart; /**< Horizontal start pixel (left).*/
uint16_t hstop; /**< Horizontal stop pixel (right).*/
uint16_t vstart; /**< Vertical start pixel (top).*/
uint16_t vstop; /**< Vertical stop pixel (bottom).*/
} ltdc_window_t;
/**
* @brief LTDC frame specifications.
*/
typedef struct ltdc_frame_t {
void *bufferp; /**< Frame buffer address.*/
uint16_t width; /**< Frame width, in pixels.*/
uint16_t height; /**< Frame height, in pixels.*/
size_t pitch; /**< Line pitch, in bytes.*/
ltdc_pixfmt_t fmt; /**< Pixel format.*/
} ltdc_frame_t;
/**
* @brief LTDC configuration flags.
*/
typedef uint8_t ltdc_flags_t;
/**
* @brief LTDC startup layer configuration.
*/
typedef struct ltdc_laycfg_t {
const ltdc_frame_t *frame; /**< Frame buffer specifications.*/
const ltdc_window_t *window; /**< Window specifications.*/
ltdc_color_t def_color; /**< Default color, ARGB-8888.*/
uint8_t const_alpha; /**< Constant alpha factor.*/
ltdc_color_t key_color; /**< Color key.*/
const ltdc_color_t *pal_colors; /**< Palette colors, or @p NULL.*/
uint16_t pal_length; /**< Palette length, or @p 0.*/
ltdc_blendf_t blending; /**< Blending factors.*/
ltdc_flags_t flags; /**< Layer configuration flags.*/
} ltdc_laycfg_t;
/**
* @brief LTDC driver configuration.
*/
typedef struct LTDCConfig {
/* Display specifications.*/
uint16_t screen_width; /**< Screen pixel width.*/
uint16_t screen_height; /**< Screen pixel height.*/
uint16_t hsync_width; /**< Horizontal sync pixel width.*/
uint16_t vsync_height; /**< Vertical sync pixel height.*/
uint16_t hbp_width; /**< Horizontal back porch pixel width.*/
uint16_t vbp_height; /**< Vertical back porch pixel height.*/
uint16_t hfp_width; /**< Horizontal front porch pixel width.*/
uint16_t vfp_height; /**< Vertical front porch pixel height.*/
ltdc_flags_t flags; /**< Driver configuration flags.*/
/* ISR callbacks.*/
ltdc_isrcb_t line_isr; /**< Line Interrupt ISR, or @p NULL.*/
ltdc_isrcb_t rr_isr; /**< Register Reload ISR, or @p NULL.*/
ltdc_isrcb_t fuerr_isr; /**< FIFO Underrun ISR, or @p NULL.*/
ltdc_isrcb_t terr_isr; /**< Transfer Error ISR, or @p NULL.*/
/* Layer and color settings.*/
ltdc_color_t clear_color; /**< Clear screen color, RGB-888.*/
const ltdc_laycfg_t *bg_laycfg; /**< Background layer specs, or @p NULL.*/
const ltdc_laycfg_t *fg_laycfg; /**< Foreground layer specs, or @p NULL.*/
} LTDCConfig;
/**
* @brief LTDC driver state.
*/
typedef enum ltdc_state_t {
LTDC_UNINIT = 0, /**< Not initialized.*/
LTDC_STOP = 1, /**< Stopped.*/
LTDC_READY = 2, /**< Ready.*/
LTDC_ACTIVE = 3, /**< Executing commands.*/
} ltdc_state_t;
/**
* @brief LTDC driver.
*/
typedef struct LTDCDriver {
ltdc_state_t state; /**< Driver state.*/
const LTDCConfig *config; /**< Driver configuration.*/
/* Handy computations.*/
ltdc_window_t active_window; /**< Active window coordinates.*/
/* Multithreading stuff.*/
#if (TRUE == LTDC_USE_WAIT) || defined(__DOXYGEN__)
thread_t *thread; /**< Waiting thread.*/
#endif /* LTDC_USE_WAIT */
#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION)
#if (TRUE == CH_CFG_USE_MUTEXES)
mutex_t lock; /**< Multithreading lock.*/
#elif (TRUE == CH_CFG_USE_SEMAPHORES)
semaphore_t lock; /**< Multithreading lock.*/
#endif
#endif /* LTDC_USE_MUTUAL_EXCLUSION */
} LTDCDriver;
/** @} */
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Makes an ARGB-8888 value from byte components.
*
* @param[in] a alpha byte component
* @param[in] r red byte component
* @param[in] g green byte component
* @param[in] b blue byte component
*
* @return color in ARGB-8888 format
*
* @api
*/
#define ltdcMakeARGB8888(a, r, g, b) \
((((ltdc_color_t)(a) & 0xFF) << 24) | \
(((ltdc_color_t)(r) & 0xFF) << 16) | \
(((ltdc_color_t)(g) & 0xFF) << 8) | \
(((ltdc_color_t)(b) & 0xFF) << 0))
/**
* @brief Compute bytes per pixel.
* @details Computes the bytes per pixel for the specified pixel format.
* Rounds to the ceiling.
*
* @param[in] fmt pixel format
*
* @return bytes per pixel
*
* @api
*/
#define ltdcBytesPerPixel(fmt) \
((ltdcBitsPerPixel(fmt) + 7) >> 3)
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
extern LTDCDriver LTDCD1;
#ifdef __cplusplus
extern "C" {
#endif
/* Driver methods.*/
void ltdcInit(void);
void ltdcObjectInit(LTDCDriver *ltdcp);
ltdc_state_t ltdcGetStateI(LTDCDriver *ltdcp);
ltdc_state_t ltdcGetState(LTDCDriver *ltdcp);
void ltdcStart(LTDCDriver *ltdcp, const LTDCConfig *configp);
void ltdcStop(LTDCDriver *ltdcp);
#if (TRUE == LTDC_USE_MUTUAL_EXCLUSION)
void ltdcAcquireBusS(LTDCDriver *ltdcp);
void ltdcAcquireBus(LTDCDriver *ltdcp);
void ltdcReleaseBusS(LTDCDriver *ltdcp);
void ltdcReleaseBus(LTDCDriver *ltdcp);
#endif /* LTDC_USE_MUTUAL_EXCLUSION */
/* Global methods.*/
ltdc_flags_t ltdcGetEnableFlagsI(LTDCDriver *ltdcp);
ltdc_flags_t ltdcGetEnableFlags(LTDCDriver *ltdcp);
void ltdcSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags);
void ltdcSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags);
bool ltdcIsReloadingI(LTDCDriver *ltdcp);
bool ltdcIsReloading(LTDCDriver *ltdcp);
void ltdcStartReloadI(LTDCDriver *ltdcp, bool immediately);
void ltdcStartReload(LTDCDriver *ltdcp, bool immediately);
void ltdcReloadS(LTDCDriver *ltdcp, bool immediately);
void ltdcReload(LTDCDriver *ltdcp, bool immediately);
bool ltdcIsDitheringEnabledI(LTDCDriver *ltdcp);
bool ltdcIsDitheringEnabled(LTDCDriver *ltdcp);
void ltdcEnableDitheringI(LTDCDriver *ltdcp);
void ltdcEnableDithering(LTDCDriver *ltdcp);
void ltdcDisableDitheringI(LTDCDriver *ltdcp);
void ltdcDisableDithering(LTDCDriver *ltdcp);
ltdc_color_t ltdcGetClearColorI(LTDCDriver *ltdcp);
ltdc_color_t ltdcGetClearColor(LTDCDriver *ltdcp);
void ltdcSetClearColorI(LTDCDriver *ltdcp, ltdc_color_t c);
void ltdcSetClearColor(LTDCDriver *ltdcp, ltdc_color_t c);
uint16_t ltdcGetLineInterruptPosI(LTDCDriver *ltdcp);
uint16_t ltdcGetLineInterruptPos(LTDCDriver *ltdcp);
void ltdcSetLineInterruptPosI(LTDCDriver *ltdcp, uint16_t line);
void ltdcSetLineInterruptPos(LTDCDriver *ltdcp, uint16_t line);
bool ltdcIsLineInterruptEnabledI(LTDCDriver *ltdcp);
bool ltdcIsLineInterruptEnabled(LTDCDriver *ltdcp);
void ltdcEnableLineInterruptI(LTDCDriver *ltdcp);
void ltdcEnableLineInterrupt(LTDCDriver *ltdcp);
void ltdcDisableLineInterruptI(LTDCDriver *ltdcp);
void ltdcDisableLineInterrupt(LTDCDriver *ltdcp);
void ltdcGetCurrentPosI(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp);
void ltdcGetCurrentPos(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp);
/* Background layer methods.*/
ltdc_flags_t ltdcBgGetEnableFlagsI(LTDCDriver *ltdcp);
ltdc_flags_t ltdcBgGetEnableFlags(LTDCDriver *ltdcp);
void ltdcBgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags);
void ltdcBgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags);
bool ltdcBgIsEnabledI(LTDCDriver *ltdcp);
bool ltdcBgIsEnabled(LTDCDriver *ltdcp);
void ltdcBgEnableI(LTDCDriver *ltdcp);
void ltdcBgEnable(LTDCDriver *ltdcp);
void ltdcBgDisableI(LTDCDriver *ltdcp);
void ltdcBgDisable(LTDCDriver *ltdcp);
bool ltdcBgIsPaletteEnabledI(LTDCDriver *ltdcp);
bool ltdcBgIsPaletteEnabled(LTDCDriver *ltdcp);
void ltdcBgEnablePaletteI(LTDCDriver *ltdcp);
void ltdcBgEnablePalette(LTDCDriver *ltdcp);
void ltdcBgDisablePaletteI(LTDCDriver *ltdcp);
void ltdcBgDisablePalette(LTDCDriver *ltdcp);
void ltdcBgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c);
void ltdcBgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c);
void ltdcBgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[],
uint16_t length);
void ltdcBgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[],
uint16_t length);
ltdc_pixfmt_t ltdcBgGetPixelFormatI(LTDCDriver *ltdcp);
ltdc_pixfmt_t ltdcBgGetPixelFormat(LTDCDriver *ltdcp);
void ltdcBgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt);
void ltdcBgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt);
bool ltdcBgIsKeyingEnabledI(LTDCDriver *ltdcp);
bool ltdcBgIsKeyingEnabled(LTDCDriver *ltdcp);
void ltdcBgEnableKeyingI(LTDCDriver *ltdcp);
void ltdcBgEnableKeying(LTDCDriver *ltdcp);
void ltdcBgDisableKeyingI(LTDCDriver *ltdcp);
void ltdcBgDisableKeying(LTDCDriver *ltdcp);
ltdc_color_t ltdcBgGetKeyingColorI(LTDCDriver *ltdcp);
ltdc_color_t ltdcBgGetKeyingColor(LTDCDriver *ltdcp);
void ltdcBgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c);
void ltdcBgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c);
uint8_t ltdcBgGetConstantAlphaI(LTDCDriver *ltdcp);
uint8_t ltdcBgGetConstantAlpha(LTDCDriver *ltdcp);
void ltdcBgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a);
void ltdcBgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a);
ltdc_color_t ltdcBgGetDefaultColorI(LTDCDriver *ltdcp);
ltdc_color_t ltdcBgGetDefaultColor(LTDCDriver *ltdcp);
void ltdcBgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c);
void ltdcBgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c);
ltdc_blendf_t ltdcBgGetBlendingFactorsI(LTDCDriver *ltdcp);
ltdc_blendf_t ltdcBgGetBlendingFactors(LTDCDriver *ltdcp);
void ltdcBgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf);
void ltdcBgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf);
void ltdcBgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp);
void ltdcBgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp);
void ltdcBgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp);
void ltdcBgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp);
void ltdcBgSetInvalidWindowI(LTDCDriver *ltdcp);
void ltdcBgSetInvalidWindow(LTDCDriver *ltdcp);
void ltdcBgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep);
void ltdcBgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep);
void ltdcBgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep);
void ltdcBgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep);
void *ltdcBgGetFrameAddressI(LTDCDriver *ltdcp);
void *ltdcBgGetFrameAddress(LTDCDriver *ltdcp);
void ltdcBgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp);
void ltdcBgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp);
void ltdcBgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp);
void ltdcBgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp);
void ltdcBgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp);
void ltdcBgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp);
/* Foreground layer methods.*/
ltdc_flags_t ltdcFgGetEnableFlagsI(LTDCDriver *ltdcp);
ltdc_flags_t ltdcFgGetEnableFlags(LTDCDriver *ltdcp);
void ltdcFgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags);
void ltdcFgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags);
bool ltdcFgIsEnabledI(LTDCDriver *ltdcp);
bool ltdcFgIsEnabled(LTDCDriver *ltdcp);
void ltdcFgEnableI(LTDCDriver *ltdcp);
void ltdcFgEnable(LTDCDriver *ltdcp);
void ltdcFgDisableI(LTDCDriver *ltdcp);
void ltdcFgDisable(LTDCDriver *ltdcp);
bool ltdcFgIsPaletteEnabledI(LTDCDriver *ltdcp);
bool ltdcFgIsPaletteEnabled(LTDCDriver *ltdcp);
void ltdcFgEnablePaletteI(LTDCDriver *ltdcp);
void ltdcFgEnablePalette(LTDCDriver *ltdcp);
void ltdcFgDisablePaletteI(LTDCDriver *ltdcp);
void ltdcFgDisablePalette(LTDCDriver *ltdcp);
void ltdcFgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c);
void ltdcFgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c);
void ltdcFgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[],
uint16_t length);
void ltdcFgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[],
uint16_t length);
ltdc_pixfmt_t ltdcFgGetPixelFormatI(LTDCDriver *ltdcp);
ltdc_pixfmt_t ltdcFgGetPixelFormat(LTDCDriver *ltdcp);
void ltdcFgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt);
void ltdcFgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt);
bool ltdcFgIsKeyingEnabledI(LTDCDriver *ltdcp);
bool ltdcFgIsKeyingEnabled(LTDCDriver *ltdcp);
void ltdcFgEnableKeyingI(LTDCDriver *ltdcp);
void ltdcFgEnableKeying(LTDCDriver *ltdcp);
void ltdcFgDisableKeyingI(LTDCDriver *ltdcp);
void ltdcFgDisableKeying(LTDCDriver *ltdcp);
ltdc_color_t ltdcFgGetKeyingColorI(LTDCDriver *ltdcp);
ltdc_color_t ltdcFgGetKeyingColor(LTDCDriver *ltdcp);
void ltdcFgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c);
void ltdcFgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c);
uint8_t ltdcFgGetConstantAlphaI(LTDCDriver *ltdcp);
uint8_t ltdcFgGetConstantAlpha(LTDCDriver *ltdcp);
void ltdcFgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a);
void ltdcFgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a);
ltdc_color_t ltdcFgGetDefaultColorI(LTDCDriver *ltdcp);
ltdc_color_t ltdcFgGetDefaultColor(LTDCDriver *ltdcp);
void ltdcFgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c);
void ltdcFgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c);
ltdc_blendf_t ltdcFgGetBlendingFactorsI(LTDCDriver *ltdcp);
ltdc_blendf_t ltdcFgGetBlendingFactors(LTDCDriver *ltdcp);
void ltdcFgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf);
void ltdcFgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf);
void ltdcFgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp);
void ltdcFgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp);
void ltdcFgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp);
void ltdcFgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp);
void ltdcFgSetInvalidWindowI(LTDCDriver *ltdcp);
void ltdcFgSetInvalidWindow(LTDCDriver *ltdcp);
void ltdcFgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep);
void ltdcFgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep);
void ltdcFgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep);
void ltdcFgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep);
void *ltdcFgGetFrameAddressI(LTDCDriver *ltdcp);
void *ltdcFgGetFrameAddress(LTDCDriver *ltdcp);
void ltdcFgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp);
void ltdcFgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp);
void ltdcFgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp);
void ltdcFgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp);
void ltdcFgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp);
void ltdcFgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp);
/* Helper functions.*/
size_t ltdcBitsPerPixel(ltdc_pixfmt_t fmt);
#if (TRUE == LTDC_USE_SOFTWARE_CONVERSIONS) || defined(__DOXYGEN__)
ltdc_color_t ltdcFromARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt);
ltdc_color_t ltdcToARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt);
#endif /* LTDC_USE_SOFTWARE_CONVERSIONS */
#ifdef __cplusplus
}
#endif
#endif /* STM32_LTDC_USE_LTDC */
#endif /* _STM32_LTDC_H_ */
/** @} */

8
os/hal/ports/STM32/STM32F4xx/platform.mk
View File

@ -1,11 +1,15 @@
include ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx/platform.mk
PLATFORMSRC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c \
PLATFORMSRC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.c \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.c \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/TIMv1/eicu_lld.c \
${CHIBIOS}/community/os/hal/src/fsmc_sdram.c
PLATFORMINC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1 \
PLATFORMINC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/DMA2Dv1 \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1 \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/LTDCv1 \
${CHIBIOS}/community/os/hal/ports/STM32/LLD/TIMv1 \
${CHIBIOS}/community/os/hal/ports/STM32/LLD