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Implemented AHB access for GPIOA - GPIOJ for TM4C123x devices. On TM4C129x devices the AHB is the only used bus for GPIO. 

Replaced the nops after starting the gpio peripheral clocks with a busy wait until all GPIO peripherals are ready.
Added Sub-Family identifier for TM4C123x devices.
This commit is contained in:
marcoveeneman 2015-03-03 21:15:21 +01:00
parent 12d6c494d3
commit 555d45f70a
5 changed files with 538 additions and 218 deletions
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13
demos/TIVA/RT-TM4C123G-LAUNCHPAD/mcuconf.h
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@ -24,6 +24,19 @@
#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \
TIVA_RCC_PWMDIV_8)
/*
* GPIO driver system settings.
*/
#define TIVA_GPIO_GPIOA_USE_AHB TRUE
#define TIVA_GPIO_GPIOB_USE_AHB TRUE
#define TIVA_GPIO_GPIOC_USE_AHB TRUE
#define TIVA_GPIO_GPIOD_USE_AHB TRUE
#define TIVA_GPIO_GPIOE_USE_AHB TRUE
#define TIVA_GPIO_GPIOF_USE_AHB TRUE
#define TIVA_GPIO_GPIOG_USE_AHB FALSE
#define TIVA_GPIO_GPIOH_USE_AHB FALSE
#define TIVA_GPIO_GPIOJ_USE_AHB FALSE
/*
* GPT driver system settings.
*/

319
os/hal/ports/TIVA/LLD/pal_lld.c
View File

@ -30,94 +30,206 @@
/* Driver local definitions. */
/*===========================================================================*/
#define RCGCGPIOA (1 << 0)
#define RCGCGPIOB (1 << 1)
#define RCGCGPIOC (1 << 2)
#define RCGCGPIOD (1 << 3)
#define RCGCGPIOE (1 << 4)
#define RCGCGPIOF (1 << 5)
#if TIVA_HAS_GPIOA || defined(__DOXYGEN__)
#define GPIOA_BIT (1 << 0)
#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x)
#define GPIOA_AHB_BIT (1 << 0)
#else
#define GPIOA_AHB_BIT 0
#endif
#else
#define GPIOA_BIT 0
#define GPIOA_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOB || defined(__DOXYGEN__)
#define GPIOB_BIT (1 << 1)
#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x)
#define GPIOB_AHB_BIT (1 << 1)
#else
#define GPIOB_AHB_BIT 0
#endif
#else
#define GPIOB_BIT 0
#define GPIOB_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOC || defined(__DOXYGEN__)
#define GPIOC_BIT (1 << 2)
#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x)
#define GPIOC_AHB_BIT (1 << 2)
#else
#define GPIOC_AHB_BIT 0
#endif
#else
#define GPIOC_BIT 0
#define GPIOC_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOD || defined(__DOXYGEN__)
#define GPIOD_BIT (1 << 3)
#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x)
#define GPIOD_AHB_BIT (1 << 3)
#else
#define GPIOD_AHB_BIT 0
#endif
#else
#define GPIOD_BIT 0
#define GPIOD_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOE || defined(__DOXYGEN__)
#define GPIOE_BIT (1 << 4)
#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x)
#define GPIOE_AHB_BIT (1 << 4)
#else
#define GPIOE_AHB_BIT 0
#endif
#else
#define GPIOE_BIT 0
#define GPIOE_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOF || defined(__DOXYGEN__)
#define GPIOF_BIT (1 << 5)
#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x)
#define GPIOF_AHB_BIT (1 << 5)
#else
#define GPIOF_AHB_BIT 0
#endif
#else
#define GPIOF_BIT 0
#define GPIOF_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
#define RCGCGPIOG (1 << 6)
#define GPIOG_BIT (1 << 6)
#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x)
#define GPIOG_AHB_BIT (1 << 6)
#else
#define RCGCGPIOG 0
#define GPIOG_AHB_BIT 0
#endif
#else
#define GPIOG_BIT 0
#define GPIOG_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
#define RCGCGPIOH (1 << 7)
#define GPIOH_BIT (1 << 7)
#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x)
#define GPIOH_AHB_BIT (1 << 7)
#else
#define RCGCGPIOH 0
#define GPIOH_AHB_BIT 0
#endif
#else
#define GPIOH_BIT 0
#define GPIOH_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
#define RCGCGPIOJ (1 << 8)
#define GPIOJ_BIT (1 << 8)
#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x)
#define GPIOJ_AHB_BIT (1 << 8)
#else
#define RCGCGPIOJ 0
#define GPIOJ_AHB_BIT 0
#endif
#else
#define GPIOJ_BIT 0
#define GPIOJ_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
#define RCGCGPIOK (1 << 9)
#define GPIOK_BIT (1 << 9)
#define GPIOK_AHB_BIT (1 << 9)
#else
#define RCGCGPIOK 0
#define GPIOK_BIT 0
#define GPIOK_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
#define RCGCGPIOL (1 << 10)
#define GPIOL_BIT (1 << 10)
#define GPIOL_AHB_BIT (1 << 10)
#else
#define RCGCGPIOL 0
#define GPIOL_BIT 0
#define GPIOL_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
#define RCGCGPIOM (1 << 11)
#define GPIOM_BIT (1 << 11)
#define GPIOM_AHB_BIT (1 << 11)
#else
#define RCGCGPIOM 0
#define GPIOM_BIT 0
#define GPIOM_AHB_BIT 0
#endif
#if TIVA_HAS_GPION || defined(__DOXYGEN__)
#define RCGCGPION (1 << 12)
#define GPION_BIT (1 << 12)
#define GPION_AHB_BIT (1 << 12)
#else
#define RCGCGPION 0
#define GPION_BIT 0
#define GPION_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
#define RCGCGPIOP (1 << 13)
#define GPIOP_BIT (1 << 13)
#define GPIOP_AHB_BIT (1 << 13)
#else
#define RCGCGPIOP 0
#define GPIOP_BIT 0
#define GPIOP_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
#define RCGCGPIOQ (1 << 14)
#define GPIOQ_BIT (1 << 14)
#define GPIOQ_AHB_BIT (1 << 14)
#else
#define RCGCGPIOQ 0
#define GPIOQ_BIT 0
#define GPIOQ_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
#define RCGCGPIOR (1 << 15)
#define GPIOR_BIT (1 << 15)
#define GPIOR_AHB_BIT (1 << 15)
#else
#define RCGCGPIOR 0
#define GPIOR_BIT 0
#define GPIOR_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
#define RCGCGPIOS (1 << 16)
#define GPIOS_BIT (1 << 16)
#define GPIOS_AHB_BIT (1 << 16)
#else
#define RCGCGPIOS 0
#define GPIOS_BIT 0
#define GPIOS_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
#define RCGCGPIOT (1 << 17)
#define GPIOT_BIT (1 << 17)
#define GPIOT_AHB_BIT (1 << 17)
#else
#define RCGCGPIOT 0
#define GPIOT_BIT 0
#define GPIOT_AHB_BIT 0
#endif
#define RCGCGPIO_MASK (RCGCGPIOA | RCGCGPIOB | RCGCGPIOC | RCGCGPIOD | \
RCGCGPIOE | RCGCGPIOF | RCGCGPIOG | RCGCGPIOH | \
RCGCGPIOJ | RCGCGPIOK | RCGCGPIOL | RCGCGPIOM | \
RCGCGPION | RCGCGPIOP | RCGCGPIOQ | RCGCGPIOR | \
RCGCGPIOS | RCGCGPIOT)
#define RCGCGPIO_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \
GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \
GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT | \
GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT | \
GPIOS_BIT | GPIOR_BIT)
#define GPIOHBCTL_MASK (GPIOA_AHB_BIT | GPIOB_AHB_BIT | GPIOC_AHB_BIT | \
GPIOD_AHB_BIT | GPIOE_AHB_BIT | GPIOF_AHB_BIT | \
GPIOG_AHB_BIT | GPIOH_AHB_BIT | GPIOJ_AHB_BIT | \
GPIOK_AHB_BIT | GPIOL_AHB_BIT | GPIOM_AHB_BIT | \
GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT | \
GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT)
/* GPIO lock password.*/
#define TIVA_GPIO_LOCK_PWD 0x4C4F434B
#define GPIOC_JTAG_MASK (0x0F)
#define GPIOD_NMI_MASK (0x80)
#define GPIOF_NMI_MASK (0x01)
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@ -130,21 +242,40 @@
/* Driver local functions. */
/*===========================================================================*/
static void gpio_init (GPIO_TypeDef *gpiop, const tiva_gpio_setup_t *config)
/**
* @brief Initializes the port with the port configuration.
*
* @param[in] port the port identifier
* @param[in] config the port configuration
*/
static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config)
{
gpiop->DATA = config->data;
gpiop->DIR = config->dir;
gpiop->AFSEL = config->afsel;
gpiop->DR2R = config->dr2r;
gpiop->DR4R = config->dr4r;
gpiop->DR8R = config->dr8r;
gpiop->ODR = config->odr;
gpiop->PUR = config->pur;
gpiop->PDR = config->pdr;
gpiop->SLR = config->slr;
gpiop->DEN = config->den;
gpiop->AMSEL = config->amsel;
gpiop->PCTL = config->pctl;
port->DATA = config->data;
port->DIR = config->dir;
port->AFSEL = config->afsel;
port->DR2R = config->dr2r;
port->DR4R = config->dr4r;
port->DR8R = config->dr8r;
port->ODR = config->odr;
port->PUR = config->pur;
port->PDR = config->pdr;
port->SLR = config->slr;
port->DEN = config->den;
port->AMSEL = config->amsel;
port->PCTL = config->pctl;
}
/**
* @brief Unlocks the masked pins of the GPIO peripheral.
* @note This function is only useful for PORTC0-3, PORTD7 and PORTF0.
*
* @param[in] port the port identifier
* @param[in] mask the pin mask
*/
static void gpio_unlock(ioportid_t port, ioportmask_t mask)
{
port->LOCK = TIVA_GPIO_LOCK_PWD;
port->CR = mask;
}
/*===========================================================================*/
@ -156,95 +287,87 @@ static void gpio_init (GPIO_TypeDef *gpiop, const tiva_gpio_setup_t *config)
/*===========================================================================*/
/**
* @brief TIVA I/O ports configuration.
* @brief Tiva I/O ports configuration.
* @details Ports A-F (G, H, J, K, L, M, N, P, Q, R, S, T) clocks enabled.
*
* @param[in] config the TIVA ports configuration
* @param[in] config the Tiva ports configuration
*
* @notapi
*/
void _pal_lld_init(const PALConfig *config)
{
/*
* Enables all GPIO clocks.
*/
SYSCTL->RCGCGPIO = RCGCGPIO_MASK;
#if defined(TM4C123x)
SYSCTL->GPIOHBCTL = GPIOHBCTL_MASK;
#endif
/* Datasheet chapter 5.2.6: "There must be a delay of 3 system clocks after a
* peripheral module clock is enabled in the RCGC register before any module
* registers are accessed." */
__NOP();
__NOP();
__NOP();
/* Wait until all GPIO modules are ready */
while (!((SYSCTL->PRGPIO & RCGCGPIO_MASK) == RCGCGPIO_MASK))
;
#if TIVA_HAS_GPIOA
gpio_init(GPIOA, &config->PAData);
#endif
#if TIVA_HAS_GPIOB
gpio_init(GPIOB, &config->PBData);
/* Unlock pin 0, 1, 2 and 3 */
GPIOC->LOCK = TIVA_GPIO_LOCK_PWD;
GPIOC->CR = 0x0F;
#endif
#if TIVA_HAS_GPIOC
/* Unlock JTAG pins.*/
gpio_unlock(GPIOC, GPIOC_JTAG_MASK);
gpio_init(GPIOC, &config->PCData);
GPIOC->LOCK = 0;
/* Unlock pin 7 */
GPIOD->LOCK = TIVA_GPIO_LOCK_PWD;
GPIOD->CR = 0x80;
#endif
#if TIVA_HAS_GPIOD
/* Unlock NMI pin.*/
gpio_unlock(GPIOD, GPIOD_NMI_MASK);
gpio_init(GPIOD, &config->PDData);
GPIOC->LOCK = 0;
#endif
#if TIVA_HAS_GPIOE
gpio_init(GPIOE, &config->PEData);
/* Unlock pin 0 */
GPIOF->LOCK = TIVA_GPIO_LOCK_PWD;
GPIOF->CR = 0x01;
#endif
#if TIVA_HAS_GPIOF
/* Unlock NMI pin.*/
gpio_unlock(GPIOF, GPIOF_NMI_MASK);
gpio_init(GPIOF, &config->PFData);
GPIOF->LOCK = 0;
#endif
#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
gpio_init(GPIOG, &config->PGData);
#endif /* TIVA_HAS_GPIOG.*/
#endif
#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
gpio_init(GPIOH, &config->PHData);
#endif /* TIVA_HAS_GPIOH.*/
#endif
#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
gpio_init(GPIOJ, &config->PJData);
#endif /* TIVA_HAS_GPIOJ.*/
#endif
#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
gpio_init(GPIOK, &config->PKData);
#endif /* TIVA_HAS_GPIOK.*/
#endif
#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
gpio_init(GPIOL, &config->PLData);
#endif /* TIVA_HAS_GPIOL.*/
#endif
#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
gpio_init(GPIOM, &config->PMData);
#endif /* TIVA_HAS_GPIOM.*/
#endif
#if TIVA_HAS_GPION || defined(__DOXYGEN__)
gpio_init(GPION, &config->PNData);
#endif /* TIVA_HAS_GPION.*/
#endif
#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
gpio_init(GPIOP, &config->PPData);
#endif /* TIVA_HAS_GPIOP.*/
#endif
#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
gpio_init(GPIOQ, &config->PQData);
#endif /* TIVA_HAS_GPIOQ.*/
#endif
#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
gpio_init(GPIOR, &config->PRData);
#endif /* TIVA_HAS_GPIOR.*/
#endif
#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
gpio_init(GPIOS, &config->PSData);
#endif /* TIVA_HAS_GPIOS.*/
#endif
#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
gpio_init(GPIOT, &config->PTData);
#endif /* TIVA_HAS_GPIOT.*/
#endif
}
/**

159
os/hal/ports/TIVA/LLD/pal_lld.h
View File

@ -178,10 +178,169 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
#if defined(TM4C123x)
/**
* @brief GPIOA AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOA. When set
* to @p FALSE the APB bus is used to access GPIOA.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOA_USE_AHB TRUE
#endif
/**
* @brief GPIOB AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOB. When set
* to @p FALSE the APB bus is used to access GPIOB.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOB_USE_AHB TRUE
#endif
/**
* @brief GPIOC AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOC. When set
* to @p FALSE the APB bus is used to access GPIOC.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOC_USE_AHB TRUE
#endif
/**
* @brief GPIOD AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOD. When set
* to @p FALSE the APB bus is used to access GPIOD.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOD_USE_AHB TRUE
#endif
/**
* @brief GPIOE AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOE. When set
* to @p FALSE the APB bus is used to access GPIOE.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOE_USE_AHB TRUE
#endif
/**
* @brief GPIOF AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOF. When set
* to @p FALSE the APB bus is used to access GPIOF.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOF_USE_AHB TRUE
#endif
/**
* @brief GPIOG AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOG. When set
* to @p FALSE the APB bus is used to access GPIOG.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOG_USE_AHB TRUE
#endif
/**
* @brief GPIOH AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOH. When set
* to @p FALSE the APB bus is used to access GPIOH.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOH_USE_AHB TRUE
#endif
/**
* @brief GPIOJ AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set
* to @p FALSE the APB bus is used to access GPIOJ.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOJ_USE_AHB TRUE
#endif
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if defined(TM4C123x)
#if TIVA_GPIO_GPIOA_USE_AHB
#define GPIOA GPIOA_AHB
#else
#define GPIOA GPIOA_APB
#endif
#if TIVA_GPIO_GPIOB_USE_AHB
#define GPIOB GPIOB_AHB
#else
#define GPIOB GPIOB_APB
#endif
#if TIVA_GPIO_GPIOC_USE_AHB
#define GPIOC GPIOC_AHB
#else
#define GPIOC GPIOC_APB
#endif
#if TIVA_GPIO_GPIOD_USE_AHB
#define GPIOD GPIOD_AHB
#else
#define GPIOD GPIOD_APB
#endif
#if TIVA_GPIO_GPIOE_USE_AHB
#define GPIOE GPIOE_AHB
#else
#define GPIOE GPIOE_APB
#endif
#if TIVA_GPIO_GPIOF_USE_AHB
#define GPIOF GPIOF_AHB
#else
#define GPIOF GPIOF_APB
#endif
#if TIVA_GPIO_GPIOG_USE_AHB
#define GPIOG GPIOG_AHB
#else
#define GPIOG GPIOG_APB
#endif
#if TIVA_GPIO_GPIOH_USE_AHB
#define GPIOH GPIOH_AHB
#else
#define GPIOH GPIOH_APB
#endif
#if TIVA_GPIO_GPIOJ_USE_AHB
#define GPIOJ GPIOJ_AHB
#else
#define GPIOJ GPIOJ_APB
#endif
#define GPIOK GPIOK_AHB
#define GPIOL GPIOL_AHB
#define GPIOM GPIOM_AHB
#define GPION GPION_AHB
#define GPIOP GPIOP_AHB
#define GPIOQ GPIOQ_AHB
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/

7
os/hal/ports/TIVA/TM4C123x/tiva_registry.h
View File

@ -58,6 +58,13 @@
#error "No valid device defined."
#endif
/**
* @brief Sub-family identifier.
*/
#if !defined(TM4C123x) || defined(__DOXYGEN__)
#define TM4C123x
#endif
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/

258
os/hal/ports/TIVA/TM4C123x/tm4c123x.h
View File

@ -784,68 +784,77 @@ typedef struct
* @{
*/
#define SYSCTL_BASE 0x400FE000
#define HIB_BASE 0x400FC000
#define FLASH_BASE 0x400FD000
#define EEPROM_BASE 0x400AF000
#define UDMA_BASE 0x400FF000
#define GPIOA_BASE 0x40004000
#define GPIOB_BASE 0x40005000
#define GPIOC_BASE 0x40006000
#define GPIOD_BASE 0x40007000
#define GPIOE_BASE 0x40024000
#define GPIOF_BASE 0x40025000
#define GPIOG_BASE 0x40026000
#define GPIOH_BASE 0x40027000
#define GPIOJ_BASE 0x4003D000
#define GPIOK_BASE 0x40061000
#define GPIOL_BASE 0x40062000
#define GPIOM_BASE 0x40063000
#define GPION_BASE 0x40064000
#define GPIOP_BASE 0x40065000
#define GPIOQ_BASE 0x40066000
#define GPT0_BASE 0x40030000
#define GPT1_BASE 0x40031000
#define GPT2_BASE 0x40032000
#define GPT3_BASE 0x40033000
#define GPT4_BASE 0x40034000
#define GPT5_BASE 0x40035000
#define WGPT0_BASE 0x40036000
#define WGPT1_BASE 0x40037000
#define WGPT2_BASE 0x4004C000
#define WGPT3_BASE 0x4004D000
#define WGPT4_BASE 0x4004E000
#define WGPT5_BASE 0x4004F000
#define WDT0_BASE 0x40000000
#define WDT1_BASE 0x40001000
#define ADC0_BASE 0x40038000
#define ADC1_BASE 0x40039000
#define UART0_BASE 0x4000C000
#define UART1_BASE 0x4000D000
#define UART2_BASE 0x4000E000
#define UART3_BASE 0x4000F000
#define UART4_BASE 0x40010000
#define UART5_BASE 0x40011000
#define UART6_BASE 0x40012000
#define UART7_BASE 0x40013000
#define SSI0_BASE 0x40008000
#define SSI1_BASE 0x40009000
#define SSI2_BASE 0x4000A000
#define SSI3_BASE 0x4000B000
#define I2C0_BASE 0x40020000
#define I2C1_BASE 0x40021000
#define I2C2_BASE 0x40022000
#define I2C3_BASE 0x40023000
#define I2C4_BASE 0x40023000
#define I2C5_BASE 0x40023000
#define CAN0_BASE 0x40040000
#define CAN1_BASE 0x40041000
#define SYSCTL_BASE 0x400FE000
#define HIB_BASE 0x400FC000
#define FLASH_BASE 0x400FD000
#define EEPROM_BASE 0x400AF000
#define UDMA_BASE 0x400FF000
#define GPIOA_APB_BASE 0x40004000
#define GPIOA_AHB_BASE 0x40058000
#define GPIOB_APB_BASE 0x40005000
#define GPIOB_AHB_BASE 0x40059000
#define GPIOC_APB_BASE 0x40006000
#define GPIOC_AHB_BASE 0x4005A000
#define GPIOD_APB_BASE 0x40007000
#define GPIOD_AHB_BASE 0x4005B000
#define GPIOE_APB_BASE 0x40024000
#define GPIOE_AHB_BASE 0x4005C000
#define GPIOF_APB_BASE 0x40025000
#define GPIOF_AHB_BASE 0x4005D000
#define GPIOG_APB_BASE 0x40026000
#define GPIOG_AHB_BASE 0x4005E000
#define GPIOH_APB_BASE 0x40027000
#define GPIOH_AHB_BASE 0x4005F000
#define GPIOJ_APB_BASE 0x4003D000
#define GPIOJ_AHB_BASE 0x40060000
#define GPIOK_AHB_BASE 0x40061000
#define GPIOL_AHB_BASE 0x40062000
#define GPIOM_AHB_BASE 0x40063000
#define GPION_AHB_BASE 0x40064000
#define GPIOP_AHB_BASE 0x40065000
#define GPIOQ_AHB_BASE 0x40066000
#define GPT0_BASE 0x40030000
#define GPT1_BASE 0x40031000
#define GPT2_BASE 0x40032000
#define GPT3_BASE 0x40033000
#define GPT4_BASE 0x40034000
#define GPT5_BASE 0x40035000
#define WGPT0_BASE 0x40036000
#define WGPT1_BASE 0x40037000
#define WGPT2_BASE 0x4004C000
#define WGPT3_BASE 0x4004D000
#define WGPT4_BASE 0x4004E000
#define WGPT5_BASE 0x4004F000
#define WDT0_BASE 0x40000000
#define WDT1_BASE 0x40001000
#define ADC0_BASE 0x40038000
#define ADC1_BASE 0x40039000
#define UART0_BASE 0x4000C000
#define UART1_BASE 0x4000D000
#define UART2_BASE 0x4000E000
#define UART3_BASE 0x4000F000
#define UART4_BASE 0x40010000
#define UART5_BASE 0x40011000
#define UART6_BASE 0x40012000
#define UART7_BASE 0x40013000
#define SSI0_BASE 0x40008000
#define SSI1_BASE 0x40009000
#define SSI2_BASE 0x4000A000
#define SSI3_BASE 0x4000B000
#define I2C0_BASE 0x40020000
#define I2C1_BASE 0x40021000
#define I2C2_BASE 0x40022000
#define I2C3_BASE 0x40023000
#define I2C4_BASE 0x40023000
#define I2C5_BASE 0x40023000
#define CAN0_BASE 0x40040000
#define CAN1_BASE 0x40041000
// usb
#define ACMP_BASE 0x4003C000
#define PWM0_BASE 0x40028000
#define PWM1_BASE 0x40029000
#define QEI0_BASE 0x4002C000
#define QEI1_BASE 0x4002D000
#define ACMP_BASE 0x4003C000
#define PWM0_BASE 0x40028000
#define PWM1_BASE 0x40029000
#define QEI0_BASE 0x4002C000
#define QEI1_BASE 0x4002D000
/**
* @}
@ -856,66 +865,75 @@ typedef struct
* @{
*/
#define SYSCTL ((SYSCTL_TypeDef *) SYSCTL_BASE)
#define HIB ((HIB_TypeDef *) HIB_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_BASE)
#define EEPROM ((EEPROM_TypeDef *) EEPROM_BASE)
#define UDMA ((UDMA_TypeDef *) UDMA_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
#define GPIOL ((GPIO_TypeDef *) GPIOL_BASE)
#define GPIOM ((GPIO_TypeDef *) GPIOM_BASE)
#define GPION ((GPIO_TypeDef *) GPION_BASE)
#define GPIOP ((GPIO_TypeDef *) GPIOP_BASE)
#define GPIOQ ((GPIO_TypeDef *) GPIOQ_BASE)
#define GPT0 ((GPT_TypeDef *) GPT0_BASE)
#define GPT1 ((GPT_TypeDef *) GPT1_BASE)
#define GPT2 ((GPT_TypeDef *) GPT2_BASE)
#define GPT3 ((GPT_TypeDef *) GPT3_BASE)
#define GPT4 ((GPT_TypeDef *) GPT4_BASE)
#define GPT5 ((GPT_TypeDef *) GPT5_BASE)
#define WGPT0 ((GPT_TypeDef *) WGPT0_BASE)
#define WGPT1 ((GPT_TypeDef *) WGPT1_BASE)
#define WGPT2 ((GPT_TypeDef *) WGPT2_BASE)
#define WGPT3 ((GPT_TypeDef *) WGPT3_BASE)
#define WGPT4 ((GPT_TypeDef *) WGPT4_BASE)
#define WGPT5 ((GPT_TypeDef *) WGPT5_BASE)
#define ADC0 ((ADC_TypeDef*) ADC0_BASE)
#define ADC1 ((ADC_TypeDef*) ADC1_BASE)
#define UART0 ((UART_TypeDef *) UART0_BASE)
#define UART1 ((UART_TypeDef *) UART1_BASE)
#define UART2 ((UART_TypeDef *) UART2_BASE)
#define UART3 ((UART_TypeDef *) UART3_BASE)
#define UART4 ((UART_TypeDef *) UART4_BASE)
#define UART5 ((UART_TypeDef *) UART5_BASE)
#define UART6 ((UART_TypeDef *) UART6_BASE)
#define UART7 ((UART_TypeDef *) UART7_BASE)
#define SSI0 ((SSI_TypeDef *) SSI0_BASE)
#define SSI1 ((SSI_TypeDef *) SSI1_BASE)
#define SSI2 ((SSI_TypeDef *) SSI2_BASE)
#define SSI3 ((SSI_TypeDef *) SSI3_BASE)
#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
#define I2C5 ((I2C_TypeDef *) I2C5_BASE)
#define CAN0 ((CAN_TypeDef *) CAN0_BASE)
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define SYSCTL ((SYSCTL_TypeDef *) SYSCTL_BASE)
#define HIB ((HIB_TypeDef *) HIB_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_BASE)
#define EEPROM ((EEPROM_TypeDef *) EEPROM_BASE)
#define UDMA ((UDMA_TypeDef *) UDMA_BASE)
#define GPIOA_APB ((GPIO_TypeDef *) GPIOA_APB_BASE)
#define GPIOA_AHB ((GPIO_TypeDef *) GPIOA_AHB_BASE)
#define GPIOB_APB ((GPIO_TypeDef *) GPIOB_APB_BASE)
#define GPIOB_AHB ((GPIO_TypeDef *) GPIOB_AHB_BASE)
#define GPIOC_APB ((GPIO_TypeDef *) GPIOC_APB_BASE)
#define GPIOC_AHB ((GPIO_TypeDef *) GPIOC_AHB_BASE)
#define GPIOD_APB ((GPIO_TypeDef *) GPIOD_APB_BASE)
#define GPIOD_AHB ((GPIO_TypeDef *) GPIOD_AHB_BASE)
#define GPIOE_APB ((GPIO_TypeDef *) GPIOE_APB_BASE)
#define GPIOE_AHB ((GPIO_TypeDef *) GPIOE_AHB_BASE)
#define GPIOF_APB ((GPIO_TypeDef *) GPIOF_APB_BASE)
#define GPIOF_AHB ((GPIO_TypeDef *) GPIOF_AHB_BASE)
#define GPIOG_APB ((GPIO_TypeDef *) GPIOG_APB_BASE)
#define GPIOG_AHB ((GPIO_TypeDef *) GPIOG_AHB_BASE)
#define GPIOH_APB ((GPIO_TypeDef *) GPIOH_APB_BASE)
#define GPIOH_AHB ((GPIO_TypeDef *) GPIOH_AHB_BASE)
#define GPIOJ_APB ((GPIO_TypeDef *) GPIOJ_APB_BASE)
#define GPIOJ_AHB ((GPIO_TypeDef *) GPIOJ_AHB_BASE)
#define GPIOK_AHB ((GPIO_TypeDef *) GPIOK_AHB_BASE)
#define GPIOL_AHB ((GPIO_TypeDef *) GPIOL_AHB_BASE)
#define GPIOM_AHB ((GPIO_TypeDef *) GPIOM_AHB_BASE)
#define GPION_AHB ((GPIO_TypeDef *) GPION_AHB_BASE)
#define GPIOP_AHB ((GPIO_TypeDef *) GPIOP_AHB_BASE)
#define GPIOQ_AHB ((GPIO_TypeDef *) GPIOQ_AHB_BASE)
#define GPT0 ((GPT_TypeDef *) GPT0_BASE)
#define GPT1 ((GPT_TypeDef *) GPT1_BASE)
#define GPT2 ((GPT_TypeDef *) GPT2_BASE)
#define GPT3 ((GPT_TypeDef *) GPT3_BASE)
#define GPT4 ((GPT_TypeDef *) GPT4_BASE)
#define GPT5 ((GPT_TypeDef *) GPT5_BASE)
#define WGPT0 ((GPT_TypeDef *) WGPT0_BASE)
#define WGPT1 ((GPT_TypeDef *) WGPT1_BASE)
#define WGPT2 ((GPT_TypeDef *) WGPT2_BASE)
#define WGPT3 ((GPT_TypeDef *) WGPT3_BASE)
#define WGPT4 ((GPT_TypeDef *) WGPT4_BASE)
#define WGPT5 ((GPT_TypeDef *) WGPT5_BASE)
#define ADC0 ((ADC_TypeDef*) ADC0_BASE)
#define ADC1 ((ADC_TypeDef*) ADC1_BASE)
#define UART0 ((UART_TypeDef *) UART0_BASE)
#define UART1 ((UART_TypeDef *) UART1_BASE)
#define UART2 ((UART_TypeDef *) UART2_BASE)
#define UART3 ((UART_TypeDef *) UART3_BASE)
#define UART4 ((UART_TypeDef *) UART4_BASE)
#define UART5 ((UART_TypeDef *) UART5_BASE)
#define UART6 ((UART_TypeDef *) UART6_BASE)
#define UART7 ((UART_TypeDef *) UART7_BASE)
#define SSI0 ((SSI_TypeDef *) SSI0_BASE)
#define SSI1 ((SSI_TypeDef *) SSI1_BASE)
#define SSI2 ((SSI_TypeDef *) SSI2_BASE)
#define SSI3 ((SSI_TypeDef *) SSI3_BASE)
#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
#define I2C5 ((I2C_TypeDef *) I2C5_BASE)
#define CAN0 ((CAN_TypeDef *) CAN0_BASE)
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
// usb
#define ACMP ((ACMP_TypeDef *) ACMP_BASE)
#define PWM0 ((PWM_TypeDef *) PWM0_BASE)
#define PWM1 ((PWM_TypeDef *) PWM1_BASE)
#define QEI0 ((QEI_TypeDef *) QEI0_BASE)
#define QEI1 ((QEI_TypeDef *) QEI1_BASE)
#define ACMP ((ACMP_TypeDef *) ACMP_BASE)
#define PWM0 ((PWM_TypeDef *) PWM0_BASE)
#define PWM1 ((PWM_TypeDef *) PWM1_BASE)
#define QEI0 ((QEI_TypeDef *) QEI0_BASE)
#define QEI1 ((QEI_TypeDef *) QEI1_BASE)
/**
* @}