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Merge pull request #91 from sdalu/nrf52832 

Nrf52832
This commit is contained in:
Fabio Utzig 2016-07-17 21:30:35 -03:00 committed by GitHub
parent bf620a05ed 194e5ec59c
commit 569aa39fba
57 changed files with 19961 additions and 529 deletions
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12
demos/NRF51/OSHCHIP_V1.0/mcuconf.h
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@ -17,15 +17,15 @@
#ifndef _MCUCONF_H_
#define _MCUCONF_H_
/* Possible value for NRF51_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth */
#define NRF51_LFCLK_SOURCE 0
/* Possible value for NRF5_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth */
#define NRF5_LFCLK_SOURCE 0
/*
* HAL driver system settings.
*/
#define NRF51_SERIAL_USE_UART0 TRUE
#define NRF51_ST_USE_RTC0 TRUE
#define NRF51_ST_USE_RTC1 FALSE
#define NRF51_ST_USE_TIMER0 FALSE
#define NRF5_SERIAL_USE_UART0 TRUE
#define NRF5_ST_USE_RTC0 TRUE
#define NRF5_ST_USE_RTC1 FALSE
#define NRF5_ST_USE_TIMER0 FALSE
#endif /* _MCUCONF_H_ */

8
demos/NRF51/RT-WVSHARE_BLE400/mcuconf.h
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@ -20,9 +20,9 @@
/*
* HAL driver system settings.
*/
#define NRF51_SERIAL_USE_UART0 TRUE
#define NRF51_ST_USE_RTC0 TRUE
#define NRF51_ST_USE_RTC1 FALSE
#define NRF51_ST_USE_TIMER0 FALSE
#define NRF5_SERIAL_USE_UART0 TRUE
#define NRF5_ST_USE_RTC0 TRUE
#define NRF5_ST_USE_RTC1 FALSE
#define NRF5_ST_USE_TIMER0 FALSE
#endif /* _MCUCONF_H_ */

251
demos/NRF52/Classic/Makefile Normal file
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@ -0,0 +1,251 @@
##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
PLATFORM=NRF5/NRF52832
BOARD=NRF52-DK
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -Os -ggdb -fomit-frame-pointer -falign-functions=16 -std=c11
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# Linker extra options here.
ifeq ($(USE_LDOPT),)
USE_LDOPT =
endif
# Enable this if you want link time optimizations (LTO)
ifeq ($(USE_LTO),)
USE_LTO = yes
endif
# If enabled, this option allows to compile the application in THUMB mode.
ifeq ($(USE_THUMB),)
USE_THUMB = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
# If enabled, this option makes the build process faster by not compiling
# modules not used in the current configuration.
ifeq ($(USE_SMART_BUILD),)
USE_SMART_BUILD = no
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Stack size to be allocated to the Cortex-M process stack. This stack is
# the stack used by the main() thread.
ifeq ($(USE_PROCESS_STACKSIZE),)
USE_PROCESS_STACKSIZE = 0x400
endif
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
# stack is used for processing interrupts and exceptions.
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
USE_EXCEPTIONS_STACKSIZE = 0x400
endif
# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
ifeq ($(USE_FPU),)
USE_FPU = no
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, sources and paths
#
# Define project name here
PROJECT = ch
# Imported source files and paths
NRF51SDK = /home/sdalu/nRF51-SDK
CHIBIOS = /home/sdalu/ChibiOS/ChibiOS
CHIBIOS_CONTRIB = /home/sdalu/ChibiOS/ChibiOS-Contrib
# Startup files.
include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS_CONTRIB)/os/hal/hal.mk
include $(CHIBIOS_CONTRIB)/os/hal/ports/$(PLATFORM)/platform.mk
include $(CHIBIOS_CONTRIB)/os/hal/boards/$(BOARD)/board.mk
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
# Other files (optional).
include $(CHIBIOS)/test/rt/test.mk
include $(CHIBIOS)/os/various/shell/shell.mk
# Define linker script file here
LDSCRIPT= $(STARTUPLD)/NRF52832.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(STARTUPSRC) \
$(KERNSRC) \
$(PORTSRC) \
$(OSALSRC) \
$(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
$(TESTSRC) \
$(SHELLSRC) \
$(CHIBIOS)/os/hal/lib/streams/memstreams.c \
$(CHIBIOS)/os/hal/lib/streams/chprintf.c
CSRC += main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC =
# C sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACSRC =
# C++ sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACPPSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCSRC =
# C++ sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCPPSRC =
# List ASM source files here
ASMSRC =
ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
INCDIR = $(CHIBIOS)/os/license \
$(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
$(SHELLINC) \
$(CHIBIOS)/os/hal/lib/streams $(CHIBIOS)/os/various
INCDIR += $(CHIBIOS_CONTRIB)/os/various
#
# Project, sources and paths
##############################################################################
##############################################################################
# Compiler settings
#
MCU = cortex-m4
TRGT = arm-none-eabi-
CC = $(TRGT)gcc
CPPC = $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
AR = $(TRGT)ar
OD = $(TRGT)objdump
SZ = $(TRGT)size
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
SREC = $(CP) -O srec
# ARM-specific options here
AOPT =
# THUMB-specific options here
TOPT = -mthumb -DTHUMB
# Define C warning options here
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Wno-unused-parameter
# Define C++ warning options here
CPPWARN = -Wall -Wextra -Wundef
#
# Compiler settings
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS =
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user defines
##############################################################################
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/
include $(RULESPATH)/rules.mk
OHEX = $(BUILDDIR)/$(PROJECT).hex
OELF = $(BUILDDIR)/$(PROJECT).elf
OBIN = $(BUILDDIR)/$(PROJECT).bin
include $(CHIBIOS_CONTRIB)/os/various/jlink.mk
include $(CHIBIOS_CONTRIB)/os/various/gdb.mk
pin-reset: jlink-pin-reset
flash: all jlink-flash
debug: gdb-debug
erase-all: jlink-erase-all
debug-server: jlink-debug-server

529
demos/NRF52/Classic/chconf.h Normal file
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/*
Copyright (C) 2016 Stephane D'Alu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
#define _CHIBIOS_RT_CONF_
/*===========================================================================*/
/**
* @name System timers settings
* @{
*/
/*===========================================================================*/
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
*/
#define CH_CFG_ST_RESOLUTION 32
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#define CH_CFG_ST_FREQUENCY 1000
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#define CH_CFG_ST_TIMEDELTA 0
/** @} */
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
* @note The round robin preemption is not supported in tickless mode and
* must be set to zero in that case.
*/
#define CH_CFG_TIME_QUANTUM 0
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#define CH_CFG_MEMCORE_SIZE 0
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread. The application @p main()
* function becomes the idle thread and must implement an
* infinite loop.
*/
#define CH_CFG_NO_IDLE_THREAD FALSE
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#define CH_CFG_OPTIMIZE_SPEED TRUE
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Time Measurement APIs.
* @details If enabled then the time measurement APIs are included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_TM FALSE
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_REGISTRY TRUE
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_WAITEXIT TRUE
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_SEMAPHORES TRUE
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_MUTEXES TRUE
/**
* @brief Enables recursive behavior on mutexes.
* @note Recursive mutexes are heavier and have an increased
* memory footprint.
*
* @note The default is @p FALSE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
#define CH_CFG_USE_CONDVARS TRUE
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_CONDVARS.
*/
#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_EVENTS TRUE
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_EVENTS.
*/
#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_MESSAGES TRUE
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_MESSAGES.
*/
#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#define CH_CFG_USE_MAILBOXES TRUE
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_QUEUES TRUE
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_MEMCORE TRUE
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
* @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#define CH_CFG_USE_HEAP TRUE
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_MEMPOOLS TRUE
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
#define CH_CFG_USE_DYNAMIC TRUE
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_STATISTICS FALSE
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_SYSTEM_STATE_CHECK TRUE
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_ENABLE_CHECKS FALSE
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_ENABLE_ASSERTS FALSE
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p CH_DBG_TRACE_MASK_NONE.
*/
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_NONE
/**
* @brief Trace buffer entries.
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
* different from @p CH_DBG_TRACE_MASK_NONE.
*/
#define CH_DBG_TRACE_BUFFER_SIZE 128
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#define CH_DBG_ENABLE_STACK_CHECK FALSE
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_FILL_THREADS FALSE
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p FALSE.
* @note This debug option is not currently compatible with the
* tickless mode.
*/
#define CH_DBG_THREADS_PROFILING FALSE
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure.
*/
#define CH_CFG_THREAD_EXTRA_FIELDS \
/* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* Context switch code here.*/ \
}
/**
* @brief ISR enter hook.
*/
#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
/* IRQ prologue code here.*/ \
}
/**
* @brief ISR exit hook.
*/
#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
/* IRQ epilogue code here.*/ \
}
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() { \
/* Idle-enter code here.*/ \
}
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() { \
/* Idle-leave code here.*/ \
}
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#define CH_CFG_IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#define CH_CFG_SYSTEM_TICK_HOOK() { \
/* System tick event code here.*/ \
}
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \
}
/**
* @brief Trace hook.
* @details This hook is invoked each time a new record is written in the
* trace buffer.
*/
#define CH_CFG_TRACE_HOOK(tep) { \
/* Trace code here.*/ \
}
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

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/*
Copyright (C) 2016 Stephane D'Alu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT TRUE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the I2S subsystem.
*/
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
#define HAL_USE_I2S FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/**
* @brief Enables the WDG subsystem.
*/
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG TRUE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* Community drivers's includes */
/*===========================================================================*/
#include "halconf_community.h"
#endif /* _HALCONF_H_ */
/** @} */

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/*
ChibiOS - Copyright (C) 2016 Stéphane D'Alu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _HALCONF_COMMUNITY_H_
#define _HALCONF_COMMUNITY_H_
/**
* @brief Enables the community overlay.
*/
#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
#define HAL_USE_COMMUNITY TRUE
#endif
/**
* @brief Enables the community subsystem.
*/
#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__)
#define HAL_USE_RNG TRUE
#endif
#define HAL_USE_QEI TRUE
/*===========================================================================*/
/* QEI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables discard of overlow
*/
#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__)
#define QEI_USE_OVERFLOW_DISCARD TRUE
#endif
/**
* @brief Enables discard of overlow
*/
#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__)
#define QEI_USE_OVERFLOW_MINMAX TRUE
#endif
//#define HAL_USE_SOFTDEVICE TRUE
#define HAL_USE_CAPSENSE TRUE
#define CAPSENSE_USE_WAIT TRUE
#define CAPSENSE_USE_MUTUAL_EXCLUSION TRUE
#endif /* _HALCONF_COMMUNITY_H_ */

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#include <stdint.h>
#include <string.h>
#include "ch.h"
#include "hal.h"
#include "chprintf.h"
#include "shell.h"
#include "ch_test.h"
#define LED_EXT 14
bool watchdog_started = false;
void watchdog_callback(void) {
palTogglePad(IOPORT1, LED2);
palTogglePad(IOPORT1, LED3);
palTogglePad(IOPORT1, LED4);
}
WDGConfig WDG_config = {
.pause_on_sleep = 0,
.pause_on_halt = 0,
.timeout_ms = 5000,
.callback = watchdog_callback,
};
void gpt_callback(GPTDriver *gptp) {
palTogglePad(IOPORT1, LED2);
}
/*
* GPT configuration
* Frequency: 31250Hz (32us period)
* Resolution: 16 bits
*/
static const GPTConfig gpt_config = {
.frequency = 31250,
.callback = gpt_callback,
.resolution = 16,
};
/*
* Command Random
*/
#define RANDOM_BUFFER_SIZE 1024
static uint8_t random_buffer[RANDOM_BUFFER_SIZE];
static void cmd_random(BaseSequentialStream *chp, int argc, char *argv[]) {
uint16_t size = 16;
uint16_t i = 0;
uint8_t nl = 0;
if (argc > 0) {
size = atoi(argv[0]);
}
if (size > RANDOM_BUFFER_SIZE) {
chprintf(chp, "random: maximum size is %d.\r\n", RANDOM_BUFFER_SIZE);
return;
}
chprintf(chp, "Fetching %d random byte(s):\r\n", size);
rngStart(&RNGD1, NULL);
rngWrite(&RNGD1, random_buffer, size, TIME_INFINITE);
rngStop(&RNGD1);
for (i = 0 ; i < size ; i++) {
chprintf(chp, "%02x ", random_buffer[i]);
if ((nl = (((i+1) % 20)) == 0))
chprintf(chp, "\r\n");
}
if (!nl)
chprintf(chp, "\r\n");
}
static void cmd_watchdog(BaseSequentialStream *chp, int argc, char *argv[]) {
if ((argc != 2) || (strcmp(argv[0], "start"))) {
usage:
chprintf(chp, "Usage: watchdog start <timeout>\r\n"
" <timeout> = 0..%d seconds\r\n",
WDG_MAX_TIMEOUT_MS/1000);
return;
}
int timeout = atoi(argv[1]);
if ((timeout < 0) || (timeout > (WDG_MAX_TIMEOUT_MS/1000)))
goto usage;
if (watchdog_started) {
chprintf(chp, "Watchdog already started."
" Can't be modified once activated.\r\n");
return;
}
chprintf(chp,
"Watchdog started\r\n"
"You need to push BTN1 every %d second(s)\r\n", timeout);
WDG_config.timeout_ms = timeout * 1000;
wdgStart(&WDGD1, &WDG_config);
watchdog_started = true;
}
static void cmd_info(BaseSequentialStream *chp, int argc, char *argv[]) {
chprintf(chp, "Watchdog max = %d ms\r\n", WDG_MAX_TIMEOUT_MS);
}
static THD_WORKING_AREA(shell_wa, 1024);
static const ShellCommand commands[] = {
{"info", cmd_info },
{"random", cmd_random },
{"watchdog", cmd_watchdog },
{NULL, NULL}
};
static const ShellConfig shell_cfg1 = {
(BaseSequentialStream *)&SD1,
commands
};
static SerialConfig serial_config = {
.speed = 115200,
.tx_pad = UART_TX,
.rx_pad = UART_RX,
#if NRF5_SERIAL_USE_HWFLOWCTRL == TRUE
.rts_pad = UART_RTS,
.cts_pad = UART_CTS,
#endif
};
static THD_WORKING_AREA(waThread1, 64);
static THD_FUNCTION(Thread1, arg) {
(void)arg;
uint8_t led = LED4;
chRegSetThreadName("blinker");
while (1) {
palTogglePad(IOPORT1, led);
chThdSleepMilliseconds(100);
}
}
#define printf(fmt, ...) \
chprintf((BaseSequentialStream*)&SD1, fmt, ##__VA_ARGS__)
/**@brief Function for application main entry.
*/
int main(void)
{
halInit();
chSysInit();
shellInit();
sdStart(&SD1, &serial_config);
palSetPad(IOPORT1, LED1);
palClearPad(IOPORT1, LED2);
palClearPad(IOPORT1, LED3);
palSetPad(IOPORT1, LED4);
gptStart(&GPTD1, &gpt_config);
gptStartContinuous(&GPTD1, 31250);
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO+1,
Thread1, NULL);
chThdCreateStatic(shell_wa, sizeof(shell_wa), NORMALPRIO+1,
shellThread, (void *)&shell_cfg1);
printf(PORT_INFO "\r\n");
chThdSleep(2);
printf("Priority levels %d\r\n", CORTEX_PRIORITY_LEVELS);
//test_execute((BaseSequentialStream *)&SD1);
NRF_P0->DETECTMODE = 0;
while (true) {
if (watchdog_started &&
(palReadPad(IOPORT1, BTN1) == 0)) {
palTogglePad(IOPORT1, LED1);
wdgReset(&WDGD1);
printf("Watchdog reseted\r\n");
}
chThdSleepMilliseconds(250);
}
}

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/*
Copyright (C) 2016 Stephane D'Alu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _MCUCONF_H_
#define _MCUCONF_H_
/*
* Board setting
*/
#define NRF5_SOFTDEVICE_THREAD_WA_SIZE 128
#define SHELL_CMD_TEST_ENABLED FALSE
#define SHELL_CMD_ECHO_ENABLED FALSE
#define SHELL_CMD_INFO_ENABLED FALSE
#define NRF5_SOFTDEVICE_LFCLK_SOURCE NRF_CLOCK_LF_SRC_XTAL
#define NRF5_SOFTDEVICE_LFCLK_ACCURACY NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM
/*
* HAL driver system settings.
*/
#define NRF5_SERIAL_USE_UART0 TRUE
#define NRF5_SERIAL_USE_HWFLOWCTRL TRUE
#define NRF5_RNG_USE_RNG0 TRUE
#define NRF5_GPT_USE_TIMER0 TRUE
#define NRF5_QEI_USE_QDEC0 TRUE
#define NRF5_QEI_USE_LED FALSE
#define WDG_USE_TIMEOUT_CALLBACK TRUE
#endif /* _MCUCONF_H_ */

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/*
Copyright (C) 2016 Stephane D'Alu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* NRF52832 memory setup.
*/
MEMORY
{
flash0 : org = 0x00000000, len = 512k
flash1 : org = 0x00000000, len = 0
flash2 : org = 0x00000000, len = 0
flash3 : org = 0x00000000, len = 0
flash4 : org = 0x00000000, len = 0
flash5 : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 64k
ram1 : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for HEAP segment.*/
REGION_ALIAS("HEAP_RAM", ram0);
INCLUDE rules.ld

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os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk Normal file
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# List of the ChibiOS generic NRF51 startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/NRF52832 \
$(CHIBIOS)/os/common/ext/CMSIS/include
STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld

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/*
Copyright (C) 2016 Stephane D'Alu
This file is part of ChibiOS.
ChibiOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file NRF51822/cmparams.h
* @brief ARM Cortex-M4 parameters for the Nordic Semi NRF52832 family.
*
* @defgroup ARMCMx_NRF52x Nordic semiconductor NRF52x.
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M4 specific parameters for the
* NRF52x platform.
* @{
*/
#ifndef _CMPARAMS_H_
#define _CMPARAMS_H_
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL 4
/**
* @brief Memory Protection unit presence.
*/
#define CORTEX_HAS_MPU 1
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU 1
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 3
/**
* @brief Number of interrupt vectors.
* @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
#define CORTEX_NUM_VECTORS 40
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
/* Including the device CMSIS header. Note, we are not using the definitions
from this header because we need this file to be usable also from
assembler source files. We verify that the info matches instead.*/
#include "nrf52.h"
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif
#endif /* !defined(_FROM_ASM_) */
#endif /* _CMPARAMS_H_ */
/** @} */

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/*
Copyright (C) 2016 Stéphane D'Alu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config =
{
.pads = {
PAL_MODE_UNCONNECTED, /* P0.0 : XTAL (32MHz) */
PAL_MODE_UNCONNECTED, /* P0.1 : XTAL (32MHz) */
PAL_MODE_UNCONNECTED, /* P0.2 */
PAL_MODE_UNCONNECTED, /* P0.3 */
PAL_MODE_UNCONNECTED, /* P0.4 */
PAL_MODE_OUTPUT_PUSHPULL, /* P0.5 : UART_RTS */
PAL_MODE_OUTPUT_PUSHPULL, /* P0.6 : UART_TX */
PAL_MODE_INPUT_PULLUP, /* P0.7 : UART_CTS */
PAL_MODE_INPUT_PULLUP, /* P0.8 : UART_RX */
PAL_MODE_UNCONNECTED, /* P0.9 */
PAL_MODE_UNCONNECTED, /* P0.10 */
PAL_MODE_UNCONNECTED, /* P0.11 */
PAL_MODE_UNCONNECTED, /* P0.12 */
PAL_MODE_INPUT_PULLUP, /* P0.13: BTN1 */
PAL_MODE_INPUT_PULLUP, /* P0.14: BTN2 */
PAL_MODE_INPUT_PULLUP, /* P0.15: BTN3 */
PAL_MODE_INPUT_PULLUP, /* P0.16: BTN4 */
PAL_MODE_OUTPUT_PUSHPULL, /* P0.17: LED1 */
PAL_MODE_OUTPUT_PUSHPULL, /* P0.18: LED2 */
PAL_MODE_OUTPUT_PUSHPULL, /* P0.19: LED3 */
PAL_MODE_OUTPUT_PUSHPULL, /* P0.20: LED4 */
PAL_MODE_UNCONNECTED, /* P0.21 */
PAL_MODE_OUTPUT_PUSHPULL, /* P0.22: SPI_SS */
PAL_MODE_INPUT_PULLUP, /* P0.23: SPI_MISO */
PAL_MODE_OUTPUT_PUSHPULL, /* P0.24: SPI_MOSI */
PAL_MODE_OUTPUT_PUSHPULL, /* P0.25: SPI_SCK */
PAL_MODE_OUTPUT_OPENDRAIN, /* P0.26: SDA */
PAL_MODE_OUTPUT_OPENDRAIN, /* P0.27: SCL */
PAL_MODE_UNCONNECTED, /* P0.28 */
PAL_MODE_UNCONNECTED, /* P0.29 */
PAL_MODE_UNCONNECTED, /* P0.30 */
PAL_MODE_UNCONNECTED, /* P0.31 */
},
};
#endif
/**
* @brief Early initialization code.
* @details This initialization is performed just after reset before BSS and
* DATA segments initialization.
*/
void __early_init(void)
{
}
/**
* @brief Late initialization code.
* @note This initialization is performed after BSS and DATA segments
* initialization and before invoking the main() function.
*/
void boardInit(void)
{
}

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/*
Copyright (C) 2016 Stephane D'Alu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/* Board identifier. */
#define BOARD_NRF52_DK
#define BOARD_NAME "nRF52 DK"
/* Board oscillators-related settings. */
#define NRF5_XTAL_VALUE 32000000
#define NRF5_LFCLK_SOURCE 1
/*
* GPIO pins.
*/
/* Defined by board */
#define BTN1 13U
#define BTN2 14U
#define BTN3 15U
#define BTN4 16U
#define LED1 17U
#define LED2 18U
#define LED3 19U
#define LED4 20U
#define UART_RTS 5U
#define UART_TX 6U
#define UART_CTS 7U
#define UART_RX 8U
#define NFC1 9U
#define NFC2 10U
#define I2C_SCL 27U
#define I2C_SDA 26U
/* Our definitions */
#define SPI_SCK 25U
#define SPI_MOSI 24U
#define SPI_MISO 23U
#define SPI_SS 22U
/* Analog input */
#define AIN0 2U
#define AIN1 3U
#define AIN2 4U
#define AIN3 5U
#define AIN4 28U
#define AIN5 29U
#define AIN6 30U
#define AIN7 31U
#define AREF0 AIN0
#define AREF1 AIN1
/*
* IO pins assignments.
*/
/* Defined by board */
#define IOPORT1_BTN1 13U
#define IOPORT1_BTN2 14U
#define IOPORT1_BTN3 15U
#define IOPORT1_BTN4 16U
#define IOPORT1_LED1 17U
#define IOPORT1_LED2 18U
#define IOPORT1_LED3 19U
#define IOPORT1_LED4 20U
#define IOPORT1_UART_RTS 5U
#define IOPORT1_UART_TX 6U
#define IOPORT1_UART_CTS 7U
#define IOPORT1_UART_RX 8U
#define IOPORT1_NFC1 9U
#define IOPORT1_NFC2 10U
#define IOPORT1_I2C_SCL 27U
#define IOPORT1_I2C_SDA 26U
#define IOPORT1_RESET 21U
/* Our definitions */
#define IOPORT1_SPI_SCK 25U
#define IOPORT1_SPI_MOSI 24U
#define IOPORT1_SPI_MISO 23U
#define IOPORT1_SPI_SS 22U
/* Analog inpupt */
#define IOPORT1_AIN0 2U
#define IOPORT1_AIN1 3U
#define IOPORT1_AIN2 4U
#define IOPORT1_AIN3 5U
#define IOPORT1_AIN4 28U
#define IOPORT1_AIN5 29U
#define IOPORT1_AIN6 30U
#define IOPORT1_AIN7 31U
#define IOPORT1_AREF0 IOPORT1_AIN0
#define IOPORT1_AREF1 IOPORT1_AIN1
/* Arduino naming */
#define IOPORT1_A0 3U
#define IOPORT1_A1 4U
#define IOPORT1_A2 28U
#define IOPORT1_A3 39U
#define IOPORT1_A4 30U
#define IOPORT1_A5 31U
#define IOPORT1_D0 11U
#define IOPORT1_D1 12U
#define IOPORT1_D2 13U
#define IOPORT1_D3 14U
#define IOPORT1_D4 15U
#define IOPORT1_D5 16U
#define IOPORT1_D6 17U
#define IOPORT1_D7 18U
#define IOPORT1_D8 19U
#define IOPORT1_D9 20U
#define IOPORT1_D10 22U
#define IOPORT1_D11 23U
#define IOPORT1_D12 24U
#define IOPORT1_D13 25U
/*
* IO lines assignments.
*/
/* Board defined */
#define LINE_BTN1 PAL_LINE(IOPORT1, IOPORT1_BTN1)
#define LINE_BTN2 PAL_LINE(IOPORT1, IOPORT1_BTN2)
#define LINE_BTN3 PAL_LINE(IOPORT1, IOPORT1_BTN3)
#define LINE_BTN4 PAL_LINE(IOPORT1, IOPORT1_BTN4)
#define LINE_LED1 PAL_LINE(IOPORT1, IOPORT1_LED1)
#define LINE_LED2 PAL_LINE(IOPORT1, IOPORT1_LED2)
#define LINE_LED3 PAL_LINE(IOPORT1, IOPORT1_LED3)
#define LINE_LED4 PAL_LINE(IOPORT1, IOPORT1_LED4)
#define LINE_UART_RTS PAL_LINE(IOPORT1, IOPORT1_UART_RTS)
#define LINE_UART_TX PAL_LINE(IOPORT1, IOPORT1_UART_TX)
#define LINE_UART_CTS PAL_LINE(IOPORT1, IOPORT1_UART_CTS)
#define LINE_UART_RX PAL_LINE(IOPORT1, IOPORT1_UART_RX)
#define LINE_NFC1 PAL_LINE(IOPORT1, IOPORT1_NFC1)
#define LINE_NFC2 PAL_LINE(IOPORT1, IOPORT1_NFC2)
#define LINE_I2C_SCL PAL_LINE(IOPORT1, IOPORT1_I2C_SCL)
#define LINE_I2C_SDA PAL_LINE(IOPORT1, IOPORT1_I2C_SDA)
/* Our definitions */
#define LINE_SPI_SCK PAL_LINE(IOPORT1, IOPORT1_SPI_SCK)
#define LINE_SPI_MOSI PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI)
#define LINE_SPI_MISO PAL_LINE(IOPORT1, IOPORT1_SPI_MISO)
#define LINE_SPI_SS PAL_LINE(IOPORT1, IOPORT1_SPI_SS)
/* Analog line */
#define LINE_AIN0 PAL_LINE(IOPORT1, IOPORT1_AIN0)
#define LINE_AIN1 PAL_LINE(IOPORT1, IOPORT1_AIN1)
#define LINE_AIN2 PAL_LINE(IOPORT1, IOPORT1_AIN2)
#define LINE_AIN3 PAL_LINE(IOPORT1, IOPORT1_AIN3)
#define LINE_AIN4 PAL_LINE(IOPORT1, IOPORT1_AIN4)
#define LINE_AIN5 PAL_LINE(IOPORT1, IOPORT1_AIN5)
#define LINE_AIN6 PAL_LINE(IOPORT1, IOPORT1_AIN6)
#define LINE_AIN7 PAL_LINE(IOPORT1, IOPORT1_AIN7)
#define LINE_AREF0 PAL_LINE(IOPORT1, IOPORT1_AREF0)
#define LINE_AREF1 PAL_LINE(IOPORT1, IOPORT1_AREF1)
/* Arduino naming */
#define LINE_A0 PAL_LINE(IOPORT1, IOPORT1_A0)
#define LINE_A1 PAL_LINE(IOPORT1, IOPORT1_A1)
#define LINE_A2 PAL_LINE(IOPORT1, IOPORT1_A2)
#define LINE_A3 PAL_LINE(IOPORT1, IOPORT1_A3)
#define LINE_A4 PAL_LINE(IOPORT1, IOPORT1_A4)
#define LINE_A5 PAL_LINE(IOPORT1, IOPORT1_A5)
#define LINE_D0 PAL_LINE(IOPORT1, IOPORT1_D0)
#define LINE_D1 PAL_LINE(IOPORT1, IOPORT1_D1)
#define LINE_D2 PAL_LINE(IOPORT1, IOPORT1_D2)
#define LINE_D3 PAL_LINE(IOPORT1, IOPORT1_D3)
#define LINE_D4 PAL_LINE(IOPORT1, IOPORT1_D4)
#define LINE_D5 PAL_LINE(IOPORT1, IOPORT1_D5)
#define LINE_D6 PAL_LINE(IOPORT1, IOPORT1_D6)
#define LINE_D7 PAL_LINE(IOPORT1, IOPORT1_D7)
#define LINE_D8 PAL_LINE(IOPORT1, IOPORT1_D8)
#define LINE_D9 PAL_LINE(IOPORT1, IOPORT1_D9)
#define LINE_D10 PAL_LINE(IOPORT1, IOPORT1_D10)
#define LINE_D11 PAL_LINE(IOPORT1, IOPORT1_D11)
#define LINE_D12 PAL_LINE(IOPORT1, IOPORT1_D12)
#define LINE_D13 PAL_LINE(IOPORT1, IOPORT1_D13)
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

12
os/hal/boards/NRF52-DK/board.mk Normal file
View File

@ -0,0 +1,12 @@
# List of all the board related files.
BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-DK/board.c
# Required include directories
BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-DK
# Flash
JLINK_DEVICE = nrf52
JLINK_PRE_FLASH = w4 4001e504 1
#JLINK_ERASE_ALL = w4 4001e504 2\nw4 4001e50c 1\nsleep 100
JLINK_PIN_RESET = w4 40000544 1

79
os/hal/ports/NRF5/NRF51822/hal_gpt_lld.c → os/hal/ports/NRF5/LLD/hal_gpt_lld.c
View File

@ -15,8 +15,8 @@
*/
/**
* @file NRF51x22/gpt_lld.c
* @brief NRF51x22 GPT subsystem low level driver source.
* @file NRF5/LLD/hal_gpt_lld.c
* @brief NRF5 GPT subsystem low level driver source.
*
* @addtogroup GPT
* @{
@ -30,8 +30,8 @@
/* Driver local definitions. */
/*===========================================================================*/
#define NRF51_TIMER_PRESCALER_NUM 10
#define NRF51_TIMER_COMPARE_NUM 4
#define NRF5_TIMER_PRESCALER_NUM 10
#define NRF5_TIMER_COMPARE_NUM 4
/*===========================================================================*/
/* Driver exported variables. */
@ -41,7 +41,7 @@
* @brief GPTD1 driver identifier.
* @note The driver GPTD1 allocates the complex timer TIM1 when enabled.
*/
#if NRF51_GPT_USE_TIMER0 || defined(__DOXYGEN__)
#if NRF5_GPT_USE_TIMER0 || defined(__DOXYGEN__)
GPTDriver GPTD1;
#endif
@ -49,7 +49,7 @@ GPTDriver GPTD1;
* @brief GPTD2 driver identifier.
* @note The driver GPTD2 allocates the timer TIM2 when enabled.
*/
#if NRF51_GPT_USE_TIMER1 || defined(__DOXYGEN__)
#if NRF5_GPT_USE_TIMER1 || defined(__DOXYGEN__)
GPTDriver GPTD2;
#endif
@ -57,7 +57,7 @@ GPTDriver GPTD2;
* @brief GPTD3 driver identifier.
* @note The driver GPTD3 allocates the timer TIM3 when enabled.
*/
#if NRF51_GPT_USE_TIMER2 || defined(__DOXYGEN__)
#if NRF5_GPT_USE_TIMER2 || defined(__DOXYGEN__)
GPTDriver GPTD3;
#endif
@ -73,19 +73,19 @@ static uint8_t prescaler(uint16_t freq)
{
uint8_t i;
static const gptfreq_t frequencies[] = {
NRF51_GPT_FREQ_16MHZ,
NRF51_GPT_FREQ_8MHZ,
NRF51_GPT_FREQ_4MHZ,
NRF51_GPT_FREQ_2MHZ,
NRF51_GPT_FREQ_1MHZ,
NRF51_GPT_FREQ_500KHZ,
NRF51_GPT_FREQ_250KHZ,
NRF51_GPT_FREQ_125KHZ,
NRF51_GPT_FREQ_62500HZ,
NRF51_GPT_FREQ_31250HZ,
NRF5_GPT_FREQ_16MHZ,
NRF5_GPT_FREQ_8MHZ,
NRF5_GPT_FREQ_4MHZ,
NRF5_GPT_FREQ_2MHZ,
NRF5_GPT_FREQ_1MHZ,
NRF5_GPT_FREQ_500KHZ,
NRF5_GPT_FREQ_250KHZ,
NRF5_GPT_FREQ_125KHZ,
NRF5_GPT_FREQ_62500HZ,
NRF5_GPT_FREQ_31250HZ,
};
for (i = 0; i < NRF51_TIMER_PRESCALER_NUM; i++)
for (i = 0; i < NRF5_TIMER_PRESCALER_NUM; i++)
if (freq == frequencies[i])
return i;
@ -102,6 +102,9 @@ static uint8_t prescaler(uint16_t freq)
static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
gptp->tim->EVENTS_COMPARE[gptp->cc_int] = 0;
#if CORTEX_MODEL >= 4
(void)gptp->tim->EVENTS_COMPARE[gptp->cc_int];
#endif
if (gptp->state == GPT_ONESHOT)
gptp->state = GPT_READY; /* Back in GPT_READY state. */
gptp->config->callback(gptp);
@ -111,7 +114,7 @@ static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_GPT_USE_TIMER0
#if NRF5_GPT_USE_TIMER0
/**
* @brief TIMER0 interrupt handler.
*
@ -125,9 +128,9 @@ OSAL_IRQ_HANDLER(Vector60) {
OSAL_IRQ_EPILOGUE();
}
#endif /* NRF51_GPT_USE_TIMER0 */
#endif /* NRF5_GPT_USE_TIMER0 */
#if NRF51_GPT_USE_TIMER1
#if NRF5_GPT_USE_TIMER1
/**
* @brief TIMER1 interrupt handler.
*
@ -141,9 +144,9 @@ OSAL_IRQ_HANDLER(Vector64) {
OSAL_IRQ_EPILOGUE();
}
#endif /* NRF51_GPT_USE_TIMER1 */
#endif /* NRF5_GPT_USE_TIMER1 */
#if NRF51_GPT_USE_TIMER2
#if NRF5_GPT_USE_TIMER2
/**
* @brief TIMER2 interrupt handler.
*
@ -157,7 +160,7 @@ OSAL_IRQ_HANDLER(Vector68) {
OSAL_IRQ_EPILOGUE();
}
#endif /* NRF51_GPT_USE_TIMER2 */
#endif /* NRF5_GPT_USE_TIMER2 */
/*===========================================================================*/
/* Driver exported functions. */
@ -170,19 +173,19 @@ OSAL_IRQ_HANDLER(Vector68) {
*/
void gpt_lld_init(void) {
#if NRF51_GPT_USE_TIMER0
#if NRF5_GPT_USE_TIMER0
/* Driver initialization.*/
GPTD1.tim = NRF_TIMER0;
gptObjectInit(&GPTD1);
#endif
#if NRF51_GPT_USE_TIMER1
#if NRF5_GPT_USE_TIMER1
/* Driver initialization.*/
GPTD2.tim = NRF_TIMER1;
gptObjectInit(&GPTD2);
#endif
#if NRF51_GPT_USE_TIMER2
#if NRF5_GPT_USE_TIMER2
/* Driver initialization.*/
GPTD3.tim = NRF_TIMER2;
gptObjectInit(&GPTD3);
@ -201,21 +204,21 @@ void gpt_lld_start(GPTDriver *gptp) {
NRF_TIMER_Type *tim = gptp->tim;
if (gptp->state == GPT_STOP) {
osalDbgAssert(gptp->cc_int < NRF51_TIMER_COMPARE_NUM,
osalDbgAssert(gptp->cc_int < NRF5_TIMER_COMPARE_NUM,
"invalid capture/compare index");
tim->INTENSET = TIMER_INTENSET_COMPARE0_Msk << gptp->cc_int;
#if NRF51_GPT_USE_TIMER0
#if NRF5_GPT_USE_TIMER0
if (&GPTD1 == gptp)
nvicEnableVector(TIMER0_IRQn, NRF51_GPT_TIMER0_IRQ_PRIORITY);
nvicEnableVector(TIMER0_IRQn, NRF5_GPT_TIMER0_IRQ_PRIORITY);
#endif
#if NRF51_GPT_USE_TIMER1
#if NRF5_GPT_USE_TIMER1
if (&GPTD2 == gptp)
nvicEnableVector(TIMER1_IRQn, NRF51_GPT_TIMER1_IRQ_PRIORITY);
nvicEnableVector(TIMER1_IRQn, NRF5_GPT_TIMER1_IRQ_PRIORITY);
#endif
#if NRF51_GPT_USE_TIMER2
#if NRF5_GPT_USE_TIMER2
if (&GPTD3 == gptp)
nvicEnableVector(TIMER2_IRQn, NRF51_GPT_TIMER2_IRQ_PRIORITY);
nvicEnableVector(TIMER2_IRQn, NRF5_GPT_TIMER2_IRQ_PRIORITY);
#endif
}
@ -235,7 +238,7 @@ void gpt_lld_start(GPTDriver *gptp) {
tim->BITMODE = TIMER_BITMODE_BITMODE_16Bit << TIMER_BITMODE_BITMODE_Pos;
break;
#if NRF51_GPT_USE_TIMER0
#if NRF5_GPT_USE_TIMER0
case 24:
tim->BITMODE = TIMER_BITMODE_BITMODE_24Bit << TIMER_BITMODE_BITMODE_Pos;
break;
@ -263,15 +266,15 @@ void gpt_lld_stop(GPTDriver *gptp) {
if (gptp->state == GPT_READY) {
gptp->tim->TASKS_SHUTDOWN = 1;
#if NRF51_GPT_USE_TIMER0
#if NRF5_GPT_USE_TIMER0
if (&GPTD1 == gptp)
nvicDisableVector(TIMER0_IRQn);
#endif
#if NRF51_GPT_USE_TIMER1
#if NRF5_GPT_USE_TIMER1
if (&GPTD2 == gptp)
nvicDisableVector(TIMER1_IRQn);
#endif
#if NRF51_GPT_USE_TIMER2
#if NRF5_GPT_USE_TIMER2
if (&GPTD3 == gptp)
nvicDisableVector(TIMER2_IRQn);
#endif

70
os/hal/ports/NRF5/NRF51822/hal_gpt_lld.h → os/hal/ports/NRF5/LLD/hal_gpt_lld.h
View File

@ -15,8 +15,8 @@
*/
/**
* @file NRF51x22/gpt_lld.h
* @brief NRF51x22 GPT subsystem low level driver header.
* @file NRF5/LLD/gpt_lld.h
* @brief NRF5 GPT subsystem low level driver header.
*
* @addtogroup GPT
* @{
@ -44,8 +44,8 @@
* @details If set to @p TRUE the support for GPTD1 is included.
* @note The default is @p TRUE.
*/
#if !defined(NRF51_GPT_USE_TIMER0) || defined(__DOXYGEN__)
#define NRF51_GPT_USE_TIMER0 FALSE
#if !defined(NRF5_GPT_USE_TIMER0) || defined(__DOXYGEN__)
#define NRF5_GPT_USE_TIMER0 FALSE
#endif
/**
@ -53,8 +53,8 @@
* @details If set to @p TRUE the support for GPTD2 is included.
* @note The default is @p TRUE.
*/
#if !defined(NRF51_GPT_USE_TIMER1) || defined(__DOXYGEN__)
#define NRF51_GPT_USE_TIMER1 FALSE
#if !defined(NRF5_GPT_USE_TIMER1) || defined(__DOXYGEN__)
#define NRF5_GPT_USE_TIMER1 FALSE
#endif
/**
@ -62,29 +62,29 @@
* @details If set to @p TRUE the support for GPTD3 is included.
* @note The default is @p TRUE.
*/
#if !defined(NRF51_GPT_USE_TIMER2) || defined(__DOXYGEN__)
#define NRF51_GPT_USE_TIMER2 FALSE
#if !defined(NRF5_GPT_USE_TIMER2) || defined(__DOXYGEN__)
#define NRF5_GPT_USE_TIMER2 FALSE
#endif
/**
* @brief GPTD1 interrupt priority level setting.
*/
#if !defined(NRF51_GPT_TIMER0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_GPT_TIMER0_IRQ_PRIORITY 3
#if !defined(NRF5_GPT_TIMER0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_GPT_TIMER0_IRQ_PRIORITY 3
#endif
/**
* @brief GPTD2 interrupt priority level setting.
*/
#if !defined(NRF51_GPT_TIMER1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_GPT_TIMER1_IRQ_PRIORITY 3
#if !defined(NRF5_GPT_TIMER1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_GPT_TIMER1_IRQ_PRIORITY 3
#endif
/**
* @brief GPTD3 interrupt priority level setting.
*/
#if !defined(NRF51_GPT_TIMER2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_GPT_TIMER2_IRQ_PRIORITY 3
#if !defined(NRF5_GPT_TIMER2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_GPT_TIMER2_IRQ_PRIORITY 3
#endif
/** @} */
@ -92,23 +92,23 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !NRF51_GPT_USE_TIMER0 && !NRF51_GPT_USE_TIMER1 && \
!NRF51_GPT_USE_TIMER2
#if !NRF5_GPT_USE_TIMER0 && !NRF5_GPT_USE_TIMER1 && \
!NRF5_GPT_USE_TIMER2
#error "GPT driver activated but no TIMER peripheral assigned"
#endif
#if NRF51_GPT_USE_TIMER0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER0_IRQ_PRIORITY)
#if NRF5_GPT_USE_TIMER0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_GPT_TIMER0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER0"
#endif
#if NRF51_GPT_USE_TIMER1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER1_IRQ_PRIORITY)
#if NRF5_GPT_USE_TIMER1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_GPT_TIMER1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER1"
#endif
#if NRF51_GPT_USE_TIMER2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_GPT_TIMER2_IRQ_PRIORITY)
#if NRF5_GPT_USE_TIMER2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_GPT_TIMER2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER2"
#endif
@ -120,16 +120,16 @@
* @brief GPT frequency type.
*/
typedef enum {
NRF51_GPT_FREQ_31250HZ = 31250,
NRF51_GPT_FREQ_62500HZ = 62500,
NRF51_GPT_FREQ_125KHZ = 125000,
NRF51_GPT_FREQ_250KHZ = 250000,
NRF51_GPT_FREQ_500KHZ = 500000,
NRF51_GPT_FREQ_1MHZ = 1000000,
NRF51_GPT_FREQ_2MHZ = 2000000,
NRF51_GPT_FREQ_4MHZ = 4000000,
NRF51_GPT_FREQ_8MHZ = 8000000,
NRF51_GPT_FREQ_16MHZ = 16000000,
NRF5_GPT_FREQ_31250HZ = 31250,
NRF5_GPT_FREQ_62500HZ = 62500,
NRF5_GPT_FREQ_125KHZ = 125000,
NRF5_GPT_FREQ_250KHZ = 250000,
NRF5_GPT_FREQ_500KHZ = 500000,
NRF5_GPT_FREQ_1MHZ = 1000000,
NRF5_GPT_FREQ_2MHZ = 2000000,
NRF5_GPT_FREQ_4MHZ = 4000000,
NRF5_GPT_FREQ_8MHZ = 8000000,
NRF5_GPT_FREQ_16MHZ = 16000000,
} gptfreq_t;
/**
@ -231,15 +231,15 @@ struct GPTDriver {
/* External declarations. */
/*===========================================================================*/
#if NRF51_GPT_USE_TIMER0 && !defined(__DOXYGEN__)
#if NRF5_GPT_USE_TIMER0 && !defined(__DOXYGEN__)
extern GPTDriver GPTD1;
#endif
#if NRF51_GPT_USE_TIMER1 && !defined(__DOXYGEN__)
#if NRF5_GPT_USE_TIMER1 && !defined(__DOXYGEN__)
extern GPTDriver GPTD2;
#endif
#if NRF51_GPT_USE_TIMER2 && !defined(__DOXYGEN__)
#if NRF5_GPT_USE_TIMER2 && !defined(__DOXYGEN__)
extern GPTDriver GPTD3;
#endif

77
os/hal/ports/NRF5/NRF51822/hal_i2c_lld.c → os/hal/ports/NRF5/LLD/hal_i2c_lld.c
View File

@ -15,8 +15,8 @@
*/
/**
* @file NRF51822/i2c_lld.c
* @brief NRF51822 I2C subsystem low level driver source.
* @file NRF5/LLD/hal_i2c_lld.c
* @brief NRF5 I2C subsystem low level driver source.
*
* @addtogroup I2C
* @{
@ -24,7 +24,7 @@
#include "osal.h"
#include "hal.h"
#include "nrf51_delay.h"
#include "nrf_delay.h"
#if HAL_USE_I2C || defined(__DOXYGEN__)
@ -33,10 +33,10 @@
/*===========================================================================*/
/* These macros are needed to see if the slave is stuck and we as master send dummy clock cycles to end its wait */
#define I2C_HIGH(p) do { NRF_GPIO->OUTSET = (1UL << (p)); } while(0) /*!< Pulls I2C line high */
#define I2C_LOW(p) do { NRF_GPIO->OUTCLR = (1UL << (p)); } while(0) /*!< Pulls I2C line low */
#define I2C_INPUT(p) do { NRF_GPIO->DIRCLR = (1UL << (p)); } while(0) /*!< Configures I2C pin as input */
#define I2C_OUTPUT(p) do { NRF_GPIO->DIRSET = (1UL << (p)); } while(0) /*!< Configures I2C pin as output */
#define I2C_HIGH(p) do { IOPORT1->OUTSET = (1UL << (p)); } while(0) /*!< Pulls I2C line high */
#define I2C_LOW(p) do { IOPORT1->OUTCLR = (1UL << (p)); } while(0) /*!< Pulls I2C line low */
#define I2C_INPUT(p) do { IOPORT1->DIRCLR = (1UL << (p)); } while(0) /*!< Configures I2C pin as input */
#define I2C_OUTPUT(p) do { IOPORT1->DIRSET = (1UL << (p)); } while(0) /*!< Configures I2C pin as output */
#define I2C_PIN_CNF \
((GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
@ -52,12 +52,12 @@
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos))
#if NRF51_I2C_USE_I2C0
#if NRF5_I2C_USE_I2C0
#define I2C_IRQ_NUM SPI0_TWI0_IRQn
#define I2C_IRQ_PRI NRF51_I2C_I2C0_IRQ_PRIORITY
#elif NRF51_I2C_USE_I2C1
#define I2C_IRQ_PRI NRF5_I2C_I2C0_IRQ_PRIORITY
#elif NRF5_I2C_USE_I2C1
#define I2C_IRQ_NUM SPI1_TWI1_IRQn
#define I2C_IRQ_PRI NRF51_I2C_I2C1_IRQ_PRIORITY
#define I2C_IRQ_PRI NRF5_I2C_I2C1_IRQ_PRIORITY
#endif
/*===========================================================================*/
@ -67,14 +67,14 @@
/**
* @brief I2C0 driver identifier.
*/
#if NRF51_I2C_USE_I2C0 || defined(__DOXYGEN__)
#if NRF5_I2C_USE_I2C0 || defined(__DOXYGEN__)
I2CDriver I2CD1;
#endif
/**
* @brief I2C1 driver identifier.
*/
#if NRF51_I2C_USE_I2C1 || defined(__DOXYGEN__)
#if NRF5_I2C_USE_I2C1 || defined(__DOXYGEN__)
I2CDriver I2CD2;
#endif
@ -102,14 +102,14 @@ static void i2c_clear_bus(I2CDriver *i2cp)
const I2CConfig *cfg = i2cp->config;
int i;
NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;
NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;
IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;
IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;
I2C_HIGH(cfg->sda_pad);
I2C_HIGH(cfg->scl_pad);
NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;
NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;
IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;
IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;
nrf_delay_us(4);
@ -165,7 +165,10 @@ static void serve_interrupt(I2CDriver *i2cp) {
if(i2c->EVENTS_TXDSENT) {
i2c->EVENTS_TXDSENT = 0;
#if CORTEX_MODEL >= 4
(void)i2c->EVENTS_TXDSENT;
#endif
if(--i2cp->txbytes) {
i2c->TXD = *i2cp->txptr++;
@ -182,6 +185,10 @@ static void serve_interrupt(I2CDriver *i2cp) {
if(i2c->EVENTS_RXDREADY) {
i2c->EVENTS_RXDREADY = 0;
#if CORTEX_MODEL >= 4
(void)i2c->EVENTS_RXDREADY;
#endif
*i2cp->rxptr++ = i2c->RXD;
if(--i2cp->rxbytes) {
@ -194,7 +201,9 @@ static void serve_interrupt(I2CDriver *i2cp) {
uint32_t err = i2c->ERRORSRC;
i2c->EVENTS_ERROR = 0;
#if CORTEX_MODEL >= 4
(void)i2c->EVENTS_ERROR;
#endif
if (err & TWI_ERRORSRC_OVERRUN_Msk)
i2cp->errors |= I2C_OVERRUN;
if (err & (TWI_ERRORSRC_ANACK_Msk | TWI_ERRORSRC_DNACK_Msk))
@ -206,6 +215,9 @@ static void serve_interrupt(I2CDriver *i2cp) {
stop_count++;
i2c->EVENTS_STOPPED = 0;
#if CORTEX_MODEL >= 4
(void)i2c->EVENTS_STOPPED;
#endif
_i2c_wakeup_isr(i2cp);
}
}
@ -214,7 +226,7 @@ static void serve_interrupt(I2CDriver *i2cp) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_I2C_USE_I2C0 || defined(__DOXYGEN__)
#if NRF5_I2C_USE_I2C0 || defined(__DOXYGEN__)
OSAL_IRQ_HANDLER(Vector4C) {
@ -225,7 +237,7 @@ OSAL_IRQ_HANDLER(Vector4C) {
#endif
#if NRF51_I2C_USE_I2C1 || defined(__DOXYGEN__)
#if NRF5_I2C_USE_I2C1 || defined(__DOXYGEN__)
OSAL_IRQ_HANDLER(Vector50) {
@ -247,13 +259,13 @@ OSAL_IRQ_HANDLER(Vector50) {
*/
void i2c_lld_init(void) {
#if NRF51_I2C_USE_I2C0
#if NRF5_I2C_USE_I2C0
i2cObjectInit(&I2CD1);
I2CD1.thread = NULL;
I2CD1.i2c = NRF_TWI0;
#endif
#if NRF51_I2C_USE_I2C1
#if NRF5_I2C_USE_I2C1
i2cObjectInit(&I2CD2);
I2CD2.thread = NULL;
I2CD2.i2c = NRF_TWI1;
@ -278,14 +290,23 @@ void i2c_lld_start(I2CDriver *i2cp) {
i2c_clear_bus(i2cp);
NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;
NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;
IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF;
IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF;
i2c->EVENTS_RXDREADY = 0;
i2c->EVENTS_TXDSENT = 0;
#if CORTEX_MODEL >= 4
(void)i2c->EVENTS_RXDREADY;
(void)i2c->EVENTS_TXDSENT;
#endif
#if NRF_SERIES == 51
i2c->PSELSCL = cfg->scl_pad;
i2c->PSELSDA = cfg->sda_pad;
#else
i2c->PSEL.SCL = cfg->scl_pad;
i2c->PSEL.SDA = cfg->sda_pad;
#endif
switch (cfg->clock) {
case 100000:
i2c->FREQUENCY = TWI_FREQUENCY_FREQUENCY_K100 << TWI_FREQUENCY_FREQUENCY_Pos;
@ -330,8 +351,8 @@ void i2c_lld_stop(I2CDriver *i2cp) {
nvicDisableVector(I2C_IRQ_NUM);
NRF_GPIO->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;
NRF_GPIO->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;
IOPORT1->PIN_CNF[cfg->scl_pad] = I2C_PIN_CNF_CLR;
IOPORT1->PIN_CNF[cfg->sda_pad] = I2C_PIN_CNF_CLR;
}
}

32
os/hal/ports/NRF5/NRF51822/hal_i2c_lld.h → os/hal/ports/NRF5/LLD/hal_i2c_lld.h
View File

@ -15,8 +15,8 @@
*/
/**
* @file NRF51822/i2c_lld.h
* @brief NRF51822 I2C subsystem low level driver header.
* @file NRF5/LLD/hal_i2c_lld.h
* @brief NRF5 I2C subsystem low level driver header.
*
* @addtogroup I2C
* @{
@ -49,8 +49,8 @@
* @details If set to @p TRUE the support for I2C0 is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_I2C_USE_I2C0) || defined(__DOXYGEN__)
#define NRF51_I2C_USE_I2C0 FALSE
#if !defined(NRF5_I2C_USE_I2C0) || defined(__DOXYGEN__)
#define NRF5_I2C_USE_I2C0 FALSE
#endif
/**
@ -58,22 +58,22 @@
* @details If set to @p TRUE the support for I2C1 is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_I2C_USE_I2C1) || defined(__DOXYGEN__)
#define NRF51_I2C_USE_I2C1 FALSE
#if !defined(NRF5_I2C_USE_I2C1) || defined(__DOXYGEN__)
#define NRF5_I2C_USE_I2C1 FALSE
#endif
/**
* @brief I2C0 interrupt priority level setting.
*/
#if !defined(NRF51_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_I2C_I2C0_IRQ_PRIORITY 3
#if !defined(NRF5_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_I2C_I2C0_IRQ_PRIORITY 3
#endif
/**
* @brief I2C1 interrupt priority level setting.
*/
#if !defined(NRF51_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_I2C_I2C1_IRQ_PRIORITY 3
#if !defined(NRF5_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_I2C_I2C1_IRQ_PRIORITY 3
#endif
/** @} */
@ -81,13 +81,13 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if NRF51_I2C_USE_I2C0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_I2C_I2C0_IRQ_PRIORITY)
#if NRF5_I2C_USE_I2C0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_I2C_I2C0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to I2C0"
#endif
#if NRF51_I2C_USE_I2C1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_I2C_I2C1_IRQ_PRIORITY)
#if NRF5_I2C_USE_I2C1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_I2C_I2C1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to I2C1"
#endif
@ -198,11 +198,11 @@ struct I2CDriver {
#if !defined(__DOXYGEN__)
#if NRF51_I2C_USE_I2C0
#if NRF5_I2C_USE_I2C0
extern I2CDriver I2CD1;
#endif
#if NRF51_I2C_USE_I2C1
#if NRF5_I2C_USE_I2C1
extern I2CDriver I2CD2;
#endif

10
os/hal/ports/NRF5/NRF51822/hal_pal_lld.c → os/hal/ports/NRF5/LLD/hal_pal_lld.c
View File

@ -15,8 +15,8 @@
*/
/**
* @file pal_lld.c
* @brief NRF51822 PAL subsystem low level driver source.
* @file NRF5/LLD/hal_pal_lld.c
* @brief NRF5 PAL subsystem low level driver source.
*
* @addtogroup PAL
* @{
@ -46,7 +46,7 @@
void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
{
(void)port;
osalDbgAssert(pad <= 31, "pal_lld_setpadmode() - invalid pad");
osalDbgAssert(pad < PAL_IOPORTS_WIDTH, "pal_lld_setpadmode() - invalid pad");
switch (mode) {
case PAL_MODE_RESET:
@ -114,9 +114,9 @@ void _pal_lld_setpadmode(ioportid_t port, uint8_t pad, iomode_t mode)
/*===========================================================================*/
/**
* @brief NRF51 I/O ports configuration.
* @brief NRF5 I/O ports configuration.
*
* @param[in] config the NRF51 ports configuration
* @param[in] config the NRF5 ports configuration
*
* @notapi
*/

10
os/hal/ports/NRF5/NRF51822/hal_pal_lld.h → os/hal/ports/NRF5/LLD/hal_pal_lld.h
View File

@ -15,8 +15,8 @@
*/
/**
* @file pal_lld.h
* @brief NRF51822 PAL subsystem low level driver header.
* @file NRF5/LLD/hal_pal_lld.h
* @brief NRF5 PAL subsystem low level driver header.
*
* @addtogroup PAL
* @{
@ -128,7 +128,11 @@ typedef NRF_GPIO_Type *ioportid_t;
* @details Low level drivers can define multiple ports, it is suggested to
* use this naming convention.
*/
#if NRF_SERIES == 51
#define IOPORT1 NRF_GPIO
#else
#define IOPORT1 NRF_P0
#endif
/*===========================================================================*/
/* Implementation, some of the following macros could be implemented as */
@ -299,7 +303,7 @@ typedef NRF_GPIO_Type *ioportid_t;
*/
#define pal_lld_togglepad(port, pad) \
do { \
uint8_t bit = (IOPORT1->IN >> (pad)) & 1; \
uint8_t bit = (IOPORT1->OUT >> (pad)) & 1; \
if (bit) \
IOPORT1->OUTCLR = 1 << (pad); \
else \

60
os/hal/ports/NRF5/NRF51822/hal_qei_lld.c → os/hal/ports/NRF5/LLD/hal_qei_lld.c
View File

@ -38,7 +38,7 @@
/**
* @brief QEID1 driver identifier.
*/
#if NRF51_QEI_USE_QDEC0 || defined(__DOXYGEN__)
#if NRF5_QEI_USE_QDEC0 || defined(__DOXYGEN__)
QEIDriver QEID1;
#endif
@ -59,12 +59,15 @@ QEIDriver QEID1;
static void serve_interrupt(QEIDriver *qeip) {
NRF_QDEC_Type *qdec = qeip->qdec;
#if NRF51_QEI_USE_ACC_OVERFLOWED_CB == TRUE
#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE
/* Accumulator overflowed
*/
if (qdec->EVENTS_ACCOF) {
qdec->EVENTS_ACCOF = 0;
#if CORTEX_MODEL >= 4
(void)qdec->EVENTS_ACCOF;
#endif
qeip->overflowed++;
if (qeip->config->overflowed_cb)
qeip->config->overflowed_cb(qeip);
@ -75,7 +78,10 @@ static void serve_interrupt(QEIDriver *qeip) {
*/
if (qdec->EVENTS_REPORTRDY) {
qdec->EVENTS_REPORTRDY = 0;
#if CORTEX_MODEL >= 4
(void)qdec->EVENTS_REPORTRDY;
#endif
/* Read (and clear counters due to shortcut) */
int16_t acc = ( int16_t)qdec->ACCREAD;
uint16_t accdbl = (uint16_t)qdec->ACCDBLREAD;
@ -93,7 +99,7 @@ static void serve_interrupt(QEIDriver *qeip) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_QEI_USE_QDEC0 == TRUE
#if NRF5_QEI_USE_QDEC0 == TRUE
/**
* @brief Quadrature decoder vector (QDEC)
*
@ -118,7 +124,7 @@ OSAL_IRQ_HANDLER(Vector88) {
*/
void qei_lld_init(void) {
#if NRF51_QEI_USE_QDEC0 == TRUE
#if NRF5_QEI_USE_QDEC0 == TRUE
/* Driver initialization.*/
qeiObjectInit(&QEID1);
QEID1.qdec = NRF_QDEC;
@ -140,39 +146,51 @@ void qei_lld_start(QEIDriver *qeip) {
/* Set Pins */
palSetLineMode(cfg->phase_a, PAL_MODE_INPUT);
palSetLineMode(cfg->phase_b, PAL_MODE_INPUT);
#if NRF51_QEI_USE_LED == TRUE
#if NRF5_QEI_USE_LED == TRUE
if (cfg->led != PAL_NOLINE) {
palSetLineMode(cfg->led, PAL_MODE_INPUT);
}
#endif
/* Set interrupt masks and enable interrupt */
#if NRF51_QEI_USE_ACC_OVERFLOWED_CB == TRUE
#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE
qdec->INTENSET = QDEC_INTENSET_REPORTRDY_Msk |
QDEC_INTENSET_ACCOF_Msk;
#else
qdec->INTENSET = QDEC_INTENSET_REPORTRDY_Msk;
#endif
#if NRF51_QEI_USE_QDEC0 == TRUE
#if NRF5_QEI_USE_QDEC0 == TRUE
if (&QEID1 == qeip) {
nvicEnableVector(QDEC_IRQn, NRF51_QEI_QDEC0_IRQ_PRIORITY);
nvicEnableVector(QDEC_IRQn, NRF5_QEI_QDEC0_IRQ_PRIORITY);
}
#endif
/* Select pin for Phase A and Phase B */
#if NRF_SERIES == 51
qdec->PSELA = PAL_PAD(cfg->phase_a);
qdec->PSELB = PAL_PAD(cfg->phase_b);
#else
qdec->PSEL.A = PAL_PAD(cfg->phase_a);
qdec->PSEL.B = PAL_PAD(cfg->phase_b);
#endif
/* Select (optional) pin for LED, and configure it */
#if NRF51_QEI_USE_LED == TRUE
#if NRF5_QEI_USE_LED == TRUE
#if NRF_SERIES == 51
qdec->PSELLED = PAL_PAD(cfg->led);
#else
qdec->PSEL.LED = PAL_PAD(cfg->led);
#endif
qdec->LEDPOL = ((cfg->led_polarity == QEI_LED_POLARITY_LOW)
? QDEC_LEDPOL_LEDPOL_ActiveLow
: QDEC_LEDPOL_LEDPOL_ActiveHigh)
<< QDEC_LEDPOL_LEDPOL_Pos;
qdec->LEDPRE = cfg->led_warming;
#else
#if NRF_SERIES == 51
qdec->PSELLED = (uint32_t)-1;
#else
qdec->PSEL.LED = (uint32_t)-1;
#endif
#endif
/* Set sampling resolution and debouncing */
@ -195,6 +213,11 @@ void qei_lld_start(QEIDriver *qeip) {
qdec->EVENTS_SAMPLERDY = 0;
qdec->EVENTS_REPORTRDY = 0;
qdec->EVENTS_ACCOF = 0;
#if CORTEX_MODEL >= 4
(void)qdec->EVENTS_SAMPLERDY;
(void)qdec->EVENTS_REPORTRDY;
(void)qdec->EVENTS_ACCOF;
#endif
}
/**
@ -214,12 +237,12 @@ void qei_lld_stop(QEIDriver *qeip) {
qdec->ENABLE = 0;
/* Unset interrupt masks and disable interrupt */
#if NRF51_QEI_USE_QDEC0 == TRUE
#if NRF5_QEI_USE_QDEC0 == TRUE
if (&QEID1 == qeip) {
nvicDisableVector(QDEC_IRQn);
}
#endif
#if NRF51_QEI_USE_ACC_OVERFLOWED_CB == TRUE
#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE
qdec->INTENCLR = QDEC_INTENCLR_REPORTRDY_Msk |
QDEC_INTENCLR_ACCOF_Msk;
#else
@ -229,7 +252,7 @@ void qei_lld_stop(QEIDriver *qeip) {
/* Return pins to reset state */
palSetLineMode(cfg->phase_a, PAL_MODE_RESET);
palSetLineMode(cfg->phase_b, PAL_MODE_RESET);
#if NRF51_QEI_USE_LED == TRUE
#if NRF5_QEI_USE_LED == TRUE
if (cfg->led != PAL_NOLINE) {
palSetLineMode(cfg->led, PAL_MODE_RESET);
}
@ -245,13 +268,18 @@ void qei_lld_stop(QEIDriver *qeip) {
* @notapi
*/
void qei_lld_enable(QEIDriver *qeip) {
#if NRF51_QEI_USE_ACC_OVERFLOWED_CB == TRUE
#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE
qeip->overflowed = 0;
#endif
qeip->qdec->EVENTS_SAMPLERDY = 0;
qeip->qdec->EVENTS_REPORTRDY = 0;
qeip->qdec->EVENTS_ACCOF = 0;
#if CORTEX_MODEL >= 4
(void)qeip->qdec->EVENTS_SAMPLERDY;
(void)qeip->qdec->EVENTS_REPORTRDY;
(void)qeip->qdec->EVENTS_ACCOF;
#endif
qeip->qdec->TASKS_START = 1;
}

34
os/hal/ports/NRF5/NRF51822/hal_qei_lld.h → os/hal/ports/NRF5/LLD/hal_qei_lld.h
View File

@ -71,8 +71,8 @@
* is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_QEI_USE_LED) || defined(__DOXYGEN__)
#define NRF51_QEI_USE_LED FALSE
#if !defined(NRF5_QEI_USE_LED) || defined(__DOXYGEN__)
#define NRF5_QEI_USE_LED FALSE
#endif
/**
@ -81,8 +81,8 @@
* is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_QEI_USE_ACC_OVERFLOWED_CB) || defined(__DOXYGEN__)
#define NRF51_QEI_USE_ACC_OVERFLOWED_CB FALSE
#if !defined(NRF5_QEI_USE_ACC_OVERFLOWED_CB) || defined(__DOXYGEN__)
#define NRF5_QEI_USE_ACC_OVERFLOWED_CB FALSE
#endif
/**
@ -90,15 +90,15 @@
* @details If set to @p TRUE the support for QEID1 is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_QEI_USE_QDEC0) || defined(__DOXYGEN__)
#define NRF51_QEI_USE_QDEC0 FALSE
#if !defined(NRF5_QEI_USE_QDEC0) || defined(__DOXYGEN__)
#define NRF5_QEI_USE_QDEC0 FALSE
#endif
/**
* @brief QEID interrupt priority level setting for QDEC0.
*/
#if !defined(NRF51_QEI_QDEC0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_QEI_QDEC0_IRQ_PRIORITY 2
#if !defined(NRF5_QEI_QDEC0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_QEI_QDEC0_IRQ_PRIORITY 2
#endif
/** @} */
@ -106,13 +106,13 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if NRF51_QEI_USE_QDEC0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_QEI_QDEC0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to QDEC0"
#if NRF5_QEI_USE_QDEC0 == FALSE
#error "Requesting QEI driver, but no QDEC peripheric attached"
#endif
#if NRF51_QEI_USE_QDEC0 == FALSE
#error "Requesting QEI driver, but no QDEC peripheric attached"
#if NRF5_QEI_USE_QDEC0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_QEI_QDEC0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to QDEC0"
#endif
@ -238,7 +238,7 @@ typedef struct {
* @brief Line for reading Phase B
*/
ioline_t phase_b;
#if (NRF51_QEI_USE_LED == TRUE) || defined(__DOXYGEN__)
#if (NRF5_QEI_USE_LED == TRUE) || defined(__DOXYGEN__)
/**
* @brief Line used to control LED
*
@ -276,7 +276,7 @@ typedef struct {
* @details Default to QEI_REPORT_10
*/
qeireport_t report;
#if NRF51_QEI_USE_ACC_OVERFLOWED_CB == TRUE
#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE
/**
* @brief Notify of internal accumulator overflowed
* (ie: MCU discarding samples)
@ -311,7 +311,7 @@ struct QEIDriver {
* @brief Counter
*/
qeicnt_t count;
#if NRF51_QEI_USE_ACC_OVERFLOWED_CB == TRUE
#if NRF5_QEI_USE_ACC_OVERFLOWED_CB == TRUE
/**
* @brief Number of time the MCU discarded updates due to
* accumulator overflow
@ -359,7 +359,7 @@ struct QEIDriver {
/* External declarations. */
/*===========================================================================*/
#if NRF51_QEI_USE_QDEC0 && !defined(__DOXYGEN__)
#if NRF5_QEI_USE_QDEC0 && !defined(__DOXYGEN__)
extern QEIDriver QEID1;
#endif

24
os/hal/ports/NRF5/NRF51822/hal_rng_lld.c → os/hal/ports/NRF5/LLD/hal_rng_lld.c
View File

@ -15,8 +15,8 @@
*/
/**
* @file NRF51/NRF518221/rng_lld.c
* @brief NRF51 RNG subsystem low level driver source.
* @file NRF5/LLD/hal_rng_lld.c
* @brief NRF5 RNG subsystem low level driver source.
*
* @addtogroup RNG
* @{
@ -41,8 +41,8 @@ static const RNGConfig default_config = {
/* Driver exported variables. */
/*===========================================================================*/
/** @brief RNG1 driver identifier.*/
#if NRF51_RNG_USE_RNG1 || defined(__DOXYGEN__)
/** @brief RNGD1 driver identifier.*/
#if NRF5_RNG_USE_RNG0 || defined(__DOXYGEN__)
RNGDriver RNGD1;
#endif
@ -87,9 +87,6 @@ void rng_lld_start(RNGDriver *rngp) {
if (rngp->config == NULL)
rngp->config = &default_config;
/* Power on peripheric */
rng->POWER = 1;
/* Configure digital error correction */
if (rngp->config->digital_error_correction)
rng->CONFIG |= RNG_CONFIG_DERCEN_Msk;
@ -98,7 +95,10 @@ void rng_lld_start(RNGDriver *rngp) {
/* Clear pending events */
rng->EVENTS_VALRDY = 0;
#if CORTEX_MODEL >= 4
(void)rng->EVENTS_VALRDY;
#endif
/* Set interrupt mask */
rng->INTENSET = RNG_INTENSET_VALRDY_Msk;
@ -117,9 +117,8 @@ void rng_lld_start(RNGDriver *rngp) {
void rng_lld_stop(RNGDriver *rngp) {
NRF_RNG_Type *rng = rngp->rng;
/* Stop and power off peripheric */
/* Stop peripheric */
rng->TASKS_STOP = 1;
rng->POWER = 0;
}
@ -155,7 +154,10 @@ msg_t rng_lld_write(RNGDriver *rngp, uint8_t *buf, size_t n,
/* Mark as read */
rng->EVENTS_VALRDY = 0;
#if CORTEX_MODEL >= 4
(void)rng->EVENTS_VALRDY;
#endif
/* Clear interrupt so we can wake up again */
nvicClearPending(rngp->irq);
}

54
os/hal/ports/NRF5/NRF51822/hal_rng_lld.h → os/hal/ports/NRF5/LLD/hal_rng_lld.h
View File

@ -15,8 +15,8 @@
*/
/**
* @file NRF51/NRF51822/rng_lld.h
* @brief NRF51 RNG subsystem low level driver header.
* @file NRF5/LLD/hal_rng_lld.h
* @brief NRF5 RNG subsystem low level driver header.
*
* @addtogroup RNG
* @{
@ -40,28 +40,19 @@
* @{
*/
/**
* @brief RNG1 driver enable switch.
* @details If set to @p TRUE the support for RNG1 is included.
* @brief RNGD1 driver enable switch.
* @details If set to @p TRUE the support for RNGD1 is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_RNG_USE_RNG1) || defined(__DOXYGEN__)
#define NRF51_RNG_USE_RNG1 FALSE
#if !defined(NRF5_RNG_USE_RNG0) || defined(__DOXYGEN__)
#define NRF5_RNG_USE_RNG0 FALSE
#endif
/**
* @brief RNG1 driver enable switch.
* @details If set to @p TRUE the support for RNG1 is included.
* @note The default is @p FALSE.
* @brief RNG interrupt priority level setting for RNG0.
*/
#if !defined(NRF51_RNG_USE_RNG1) || defined(__DOXYGEN__)
#define NRF51_RNG_USE_POWER_ON_WRITE FALSE
#endif
/**
* @brief RNG1 interrupt priority level setting.
*/
#if !defined(NRF51_RNG_RNG1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_RNG_RNG1_IRQ_PRIORITY 3
#if !defined(NRF5_RNG_RNG0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_RNG_RNG0_IRQ_PRIORITY 3
#endif
@ -69,9 +60,13 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if NRF51_RNG_USE_RNG1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_RNG_RNG1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to RNG1"
#if NRF5_RNG_USE_RNG0 == FALSE
#error "Requesting RNG driver, but no RNG peripheric attached"
#endif
#if NRF5_RNG_USE_RNG0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_RNG_RNG0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to RNG0"
#endif
/*===========================================================================*/
@ -96,18 +91,11 @@ typedef struct {
* speed advantage, but may result in a statistical distribution
* that is not perfectly uniform.
*
* @note On average, it take 167µs to get a byte without digitial
* error correction and 677µs with, but no garantee is made
* on the necessary time to generate one byte.
* @note For nRF51, on average, it take 167µs to get a byte without
* digitial error correction and 677µs with, but no garantee
* is made on the necessary time to generate one byte.
*/
uint8_t digital_error_correction:1;
/**
* @brief Only power the RNG device when requeting random bytes
*
* @details Device will not be powered when started/stopped
* but only when writint bytes.
*/
uint8_t power_on_write:1;
} RNGConfig;
@ -148,9 +136,9 @@ struct RNGDriver {
/* External declarations. */
/*===========================================================================*/
#if NRF51_RNG_USE_RNG1 && !defined(__DOXYGEN__)
#if NRF5_RNG_USE_RNG0 && !defined(__DOXYGEN__)
extern RNGDriver RNGD1;
#endif /* NRF51_RNG_USE_RNG1 */
#endif /* NRF5_RNG_USE_RNG0 */
#ifdef __cplusplus
extern "C" {

82
os/hal/ports/NRF5/NRF51822/hal_serial_lld.c → os/hal/ports/NRF5/LLD/hal_serial_lld.c
View File

@ -15,8 +15,8 @@
*/
/**
* @file serial_lld.c
* @brief NRF51822 serial subsystem low level driver source.
* @file NRF5/LLD/hal_serial_lld.c
* @brief NRF5 serial subsystem low level driver source.
*
* @addtogroup SERIAL
* @{
@ -26,18 +26,24 @@
#if (HAL_USE_SERIAL == TRUE) || defined(__DOXYGEN__)
#if NRF_SERIES == 51
#include "nrf51.h"
#elif NRF_SERIES == 52
#include "nrf52.h"
#define UART0_IRQn UARTE0_UART0_IRQn
#endif
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/** @brief USART1 serial driver identifier.*/
#if (NRF51_SERIAL_USE_UART0 == TRUE) || defined(__DOXYGEN__)
#if (NRF5_SERIAL_USE_UART0 == TRUE) || defined(__DOXYGEN__)
SerialDriver SD1;
#endif
@ -50,11 +56,11 @@ SerialDriver SD1;
*/
static const SerialConfig default_config = {
.speed = 38400,
.tx_pad = NRF51_SERIAL_PAD_DISCONNECTED,
.rx_pad = NRF51_SERIAL_PAD_DISCONNECTED,
#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
.rts_pad = NRF51_SERIAL_PAD_DISCONNECTED,
.cts_pad = NRF51_SERIAL_PAD_DISCONNECTED,
.tx_pad = NRF5_SERIAL_PAD_DISCONNECTED,
.rx_pad = NRF5_SERIAL_PAD_DISCONNECTED,
#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)
.rts_pad = NRF5_SERIAL_PAD_DISCONNECTED,
.cts_pad = NRF5_SERIAL_PAD_DISCONNECTED,
#endif
};
@ -95,17 +101,17 @@ static void configure_uart(const SerialConfig *config)
};
/* Configure PINs mode */
if (config->tx_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
if (config->tx_pad != NRF5_SERIAL_PAD_DISCONNECTED) {
palSetPadMode(IOPORT1, config->tx_pad, PAL_MODE_OUTPUT_PUSHPULL);
}
if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
if (config->rx_pad != NRF5_SERIAL_PAD_DISCONNECTED) {
palSetPadMode(IOPORT1, config->rx_pad, PAL_MODE_INPUT);
}
#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
if (config->rts_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)
if (config->rts_pad != NRF5_SERIAL_PAD_DISCONNECTED) {
palSetPadMode(IOPORT1, config->rts_pad, PAL_MODE_OUTPUT_PUSHPULL);
}
if (config->cts_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
if (config->cts_pad != NRF5_SERIAL_PAD_DISCONNECTED) {
palSetPadMode(IOPORT1, config->cts_pad, PAL_MODE_INPUT);
}
#endif
@ -113,12 +119,12 @@ static void configure_uart(const SerialConfig *config)
/* Select PINs used by UART */
NRF_UART0->PSELTXD = config->tx_pad;
NRF_UART0->PSELRXD = config->rx_pad;
#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)
NRF_UART0->PSELRTS = config->rts_pad;
NRF_UART0->PSELCTS = config->cts_pad;
#else
NRF_UART0->PSELRTS = NRF51_SERIAL_PAD_DISCONNECTED;
NRF_UART0->PSELCTS = NRF51_SERIAL_PAD_DISCONNECTED;
NRF_UART0->PSELRTS = NRF5_SERIAL_PAD_DISCONNECTED;
NRF_UART0->PSELCTS = NRF5_SERIAL_PAD_DISCONNECTED;
#endif
/* Set baud rate */
@ -128,7 +134,7 @@ static void configure_uart(const SerialConfig *config)
NRF_UART0->CONFIG = (UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos);
/* Adjust flow control */
#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)
if ((config->rts_pad < TOTAL_GPIO_PADS) ||
(config->cts_pad < TOTAL_GPIO_PADS)) {
NRF_UART0->CONFIG |= UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos;
@ -143,9 +149,12 @@ static void configure_uart(const SerialConfig *config)
NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Enabled;
NRF_UART0->EVENTS_RXDRDY = 0;
NRF_UART0->EVENTS_TXDRDY = 0;
if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED) {
#if CORTEX_MODEL >= 4
(void)NRF_UART0->EVENTS_RXDRDY;
(void)NRF_UART0->EVENTS_TXDRDY;
#endif
if (config->rx_pad != NRF5_SERIAL_PAD_DISCONNECTED) {
while (NRF_UART0->EVENTS_RXDRDY != 0) {
(void)NRF_UART0->RXD;
}
@ -156,14 +165,14 @@ static void configure_uart(const SerialConfig *config)
/**
* @brief Driver output notification.
*/
#if NRF51_SERIAL_USE_UART0 || defined(__DOXYGEN__)
#if NRF5_SERIAL_USE_UART0 || defined(__DOXYGEN__)
static void notify1(io_queue_t *qp)
{
SerialDriver *sdp = &SD1;
(void)qp;
if (NRF_UART0->PSELTXD == NRF51_SERIAL_PAD_DISCONNECTED)
if (NRF_UART0->PSELTXD == NRF5_SERIAL_PAD_DISCONNECTED)
return;
if (!sdp->tx_busy) {
@ -186,7 +195,7 @@ static void notify1(io_queue_t *qp)
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_SERIAL_USE_UART0 || defined(__DOXYGEN__)
#if NRF5_SERIAL_USE_UART0 || defined(__DOXYGEN__)
OSAL_IRQ_HANDLER(Vector48) {
OSAL_IRQ_PROLOGUE();
@ -197,7 +206,10 @@ OSAL_IRQ_HANDLER(Vector48) {
if ((NRF_UART0->EVENTS_RXDRDY != 0) && (isr & UART_INTENSET_RXDRDY_Msk)) {
// Clear UART RX event flag
NRF_UART0->EVENTS_RXDRDY = 0;
#if CORTEX_MODEL >= 4
(void)NRF_UART0->EVENTS_RXDRDY;
#endif
osalSysLockFromISR();
if (iqIsEmptyI(&sdp->iqueue))
chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
@ -211,7 +223,10 @@ OSAL_IRQ_HANDLER(Vector48) {
// Clear UART TX event flag.
NRF_UART0->EVENTS_TXDRDY = 0;
#if CORTEX_MODEL >= 4
(void)NRF_UART0->EVENTS_TXDRDY;
#endif
osalSysLockFromISR();
b = oqGetI(&sdp->oqueue);
osalSysUnlockFromISR();
@ -232,6 +247,9 @@ OSAL_IRQ_HANDLER(Vector48) {
if ((NRF_UART0->EVENTS_ERROR != 0) && (isr & UART_INTENSET_ERROR_Msk)) {
// Clear UART ERROR event flag.
NRF_UART0->EVENTS_ERROR = 0;
#if CORTEX_MODEL >= 4
(void)NRF_UART0->EVENTS_ERROR;
#endif
}
@ -250,7 +268,7 @@ OSAL_IRQ_HANDLER(Vector48) {
*/
void sd_lld_init(void) {
#if NRF51_SERIAL_USE_UART0 == TRUE
#if NRF5_SERIAL_USE_UART0 == TRUE
sdObjectInit(&SD1, NULL, notify1);
#endif
}
@ -276,21 +294,21 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
if (sdp->state == SD_STOP) {
#if NRF51_SERIAL_USE_UART0 == TRUE
#if NRF5_SERIAL_USE_UART0 == TRUE
if (sdp == &SD1) {
configure_uart(config);
// Enable UART interrupt
NRF_UART0->INTENCLR = (uint32_t)-1;
NRF_UART0->INTENSET = UART_INTENSET_ERROR_Msk;
if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED)
if (config->rx_pad != NRF5_SERIAL_PAD_DISCONNECTED)
NRF_UART0->INTENSET |= UART_INTENSET_RXDRDY_Msk;
if (config->tx_pad != NRF51_SERIAL_PAD_DISCONNECTED)
if (config->tx_pad != NRF5_SERIAL_PAD_DISCONNECTED)
NRF_UART0->INTENSET |= UART_INTENSET_TXDRDY_Msk;
nvicEnableVector(UART0_IRQn, NRF51_SERIAL_UART0_PRIORITY);
nvicEnableVector(UART0_IRQn, NRF5_SERIAL_UART0_PRIORITY);
if (config->rx_pad != NRF51_SERIAL_PAD_DISCONNECTED)
if (config->rx_pad != NRF5_SERIAL_PAD_DISCONNECTED)
NRF_UART0->TASKS_STARTRX = 1;
}
#endif
@ -311,7 +329,7 @@ void sd_lld_stop(SerialDriver *sdp) {
if (sdp->state == SD_READY) {
#if NRF51_SERIAL_USE_UART0 == TRUE
#if NRF5_SERIAL_USE_UART0 == TRUE
if (&SD1 == sdp) {
nvicDisableVector(UART0_IRQn);
NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Disabled;

28
os/hal/ports/NRF5/NRF51822/hal_serial_lld.h → os/hal/ports/NRF5/LLD/hal_serial_lld.h
View File

@ -15,8 +15,8 @@
*/
/**
* @file serial_lld.h
* @brief NRF51822 serial subsystem low level driver header.
* @file NRF5/LLD/hal_serial_lld.h
* @brief NRF5 serial subsystem low level driver header.
*
* @addtogroup SERIAL
* @{
@ -45,8 +45,8 @@
* is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_SERIAL_USE_HWFLOWCTRL) || defined(__DOXYGEN__)
#define NRF51_SERIAL_USE_HWFLOWCTRL FALSE
#if !defined(NRF5_SERIAL_USE_HWFLOWCTRL) || defined(__DOXYGEN__)
#define NRF5_SERIAL_USE_HWFLOWCTRL FALSE
#endif
/**
@ -54,20 +54,20 @@
* @details If set to @p TRUE the support for SD1 is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_SERIAL_USE_UART0) || defined(__DOXYGEN__)
#define NRF51_SERIAL_USE_UART0 FALSE
#if !defined(NRF5_SERIAL_USE_UART0) || defined(__DOXYGEN__)
#define NRF5_SERIAL_USE_UART0 FALSE
#endif
/**
* @brief UART0 interrupt priority level setting.
*/
#if !defined(NRF51_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_SERIAL_UART0_PRIORITY 3
#if !defined(NRF5_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_SERIAL_UART0_PRIORITY 3
#endif
/* Value indicating that no pad is connected to this UART register. */
#define NRF51_SERIAL_PAD_DISCONNECTED 0xFFFFFFFFU
#define NRF51_SERIAL_INVALID_BAUDRATE 0xFFFFFFFFU
#define NRF5_SERIAL_PAD_DISCONNECTED 0xFFFFFFFFU
#define NRF5_SERIAL_INVALID_BAUDRATE 0xFFFFFFFFU
/** @} */
@ -75,8 +75,8 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if NRF51_SERIAL_USE_UART0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SERIAL_UART0_PRIORITY)
#if NRF5_SERIAL_USE_UART0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_SERIAL_UART0_PRIORITY)
#error "Invalid IRQ priority assigned to UART0"
#endif
@ -100,7 +100,7 @@ typedef struct {
/* End of the mandatory fields.*/
uint32_t tx_pad;
uint32_t rx_pad;
#if (NRF51_SERIAL_USE_HWFLOWCTRL == TRUE)
#if (NRF5_SERIAL_USE_HWFLOWCTRL == TRUE)
uint32_t rts_pad;
uint32_t cts_pad;
#endif
@ -134,7 +134,7 @@ typedef struct {
/* External declarations. */
/*===========================================================================*/
#if (NRF51_SERIAL_USE_UART0 == TRUE) && !defined(__DOXYGEN__)
#if (NRF5_SERIAL_USE_UART0 == TRUE) && !defined(__DOXYGEN__)
extern SerialDriver SD1;
#endif

45
os/hal/ports/NRF5/NRF51822/hal_spi_lld.c → os/hal/ports/NRF5/LLD/hal_spi_lld.c
View File

@ -15,8 +15,8 @@
*/
/**
* @file NRF51822/spi_lld.c
* @brief NRF51822 low level SPI driver code.
* @file NRF5/LLD/hal_spi_lld.c
* @brief NRF5 low level SPI driver code.
*
* @addtogroup SPI
* @{
@ -30,12 +30,12 @@
/* Driver exported variables. */
/*===========================================================================*/
#if NRF51_SPI_USE_SPI0 || defined(__DOXYGEN__)
#if NRF5_SPI_USE_SPI0 || defined(__DOXYGEN__)
/** @brief SPI1 driver identifier.*/
SPIDriver SPID1;
#endif
#if NRF51_SPI_USE_SPI1 || defined(__DOXYGEN__)
#if NRF5_SPI_USE_SPI1 || defined(__DOXYGEN__)
/** @brief SPI2 driver identifier.*/
SPIDriver SPID2;
#endif
@ -76,7 +76,10 @@ static void serve_interrupt(SPIDriver *spip) {
// Clear SPI READY event flag
port->EVENTS_READY = 0;
#if CORTEX_MODEL >= 4
(void)port->EVENTS_READY;
#endif
if (spip->rxptr != NULL) {
*(uint8_t *)spip->rxptr++ = port->RXD;
}
@ -107,7 +110,7 @@ static void serve_interrupt(SPIDriver *spip) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_SPI_USE_SPI0 || defined(__DOXYGEN__)
#if NRF5_SPI_USE_SPI0 || defined(__DOXYGEN__)
/**
* @brief SPI0 interrupt handler.
*
@ -120,7 +123,7 @@ CH_IRQ_HANDLER(Vector4C) {
CH_IRQ_EPILOGUE();
}
#endif
#if NRF51_SPI_USE_SPI1 || defined(__DOXYGEN__)
#if NRF5_SPI_USE_SPI1 || defined(__DOXYGEN__)
/**
* @brief SPI1 interrupt handler.
*
@ -145,11 +148,11 @@ CH_IRQ_HANDLER(Vector50) {
*/
void spi_lld_init(void) {
#if NRF51_SPI_USE_SPI0
#if NRF5_SPI_USE_SPI0
spiObjectInit(&SPID1);
SPID1.port = NRF_SPI0;
#endif
#if NRF51_SPI_USE_SPI1
#if NRF5_SPI_USE_SPI1
spiObjectInit(&SPID2);
SPID2.port = NRF_SPI1;
#endif
@ -166,13 +169,13 @@ void spi_lld_start(SPIDriver *spip) {
uint32_t config;
if (spip->state == SPI_STOP) {
#if NRF51_SPI_USE_SPI0
#if NRF5_SPI_USE_SPI0
if (&SPID1 == spip)
nvicEnableVector(SPI0_TWI0_IRQn, NRF51_SPI_SPI0_IRQ_PRIORITY);
nvicEnableVector(SPI0_TWI0_IRQn, NRF5_SPI_SPI0_IRQ_PRIORITY);
#endif
#if NRF51_SPI_USE_SPI1
#if NRF5_SPI_USE_SPI1
if (&SPID2 == spip)
nvicEnableVector(SPI1_TWI1_IRQn, NRF51_SPI_SPI1_IRQ_PRIORITY);
nvicEnableVector(SPI1_TWI1_IRQn, NRF5_SPI_SPI1_IRQ_PRIORITY);
#endif
}
@ -201,14 +204,23 @@ void spi_lld_start(SPIDriver *spip) {
/* Configuration.*/
spip->port->CONFIG = config;
#if NRF_SERIES == 51
spip->port->PSELSCK = spip->config->sckpad;
spip->port->PSELMOSI = spip->config->mosipad;
spip->port->PSELMISO = spip->config->misopad;
#else
spip->port->PSEL.SCK = spip->config->sckpad;
spip->port->PSEL.MOSI = spip->config->mosipad;
spip->port->PSEL.MISO = spip->config->misopad;
#endif
spip->port->FREQUENCY = spip->config->freq;
spip->port->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
/* clear events flag */
spip->port->EVENTS_READY = 0;
#if CORTEX_MODEL >= 4
(void)spip->port->EVENTS_READY;
#endif
}
/**
@ -223,11 +235,11 @@ void spi_lld_stop(SPIDriver *spip) {
if (spip->state != SPI_STOP) {
spip->port->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
spip->port->INTENCLR = (SPI_INTENCLR_READY_Clear << SPI_INTENCLR_READY_Pos);
#if NRF51_SPI_USE_SPI0
#if NRF5_SPI_USE_SPI0
if (&SPID1 == spip)
nvicDisableVector(SPI0_TWI0_IRQn);
#endif
#if NRF51_SPI_USE_SPI1
#if NRF5_SPI_USE_SPI1
if (&SPID2 == spip)
nvicDisableVector(SPI1_TWI1_IRQn);
#endif
@ -366,6 +378,9 @@ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
while (spip->port->EVENTS_READY == 0)
;
spip->port->EVENTS_READY = 0;
#if CORTEX_MODEL >= 4
(void)spip->port->EVENTS_READY;
#endif
return spip->port->RXD;
}

44
os/hal/ports/NRF5/NRF51822/hal_spi_lld.h → os/hal/ports/NRF5/LLD/hal_spi_lld.h
View File

@ -15,8 +15,8 @@
*/
/**
* @file NRF51822/spi_lld.h
* @brief NRF51822 low level SPI driver header.
* @file NRF/LLD/hal_spi_lld.h
* @brief NRF5 low level SPI driver header.
*
* @addtogroup SPI
* @{
@ -38,40 +38,40 @@
/**
* @brief SPI0 interrupt priority level setting.
*/
#if !defined(NRF51_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_SPI_SPI0_IRQ_PRIORITY 3
#if !defined(NRF5_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_SPI_SPI0_IRQ_PRIORITY 3
#endif
/**
* @brief SPI1 interrupt priority level setting.
*/
#if !defined(NRF51_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_SPI_SPI1_IRQ_PRIORITY 3
#if !defined(NRF5_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_SPI_SPI1_IRQ_PRIORITY 3
#endif
/**
* @brief Overflow error hook.
* @details The default action is to stop the system.
*/
#if !defined(NRF51_SPI_SPI_ERROR_HOOK) || defined(__DOXYGEN__)
#define NRF51_SPI_SPI_ERROR_HOOK() chSysHalt()
#if !defined(NRF5_SPI_SPI_ERROR_HOOK) || defined(__DOXYGEN__)
#define NRF5_SPI_SPI_ERROR_HOOK() chSysHalt()
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if !NRF51_SPI_USE_SPI0 && !NRF51_SPI_USE_SPI1
#if !NRF5_SPI_USE_SPI0 && !NRF5_SPI_USE_SPI1
#error "SPI driver activated but no SPI peripheral assigned"
#endif
#if NRF51_SPI_USE_SPI0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SPI_SPI0_IRQ_PRIORITY)
#if NRF5_SPI_USE_SPI0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_SPI_SPI0_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI0"
#endif
#if NRF51_SPI_USE_SPI1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_SPI_SPI1_IRQ_PRIORITY)
#if NRF5_SPI_USE_SPI1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_SPI_SPI1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI1"
#endif
@ -96,13 +96,13 @@ typedef void (*spicallback_t)(SPIDriver *spip);
* @brief SPI frequency
*/
typedef enum {
NRF51_SPI_FREQ_125KBPS = (SPI_FREQUENCY_FREQUENCY_K125 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF51_SPI_FREQ_250KBPS = (SPI_FREQUENCY_FREQUENCY_K250 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF51_SPI_FREQ_500KBPS = (SPI_FREQUENCY_FREQUENCY_K500 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF51_SPI_FREQ_1MBPS = (SPI_FREQUENCY_FREQUENCY_M1 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF51_SPI_FREQ_2MBPS = (SPI_FREQUENCY_FREQUENCY_M2 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF51_SPI_FREQ_4MBPS = (SPI_FREQUENCY_FREQUENCY_M4 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF51_SPI_FREQ_8MBPS = (SPI_FREQUENCY_FREQUENCY_M8 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_125KBPS = (SPI_FREQUENCY_FREQUENCY_K125 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_250KBPS = (SPI_FREQUENCY_FREQUENCY_K250 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_500KBPS = (SPI_FREQUENCY_FREQUENCY_K500 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_1MBPS = (SPI_FREQUENCY_FREQUENCY_M1 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_2MBPS = (SPI_FREQUENCY_FREQUENCY_M2 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_4MBPS = (SPI_FREQUENCY_FREQUENCY_M4 << SPI_FREQUENCY_FREQUENCY_Pos),
NRF5_SPI_FREQ_8MBPS = (SPI_FREQUENCY_FREQUENCY_M8 << SPI_FREQUENCY_FREQUENCY_Pos),
} spifreq_t;
/**
@ -206,10 +206,10 @@ struct SPIDriver {
/* External declarations. */
/*===========================================================================*/
#if NRF51_SPI_USE_SPI0 && !defined(__DOXYGEN__)
#if NRF5_SPI_USE_SPI0 && !defined(__DOXYGEN__)
extern SPIDriver SPID1;
#endif
#if NRF51_SPI_USE_SPI1 && !defined(__DOXYGEN__)
#if NRF5_SPI_USE_SPI1 && !defined(__DOXYGEN__)
extern SPIDriver SPID2;
#endif

122
os/hal/ports/NRF5/NRF51822/hal_st_lld.c → os/hal/ports/NRF5/LLD/hal_st_lld.c
View File

@ -16,8 +16,8 @@
*/
/**
* @file st_lld.c
* @brief NRF51822 ST subsystem low level driver source.
* @file NRF5/LLD/hal_st_lld.c
* @brief NRF5 ST subsystem low level driver source.
*
* @addtogroup ST
* @{
@ -52,11 +52,11 @@
/*===========================================================================*/
#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
/**
* @brief System Timer vector (RTC0)
* @details This interrupt is used for system tick in periodic mode
* if selected with NRF51_ST_USE_RTC0
* if selected with NRF5_ST_USE_RTC0
*
* @isr
*/
@ -65,7 +65,10 @@ OSAL_IRQ_HANDLER(Vector6C) {
OSAL_IRQ_PROLOGUE();
NRF_RTC0->EVENTS_TICK = 0;
#if CORTEX_MODEL >= 4
(void)NRF_RTC0->EVENTS_TICK;
#endif
osalSysLockFromISR();
osalOsTimerHandlerI();
osalSysUnlockFromISR();
@ -74,11 +77,11 @@ OSAL_IRQ_HANDLER(Vector6C) {
}
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
/**
* @brief System Timer vector (RTC1)
* @details This interrupt is used for system tick in periodic mode
* if selected with NRF51_ST_USE_RTC1
* if selected with NRF5_ST_USE_RTC1
*
* @isr
*/
@ -87,7 +90,10 @@ OSAL_IRQ_HANDLER(Vector84) {
OSAL_IRQ_PROLOGUE();
NRF_RTC1->EVENTS_TICK = 0;
#if CORTEX_MODEL >= 4
(void)NRF_RTC1->EVENTS_TICK;
#endif
osalSysLockFromISR();
osalOsTimerHandlerI();
osalSysUnlockFromISR();
@ -96,11 +102,11 @@ OSAL_IRQ_HANDLER(Vector84) {
}
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
/**
* @brief System Timer vector. (TIMER0)
* @details This interrupt is used for system tick in periodic mode
* if selected with NRF51_ST_USE_TIMER0
* if selected with NRF5_ST_USE_TIMER0
*
* @isr
*/
@ -109,12 +115,16 @@ OSAL_IRQ_HANDLER(Vector60) {
OSAL_IRQ_PROLOGUE();
/* Clear timer compare event */
if (NRF_TIMER0->EVENTS_COMPARE[0] != 0)
if (NRF_TIMER0->EVENTS_COMPARE[0] != 0) {
NRF_TIMER0->EVENTS_COMPARE[0] = 0;
osalSysLockFromISR();
osalOsTimerHandlerI();
osalSysUnlockFromISR();
#if CORTEX_MODEL >= 4
(void)NRF_TIMER0->EVENTS_COMPARE[0];
#endif
osalSysLockFromISR();
osalOsTimerHandlerI();
osalSysUnlockFromISR();
}
OSAL_IRQ_EPILOGUE();
}
@ -122,11 +132,11 @@ OSAL_IRQ_HANDLER(Vector60) {
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
/**
* @brief System Timer vector (RTC0)
* @details This interrupt is used for freerunning mode (tick-less)
* if selected with NRF51_ST_USE_RTC0
* if selected with NRF5_ST_USE_RTC0
*
* @isr
*/
@ -136,7 +146,10 @@ OSAL_IRQ_HANDLER(Vector6C) {
if (NRF_RTC0->EVENTS_COMPARE[0]) {
NRF_RTC0->EVENTS_COMPARE[0] = 0;
#if CORTEX_MODEL >= 4
(void)NRF_RTC0->EVENTS_COMPARE[0];
#endif
osalSysLockFromISR();
osalOsTimerHandlerI();
osalSysUnlockFromISR();
@ -145,6 +158,9 @@ OSAL_IRQ_HANDLER(Vector6C) {
#if OSAL_ST_RESOLUTION == 16
if (NRF_RTC0->EVENTS_COMPARE[1]) {
NRF_RTC0->EVENTS_COMPARE[1] = 0;
#if CORTEX_MODEL >= 4
(void)NRF_RTC0->EVENTS_COMPARE[1];
#endif
NRF_RTC0->TASKS_CLEAR = 1;
}
#endif
@ -153,11 +169,11 @@ OSAL_IRQ_HANDLER(Vector6C) {
}
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
/**
* @brief System Timer vector (RTC1)
* @details This interrupt is used for freerunning mode (tick-less)
* if selected with NRF51_ST_USE_RTC1
* if selected with NRF5_ST_USE_RTC1
*
* @isr
*/
@ -167,7 +183,10 @@ OSAL_IRQ_HANDLER(Vector84) {
if (NRF_RTC1->EVENTS_COMPARE[0]) {
NRF_RTC1->EVENTS_COMPARE[0] = 0;
#if CORTEX_MODEL >= 4
(void)NRF_RTC1->EVENTS_COMPARE[0];
#endif
osalSysLockFromISR();
osalOsTimerHandlerI();
osalSysUnlockFromISR();
@ -176,6 +195,9 @@ OSAL_IRQ_HANDLER(Vector84) {
#if OSAL_ST_RESOLUTION == 16
if (NRF_RTC1->EVENTS_COMPARE[1]) {
NRF_RTC1->EVENTS_COMPARE[1] = 0;
#if CORTEX_MODEL >= 4
(void)NRF_RTC1->EVENTS_COMPARE[1];
#endif
NRF_RTC1->TASKS_CLEAR = 1;
}
#endif
@ -197,80 +219,92 @@ OSAL_IRQ_HANDLER(Vector84) {
void st_lld_init(void) {
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
/* Using RTC with prescaler */
NRF_RTC0->TASKS_STOP = 1;
NRF_RTC0->PRESCALER = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC0->PRESCALER = (NRF5_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC0->EVTENCLR = RTC_EVTENSET_COMPARE0_Msk;
NRF_RTC0->EVENTS_COMPARE[0] = 0;
#if CORTEX_MODEL >= 4
(void)NRF_RTC0->EVENTS_COMPARE[0];
#endif
NRF_RTC0->INTENSET = RTC_INTENSET_COMPARE0_Msk;
#if OSAL_ST_RESOLUTION == 16
NRF_RTC0->CC[1] = 0x10000; /* 2^16 */
NRF_RTC0->EVENTS_COMPARE[1] = 0;
#if CORTEX_MODEL >= 4
(void)NRF_RTC0->EVENTS_COMPARE[1];
#endif
NRF_RTC0->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
NRF_RTC0->INTENSET = RTC_INTENSET_COMPARE1_Msk;
#endif
NRF_RTC0->TASKS_CLEAR = 1;
/* Start timer */
nvicEnableVector(RTC0_IRQn, NRF51_ST_PRIORITY);
nvicEnableVector(RTC0_IRQn, NRF5_ST_PRIORITY);
NRF_RTC0->TASKS_START = 1;
#endif /* NRF51_ST_USE_RTC0 == TRUE */
#endif /* NRF5_ST_USE_RTC0 == TRUE */
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
/* Using RTC with prescaler */
NRF_RTC1->TASKS_STOP = 1;
NRF_RTC1->PRESCALER = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC1->PRESCALER = (NRF5_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC1->EVTENCLR = RTC_EVTENSET_COMPARE0_Msk;
NRF_RTC1->EVENTS_COMPARE[0] = 0;
#if CORTEX_MODEL >= 4
(void)NRF_RTC1->EVENTS_COMPARE[0];
#endif
NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE0_Msk;
#if OSAL_ST_RESOLUTION == 16
NRF_RTC1->CC[1] = 0x10000; /* 2^16 */
NRF_RTC1->EVENTS_COMPARE[1] = 0;
#if CORTEX_MODEL >= 4
NRF_RTC1->EVENTS_COMPARE[1];
#endif
NRF_RTC1->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE1_Msk;
#endif
NRF_RTC1->TASKS_CLEAR = 1;
/* Start timer */
nvicEnableVector(RTC1_IRQn, NRF51_ST_PRIORITY);
nvicEnableVector(RTC1_IRQn, NRF5_ST_PRIORITY);
NRF_RTC1->TASKS_START = 1;
#endif /* NRF51_ST_USE_RTC1 == TRUE */
#endif /* NRF5_ST_USE_RTC1 == TRUE */
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
/* Using RTC with prescaler */
NRF_RTC0->TASKS_STOP = 1;
NRF_RTC0->PRESCALER = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC0->PRESCALER = (NRF5_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC0->INTENSET = RTC_INTENSET_TICK_Msk;
/* Start timer */
nvicEnableVector(RTC0_IRQn, NRF51_ST_PRIORITY);
nvicEnableVector(RTC0_IRQn, NRF5_ST_PRIORITY);
NRF_RTC0->TASKS_START = 1;
#endif /* NRF51_ST_USE_RTC0 == TRUE */
#endif /* NRF5_ST_USE_RTC0 == TRUE */
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
/* Using RTC with prescaler */
NRF_RTC1->TASKS_STOP = 1;
NRF_RTC1->PRESCALER = (NRF51_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC1->PRESCALER = (NRF5_LFCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
NRF_RTC1->INTENSET = RTC_INTENSET_TICK_Msk;
/* Start timer */
nvicEnableVector(RTC1_IRQn, NRF51_ST_PRIORITY);
nvicEnableVector(RTC1_IRQn, NRF5_ST_PRIORITY);
NRF_RTC1->TASKS_START = 1;
#endif /* NRF51_ST_USE_RTC1 == TRUE */
#endif /* NRF5_ST_USE_RTC1 == TRUE */
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
NRF_TIMER0->TASKS_CLEAR = 1;
/*
* Using 32-bit mode with prescaler 16 configures this
* timer with a 1MHz clock.
* Using 32-bit mode with prescaler 1/16 configures this
* timer with a 1MHz clock, reducing power consumption.
*/
NRF_TIMER0->BITMODE = 3;
NRF_TIMER0->BITMODE = TIMER_BITMODE_BITMODE_32Bit;
NRF_TIMER0->PRESCALER = 4;
/*
@ -279,12 +313,12 @@ void st_lld_init(void) {
*/
NRF_TIMER0->CC[0] = (1000000 / OSAL_ST_FREQUENCY) - 1;
NRF_TIMER0->SHORTS = 1;
NRF_TIMER0->INTENSET = 0x10000;
NRF_TIMER0->INTENSET = TIMER_INTENSET_COMPARE0_Msk;
/* Start timer */
nvicEnableVector(TIMER0_IRQn, NRF51_ST_PRIORITY);
nvicEnableVector(TIMER0_IRQn, NRF5_ST_PRIORITY);
NRF_TIMER0->TASKS_START = 1;
#endif /* NRF51_ST_USE_TIMER0 == TRUE */
#endif /* NRF5_ST_USE_TIMER0 == TRUE */
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
}

106
os/hal/ports/NRF5/NRF51822/hal_st_lld.h → os/hal/ports/NRF5/LLD/hal_st_lld.h
View File

@ -15,8 +15,8 @@
*/
/**
* @file st_lld.h
* @brief NRF51822 ST subsystem low level driver header.
* @file NRF5/LLD/st_lld.h
* @brief NRF5 ST subsystem low level driver header.
* @details This header is designed to be include-able without having to
* include other files from the HAL.
*
@ -39,41 +39,38 @@
/**
* @brief Use RTC0 to generates system ticks
*
* @note Avoid using RTC0, as PPI has pre-programmed channels on it
* that can be used to control RADIO or TIMER0
*/
#if !defined(NRF51_ST_USE_RTC0) || defined(__DOXYGEN__)
#if !defined(SOFTDEVICE_PRESENT)
#define NRF51_ST_USE_RTC0 TRUE
#else
#define NRF51_ST_USE_RTC0 FALSE
#endif
#if !defined(NRF5_ST_USE_RTC0) || defined(__DOXYGEN__)
#define NRF5_ST_USE_RTC0 FALSE
#endif
/**
* @brief Use RTC1 to generates system ticks
*/
#if !defined(NRF51_ST_USE_RTC1) || defined(__DOXYGEN__)
#if !defined(SOFTDEVICE_PRESENT)
#define NRF51_ST_USE_RTC1 FALSE
#else
#define NRF51_ST_USE_RTC1 TRUE
#endif
#if !defined(NRF5_ST_USE_RTC1) || defined(__DOXYGEN__)
#define NRF5_ST_USE_RTC1 TRUE
#endif
/**
* @brief Use TIMER0 to generates system ticks
*
* @note Avoid using TIMER0 as it will draw more current
*/
#if !defined(NRF51_ST_USE_TIMER0) || defined(__DOXYGEN__)
#define NRF51_ST_USE_TIMER0 FALSE
#if !defined(NRF5_ST_USE_TIMER0) || defined(__DOXYGEN__)
#define NRF5_ST_USE_TIMER0 FALSE
#endif
/**
* @brief ST interrupt priority level setting.
*/
#if !defined(NRF51_ST_PRIORITY) || defined(__DOXYGEN__)
#if !defined(NRF5_ST_PRIORITY) || defined(__DOXYGEN__)
#if !defined(SOFTDEVICE_PRESENT)
#define NRF51_ST_PRIORITY 1
#define NRF5_ST_PRIORITY CORTEX_MAX_KERNEL_PRIORITY
#else
#define NRF51_ST_PRIORITY 1
#define NRF5_ST_PRIORITY 1
#endif
#endif
@ -82,32 +79,32 @@
/*===========================================================================*/
#if OSAL_ST_MODE != OSAL_ST_MODE_NONE
#if (NRF51_ST_USE_TIMER0 == TRUE) && (NRF51_GPT_USE_TIMER0 == TRUE)
#if (NRF5_ST_USE_TIMER0 == TRUE) && (NRF5_GPT_USE_TIMER0 == TRUE)
#error "TIMER0 already used by GPT driver"
#endif
#if (NRF51_ST_USE_RTC0 == FALSE) && \
(NRF51_ST_USE_RTC1 == FALSE) && \
(NRF51_ST_USE_TIMER0 == FALSE)
#if (NRF5_ST_USE_RTC0 == FALSE) && \
(NRF5_ST_USE_RTC1 == FALSE) && \
(NRF5_ST_USE_TIMER0 == FALSE)
#error "One clock source is needed, enable one (RTC0, RTC1, or TIMER0)"
#endif
#if ((NRF51_ST_USE_RTC0 == TRUE ? 1 : 0) + \
(NRF51_ST_USE_RTC1 == TRUE ? 1 : 0) + \
(NRF51_ST_USE_TIMER0 == TRUE ? 1 : 0)) > 1
#if ((NRF5_ST_USE_RTC0 == TRUE ? 1 : 0) + \
(NRF5_ST_USE_RTC1 == TRUE ? 1 : 0) + \
(NRF5_ST_USE_TIMER0 == TRUE ? 1 : 0)) > 1
#error "Only one clock source can be used (RTC0, RTC1, or TIMER0)"
#endif
#if defined(SOFTDEVICE_PRESENT)
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
#error "RTC0 cannot be used for system ticks when SOFTDEVICE present"
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
#error "TIMER0 cannot be used for system ticks when SOFTDEVICE present"
#endif
#if NRF51_ST_PRIORITY != 1
#if NRF5_ST_PRIORITY != 1
#error "ST priority must be 1 when SOFTDEVICE present"
#endif
@ -118,15 +115,16 @@
#if defined(CH_CFG_ST_TIMEDELTA) && (CH_CFG_ST_TIMEDELTA < 5)
#error "CH_CFG_ST_TIMEDELTA is too low"
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
#error "Freeruning (tick-less) mode not supported with TIMER, use RTC"
#endif
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
#if !OSAL_IRQ_IS_VALID_PRIORITY(NRF51_ST_PRIORITY)
#if !OSAL_IRQ_IS_VALID_PRIORITY(NRF5_ST_PRIORITY)
#error "Invalid IRQ priority assigned to ST driver"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@ -159,13 +157,13 @@ extern "C" {
* @notapi
*/
static inline systime_t st_lld_get_counter(void) {
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
return (systime_t)NRF_RTC0->COUNTER;
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
return (systime_t)NRF_RTC1->COUNTER;
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
return (systime_t)0;
#endif
}
@ -180,17 +178,23 @@ static inline systime_t st_lld_get_counter(void) {
* @notapi
*/
static inline void st_lld_start_alarm(systime_t abstime) {
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
NRF_RTC0->CC[0] = abstime;
NRF_RTC0->EVENTS_COMPARE[0] = 0;
#if CORTEX_MODEL >= 4
(void)NRF_RTC0->EVENTS_COMPARE[0];
#endif
NRF_RTC0->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
NRF_RTC1->CC[0] = abstime;
NRF_RTC1->EVENTS_COMPARE[0] = 0;
#if CORTEX_MODEL >= 4
(void)NRF_RTC1->EVENTS_COMPARE[0];
#endif
NRF_RTC1->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
(void)abstime;
#endif
}
@ -201,13 +205,19 @@ static inline void st_lld_start_alarm(systime_t abstime) {
* @notapi
*/
static inline void st_lld_stop_alarm(void) {
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
NRF_RTC0->EVTENCLR = RTC_EVTENCLR_COMPARE0_Msk;
NRF_RTC0->EVENTS_COMPARE[0] = 0;
#if CORTEX_MODEL >= 4
(void)NRF_RTC0->EVENTS_COMPARE[0];
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#endif
#if NRF5_ST_USE_RTC1 == TRUE
NRF_RTC1->EVTENCLR = RTC_EVTENCLR_COMPARE0_Msk;
NRF_RTC1->EVENTS_COMPARE[0] = 0;
#if CORTEX_MODEL >= 4
(void)NRF_RTC1->EVENTS_COMPARE[0];
#endif
#endif
}
@ -219,13 +229,13 @@ static inline void st_lld_stop_alarm(void) {
* @notapi
*/
static inline void st_lld_set_alarm(systime_t abstime) {
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
NRF_RTC0->CC[0] = abstime;
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
NRF_RTC1->CC[0] = abstime;
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
(void)abstime;
#endif
}
@ -238,13 +248,13 @@ static inline void st_lld_set_alarm(systime_t abstime) {
* @notapi
*/
static inline systime_t st_lld_get_alarm(void) {
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
return (systime_t)NRF_RTC0->CC[0];
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
return (systime_t)NRF_RTC1->CC[0];
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
return (systime_t)0;
#endif
}
@ -259,13 +269,13 @@ static inline systime_t st_lld_get_alarm(void) {
* @notapi
*/
static inline bool st_lld_is_alarm_active(void) {
#if NRF51_ST_USE_RTC0 == TRUE
#if NRF5_ST_USE_RTC0 == TRUE
return NRF_RTC0->EVTEN & RTC_EVTEN_COMPARE0_Msk;
#endif
#if NRF51_ST_USE_RTC1 == TRUE
#if NRF5_ST_USE_RTC1 == TRUE
return NRF_RTC1->EVTEN & RTC_EVTEN_COMPARE0_Msk;
#endif
#if NRF51_ST_USE_TIMER0 == TRUE
#if NRF5_ST_USE_TIMER0 == TRUE
return false;
#endif
}

27
os/hal/ports/NRF5/NRF51822/hal_wdg_lld.c → os/hal/ports/NRF5/LLD/hal_wdg_lld.c
View File

@ -15,8 +15,8 @@
*/
/**
* @file NRF51822/wdg_lld.c
* @brief WDG Driver subsystem low level driver source template.
* @file NRF5/LLD/hal_wdg_lld.c
* @brief NRF5 Watchdog Driver subsystem low level driver source template.
*
* @addtogroup WDG
* @{
@ -55,12 +55,12 @@ WDGDriver WDGD1;
* @brief Watchdog vector.
* @details This interrupt is used when watchdog timeout.
*
* @note Only 2 cycles at NRF51_LFCLK_FREQUENCY are available
* @note Only 2 cycles at NRF5_LFCLK_FREQUENCY are available
* to they good bye.
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector84) {
OSAL_IRQ_HANDLER(Vector80) {
OSAL_IRQ_PROLOGUE();
osalSysLockFromISR();
@ -101,18 +101,25 @@ void wdg_lld_init(void) {
* @notapi
*/
void wdg_lld_start(WDGDriver *wdgp) {
osalDbgAssert((wdgp->state == WDG_STOP),
"This WDG driver cannot be restarted once activated");
/* Generate interrupt on timeout */
#if WDG_USE_TIMEOUT_CALLBACK == TRUE
wdgp->wdt->INTENSET = WDT_INTENSET_TIMEOUT_Msk;
#endif
/* When to pause? (halt, sleep) */
wdgp->wdt->CONFIG =
(wdgp->config->flags.pause_on_sleep * WDT_CONFIG_SLEEP_Msk) |
(wdgp->config->flags.pause_on_halt * WDT_CONFIG_HALT_Msk );
uint32_t config = 0;
if (!wdgp->config->pause_on_sleep)
config |= WDT_CONFIG_SLEEP_Msk;
if (!wdgp->config->pause_on_halt)
config |= WDT_CONFIG_HALT_Msk;
wdgp->wdt->CONFIG = config;
/* Timeout in milli-seconds */
uint64_t tout = (NRF51_LFCLK_FREQUENCY * wdgp->config->timeout_ms / 1000) - 1;
osalDbgAssert(tout <= 0xFFFFFFFF, "watchdog timout value exceeded");
uint64_t tout = (NRF5_LFCLK_FREQUENCY * wdgp->config->timeout_ms / 1000) - 1;
osalDbgAssert(tout <= 0xFFFFFFFF, "watchdog timout value exceeded");
wdgp->wdt->CRV = (uint32_t)tout;
/* Reload request (using RR0) */
@ -131,7 +138,7 @@ void wdg_lld_start(WDGDriver *wdgp) {
*/
void wdg_lld_stop(WDGDriver *wdgp) {
(void)wdgp;
osalDbgAssert(false, "WDG cannot be stopped once activated");
osalDbgAssert(false, "This WDG driver cannot be stopped once activated");
}
/**

28
os/hal/ports/NRF5/NRF51822/hal_wdg_lld.h → os/hal/ports/NRF5/LLD/hal_wdg_lld.h
View File

@ -15,8 +15,8 @@
*/
/**
* @file NRF51822/wdg_lld.h
* @brief WDG Driver subsystem low level driver header template.
* @file NRF5/LLD/hal_wdg_lld.h
* @brief NRF5 Watchdog Driver subsystem low level driver header template.
*
* @addtogroup WDG
* @{
@ -32,7 +32,7 @@
/*===========================================================================*/
#define WDG_MAX_TIMEOUT_MS \
((uint32_t)(0xFFFFFFFFu * 1000 / NRF51_LFCLK_FREQUENCY))
((uint32_t)(0xFFFFFFFFu * 1000 / NRF5_LFCLK_FREQUENCY))
/*===========================================================================*/
/* Driver pre-compile time settings. */
@ -72,11 +72,27 @@ typedef struct WDGDriver WDGDriver;
*/
typedef struct {
struct {
uint8_t pause_on_sleep : 1;
uint8_t pause_on_halt : 1;
} flags;
/**
* @brief Pause watchdog while the CPU is sleeping
*/
uint8_t pause_on_sleep : 1;
/**
* @brief Pause watchdog while the CPU is halted by the debugger
*/
uint8_t pause_on_halt : 1;
};
/**
*
*/
uint32_t timeout_ms;
#if WDG_USE_TIMEOUT_CALLBACK == TRUE
/**
* @brief Notification callback when watchdog timedout
*
* @note About 2 cycles at NRF5_LFCLK_FREQUENCY are available
* before automatic reboot.
*
*/
void (*callback)(void);
#endif
} WDGConfig;

14
os/hal/ports/NRF5/NRF51822/hal_adc_lld.c
View File

@ -36,7 +36,7 @@
/*===========================================================================*/
/** @brief ADC1 driver identifier.*/
#if NRF51_ADC_USE_ADC1 || defined(__DOXYGEN__)
#if NRF5_ADC_USE_ADC1 || defined(__DOXYGEN__)
ADCDriver ADCD1;
#endif
@ -68,7 +68,7 @@ static void adc_lld_config_next_channel(ADCDriver *adcp, uint32_t config) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_ADC_USE_ADC1 || defined(__DOXYGEN__)
#if NRF5_ADC_USE_ADC1 || defined(__DOXYGEN__)
/**
* @brief ADC interrupt handler.
*
@ -130,7 +130,7 @@ OSAL_IRQ_HANDLER(Vector5C) {
*/
void adc_lld_init(void) {
#if NRF51_ADC_USE_ADC1
#if NRF5_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = NRF_ADC;
@ -148,13 +148,13 @@ void adc_lld_start(ADCDriver *adcp) {
/* If in stopped state then configures and enables the ADC. */
if (adcp->state == ADC_STOP) {
#if NRF51_ADC_USE_ADC1
#if NRF5_ADC_USE_ADC1
if (&ADCD1 == adcp) {
adcp->adc->INTENSET = ADC_INTENSET_END_Enabled << ADC_INTENSET_END_Pos;
nvicEnableVector(ADC_IRQn, NRF51_ADC_IRQ_PRIORITY);
nvicEnableVector(ADC_IRQn, NRF5_ADC_IRQ_PRIORITY);
}
#endif /* NRF51_ADC_USE_ADC1 */
#endif /* NRF5_ADC_USE_ADC1 */
}
}
@ -170,7 +170,7 @@ void adc_lld_stop(ADCDriver *adcp) {
/* If in ready state then disables the ADC clock and analog part.*/
if (adcp->state == ADC_READY) {
#if NRF51_ADC_USE_ADC1
#if NRF5_ADC_USE_ADC1
if (&ADCD1 == adcp) {
nvicDisableVector(ADC_IRQn);

16
os/hal/ports/NRF5/NRF51822/hal_adc_lld.h
View File

@ -44,15 +44,15 @@
* @details If set to @p TRUE the support for ADC1 is included.
* @note The default is @p FALSE.
*/
#if !defined(NRF51_ADC_USE_ADC1) || defined(__DOXYGEN__)
#define NRF51_ADC_USE_ADC1 FALSE
#if !defined(NRF5_ADC_USE_ADC1) || defined(__DOXYGEN__)
#define NRF5_ADC_USE_ADC1 FALSE
#endif
/**
* @brief ADC interrupt priority level setting.
*/
#if !defined(NRF51_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_ADC_IRQ_PRIORITY 2
#if !defined(NRF5_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_ADC_IRQ_PRIORITY 2
#endif
/** @} */
@ -61,12 +61,12 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !NRF51_ADC_USE_ADC1
#if !NRF5_ADC_USE_ADC1
#error "ADC driver activated but no ADC peripheral assigned"
#endif
#if NRF51_ADC_USE_ADC1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_ADC_IRQ_PRIORITY)
#if NRF5_ADC_USE_ADC1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_ADC_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to ADC1"
#endif
@ -206,7 +206,7 @@ struct ADCDriver {
/* External declarations. */
/*===========================================================================*/
#if NRF51_ADC_USE_ADC1 && !defined(__DOXYGEN__)
#if NRF5_ADC_USE_ADC1 && !defined(__DOXYGEN__)
extern ADCDriver ADCD1;
#endif

2
os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c
View File

@ -92,7 +92,7 @@ OSAL_IRQ_HANDLER(Vector58) {
*/
void ext_lld_exti_irq_enable(void) {
nvicEnableVector(GPIOTE_IRQn, NRF51_EXT_GPIOTE_IRQ_PRIORITY);
nvicEnableVector(GPIOTE_IRQn, NRF5_EXT_GPIOTE_IRQ_PRIORITY);
}
/**

4
os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.h
View File

@ -42,8 +42,8 @@
/**
* @brief GPIOTE interrupt priority level setting.
*/
#if !defined(NRF51_EXT_GPIOTE_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_EXT_GPIOTE_IRQ_PRIORITY 3
#if !defined(NRF5_EXT_GPIOTE_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_EXT_GPIOTE_IRQ_PRIORITY 3
#endif
/** @} */

14
os/hal/ports/NRF5/NRF51822/hal_lld.c
View File

@ -56,14 +56,16 @@
void hal_lld_init(void)
{
/* High frequency clock initialisation
* (If NRF51_XTAL_VALUE is not defined assume its an RC oscillator)
* (If NRF5_XTAL_VALUE is not defined assume its an 16Mhz RC oscillator)
*/
NRF_CLOCK->TASKS_HFCLKSTOP = 1;
#if defined(NRF51_XTAL_VALUE)
#if NRF51_XTAL_VALUE == 16000000
#if defined(NRF5_XTAL_VALUE)
#if NRF5_XTAL_VALUE == 16000000
NRF_CLOCK->XTALFREQ = 0xFF;
#elif NRF51_XTAL_VALUE == 32000000
#elif NRF5_XTAL_VALUE == 32000000
NRF_CLOCK->XTALFREQ = 0x00;
#else
#error "Unsupported XTAL value"
#endif
#endif
@ -72,10 +74,10 @@ void hal_lld_init(void)
* Clock is only started if st driver requires it
*/
NRF_CLOCK->TASKS_LFCLKSTOP = 1;
NRF_CLOCK->LFCLKSRC = NRF51_LFCLK_SOURCE;
NRF_CLOCK->LFCLKSRC = NRF5_LFCLK_SOURCE;
#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) && \
(NRF51_SYSTEM_TICKS == NRF51_SYSTEM_TICKS_AS_RTC)
(NRF5_SYSTEM_TICKS == NRF5_SYSTEM_TICKS_AS_RTC)
NRF_CLOCK->TASKS_LFCLKSTART = 1;
#endif
}

33
os/hal/ports/NRF5/NRF51822/hal_lld.h
View File

@ -15,7 +15,7 @@
*/
/**
* @file NRF51/NRF51822/hal_lld.h
* @file NRF5/NRF51822/hal_lld.h
* @brief NRF51822 HAL subsystem low level driver header.
*
* @addtogroup HAL
@ -35,14 +35,26 @@
*/
#define PLATFORM_NAME "Nordic Semiconductor nRF51822"
/**
* @name Chip series
*/
#define NRF_SERIES 51
/**
* @brief Frequency value for the Low Frequency Clock
*/
#define NRF5_LFCLK_FREQUENCY 32768
/**
* @brief Frequency value for the High Frequency Clock
*/
#define NRF5_HFCLK_FREQUENCY 16000000
/**
* @}
*/
/**
* @brief Frequency valuefor the Low Frequency Clock
*/
#define NRF51_LFCLK_FREQUENCY 32768
/*===========================================================================*/
/* Driver pre-compile time settings. */
@ -57,16 +69,16 @@
* When cristal is not available it's preferable to use the
* internal RC oscillator that synthezing the clock.
*/
#if !defined(NRF51_LFCLK_SOURCE) || defined(__DOXYGEN__)
#define NRF51_LFCLK_SOURCE 0
#if !defined(NRF5_LFCLK_SOURCE) || defined(__DOXYGEN__)
#define NRF5_LFCLK_SOURCE 0
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if (NRF51_LFCLK_SOURCE < 0) || (NRF51_LFCLK_SOURCE > 2)
#error "Possible value for NRF51_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth"
#if (NRF5_LFCLK_SOURCE < 0) || (NRF5_LFCLK_SOURCE > 2)
#error "Possible value for NRF5_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth"
#endif
/*===========================================================================*/
@ -83,14 +95,11 @@
#include "nvic.h"
#define NRF51_LFCLK_FREQUENCY 32768
#define NRF51_HFCLK_FREQUENCY 16000000
#ifdef __cplusplus
extern "C" {
#endif
void hal_lld_init(void);
void nrf51_clock_init(void);
#ifdef __cplusplus
}
#endif

48
os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c
View File

@ -39,7 +39,7 @@
* @brief PWMD1 driver identifier.
* @note The driver PWMD1 allocates the timer TIMER0 when enabled.
*/
#if NRF51_PWM_USE_TIMER0 || defined(__DOXYGEN__)
#if NRF5_PWM_USE_TIMER0 || defined(__DOXYGEN__)
PWMDriver PWMD1;
#endif
@ -47,7 +47,7 @@ PWMDriver PWMD1;
* @brief PWMD2 driver identifier.
* @note The driver PWMD2 allocates the timer TIMER1 when enabled.
*/
#if NRF51_PWM_USE_TIMER1 || defined(__DOXYGEN__)
#if NRF5_PWM_USE_TIMER1 || defined(__DOXYGEN__)
PWMDriver PWMD2;
#endif
@ -55,7 +55,7 @@ PWMDriver PWMD2;
* @brief PWMD3 driver identifier.
* @note The driver PWMD3 allocates the timer TIMER2 when enabled.
*/
#if NRF51_PWM_USE_TIMER2 || defined(__DOXYGEN__)
#if NRF5_PWM_USE_TIMER2 || defined(__DOXYGEN__)
PWMDriver PWMD3;
#endif
@ -95,7 +95,7 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if NRF51_PWM_USE_TIMER0
#if NRF5_PWM_USE_TIMER0
/**
* @brief TIMER0 interrupt handler.
*
@ -106,9 +106,9 @@ OSAL_IRQ_HANDLER(Vector60) {
pwm_lld_serve_interrupt(&PWMD1);
OSAL_IRQ_EPILOGUE();
}
#endif /* NRF51_PWM_USE_TIMER0 */
#endif /* NRF5_PWM_USE_TIMER0 */
#if NRF51_PWM_USE_TIMER1
#if NRF5_PWM_USE_TIMER1
/**
* @brief TIMER1 interrupt handler.
*
@ -119,9 +119,9 @@ OSAL_IRQ_HANDLER(Vector64) {
pwm_lld_serve_interrupt(&PWMD2);
OSAL_IRQ_EPILOGUE();
}
#endif /* NRF51_PWM_USE_TIMER1 */
#endif /* NRF5_PWM_USE_TIMER1 */
#if NRF51_PWM_USE_TIMER2
#if NRF5_PWM_USE_TIMER2
/**
* @brief TIMER2 interrupt handler.
*
@ -132,7 +132,7 @@ OSAL_IRQ_HANDLER(Vector68) {
pwm_lld_serve_interrupt(&PWMD3);
OSAL_IRQ_EPILOGUE();
}
#endif /* NRF51_PWM_USE_TIMER2 */
#endif /* NRF5_PWM_USE_TIMER2 */
/*===========================================================================*/
/* Driver exported functions. */
@ -145,19 +145,19 @@ OSAL_IRQ_HANDLER(Vector68) {
*/
void pwm_lld_init(void) {
#if NRF51_PWM_USE_TIMER0
#if NRF5_PWM_USE_TIMER0
pwmObjectInit(&PWMD1);
PWMD1.channels = PWM_CHANNELS;
PWMD1.timer = NRF_TIMER0;
#endif
#if NRF51_PWM_USE_TIMER1
#if NRF5_PWM_USE_TIMER1
pwmObjectInit(&PWMD2);
PWMD2.channels = PWM_CHANNELS;
PWMD2.timer = NRF_TIMER1;
#endif
#if NRF51_PWM_USE_TIMER2
#if NRF5_PWM_USE_TIMER2
pwmObjectInit(&PWMD3);
PWMD3.channels = PWM_CHANNELS;
PWMD3.timer = NRF_TIMER2;
@ -175,7 +175,7 @@ void pwm_lld_init(void) {
*/
void pwm_lld_start(PWMDriver *pwmp) {
// Prescaler value calculation: ftimer = 16MHz / 2^PRESCALER
uint16_t psc_ratio = NRF51_HFCLK_FREQUENCY / pwmp->config->frequency;
uint16_t psc_ratio = NRF5_HFCLK_FREQUENCY / pwmp->config->frequency;
// Prescaler ratio must be between 1 and 512, and a power of two.
osalDbgAssert(psc_ratio <= 512 && !(psc_ratio & (psc_ratio - 1)),
"invalid frequency");
@ -215,21 +215,21 @@ void pwm_lld_start(PWMDriver *pwmp) {
// Enable interrupt
#if NRF51_PWM_USE_TIMER0
#if NRF5_PWM_USE_TIMER0
if (&PWMD1 == pwmp) {
nvicEnableVector(TIMER0_IRQn, NRF51_PWM_TIMER0_PRIORITY);
nvicEnableVector(TIMER0_IRQn, NRF5_PWM_TIMER0_PRIORITY);
}
#endif
#if NRF51_PWM_USE_TIMER1
#if NRF5_PWM_USE_TIMER1
if (&PWMD2 == pwmp) {
nvicEnableVector(TIMER1_IRQn, NRF51_PWM_TIMER1_PRIORITY);
nvicEnableVector(TIMER1_IRQn, NRF5_PWM_TIMER1_PRIORITY);
}
#endif
#if NRF51_PWM_USE_TIMER2
#if NRF5_PWM_USE_TIMER2
if (&PWMD3 == pwmp) {
nvicEnableVector(TIMER2_IRQn, NRF51_PWM_TIMER2_PRIORITY);
nvicEnableVector(TIMER2_IRQn, NRF5_PWM_TIMER2_PRIORITY);
}
#endif
@ -247,19 +247,19 @@ void pwm_lld_start(PWMDriver *pwmp) {
void pwm_lld_stop(PWMDriver *pwmp) {
pwmp->timer->TASKS_STOP = 1;
#if NRF51_PWM_USE_TIMER0
#if NRF5_PWM_USE_TIMER0
if (&PWMD1 == pwmp) {
nvicDisableVector(TIMER0_IRQn);
}
#endif
#if NRF51_PWM_USE_TIMER1
#if NRF5_PWM_USE_TIMER1
if (&PWMD2 == pwmp) {
nvicDisableVector(TIMER1_IRQn);
}
#endif
#if NRF51_PWM_USE_TIMER2
#if NRF5_PWM_USE_TIMER2
if (&PWMD3 == pwmp) {
nvicDisableVector(TIMER2_IRQn);
}
@ -282,7 +282,7 @@ void pwm_lld_stop(PWMDriver *pwmp) {
void pwm_lld_enable_channel(PWMDriver *pwmp,
pwmchannel_t channel,
pwmcnt_t width) {
#if NRF51_PWM_USE_GPIOTE_PPI
#if NRF5_PWM_USE_GPIOTE_PPI
const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];
uint32_t outinit;
@ -340,7 +340,7 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
*/
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
pwmp->timer->CC[channel] = 0;
#if NRF51_PWM_USE_GPIOTE_PPI
#if NRF5_PWM_USE_GPIOTE_PPI
const PWMChannelConfig *cfg_channel = &pwmp->config->channels[channel];
switch(cfg_channel->mode & PWM_OUTPUT_MASK) {
case PWM_OUTPUT_ACTIVE_LOW:

54
os/hal/ports/NRF5/NRF51822/hal_pwm_lld.h
View File

@ -60,50 +60,50 @@
/**
* @brief TIMER0 as driver implementation
*/
#if !defined(NRF51_PWM_USE_TIMER0)
#define NRF51_PWM_USE_TIMER0 FALSE
#if !defined(NRF5_PWM_USE_TIMER0)
#define NRF5_PWM_USE_TIMER0 FALSE
#endif
/**
* @brief TIMER1 as driver implementation
*/
#if !defined(NRF51_PWM_USE_TIMER1)
#define NRF51_PWM_USE_TIMER1 FALSE
#if !defined(NRF5_PWM_USE_TIMER1)
#define NRF5_PWM_USE_TIMER1 FALSE
#endif
/**
* @brief TIMER2 as driver implementation
*/
#if !defined(NRF51_PWM_USE_TIMER2)
#define NRF51_PWM_USE_TIMER2 FALSE
#if !defined(NRF5_PWM_USE_TIMER2)
#define NRF5_PWM_USE_TIMER2 FALSE
#endif
/**
* @brief TIMER0 interrupt priority level setting.
*/
#if !defined(NRF51_PWM_TIMER0_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_PWM_TIMER0_PRIORITY 3
#if !defined(NRF5_PWM_TIMER0_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_PWM_TIMER0_PRIORITY 3
#endif
/**
* @brief TIMER1 interrupt priority level setting.
*/
#if !defined(NRF51_PWM_TIMER1_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_PWM_TIMER1_PRIORITY 3
#if !defined(NRF5_PWM_TIMER1_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_PWM_TIMER1_PRIORITY 3
#endif
/**
* @brief TIMER2 interrupt priority level setting.
*/
#if !defined(NRF51_PWM_TIMER2_PRIORITY) || defined(__DOXYGEN__)
#define NRF51_PWM_TIMER2_PRIORITY 3
#if !defined(NRF5_PWM_TIMER2_PRIORITY) || defined(__DOXYGEN__)
#define NRF5_PWM_TIMER2_PRIORITY 3
#endif
/**
* @brief Allow driver to use GPIOTE/PPI to control PAL line
*/
#if !defined(NRF51_PWM_USE_GPIOTE_PPI)
#define NRF51_PWM_USE_GPIOTE_PPI FALSE
#if !defined(NRF5_PWM_USE_GPIOTE_PPI)
#define NRF5_PWM_USE_GPIOTE_PPI FALSE
#endif
/** @} */
@ -112,26 +112,26 @@
/* Configuration checks. */
/*===========================================================================*/
#if !NRF51_PWM_USE_TIMER0 && !NRF51_PWM_USE_TIMER1 && !NRF51_PWM_USE_TIMER2
#if !NRF5_PWM_USE_TIMER0 && !NRF5_PWM_USE_TIMER1 && !NRF5_PWM_USE_TIMER2
#error "PWM driver activated but no TIMER peripheral assigned"
#endif
#if (NRF51_ST_USE_TIMER0 == TRUE) && (NRF51_PWM_USE_TIMER0 == TRUE)
#if (NRF5_ST_USE_TIMER0 == TRUE) && (NRF5_PWM_USE_TIMER0 == TRUE)
#error "TIMER0 used for ST and PWM"
#endif
#if NRF51_PWM_USE_TIMER0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER0_PRIORITY)
#if NRF5_PWM_USE_TIMER0 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_PWM_TIMER0_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER0"
#endif
#if NRF51_PWM_USE_TIMER1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER1_PRIORITY)
#if NRF5_PWM_USE_TIMER1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_PWM_TIMER1_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER1"
#endif
#if NRF51_PWM_USE_TIMER2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF51_PWM_TIMER2_PRIORITY)
#if NRF5_PWM_USE_TIMER2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(NRF5_PWM_TIMER2_PRIORITY)
#error "Invalid IRQ priority assigned to TIMER2"
#endif
@ -180,13 +180,13 @@ typedef struct {
/**
* @brief PAL line to toggle.
* @note Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.
* @note When NRF51_PWM_USE_GPIOTE_PPI is used and channel enabled,
* @note When NRF5_PWM_USE_GPIOTE_PPI is used and channel enabled,
* it wont be possible to access this PAL line using the PAL
* driver.
*/
ioline_t ioline;
#if NRF51_PWM_USE_GPIOTE_PPI || defined(__DOXYGEN__)
#if NRF5_PWM_USE_GPIOTE_PPI || defined(__DOXYGEN__)
/**
* @brief Unique GPIOTE channel to use. (1 channel)
* @note Only used if mode is PWM_OUTPUT_HIGH or PWM_OUTPUT_LOW.
@ -296,13 +296,13 @@ struct PWMDriver {
/* External declarations. */
/*===========================================================================*/
#if NRF51_PWM_USE_TIMER0 || defined(__DOXYGEN__)
#if NRF5_PWM_USE_TIMER0 || defined(__DOXYGEN__)
extern PWMDriver PWMD1;
#endif
#if NRF51_PWM_USE_TIMER1 || defined(__DOXYGEN__)
#if NRF5_PWM_USE_TIMER1 || defined(__DOXYGEN__)
extern PWMDriver PWMD2;
#endif
#if NRF51_PWM_USE_TIMER2 || defined(__DOXYGEN__)
#if NRF5_PWM_USE_TIMER2 || defined(__DOXYGEN__)
extern PWMDriver PWMD3;
#endif

6
os/hal/ports/NRF5/NRF51822/nrf51_delay.h → os/hal/ports/NRF5/NRF51822/nrf_delay.h
View File

@ -15,8 +15,8 @@
*/
/**
* @file NRF51822/nrf51_delay.h
* @brief NRF51822 Delay routines
* @file NRF5/NRF51822/nrf_delay.h
* @brief NRF5 Delay routines
*
* @{
*/
@ -27,7 +27,7 @@
inline static void nrf_delay_us(uint32_t volatile number_of_us) __attribute__((always_inline));
inline static void nrf_delay_us(uint32_t volatile number_of_us)
{
register uint32_t delay asm ("r0") = number_of_us;
register uint32_t delay __asm ("r0") = number_of_us;
__asm volatile (
".syntax unified\n"
"1:\n"

39
os/hal/ports/NRF5/NRF51822/platform.mk
View File

@ -4,62 +4,63 @@ HALCONF := $(strip $(shell cat halconf.h halconf_community.h 2>/dev/null | egrep
# List of all the NRF51x platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_st_lld.c
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_st_lld.c
ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_pal_lld.c
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_pal_lld.c
endif
ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_serial_lld.c
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_serial_lld.c
endif
ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_spi_lld.c
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c
endif
ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c
endif
ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_i2c_lld.c
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c
endif
ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c
endif
ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_gpt_lld.c
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c
endif
ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_wdg_lld.c
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c
endif
ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_rng_lld.c
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_rng_lld.c
endif
ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c
endif
ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_qei_lld.c
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_qei_lld.c
endif
else
PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_pal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_serial_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_st_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_spi_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_pal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_serial_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_st_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_i2c_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_gpt_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_wdg_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_rng_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_rng_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_qei_lld.c
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_qei_lld.c
endif
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822

80
os/hal/ports/NRF5/NRF52832/hal_lld.c Normal file
View File

@ -0,0 +1,80 @@
/*
Copyright (C) 2016 Stephane D'Alu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file NRF5/NRF52832/hal_lld.c
* @brief NRF52832 HAL Driver subsystem low level driver source.
*
* @addtogroup HAL
* @{
*/
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void)
{
/* High frequency clock initialisation
*/
NRF_CLOCK->TASKS_HFCLKSTOP = 1;
#if !defined(NRF5_XTAL_VALUE) && (NRF5_XTAL_VALUE != 32000000)
#error "A 32Mhz crystal is mandatory on nRF52 boards."
#endif
/* Low frequency clock initialisation
* Clock is only started if st driver requires it
*/
NRF_CLOCK->TASKS_LFCLKSTOP = 1;
NRF_CLOCK->LFCLKSRC = NRF5_LFCLK_SOURCE;
#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) && \
(NRF5_SYSTEM_TICKS == NRF5_SYSTEM_TICKS_AS_RTC)
NRF_CLOCK->TASKS_LFCLKSTART = 1;
#endif
}
/**
* @}
*/

110
os/hal/ports/NRF5/NRF52832/hal_lld.h Normal file
View File

@ -0,0 +1,110 @@
/*
Copyright (C) 2016 Stephane D'Alu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file NRF5/NRF52832/hal_lld.h
* @brief NRF52832 HAL subsystem low level driver header.
*
* @addtogroup HAL
* @{
*/
#ifndef HAL_LLD_H
#define HAL_LLD_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name Platform identification
* @{
*/
#define PLATFORM_NAME "Nordic Semiconductor nRF52832"
/**
* @name Chip series
*/
#define NRF_SERIES 52
/**
* @brief Frequency value for the Low Frequency Clock
*/
#define NRF5_LFCLK_FREQUENCY 32768
/**
* @brief Frequency value for the High Frequency Clock
*/
#define NRF5_HFCLK_FREQUENCY 64000000
/**
* @}
*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @brief Select source of Low Frequency Clock (LFCLK)
* @details Possible values for source are:
* 0 : RC oscillator
* 1 : External cristal
* 2 : Synthetized clock from High Frequency Clock (HFCLK)
* When cristal is not available it's preferable to use the
* internal RC oscillator that synthezing the clock.
*/
#if !defined(NRF5_LFCLK_SOURCE) || defined(__DOXYGEN__)
#define NRF5_LFCLK_SOURCE 0
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if (NRF5_LFCLK_SOURCE < 0) || (NRF5_LFCLK_SOURCE > 2)
#error "Possible value for NRF5_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#include "nvic.h"
#ifdef __cplusplus
extern "C" {
#endif
void hal_lld_init(void);
#ifdef __cplusplus
}
#endif
#endif /* HAL_LLD_H */
/**
* @}
*/

2126
os/hal/ports/NRF5/NRF52832/nrf52.h Normal file
View File

File diff suppressed because it is too large Load Diff

14861
os/hal/ports/NRF5/NRF52832/nrf52_bitfields.h Normal file
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File diff suppressed because it is too large Load Diff

97
os/hal/ports/NRF5/NRF52832/nrf_delay.h Normal file
View File

@ -0,0 +1,97 @@
/*
Copyright (C) 2015 Stephen Caudle
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file NRF5/NRF52832/nrf_delay.h
* @brief NRF5 Delay routines
*
* @{
*/
#ifndef _NRF_DELAY_H
#define _NRF_DELAY_H
inline static void nrf_delay_us(uint32_t volatile number_of_us) __attribute__((always_inline));
inline static void nrf_delay_us(uint32_t volatile number_of_us)
{
register uint32_t delay __asm ("r0") = number_of_us;
__asm volatile (
".syntax unified\n"
"1:\n"
" SUBS %0, %0, #1\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" NOP\n"
" BNE 1b\n"
".syntax divided\n"
: "+r" (delay));
}
#endif //__NRF_DELAY_H

52
os/hal/ports/NRF5/NRF52832/platform.mk Normal file
View File

@ -0,0 +1,52 @@
ifeq ($(USE_SMART_BUILD),yes)
HALCONF := $(strip $(shell cat halconf.h halconf_community.h 2>/dev/null | egrep -e "define"))
# List of all the NRF51x platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF52832/hal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_st_lld.c
ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_pal_lld.c
endif
ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_serial_lld.c
endif
ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c
endif
ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c
endif
ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c
endif
ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c
endif
ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_rng_lld.c
endif
ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),)
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_qei_lld.c
endif
else
PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF52832/hal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_pal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_serial_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_spi_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_i2c_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_st_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_gpt_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_wdg_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_rng_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD/hal_qei_lld.c
endif
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/LLD \
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF52832

7
os/hal/ports/NRF5/NRF52832/todo.txt Normal file
View File

@ -0,0 +1,7 @@
* add extra RTC, TIMER
* assert size constraints on TIMER
* clarify write-buffer for events handling
https://devzone.nordicsemi.com/question/86564/nrf52-write-buffer/
* implement pin-reset, swo trace, trace pin configuration
* implement errata (see system_nrf52.c)
* check GPIO DETECTMODE and LATCH

4
os/various/jlink.mk
View File

@ -27,6 +27,10 @@ jlink-reset:
printf "r\nexit\n" > $(BUILDDIR)/reset.jlink
$(JLINK) $(JLINK_COMMON_OPTS) $(BUILDDIR)/reset.jlink
jlink-pin-reset:
printf "$(JLINK_PIN_RESET)\nexit\n" > $(BUILDDIR)/pin-reset.jlink
$(JLINK) $(JLINK_COMMON_OPTS) $(BUILDDIR)/pin-reset.jlink
jlink-debug-server:
$(JLINK_GDB_SERVER) $(JLINK_COMMON_OPTS) -port $(JLINK_GDB_PORT)

2
testhal/NRF51/NRF51822/ADC/mcuconf.h
View File

@ -20,6 +20,6 @@
/*
* NRF51 driver system settings.
*/
#define NRF51_ADC_USE_ADC1 TRUE
#define NRF5_ADC_USE_ADC1 TRUE
#endif /* _MCUCONF_H_ */

4
testhal/NRF51/NRF51822/GPT/mcuconf.h
View File

@ -20,7 +20,7 @@
/*
* NRF51 driver system settings.
*/
#define NRF51_GPT_USE_TIMER1 TRUE
#define NRF51_GPT_USE_TIMER2 TRUE
#define NRF5_GPT_USE_TIMER1 TRUE
#define NRF5_GPT_USE_TIMER2 TRUE
#endif /* _MCUCONF_H_ */

2
testhal/NRF51/NRF51822/I2C/mcuconf.h
View File

@ -20,6 +20,6 @@
/*
* HAL driver system settings.
*/
#define NRF51_I2C_USE_I2C0 TRUE
#define NRF5_I2C_USE_I2C0 TRUE
#endif /* _MCUCONF_H_ */

12
testhal/NRF51/NRF51822/PWM/mcuconf.h
View File

@ -20,11 +20,11 @@
/*
* HAL driver system settings.
*/
#define NRF51_SERIAL_USE_UART0 TRUE
#define NRF51_ST_USE_RTC0 TRUE
#define NRF51_ST_USE_RTC1 FALSE
#define NRF51_ST_USE_TIMER0 FALSE
#define NRF51_PWM_USE_TIMER0 TRUE
#define NRF51_PWM_USE_GPIOTE_PPI TRUE
#define NRF5_SERIAL_USE_UART0 TRUE
#define NRF5_ST_USE_RTC0 TRUE
#define NRF5_ST_USE_RTC1 FALSE
#define NRF5_ST_USE_TIMER0 FALSE
#define NRF5_PWM_USE_TIMER0 TRUE
#define NRF5_PWM_USE_GPIOTE_PPI TRUE
#endif /* _MCUCONF_H_ */

4
testhal/NRF51/NRF51822/RNG/mcuconf.h
View File

@ -17,8 +17,8 @@
#ifndef _MCUCONF_H_
#define _MCUCONF_H_
#define NRF51_RNG_USE_RNG1 TRUE
#define NRF51_SERIAL_USE_UART0 TRUE
#define NRF5_RNG_USE_RNG0 TRUE
#define NRF5_SERIAL_USE_UART0 TRUE
#endif /* _MCUCONF_H_ */

2
testhal/NRF51/NRF51822/SPI/mcuconf.h
View File

@ -20,6 +20,6 @@
/*
* HAL driver system settings.
*/
#define NRF51_SPI_USE_SPI0 TRUE
#define NRF5_SPI_USE_SPI0 TRUE
#endif /* _MCUCONF_H_ */

8
testhal/NRF51/NRF51822/WDG/main.c
View File

@ -40,10 +40,10 @@ int main(void) {
palSetPad(IOPORT1, LED1);
WDGConfig WDG_config = {
.flags.pause_on_sleep = 0,
.flags.pause_on_halt = 0,
.timeout_ms = 5000,
.callback = timeout_callback
.pause_on_sleep = 0,
.pause_on_halt = 0,
.timeout_ms = 5000,
.callback = timeout_callback
};
wdgStart(&WDGD1, &WDG_config);