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fix a couple of forgotten SET calls

This commit is contained in:
Michael Stapelberg 2020-06-03 22:02:29 +02:00
parent 4ee0b8fa26
commit 571691aeab
2 changed files with 14 additions and 14 deletions
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12
os/common/ext/CMSIS/KINETIS/MK66F18.h
View File

@ -11592,7 +11592,7 @@ typedef struct {
#define MCG_S_CLKST_SHIFT (2U)
#define MCG_S_CLKST_SET(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
#define MCG_S_CLKST MCG_S_CLKST_MASK
#define MCG_S_CLKST_PLL MCG_S_CLKST(3) /*!< Output of the PLL is selected */
#define MCG_S_CLKST_PLL MCG_S_CLKST_SET(3) /*!< Output of the PLL is selected */
#define MCG_S_IREFST_MASK (0x10U)
#define MCG_S_IREFST_SHIFT (4U)
#define MCG_S_IREFST_SET(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
@ -11717,28 +11717,28 @@ typedef struct {
#define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK)
#define MCG_C5_PLLCLKEN0_SHIFT (MCG_C5_PLLCLKEN_SHIFT)
#define MCG_C5_PLLCLKEN0_WIDTH (MCG_C5_PLLCLKEN_WIDTH)
#define MCG_C5_PLLCLKEN0_SET(x) (MCG_C5_PLLCLKEN(x))
#define MCG_C5_PLLCLKEN0_SET(x) (MCG_C5_PLLCLKEN_SET(x))
#define MCG_C5_PLLCLKEN0 MCG_C5_PLLCLKEN0_MASK
/* MCG C5[PLLSTEN0] backward compatibility */
#define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK)
#define MCG_C5_PLLSTEN0_SHIFT (MCG_C5_PLLSTEN_SHIFT)
#define MCG_C5_PLLSTEN0_WIDTH (MCG_C5_PLLSTEN_WIDTH)
#define MCG_C5_PLLSTEN0_SET(x) (MCG_C5_PLLSTEN(x))
#define MCG_C5_PLLSTEN0_SET(x) (MCG_C5_PLLSTEN_SET(x))
#define MCG_C5_PLLSTEN0 MCG_C5_PLLSTEN0_MASK
/* MCG C5[PRDIV0] backward compatibility */
#define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK)
#define MCG_C5_PRDIV0_SHIFT (MCG_C5_PRDIV_SHIFT)
#define MCG_C5_PRDIV0_WIDTH (MCG_C5_PRDIV_WIDTH)
#define MCG_C5_PRDIV0_SET(x) (MCG_C5_PRDIV(x))
#define MCG_C5_PRDIV0_SET(x) (MCG_C5_PRDIV_SET(x))
#define MCG_C5_PRDIV0 MCG_C5_PRDIV0_MASK
/* MCG C6[VDIV0] backward compatibility */
#define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK)
#define MCG_C6_VDIV0_SHIFT (MCG_C6_VDIV_SHIFT)
#define MCG_C6_VDIV0_WIDTH (MCG_C6_VDIV_WIDTH)
#define MCG_C6_VDIV0_SET(x) (MCG_C6_VDIV(x))
#define MCG_C6_VDIV0_SET(x) (MCG_C6_VDIV_SET(x))
#define MCG_C6_VDIV0 MCG_C6_VDIV0_MASK
@ -20975,7 +20975,7 @@ typedef struct {
#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
#define MCG_C2_RANGE0_SET(x) MCG_C2_RANGE(x)
#define MCG_C2_RANGE0_SET(x) MCG_C2_RANGE_SET(x)
#define MCG_C2_RANGE0 MCG_C2_RANGE0_MASK
#define PMC_REGSC_BGBDS_MASK This_symbol_has_been_deprecated
#define PMC_REGSC_BGBDS_SHIFT This_symbol_has_been_deprecated

16
os/hal/ports/KINETIS/MK66F18/hal_lld.c
View File

@ -157,9 +157,9 @@ void MK66F18_clock_init(void) {
*/
/* Enable OSC, low power mode */
if (KINETIS_XTAL_FREQUENCY > 8000000UL)
MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(2);
MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0_SET(2);
else
MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(1);
MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0_SET(1);
frdiv = 7;
ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
@ -171,7 +171,7 @@ void MK66F18_clock_init(void) {
}
/* Switch to crystal as clock source, FLL input of 31.25 KHz */
MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(frdiv);
MCG->C1 = MCG_C1_CLKS_SET(2) | MCG_C1_FRDIV_SET(frdiv);
/* Wait for crystal oscillator to begin */
while (!(MCG->S & MCG_S_OSCINIT0));
@ -180,7 +180,7 @@ void MK66F18_clock_init(void) {
while (MCG->S & MCG_S_IREFST);
/* Wait for the MCGOUTCLK to use the oscillator */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_SET(2));
/*
* Now in FBE mode
@ -190,7 +190,7 @@ void MK66F18_clock_init(void) {
* Config PLL input for 2 MHz
* TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz
*/
MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
MCG->C5 = MCG_C5_PRDIV0_SET((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
/*
* Config PLL output to match KINETIS_SYSCLK_FREQUENCY
@ -201,13 +201,13 @@ void MK66F18_clock_init(void) {
if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY))
{
/* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0_SET(i-24);
break;
}
}
if(i>=56) /* Config PLL for 96 MHz output as default setting */
MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0_SET(0);
/* Wait for PLL to start using crystal as its input, and to lock */
while ((MCG->S & (MCG_S_PLLST|MCG_S_LOCK0))!=(MCG_S_PLLST|MCG_S_LOCK0));
@ -225,7 +225,7 @@ void MK66F18_clock_init(void) {
SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL;
/* Switch to PLL as clock source */
MCG->C1 = MCG_C1_CLKS(0);
MCG->C1 = MCG_C1_CLKS_SET(0);
/* Wait for PLL clock to be used */
while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);