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Merge branch 'tm4c129x_ethernet'

This commit is contained in:
marcoveeneman 2015-02-16 21:53:32 +01:00
parent 4094380795 7b73ccd1d0
commit 5dab4ce8c2
19 changed files with 5175 additions and 87 deletions
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63
demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/.cproject Normal file
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demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/.project Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>RT-TM4C1294-LAUNCHPAD-LWIP</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
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<linkedResources>
<link>
<name>board</name>
<type>2</type>
<locationURI>CHIBIOS3/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD</locationURI>
</link>
<link>
<name>community_os</name>
<type>2</type>
<locationURI>CHIBIOS3/community</locationURI>
</link>
<link>
<name>os</name>
<type>2</type>
<locationURI>CHIBIOS3/os</locationURI>
</link>
<link>
<name>test</name>
<type>2</type>
<locationURI>CHIBIOS3/test</locationURI>
</link>
</linkedResources>
<variableList>
<variable>
<name>CHIBIOS3</name>
<value>file:/C:/ChibiStudio/chibios3</value>
</variable>
</variableList>
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202
demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile Normal file
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##############################################################################
# Build global options
# NOTE: Can be overridden externally.
#
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 -lm
endif
# C specific options here (added to USE_OPT).
ifeq ($(USE_COPT),)
USE_COPT =
endif
# C++ specific options here (added to USE_OPT).
ifeq ($(USE_CPPOPT),)
USE_CPPOPT = -fno-rtti
endif
# Enable this if you want the linker to remove unused code and data
ifeq ($(USE_LINK_GC),)
USE_LINK_GC = yes
endif
# Enable this if you want link time optimizations (LTO)
ifeq ($(USE_LTO),)
USE_LTO = yes
endif
# If enabled, this option allows to compile the application in THUMB mode.
ifeq ($(USE_THUMB),)
USE_THUMB = yes
endif
# Enable this if you want to see the full log while compiling.
ifeq ($(USE_VERBOSE_COMPILE),)
USE_VERBOSE_COMPILE = no
endif
#
# Build global options
##############################################################################
##############################################################################
# Architecture or project specific options
#
# Stack size to be allocated to the Cortex-M process stack. This stack is
# the stack used by the main() thread.
ifeq ($(USE_PROCESS_STACKSIZE),)
USE_PROCESS_STACKSIZE = 0x400
endif
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
# stack is used for processing interrupts and exceptions.
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
USE_EXCEPTIONS_STACKSIZE = 0x400
endif
# Enables the use of FPU on Cortex-M4.
ifeq ($(USE_FPU),)
USE_FPU = no
endif
#
# Architecture or project specific options
##############################################################################
##############################################################################
# Project, sources and paths
#
# Define project name here
PROJECT = ch
# Imported source files and paths
CHIBIOS = ../../../..
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk
include $(CHIBIOS)/community/os/hal/ports/TIVA/TM4C129x/platform.mk
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/community/os/rt/ports/ARMCMx/compilers/GCC/mk/port_tm4c129x.mk
include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/TM4C129xNC.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(PORTSRC) \
$(KERNSRC) \
$(TESTSRC) \
$(HALSRC) \
$(OSALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
$(LWSRC) \
$(CHIBIOS)/os/various/evtimer.c \
main.c \
web/web.c \
$(CHIBIOS)/os/various/chprintf.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC =
# C sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACSRC =
# C++ sources to be compiled in ARM mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
ACPPSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCSRC =
# C sources to be compiled in THUMB mode regardless of the global setting.
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
# option that results in lower performance and larger code size.
TCPPSRC =
# List ASM source files here
ASMSRC = $(PORTASM)
INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
$(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \
$(CHIBIOS)/os/various
#
# Project, sources and paths
##############################################################################
##############################################################################
# Compiler settings
#
MCU = cortex-m4
#TRGT = arm-elf-
TRGT = arm-none-eabi-
CC = $(TRGT)gcc
CPPC = $(TRGT)g++
# Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
OD = $(TRGT)objdump
SZ = $(TRGT)size
HEX = $(CP) -O ihex
BIN = $(CP) -O binary
# ARM-specific options here
AOPT =
# THUMB-specific options here
TOPT = -mthumb -DTHUMB
# Define C warning options here
CWARN = -Wall -Wextra -Wstrict-prototypes
# Define C++ warning options here
CPPWARN = -Wall -Wextra
#
# Compiler settings
##############################################################################
##############################################################################
# Start of user section
#
# List all user C define here, like -D_DEBUG=1
UDEFS = -DLWIP_DEBUG=0
# Define ASM defines here
UADEFS =
# List all user directories here
UINCDIR =
# List the user directory to look for the libraries here
ULIBDIR =
# List all user libraries here
ULIBS =
#
# End of user defines
##############################################################################
RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
include $(RULESPATH)/rules.mk

468
demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/chconf.h Normal file
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#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name System timers settings
* @{
*/
/*===========================================================================*/
/**
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
*/
#define CH_CFG_ST_RESOLUTION 32
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#define CH_CFG_ST_FREQUENCY 10000
/**
* @brief Time delta constant for the tick-less mode.
* @note If this value is zero then the system uses the classic
* periodic tick. This value represents the minimum number
* of ticks that is safe to specify in a timeout directive.
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#define CH_CFG_ST_TIMEDELTA 0
/**
* @brief Realtime Counter frequency.
* @details Frequency of the system counter used for realtime delays and
* measurements.
*/
#define CH_CFG_RTC_FREQUENCY 80000000
/** @} */
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
* @note The round robin preemption is not supported in tickless mode and
* must be set to zero in that case.
*/
#define CH_CFG_TIME_QUANTUM 0
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
#define CH_CFG_MEMCORE_SIZE 0
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread. The application @p main()
* function becomes the idle thread and must implement an
* infinite loop. */
#define CH_CFG_NO_IDLE_THREAD FALSE
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#define CH_CFG_OPTIMIZE_SPEED TRUE
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Time Measurement APIs.
* @details If enabled then the time measurement APIs are included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_TM TRUE
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_REGISTRY TRUE
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_WAITEXIT TRUE
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_SEMAPHORES TRUE
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_MUTEXES TRUE
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
#define CH_CFG_USE_CONDVARS TRUE
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_CONDVARS.
*/
#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_EVENTS TRUE
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_EVENTS.
*/
#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_MESSAGES TRUE
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special
* requirements.
* @note Requires @p CH_CFG_USE_MESSAGES.
*/
#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
#define CH_CFG_USE_MAILBOXES TRUE
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_QUEUES TRUE
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_MEMCORE TRUE
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
* @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#define CH_CFG_USE_HEAP TRUE
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#define CH_CFG_USE_MEMPOOLS TRUE
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
#define CH_CFG_USE_DYNAMIC TRUE
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, kernel statistics.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_STATISTICS TRUE
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_SYSTEM_STATE_CHECK TRUE
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_ENABLE_CHECKS TRUE
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_ENABLE_ASSERTS TRUE
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_ENABLE_TRACE TRUE
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#define CH_DBG_ENABLE_STACK_CHECK TRUE
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#define CH_DBG_FILL_THREADS TRUE
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p thread_t structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p FALSE.
* @note This debug option is not currently compatible with the
* tickless mode.
*/
#define CH_DBG_THREADS_PROFILING TRUE
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure.
*/
#define CH_CFG_THREAD_EXTRA_FIELDS \
/* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \
}
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() { \
}
/**
* @brief Idle thread leave hook.
* @note This hook is invoked within a critical zone, no OS functions
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() { \
}
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#define CH_CFG_IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#define CH_CFG_SYSTEM_TICK_HOOK() { \
/* System tick event code here.*/ \
}
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \
}
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

52
demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/debug/RT-TM4C1294-LAUNCHPAD-LWIP (OpenOCD, Flash and Run).launch Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
<stringAttribute key="bad_container_name" value="\TM4C129x-ETH\debu"/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="monitor reset halt&#13;&#10;monitor reset init&#13;&#10;cortex_m maskisr auto"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList&gt;&lt;content id=&quot;dmaris-VectorE0-(format)&quot; val=&quot;2&quot;/&gt;&lt;/contentList&gt;"/>
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-TM4C1294-LAUNCHPAD-LWIP"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.114656749"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/RT-TM4C1294-LAUNCHPAD-LWIP"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
</listAttribute>
</launchConfiguration>

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demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/halconf.h Normal file
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#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC TRUE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI FALSE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 64
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

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demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/lwipopts.h Normal file
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60
demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/main.c Normal file
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/*
Copyright (C) 2014 Marco Veeneman
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
#include "lwipthread.h"
#include "web/web.h"
/*
* Application entry point.
*/
int main(void)
{
/*
* System initializations.
* - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the
* RTOS is active.
*/
halInit();
chSysInit();
/*
* Start the serial driver with the default configuration.
* Used for debug output of LwIP.
*/
sdStart(&SD1, NULL);
/*
* Creates the LWIP threads (it changes priority internally).
*/
chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 2,
lwip_thread, NULL);
/*
* Creates the HTTP thread (it changes priority internally).
*/
chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1,
http_server, NULL);
while (1) {
osalThreadSleepMilliseconds(500);
}
return 0;
}

100
demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h Normal file
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/*
* TM4C129x drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 7...0 Lowest...Highest.
*/
#define TM4C129x_MCUCONF
/*
* HAL driver system settings.
*/
#define TIVA_MOSC_SINGLE_ENDED FALSE
#define TIVA_RSCLKCFG_OSCSRC RSCLKCFG_OSCSRC_MOSC
/*
* GPT driver system settings.
*/
#define TIVA_GPT_USE_GPT0 FALSE
#define TIVA_GPT_USE_GPT1 FALSE
#define TIVA_GPT_USE_GPT2 FALSE
#define TIVA_GPT_USE_GPT3 FALSE
#define TIVA_GPT_USE_GPT4 FALSE
#define TIVA_GPT_USE_GPT5 FALSE
#define TIVA_GPT_USE_GPT6 FALSE
#define TIVA_GPT_USE_GPT7 FALSE
#define TIVA_GPT_GPT0A_IRQ_PRIORITY 7
#define TIVA_GPT_GPT1A_IRQ_PRIORITY 7
#define TIVA_GPT_GPT2A_IRQ_PRIORITY 7
#define TIVA_GPT_GPT3A_IRQ_PRIORITY 7
#define TIVA_GPT_GPT4A_IRQ_PRIORITY 7
#define TIVA_GPT_GPT5A_IRQ_PRIORITY 7
#define TIVA_GPT_GPT6A_IRQ_PRIORITY 7
#define TIVA_GPT_GPT7A_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define TIVA_I2C_USE_I2C0 FALSE
#define TIVA_I2C_USE_I2C1 FALSE
#define TIVA_I2C_USE_I2C2 FALSE
#define TIVA_I2C_USE_I2C3 FALSE
#define TIVA_I2C_USE_I2C4 FALSE
#define TIVA_I2C_USE_I2C5 FALSE
#define TIVA_I2C_USE_I2C6 FALSE
#define TIVA_I2C_USE_I2C7 FALSE
#define TIVA_I2C_USE_I2C8 FALSE
#define TIVA_I2C_USE_I2C9 FALSE
#define TIVA_I2C_I2C0_IRQ_PRIORITY 4
#define TIVA_I2C_I2C1_IRQ_PRIORITY 4
#define TIVA_I2C_I2C2_IRQ_PRIORITY 4
#define TIVA_I2C_I2C3_IRQ_PRIORITY 4
#define TIVA_I2C_I2C4_IRQ_PRIORITY 4
#define TIVA_I2C_I2C5_IRQ_PRIORITY 4
#define TIVA_I2C_I2C6_IRQ_PRIORITY 4
#define TIVA_I2C_I2C7_IRQ_PRIORITY 4
#define TIVA_I2C_I2C8_IRQ_PRIORITY 4
#define TIVA_I2C_I2C9_IRQ_PRIORITY 4
/*
* PWM driver system settings.
*/
#define TIVA_PWM_USE_PWM0 FALSE
#define TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY 4
#define TIVA_PWM_PWM0_0_IRQ_PRIORITY 4
#define TIVA_PWM_PWM0_1_IRQ_PRIORITY 4
#define TIVA_PWM_PWM0_2_IRQ_PRIORITY 4
#define TIVA_PWM_PWM0_3_IRQ_PRIORITY 4
/*
* SERIAL driver system settings.
*/
#define TIVA_SERIAL_USE_UART0 TRUE
#define TIVA_SERIAL_USE_UART1 FALSE
#define TIVA_SERIAL_USE_UART2 FALSE
#define TIVA_SERIAL_USE_UART3 FALSE
#define TIVA_SERIAL_USE_UART4 FALSE
#define TIVA_SERIAL_USE_UART5 FALSE
#define TIVA_SERIAL_USE_UART6 FALSE
#define TIVA_SERIAL_USE_UART7 FALSE
#define TIVA_SERIAL_UART0_PRIORITY 5
#define TIVA_SERIAL_UART1_PRIORITY 5
#define TIVA_SERIAL_UART2_PRIORITY 5
#define TIVA_SERIAL_UART3_PRIORITY 5
#define TIVA_SERIAL_UART4_PRIORITY 5
#define TIVA_SERIAL_UART5_PRIORITY 5
#define TIVA_SERIAL_UART6_PRIORITY 5
#define TIVA_SERIAL_UART7_PRIORITY 5
/*
* ST driver system settings.
*/
#define TIVA_ST_IRQ_PRIORITY 2
#define TIVA_ST_USE_WIDE_TIMER TRUE
#define TIVA_ST_TIMER_NUMBER 5
#define TIVA_ST_TIMER_LETTER A

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demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/web/web.c Normal file
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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file is a modified version of the lwIP web server demo. The original
* author is unknown because the file didn't contain any license information.
*/
/**
* @file web.c
* @brief HTTP server wrapper thread code.
* @addtogroup WEB_THREAD
* @{
*/
#include "ch.h"
#include "lwip/opt.h"
#include "lwip/arch.h"
#include "lwip/api.h"
#include "web.h"
#if LWIP_NETCONN
static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n";
static const char http_index_html[] = "<html><head><title>Congrats!</title></head><body><h1>Welcome to our lwIP HTTP server!</h1><p>This is a small test page.</body></html>";
static void http_server_serve(struct netconn *conn) {
struct netbuf *inbuf;
char *buf;
u16_t buflen;
err_t err;
/* Read the data from the port, blocking if nothing yet there.
We assume the request (the part we care about) is in one netbuf */
err = netconn_recv(conn, &inbuf);
if (err == ERR_OK) {
netbuf_data(inbuf, (void **)&buf, &buflen);
/* Is this an HTTP GET command? (only check the first 5 chars, since
there are other formats for GET, and we're keeping it very simple )*/
if (buflen>=5 &&
buf[0]=='G' &&
buf[1]=='E' &&
buf[2]=='T' &&
buf[3]==' ' &&
buf[4]=='/' ) {
/* Send the HTML header
* subtract 1 from the size, since we dont send the \0 in the string
* NETCONN_NOCOPY: our data is const static, so no need to copy it
*/
netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY);
/* Send our HTML page */
netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY);
}
}
/* Close the connection (server closes in HTTP) */
netconn_close(conn);
/* Delete the buffer (netconn_recv gives us ownership,
so we have to make sure to deallocate the buffer) */
netbuf_delete(inbuf);
}
/**
* Stack area for the http thread.
*/
THD_WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
/**
* HTTP server thread.
*/
msg_t http_server(void *p) {
struct netconn *conn, *newconn;
err_t err;
(void)p;
/* Create a new TCP connection handle */
conn = netconn_new(NETCONN_TCP);
LWIP_ERROR("http_server: invalid conn", (conn != NULL), return MSG_RESET;);
/* Bind to port 80 (HTTP) with default IP address */
netconn_bind(conn, NULL, WEB_THREAD_PORT);
/* Put the connection into LISTEN state */
netconn_listen(conn);
/* Goes to the final priority after initialization.*/
chThdSetPriority(WEB_THREAD_PRIORITY);
while(1) {
err = netconn_accept(conn, &newconn);
if (err != ERR_OK)
continue;
http_server_serve(newconn);
netconn_delete(newconn);
}
return MSG_OK;
}
#endif /* LWIP_NETCONN */
/** @} */

51
demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/web/web.h Normal file
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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file web.h
* @brief HTTP server wrapper thread macros and structures.
* @addtogroup WEB_THREAD
* @{
*/
#ifndef _WEB_H_
#define _WEB_H_
#ifndef WEB_THREAD_STACK_SIZE
#define WEB_THREAD_STACK_SIZE 1024
#endif
#ifndef WEB_THREAD_PORT
#define WEB_THREAD_PORT 80
#endif
#ifndef WEB_THREAD_PRIORITY
#define WEB_THREAD_PRIORITY (LOWPRIO + 2)
#endif
extern THD_WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
#ifdef __cplusplus
extern "C" {
#endif
msg_t http_server(void *p);
#ifdef __cplusplus
}
#endif
#endif /* _WEB_H_ */
/** @} */

16
os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
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@ -27,6 +27,14 @@
#define BOARD_TI_TM4C1294_LAUNCHPAD
#define BOARD_NAME "Texas Instruments TM4C1294 Launchpad"
/*
* Ethernet PHY type.
*/
#define BOARD_PHY_ADDR 0 /* 0 is internal PHY */
#define BOARD_PHY_ID 0x2000A221 /* internal PHY ID */
/* uncomment when using RMII */
//#define BOARD_PHY_RMII
/*
* MCU type
*/
@ -269,18 +277,18 @@
#define VAL_GPIOE_PCTL 0x00000000
#define VAL_GPIOF_DATA 0b00000000
#define VAL_GPIOF_DIR 0b00010001
#define VAL_GPIOF_AFSEL 0b00000000
#define VAL_GPIOF_DIR 0b00010011
#define VAL_GPIOF_AFSEL 0b00010011
#define VAL_GPIOF_DR2R 0b11111111
#define VAL_GPIOF_DR4R 0b00000000
#define VAL_GPIOF_DR8R 0b00000000
#define VAL_GPIOF_ODR 0b00000000
#define VAL_GPIOF_PUR 0b00010001
#define VAL_GPIOF_PUR 0b00000000
#define VAL_GPIOF_PDR 0b00000000
#define VAL_GPIOF_SLR 0b00000000
#define VAL_GPIOF_DEN 0b11111111
#define VAL_GPIOF_AMSEL 0b0000
#define VAL_GPIOF_PCTL 0x00000000
#define VAL_GPIOF_PCTL 0x00050055
#define VAL_GPIOG_DATA 0b00000000
#define VAL_GPIOG_DIR 0b00000000

823
os/hal/ports/TIVA/LLD/mac_lld.c Normal file
View File

@ -0,0 +1,823 @@
/*
Copyright (C) 2014 Marco Veeneman
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file TIVA/mac_lld.c
* @brief MAC Driver subsystem low level driver source.
*
* @addtogroup MAC
* @{
*/
#include <string.h>
#include "hal.h"
#if HAL_USE_MAC || defined(__DOXYGEN__)
#include "mii.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define BUFFER_SIZE ((((TIVA_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4)
/* MII divider optimal value.*/
#if (TIVA_SYSCLK >= 100000000)
#define MACMIIADDR_CR (0x01 << 2)
#elif (TIVA_SYSCLK >= 60000000)
#define MACMIIADDR_CR (0x00 << 2)
#elif (TIVA_SYSCLK >= 35000000)
#define MACMIIADDR_CR (0x03 << 2)
#elif (TIVA_SYSCLK >= 20000000)
#define MACMIIADDR_CR (0x02 << 2)
#else
#error "TIVA_SYSCLK below minimum frequency for ETH operations (20MHz)"
#endif
#define EMAC_MIIADDR_MIIW 0x00000002 /* MII Write */
#define EMAC_MIIADDR_MIIB 0x00000001 /* MII Busy */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief Ethernet driver 1.
*/
MACDriver ETHD1;
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13,
0x37, 0x01, 0x10};
static tiva_eth_rx_descriptor_t rd[TIVA_MAC_RECEIVE_BUFFERS];
static tiva_eth_tx_descriptor_t td[TIVA_MAC_TRANSMIT_BUFFERS];
static uint32_t rb[TIVA_MAC_RECEIVE_BUFFERS][BUFFER_SIZE];
static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE];
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Writes a PHY register.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[in] reg register number
* @param[in] value new register value
*
* @notapi
*/
static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value)
{
ETH->MIIDATA = value;
ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB;
while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0)
;
}
/**
* @brief Writes an extended PHY register.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[in] reg register number
* @param[in] value new register value
*
* @notapi
*/
static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value)
{
mii_write(macp, TIVA_REGCTL, 0x001F);
mii_write(macp, TIVA_ADDAR, reg);
mii_write(macp, TIVA_REGCTL, 0x401F);
mii_write(macp, TIVA_ADDAR, value);
}
/**
* @brief Reads a PHY register.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[in] reg register number
*
* @return The PHY register content.
*
* @notapi
*/
static uint32_t mii_read(MACDriver *macp, uint32_t reg)
{
ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB;
while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0)
;
return ETH->MIIDATA;
}
/**
* @brief Reads an extended PHY register.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[in] reg register number
*
* @return The extended PHY register content.
*
* @notapi
*/
static uint32_t mii_read_extended(MACDriver *macp, uint32_t reg)
{
mii_write(macp, TIVA_REGCTL, 0x001F);
mii_write(macp, TIVA_ADDAR, reg);
mii_write(macp, TIVA_REGCTL, 0x401F);
return mii_read(macp, TIVA_ADDAR);
}
#if !defined(BOARD_PHY_ADDRESS)
/**
* @brief PHY address detection.
*
* @param[in] macp pointer to the @p MACDriver object
*/
static void mii_find_phy(MACDriver *macp)
{
uint32_t i;
#if TIVA_MAC_PHY_TIMEOUT > 0
rtcnt_t start = chSysGetRealtimeCounterX();
rtcnt_t timeout = start + MS2RTC(STM32_HCLK,STM32_MAC_PHY_TIMEOUT);
rtcnt_t time = start;
while (chSysIsCounterWithinX(time, start, timeout)) {
#endif
for (i = 0; i < 31; i++) {
macp->phyaddr = i << 11;
ETH->MIIDATA = (i << 6) | MACMIIADDR_CR;
if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) &&
((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
return;
}
}
#if TIVA_MAC_PHY_TIMEOUT > 0
time = chSysGetRealtimeCounterX();
}
#endif
/* Wrong or defective board.*/
osalSysHalt("MAC failure");
}
#endif
/**
* @brief MAC address setup.
*
* @param[in] p pointer to a six bytes buffer containing the MAC
* address
*/
static void mac_lld_set_address(const uint8_t *p)
{
/* MAC address configuration, only a single address comparator is used,
hash table not used.*/
ETH->ADDR0H = ((uint32_t)p[5] << 8) |
((uint32_t)p[4] << 0);
ETH->ADDR0L = ((uint32_t)p[3] << 24) |
((uint32_t)p[2] << 16) |
((uint32_t)p[1] << 8) |
((uint32_t)p[0] << 0);
ETH->ADDR1H = 0x0000FFFF;
ETH->ADDR1L = 0xFFFFFFFF;
ETH->ADDR2H = 0x0000FFFF;
ETH->ADDR2L = 0xFFFFFFFF;
ETH->ADDR3H = 0x0000FFFF;
ETH->ADDR3L = 0xFFFFFFFF;
ETH->HASHTBLH = 0;
ETH->HASHTBLL = 0;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
CH_IRQ_HANDLER(TIVA_MAC_HANDLER)
{
uint32_t dmaris;
CH_IRQ_PROLOGUE();
dmaris = ETH->DMARIS;
ETH->DMARIS = dmaris & 0x0001FFFF; /* Clear status bits.*/
if (dmaris & (1 << 6)) {
/* Data Received.*/
osalSysLockFromISR();
osalThreadDequeueAllI(&ETHD1.rdqueue, MSG_RESET);
#if MAC_USE_EVENTS
osalEventBroadcastFlagsI(&ETHD1.rdevent, 0);
#endif
osalSysUnlockFromISR();
}
if (dmaris & (1 << 0)) {
/* Data Transmitted.*/
osalSysLockFromISR();
osalThreadDequeueAllI(&ETHD1.tdqueue, MSG_RESET);
osalSysUnlockFromISR();
}
CH_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level MAC initialization.
*
* @notapi
*/
void mac_lld_init(void)
{
uint8_t i;
macObjectInit(&ETHD1);
ETHD1.link_up = false;
/* Descriptor tables are initialized in chained mode, note that the first
word is not initialized here but in mac_lld_start().*/
for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) {
rd[i].rdes1 = TIVA_RDES1_RCH | TIVA_RDES1_RBS1(TIVA_MAC_BUFFERS_SIZE);
rd[i].rdes2 = (uint32_t)rb[i];
rd[i].rdes3 = (uint32_t)&rd[(i + 1) % TIVA_MAC_RECEIVE_BUFFERS];
}
for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) {
td[i].tdes1 = 0;
td[i].tdes2 = (uint32_t)tb[i];
td[i].tdes3 = (uint32_t)&td[(i + 1) % TIVA_MAC_TRANSMIT_BUFFERS];
}
/* Enable MAC clock */
SYSCTL->RCGCEMAC = 1;
while (SYSCTL->PREMAC != 0x01)
;
/* Set PHYHOLD bit */
ETH->PC |= 1;
/* Enable PHY clock */
SYSCTL->RCGCEPHY = 1;
while (SYSCTL->PREPHY != 0x01)
;
/* Enable power to PHY */
SYSCTL->PCEPHY |= 1;
while (SYSCTL->PREPHY != 0x01)
;
#if BOARD_PHY_RMII
ETH->PC = EMAC_PHY_CONFIG | (0x04 << 28);
#else
ETH->PC = EMAC_PHY_CONFIG;
#endif
/*
* Write OHY led configuration.
* 0: link ok
* 1: tx activity
* 2: link ok
* blink rate: 20Hz
*/
mii_write_extended(&ETHD1, TIVA_LEDCFG, (0 << 8) | (2 << 4) | (0 << 0));
mii_write(&ETHD1, TIVA_LEDCR, (0 << 9));
/* Set done bit after writing EMACPC register */
mii_write(&ETHD1, TIVA_CFG1, (1 << 15) | mii_read(&ETHD1, TIVA_CFG1));
while(ETH->DMABUSMOD & 1)
;
/* Reset MAC */
ETH->DMABUSMOD |= 1;
while (ETH->DMABUSMOD & 1)
;
/* PHY address setup.*/
#if defined(BOARD_PHY_ADDRESS)
ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11;
#else
mii_find_phy(&ETHD1);
#endif
#if defined(BOARD_PHY_RESET)
/* PHY board-specific reset procedure.*/
BOARD_PHY_RESET();
#else
/* PHY soft reset procedure.*/
mii_write(&ETHD1, MII_BMCR, BMCR_RESET);
#if defined(BOARD_PHY_RESET_DELAY)
chSysPolledDelayX(BOARD_PHY_RESET_DELAY);
#endif
while (mii_read(&ETHD1, MII_BMCR) & BMCR_RESET)
;
#endif
#if TIVA_MAC_CHANGE_PHY_STATE
/* PHY in power down mode until the driver will be started.*/
mii_write(&ETHD1, MII_BMCR, mii_read(&ETHD1, MII_BMCR) | BMCR_PDOWN);
#endif
/* Disable MAC clock */
SYSCTL->RCGCEMAC = 0;
/* Disable PHY clock */
SYSCTL->RCGCEPHY = 0;
}
/**
* @brief Configures and activates the MAC peripheral.
*
* @param[in] macp pointer to the @p MACDriver object
*
* @notapi
*/
void mac_lld_start(MACDriver *macp)
{
uint8_t i;
/* Resets the state of all descriptors.*/
for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) {
rd[i].rdes0 = TIVA_RDES0_OWN;
}
macp->rxptr = (tiva_eth_rx_descriptor_t *)rd;
for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) {
td[i].tdes0 = TIVA_TDES0_TCH;
td[i].locked = 0;
}
macp->txptr = (tiva_eth_tx_descriptor_t *)td;
/* Enable MAC clock */
SYSCTL->RCGCEMAC = 1;
while (SYSCTL->PREMAC != 0x01)
;
/* Enable PHY clock */
SYSCTL->RCGCEPHY = 1;
while (!SYSCTL->PREPHY)
;
/* ISR vector enabled.*/
nvicEnableVector(TIVA_MAC_NUMBER, TIVA_MAC_IRQ_PRIORITY);
#if TIVA_MAC_CHANGE_PHY_STATE
/* PHY in power up mode.*/
mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN);
#endif
/* MAC configuration.*/
ETH->FRAMEFLTR = 0;
ETH->FLOWCTL = 0;
ETH->VLANTG = 0;
/* MAC address setup.*/
if (macp->config->mac_address == NULL)
mac_lld_set_address(default_mac_address);
else
mac_lld_set_address(macp->config->mac_address);
/* Transmitter and receiver enabled.
Note that the complete setup of the MAC is performed when the link
status is detected.*/
#if TIVA_MAC_IP_CHECKSUM_OFFLOAD
ETH->CFG = (1 << 10) | (1 << 3) | (1 << 2);
#else
ETH->CFG = (1 << 3) | (1 << 2);
#endif
/* DMA configuration:
Descriptor chains pointers.*/
ETH->RXDLADDR = (uint32_t)rd;
ETH->TXDLADDR = (uint32_t)td;
/* Enabling required interrupt sources.*/
ETH->DMARIS &= 0xFFFF;
ETH->DMAIM = (1 << 16) | (1 << 6) | (1 << 0);
/* DMA general settings.*/
ETH->DMABUSMOD = (1 << 25) | (1 << 17) | (1 << 8);
/* Transmit FIFO flush.*/
ETH->DMAOPMODE = (1 << 20);
while (ETH->DMAOPMODE & (1 << 20))
;
/* DMA final configuration and start.*/
ETH->DMAOPMODE = (1 << 26) | (1 << 25) | (1 << 21) |
(1 << 13) | (1 << 1);
}
/**
* @brief Deactivates the MAC peripheral.
*
* @param[in] macp pointer to the @p MACDriver object
*
* @notapi
*/
void mac_lld_stop(MACDriver *macp)
{
if (macp->state != MAC_STOP) {
#if TIVA_MAC_CHANGE_PHY_STATE
/* PHY in power down mode until the driver will be restarted.*/
mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN);
#endif
/* MAC and DMA stopped.*/
ETH->CFG = 0;
ETH->DMAOPMODE = 0;
ETH->DMAIM = 0;
ETH->DMARIS &= 0xFFFF;
/* MAC clocks stopped.*/
SYSCTL->RCGCEMAC = 0;
/* PHY clock stopped.*/
SYSCTL->RCGCEPHY = 0;
/* ISR vector disabled.*/
nvicDisableVector(TIVA_MAC_NUMBER);
}
}
/**
* @brief Returns a transmission descriptor.
* @details One of the available transmission descriptors is locked and
* returned.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[out] tdp pointer to a @p MACTransmitDescriptor structure
* @return The operation status.
* @retval RDY_OK the descriptor has been obtained.
* @retval RDY_TIMEOUT descriptor not available.
*
* @notapi
*/
msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
MACTransmitDescriptor *tdp)
{
tiva_eth_tx_descriptor_t *tdes;
if (!macp->link_up)
return MSG_TIMEOUT;
osalSysLock();
/* Get Current TX descriptor.*/
tdes = macp->txptr;
/* Ensure that descriptor isn't owned by the Ethernet DMA or locked by
another thread.*/
if (tdes->tdes0 & (TIVA_TDES0_OWN) || (tdes->locked)) {
osalSysUnlock();
return MSG_TIMEOUT;
}
/* Marks the current descriptor as locked.*/
tdes->locked = 1;
/* Next TX descriptor to use.*/
macp->txptr = (tiva_eth_tx_descriptor_t *)tdes->tdes3;
osalSysUnlock();
/* Set the buffer size and configuration.*/
tdp->offset = 0;
tdp->size = TIVA_MAC_BUFFERS_SIZE;
tdp->physdesc = tdes;
return MSG_OK;
}
/**
* @brief Releases a transmit descriptor and starts the transmission of the
* enqueued data as a single frame.
*
* @param[in] tdp the pointer to the @p MACTransmitDescriptor structure
*
* @notapi
*/
void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp)
{
osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN),
"attempt to release descriptor already owned by DMA");
osalSysLock();
/* Unlocks the descriptor and returns it to the DMA engine.*/
tdp->physdesc->tdes1 = tdp->offset;
tdp->physdesc->tdes0 = TIVA_TDES0_CIC(TIVA_MAC_IP_CHECKSUM_OFFLOAD) |
TIVA_TDES0_IC | TIVA_TDES0_LS | TIVA_TDES0_FS |
TIVA_TDES0_TCH | TIVA_TDES0_OWN;
tdp->physdesc->locked = 0;
/* If the DMA engine is stalled then a restart request is issued.*/
if ((ETH->DMARIS & (0x7 << 20)) == (6 << 20)) {
ETH->DMARIS = (1 << 2);
ETH->TXPOLLD = 1; /* Any value is OK.*/
}
osalSysUnlock();
}
/**
* @brief Returns a receive descriptor.
*
* @param[in] macp pointer to the @p MACDriver object
* @param[out] rdp pointer to a @p MACReceiveDescriptor structure
* @return The operation status.
* @retval RDY_OK the descriptor has been obtained.
* @retval RDY_TIMEOUT descriptor not available.
*
* @notapi
*/
msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
MACReceiveDescriptor *rdp)
{
tiva_eth_rx_descriptor_t *rdes;
osalSysLock();
/* Get Current RX descriptor.*/
rdes = macp->rxptr;
/* Iterates through received frames until a valid one is found, invalid
frames are discarded.*/
while (!(rdes->rdes0 & TIVA_RDES0_OWN)) {
if (!(rdes->rdes0 & (TIVA_RDES0_AFM | TIVA_RDES0_ES))
#if TIVA_MAC_IP_CHECKSUM_OFFLOAD
&& (rdes->rdes0 & TIVA_RDES0_FT)
&& !(rdes->rdes0 & (TIVA_RDES0_IPHCE | TIVA_RDES0_PCE))
#endif
&& (rdes->rdes0 & TIVA_RDES0_FS) && (rdes->rdes0 & TIVA_RDES0_LS)) {
/* Found a valid one.*/
rdp->offset = 0;
rdp->size = ((rdes->rdes0 & TIVA_RDES0_FL_MASK) >> 16) - 4;
rdp->physdesc = rdes;
macp->rxptr = (tiva_eth_rx_descriptor_t *)rdes->rdes3;
osalSysUnlock();
return MSG_OK;
}
/* Invalid frame found, purging.*/
rdes->rdes0 = TIVA_RDES0_OWN;
rdes = (tiva_eth_rx_descriptor_t *)rdes->rdes3;
}
/* Next descriptor to check.*/
macp->rxptr = rdes;
osalSysUnlock();
return MSG_TIMEOUT;
}
/**
* @brief Releases a receive descriptor.
* @details The descriptor and its buffer are made available for more incoming
* frames.
*
* @param[in] rdp the pointer to the @p MACReceiveDescriptor structure
*
* @notapi
*/
void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp)
{
osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN),
"attempt to release descriptor already owned by DMA");
osalSysLock();
/* Give buffer back to the Ethernet DMA.*/
rdp->physdesc->rdes0 = TIVA_RDES0_OWN;
/* If the DMA engine is stalled then a restart request is issued.*/
if ((ETH->STATUS & (0xf << 17)) == (4 << 17)) {
ETH->DMARIS = (1 << 7);
ETH->TXPOLLD = 1; /* Any value is OK.*/
}
osalSysUnlock();
}
/**
* @brief Updates and returns the link status.
*
* @param[in] macp pointer to the @p MACDriver object
* @return The link status.
* @retval TRUE if the link is active.
* @retval FALSE if the link is down.
*
* @notapi
*/
bool mac_lld_poll_link_status(MACDriver *macp)
{
uint32_t maccfg, bmsr, bmcr;
maccfg = ETH->CFG;
/* PHY CR and SR registers read.*/
(void)mii_read(macp, MII_BMSR);
bmsr = mii_read(macp, MII_BMSR);
bmcr = mii_read(macp, MII_BMCR);
/* Check on auto-negotiation mode.*/
if (bmcr & BMCR_ANENABLE) {
uint32_t lpa;
/* Auto-negotiation must be finished without faults and link established.*/
if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) !=
(BMSR_LSTATUS | BMSR_ANEGCOMPLETE))
return macp->link_up = false;
/* Auto-negotiation enabled, checks the LPA register.*/
lpa = mii_read(macp, MII_LPA);
/* Check on link speed.*/
if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
maccfg |= (1 << 14);
else
maccfg &= ~(1 << 14);
/* Check on link mode.*/
if (lpa & (LPA_10FULL | LPA_100FULL))
maccfg |= (1 << 11);
else
maccfg &= ~(1 << 11);
}
else {
/* Link must be established.*/
if (!(bmsr & BMSR_LSTATUS))
return macp->link_up = false;
/* Check on link speed.*/
if (bmcr & BMCR_SPEED100)
maccfg |= (1 << 14);
else
maccfg &= ~(1 << 14);
/* Check on link mode.*/
if (bmcr & BMCR_FULLDPLX)
maccfg |= (1 << 11);
else
maccfg &= ~(1 << 11);
}
/* Changes the mode in the MAC.*/
ETH->CFG = maccfg;
/* Returns the link status.*/
return macp->link_up = true;
}
/**
* @brief Writes to a transmit descriptor's stream.
*
* @param[in] tdp pointer to a @p MACTransmitDescriptor structure
* @param[in] buf pointer to the buffer containing the data to be
* written
* @param[in] size number of bytes to be written
* @return The number of bytes written into the descriptor's
* stream, this value can be less than the amount
* specified in the parameter @p size if the maximum
* frame size is reached.
*
* @notapi
*/
size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
uint8_t *buf,
size_t size)
{
osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN),
"attempt to write descriptor already owned by DMA");
if (size > tdp->size - tdp->offset)
size = tdp->size - tdp->offset;
if (size > 0) {
memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size);
tdp->offset += size;
}
return size;
}
/**
* @brief Reads from a receive descriptor's stream.
*
* @param[in] rdp pointer to a @p MACReceiveDescriptor structure
* @param[in] buf pointer to the buffer that will receive the read data
* @param[in] size number of bytes to be read
* @return The number of bytes read from the descriptor's
* stream, this value can be less than the amount
* specified in the parameter @p size if there are
* no more bytes to read.
*
* @notapi
*/
size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
uint8_t *buf,
size_t size)
{
osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN),
"attempt to read descriptor already owned by DMA");
if (size > rdp->size - rdp->offset)
size = rdp->size - rdp->offset;
if (size > 0) {
memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size);
rdp->offset += size;
}
return size;
}
#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__)
/**
* @brief Returns a pointer to the next transmit buffer in the descriptor
* chain.
* @note The API guarantees that enough buffers can be requested to fill
* a whole frame.
*
* @param[in] tdp pointer to a @p MACTransmitDescriptor structure
* @param[in] size size of the requested buffer. Specify the frame size
* on the first call then scale the value down subtracting
* the amount of data already copied into the previous
* buffers.
* @param[out] sizep pointer to variable receiving the buffer size, it is
* zero when the last buffer has already been returned.
* Note that a returned size lower than the amount
* requested means that more buffers must be requested
* in order to fill the frame data entirely.
* @return Pointer to the returned buffer.
* @retval NULL if the buffer chain has been entirely scanned.
*
* @notapi
*/
uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
size_t size,
size_t *sizep)
{
if (tdp->offset == 0) {
*sizep = tdp->size;
tdp->offset = size;
return (uint8_t *)tdp->physdesc->tdes2;
}
*sizep = 0;
return NULL;
}
/**
* @brief Returns a pointer to the next receive buffer in the descriptor
* chain.
* @note The API guarantees that the descriptor chain contains a whole
* frame.
*
* @param[in] rdp pointer to a @p MACReceiveDescriptor structure
* @param[out] sizep pointer to variable receiving the buffer size, it is
* zero when the last buffer has already been returned.
* @return Pointer to the returned buffer.
* @retval NULL if the buffer chain has been entirely scanned.
*
* @notapi
*/
const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
size_t *sizep)
{
if (rdp->size > 0) {
*sizep = rdp->size;
rdp->offset = rdp->size;
rdp->size = 0;
return (uint8_t *)rdp->physdesc->rdes2;
}
*sizep = 0;
return NULL;
}
#endif /* MAC_USE_ZERO_COPY */
#endif /* HAL_USE_MAC */
/** @} */

434
os/hal/ports/TIVA/LLD/mac_lld.h Normal file
View File

@ -0,0 +1,434 @@
/*
Copyright (C) 2014 Marco Veeneman
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file TIVA/mac_lld.h
* @brief MAC Driver subsystem low level driver header.
*
* @addtogroup MAC
* @{
*/
#ifndef _MAC_LLD_H_
#define _MAC_LLD_H_
#if HAL_USE_MAC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief This implementation supports the zero-copy mode API.
*/
#define MAC_SUPPORTS_ZERO_COPY TRUE
/**
* @name RDES0 constants
* @{
*/
#define TIVA_RDES0_OWN 0x80000000
#define TIVA_RDES0_AFM 0x40000000
#define TIVA_RDES0_FL_MASK 0x3FFF0000
#define TIVA_RDES0_FL(n) ((n) << 16)
#define TIVA_RDES0_ES 0x00008000
#define TIVA_RDES0_DESERR 0x00004000
#define TIVA_RDES0_SAF 0x00002000
#define TIVA_RDES0_LE 0x00001000
#define TIVA_RDES0_OE 0x00000800
#define TIVA_RDES0_VLAN 0x00000400
#define TIVA_RDES0_FS 0x00000200
#define TIVA_RDES0_LS 0x00000100
#define TIVA_RDES0_TAGF 0x00000080
#define TIVA_RDES0_LC 0x00000040
#define TIVA_RDES0_FT 0x00000020
#define TIVA_RDES0_RWT 0x00000010
#define TIVA_RDES0_RE 0x00000008
#define TIVA_RDES0_DE 0x00000004
#define TIVA_RDES0_CE 0x00000002
#define TIVA_RDES0_ESA 0x00000001
/** @} */
/**
* @name RDES1 constants
* @{
*/
#define TIVA_RDES1_DIC 0x80000000
#define TIVA_RDES1_RBS2_MASK 0x1FFF0000
#define TIVA_RDES1_RBS2(n) ((n) << 16)
#define TIVA_RDES1_RER 0x00008000
#define TIVA_RDES1_RCH 0x00004000
#define TIVA_RDES1_RBS1_MASK 0x00001FFF
#define TIVA_RDES1_RBS1(n) ((n) << 0)
/** @} */
/**
* @name TDES0 constants
* @{
*/
#define TIVA_TDES0_OWN 0x80000000
#define TIVA_TDES0_IC 0x40000000
#define TIVA_TDES0_LS 0x20000000
#define TIVA_TDES0_FS 0x10000000
#define TIVA_TDES0_DC 0x08000000
#define TIVA_TDES0_DP 0x04000000
#define TIVA_TDES0_TTSE 0x02000000
#define TIVA_TDES0_CRCR 0x01000000
#define TIVA_TDES0_CIC_MASK 0x00C00000
#define TIVA_TDES0_CIC(n) ((n) << 22)
#define TIVA_TDES0_TER 0x00200000
#define TIVA_TDES0_TCH 0x00100000
#define TIVA_TDES0_VLIC 0x000C0000
#define TIVA_TDES0_TTSS 0x00020000
#define TIVA_TDES0_IHE 0x00010000
#define TIVA_TDES0_ES 0x00008000
#define TIVA_TDES0_JT 0x00004000
#define TIVA_TDES0_FF 0x00002000
#define TIVA_TDES0_IPE 0x00001000
#define TIVA_TDES0_LC 0x00000800
#define TIVA_TDES0_NC 0x00000400
#define TIVA_TDES0_LCO 0x00000200
#define TIVA_TDES0_EC 0x00000100
#define TIVA_TDES0_VF 0x00000080
#define TIVA_TDES0_CC_MASK 0x00000078
#define TIVA_TDES0_CC(n) ((n) << 3)
#define TIVA_TDES0_ED 0x00000004
#define TIVA_TDES0_UF 0x00000002
#define TIVA_TDES0_DB 0x00000001
/** @} */
/**
* @name TDES1 constants
* @{
*/
#define TIVA_TDES1_SAIC_MASK 0xE0000000
#define TIVA_TDES1_SAIC(n) ((n) << 29)
#define TIVA_TDES1_TBS2_MASK 0x1FFF0000
#define TIVA_TDES1_TBS2(n) ((n) << 16)
#define TIVA_TDES1_TBS1_MASK 0x00001FFF
#define TIVA_TDES1_TBS1(n) ((n) << 0)
/** @} */
/**
* @name Ethernet PHY registers
*/
#define TIVA_BMCR 0x00000000 /* MR0 - Basic Mode Control */
#define TIVA_BMSR 0x00000001 /* MR1 - Basic Mode Status */
#define TIVA_ID1 0x00000002 /* MR2 - Identifier Register 1 */
#define TIVA_ID2 0x00000003 /* MR3 - Identifier Register 2 */
#define TIVA_ANA 0x00000004 /* MR4 - Auto-Negotiation Advertisement */
#define TIVA_ANLPA 0x00000005 /* MR5 - Auto-Negotiation Link Partner Ability */
#define TIVA_ANER 0x00000006 /* MR6 - Auto-Negotiation Expansion */
#define TIVA_ANNPTR 0x00000007 /* MR7 - Auto-Negotiation Next Page TX */
#define TIVA_ANLNPTR 0x00000008 /* MR8 - Auto-Negotiation Link Partner Ability Next Page */
#define TIVA_CFG1 0x00000009 /* MR9 - Configuration 1 */
#define TIVA_CFG2 0x0000000A /* MR10 - Configuration 2 */
#define TIVA_CFG3 0x0000000B /* MR11 - Configuration 3 */
#define TIVA_REGCTL 0x0000000D /* MR13 - Register Control */
#define TIVA_ADDAR 0x0000000E /* MR14 - Address or Data */
#define TIVA_STS 0x00000010 /* MR16 - Status */
#define TIVA_SCR 0x00000011 /* MR17 - Specific Control */
#define TIVA_MISR1 0x00000012 /* MR18 - MII Interrupt Status 1 */
#define TIVA_MISR2 0x00000013 /* MR19 - MII Interrupt Status 2 */
#define TIVA_FCSCR 0x00000014 /* MR20 - False Carrier Sense Counter */
#define TIVA_RXERCNT 0x00000015 /* MR21 - Receive Error Count */
#define TIVA_BISTCR 0x00000016 /* MR22 - BIST Control */
#define TIVA_LEDCR 0x00000018 /* MR24 - LED Control */
#define TIVA_CTL 0x00000019 /* MR25 - Control */
#define TIVA_10BTSC 0x0000001A /* MR26 - 10Base-T Status/Control - MR26 */
#define TIVA_BICSR1 0x0000001B /* MR27 - BIST Control and Status 1 */
#define TIVA_BICSR2 0x0000001C /* MR28 - BIST Control and Status 2 */
#define TIVA_CDCR 0x0000001E /* MR30 - Cable Diagnostic Control */
#define TIVA_RCR 0x0000001F /* MR31 - Reset Control */
#define TIVA_LEDCFG 0x00000025 /* MR37 - LED Configuration */
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief Number of available transmit buffers.
*/
#if !defined(TIVA_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
#define TIVA_MAC_TRANSMIT_BUFFERS 2
#endif
/**
* @brief Number of available receive buffers.
*/
#if !defined(TIVA_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
#define TIVA_MAC_RECEIVE_BUFFERS 4
#endif
/**
* @brief Maximum supported frame size.
*/
#if !defined(TIVA_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define TIVA_MAC_BUFFERS_SIZE 1522
#endif
/**
* @brief PHY detection timeout.
* @details Timeout, in milliseconds, for PHY address detection, if a PHY
* is not detected within the timeout then the driver halts during
* initialization. This setting applies only if the PHY address is
* not explicitly set in the board header file using
* @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a
* single search path is performed.
*/
#if !defined(TIVA_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__)
#define TIVA_MAC_PHY_TIMEOUT 0
#endif
/**
* @brief Change the PHY power state inside the driver.
*/
#if !defined(TIVA_MAC_CHANGE_PHY_STATE) || defined(__DOXYGEN__)
#define TIVA_MAC_CHANGE_PHY_STATE TRUE
#endif
/**
* @brief ETHD1 interrupt priority level setting.
*/
#if !defined(TIVA_MAC_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define TIVA_MAC_IRQ_PRIORITY 5
#endif
/**
* @brief IP checksum offload.
* @details The following modes are available:
* - 0 Function disabled.
* - 1 Only IP header checksum calculation and insertion are enabled.
* - 2 IP header checksum and payload checksum calculation and
* insertion are enabled, but pseudo-header checksum is not
* calculated in hardware.
* - 3 IP Header checksum and payload checksum calculation and
* insertion are enabled, and pseudo-header checksum is
* calculated in hardware.
* .
*/
#if !defined(TIVA_MAC_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__)
#define TIVA_MAC_IP_CHECKSUM_OFFLOAD 0
#endif
/** @} */
#ifndef EMAC_PHY_CONFIG
#define EMAC_PHY_CONFIG ((0 << 31) | \
(1 << 23) | \
(1 << 10) | \
(1 << 3) | \
(3 << 1) | \
(1 << 0))
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if (TIVA_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS
#error "TIVA_MAC_PHY_TIMEOUT requires the realtime counter service"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Type of an Tiva Ethernet receive descriptor.
*/
typedef struct
{
volatile uint32_t rdes0;
volatile uint32_t rdes1;
volatile uint32_t rdes2;
volatile uint32_t rdes3;
} tiva_eth_rx_descriptor_t;
/**
* @brief Type of an Tiva Ethernet transmit descriptor.
*/
typedef struct
{
volatile uint32_t tdes0;
volatile uint32_t tdes1;
volatile uint32_t tdes2;
volatile uint32_t tdes3;
volatile uint32_t locked;
} tiva_eth_tx_descriptor_t;
/**
* @brief Driver configuration structure.
*/
typedef struct
{
/**
* @brief MAC address.
*/
uint8_t *mac_address;
/* End of the mandatory fields.*/
} MACConfig;
/**
* @brief Structure representing a MAC driver.
*/
struct MACDriver
{
/**
* @brief Driver state.
*/
macstate_t state;
/**
* @brief Current configuration data.
*/
const MACConfig *config;
/**
* @brief Transmit semaphore.
*/
threads_queue_t tdqueue;
/**
* @brief Receive semaphore.
*/
threads_queue_t rdqueue;
#if MAC_USE_EVENTS || defined(__DOXYGEN__)
/**
* @brief Receive event.
*/
event_source_t rdevent;
#endif
/* End of the mandatory fields.*/
/**
* @brief Link status flag.
*/
bool link_up;
/**
* @brief PHY address (pre shifted).
*/
uint32_t phyaddr;
/**
* @brief Receive next frame pointer.
*/
tiva_eth_rx_descriptor_t *rxptr;
/**
* @brief Transmit next frame pointer.
*/
tiva_eth_tx_descriptor_t *txptr;
};
/**
* @brief Structure representing a transmit descriptor.
*/
typedef struct
{
/**
* @brief Current write offset.
*/
size_t offset;
/**
* @brief Available space size.
*/
size_t size;
/* End of the mandatory fields.*/
/**
* @brief Pointer to the physical descriptor.
*/
tiva_eth_tx_descriptor_t *physdesc;
} MACTransmitDescriptor;
/**
* @brief Structure representing a receive descriptor.
*/
typedef struct
{
/**
* @brief Current read offset.
*/
size_t offset;
/**
* @brief Available data size.
*/
size_t size;
/* End of the mandatory fields.*/
/**
* @brief Pointer to the physical descriptor.
*/
tiva_eth_rx_descriptor_t *physdesc;
} MACReceiveDescriptor;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
extern MACDriver ETHD1;
#ifdef __cplusplus
extern "C" {
#endif
void mac_lld_init(void);
void mac_lld_start(MACDriver *macp);
void mac_lld_stop(MACDriver *macp);
msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
MACTransmitDescriptor *tdp);
void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp);
msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
MACReceiveDescriptor *rdp);
void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
bool mac_lld_poll_link_status(MACDriver *macp);
size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
uint8_t *buf,
size_t size);
size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
uint8_t *buf,
size_t size);
#if MAC_USE_ZERO_COPY
uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp,
size_t size,
size_t *sizep);
const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp,
size_t *sizep);
#endif /* MAC_USE_ZERO_COPY */
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_MAC */
#endif /* _MAC_LLD_H_ */
/** @} */

2
os/hal/ports/TIVA/LLD/pal_lld.c
View File

@ -165,7 +165,7 @@ void gpio_init (GPIO_TypeDef *gpiop, const tiva_gpio_setup_t *config)
*/
void _pal_lld_init(const PALConfig *config)
{
SYSCTL->RCGC.GPIO = RCGCGPIO_VALUE;
SYSCTL->RCGCGPIO = RCGCGPIO_VALUE;
__NOP();
__NOP();

4
os/hal/ports/TIVA/LLD/serial_lld.c
View File

@ -507,7 +507,7 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
if (sdp->state == SD_STOP) {
#if TIVA_SERIAL_USE_UART0
if (&SD1 == sdp) {
SYSCTL->RCGC.UART |= (1 << 0);
SYSCTL->RCGCUART |= (1 << 0);
nvicEnableVector(TIVA_UART0_NUMBER, TIVA_SERIAL_UART0_PRIORITY);
}
#endif
@ -570,7 +570,7 @@ void sd_lld_stop(SerialDriver *sdp)
uart_deinit(sdp->uart);
#if TIVA_SERIAL_USE_UART0
if (&SD1 == sdp) {
SYSCTL->RCGC.UART &= ~(1 << 0); /* disable UART0 module */
SYSCTL->RCGCUART &= ~(1 << 0); /* disable UART0 module */
nvicDisableVector(TIVA_UART0_NUMBER);
return;
}

4
os/hal/ports/TIVA/TM4C129x/hal_lld.c
View File

@ -109,8 +109,8 @@ void tiva_clock_init(void)
* 6. Write the PLLFREQ0 and PLLFREQ1 registers with the values of Q, N, MINT, and MFRAC to
* the configure the desired VCO frequency setting.
*/
SYSCTL->PLLFREQ[1] = (0x04 << 0); // 5 - 1
SYSCTL->PLLFREQ[0] = (0x60 << 0) | PLLFREQ0_PLLPWR;
SYSCTL->PLLFREQ1 = (0x04 << 0); // 5 - 1
SYSCTL->PLLFREQ0 = (0x60 << 0) | PLLFREQ0_PLLPWR;
/*
* 7. Write the MEMTIM0 register to correspond to the new system clock setting.

3
os/hal/ports/TIVA/TM4C129x/platform.mk
View File

@ -3,7 +3,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
${CHIBIOS}/community/os/hal/ports/TIVA/TM4C129x/hal_lld.c \
${CHIBIOS}/community/os/hal/ports/TIVA/LLD/st_lld.c \
${CHIBIOS}/community/os/hal/ports/TIVA/LLD/pal_lld.c \
${CHIBIOS}/community/os/hal/ports/TIVA/LLD/serial_lld.c
${CHIBIOS}/community/os/hal/ports/TIVA/LLD/serial_lld.c \
${CHIBIOS}/community/os/hal/ports/TIVA/LLD/mac_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \

400
os/hal/ports/TIVA/TM4C129x/tm4c129x.h
View File

@ -534,109 +534,251 @@ typedef struct
*/
typedef struct
{
__I uint32_t PDS; /**< Power Domain Status */
__IO uint32_t MPC; /**< Memory Power Control */
} SYSCTL_PDSMPC_t;
typedef struct
{
uint32_t WD; /**< Watchdog Timer */
uint32_t TIMER; /**< General-Purpose Timer */
uint32_t GPIO; /**< General-Purpose Input/Output */
uint32_t DMA; /**< Micro Direct Memory Access */
uint32_t EPI; /**< EPI */
uint32_t HIB; /**< Hibernation */
uint32_t UART; /**< Universal Asynchronous
Receiver/Transmitter */
uint32_t SSI; /**< Synchronous Serial Interface */
uint32_t I2C; /**< Inter-Integrated Circuit */
uint32_t _RESERVED0[1]; /**< Reserved */
uint32_t USB; /**< Universal Serial Bus */
uint32_t _RESERVED1[1]; /**< Reserved */
uint32_t EPHY; /**< Ethernet PHY*/
uint32_t CAN; /**< Controller Area Network */
uint32_t ADC; /**< Analog-to-Digital Converter */
uint32_t ACMP; /**< Analog Comparator */
uint32_t PWM; /**< Pulse Width Modulator */
uint32_t QEI; /**< Quadrature Encoder Interface */
uint32_t LPC; /**< Low Pin Count Interface */
uint32_t _RESERVED2[1]; /**< Reserved */
uint32_t PECI; /**< Platform Environment Control Interface */
uint32_t FAN; /**< Fan Control */
uint32_t EEPROM; /**< EEPROM */
uint32_t WTIMER; /**< Wide General-Purpose Timer */
uint32_t _RESERVED3[4]; /**< Reserved */
uint32_t RTS; /**< Remote Temperature Sensor */
uint32_t CCM; /**< CRC Module */
uint32_t _RESERVED4[6]; /**< Reserved */
uint32_t LCD; /**< LCD */
uint32_t _RESERVED5[1]; /**< Reserved */
uint32_t OWIRE; /**< 1-Wire */
uint32_t EMAC; /**< Ethernet MAC */
uint32_t PRB; /**< Power Regulator Bus */
uint32_t HIM; /**< Human Interface Master */
uint32_t _RESERVED6[24]; /**< Reserved */
} SYSCTL_PERIPH_t;
typedef struct
{
__I uint32_t DID[2]; /**< Device Identification 0 and 1 */
__I uint32_t _RESERVED0[12]; /**< Reserved */
__IO uint32_t PBORCTL; /**< Power-Temp Brown Out Control */
__I uint32_t _RESERVED1[5]; /**< Reserved */
__I uint32_t DID0; /**< Device Identification 0 */
__I uint32_t DID1; /**< Device Identification 1 */
__I uint32_t RESERVED0[12]; /**< Reserved */
__IO uint32_t PBORCTL; /**< Power-Temp Brown Out Control */
__I uint32_t RESERVED1[5]; /**< Reserved */
__I uint32_t RIS; /**< Raw Interrupt Status */
__IO uint32_t IMC; /**< Interrupt Mask Control */
__IO uint32_t MISC; /**< Interrupt Status and Clear */
__IO uint32_t RESC; /**< Reset Cause */
__IO uint32_t PWRTC; /**< Power-Temperature Cause */
__IO uint32_t NMIC; /**< NMI Cause Register */
__I uint32_t _RESERVED2[5]; /**< Reserved */
__I uint32_t RESERVED2[5]; /**< Reserved */
__IO uint32_t MOSCCTL; /**< Main Oscillator Control */
__I uint32_t _RESERVED3[12]; /**< Reserved */
__I uint32_t RESERVED3[12]; /**< Reserved */
__IO uint32_t RSCLKCFG; /**< Run and Sleep Mode Configuration Register */
__I uint32_t _RESERVED4[3];
__I uint32_t RESERVEDx[3];
__IO uint32_t MEMTIM0; /**< Memory Timing Parameter Register 0 for Main Flash and EEPROM */
__I uint32_t _RESERVED5[29]; /**< Reserved */
__I uint32_t RESERVED4[29]; /**< Reserved */
__IO uint32_t ALTCLKCFG; /**< Alternate Clock Configuration */
__I uint32_t _RESERVED6[2]; /**< Reserved */
__I uint32_t RESERVED5[2]; /**< Reserved */
__IO uint32_t DSLPCLKCFG; /**< Deep Sleep Clock Configuration */
__IO uint32_t DIVSCLK; /**< Divisor and Source Clock Configuration */
__I uint32_t SYSPROP; /**< System Properties */
__IO uint32_t PIOSCCAL; /**< PIOSC Calibration */
__I uint32_t PIOSCSTAT; /**< PIOSC Statistics */
__I uint32_t _RESERVED7[2]; /**< Reserved */
__IO uint32_t PLLFREQ[2]; /**< PLL Frequency 0 and 1 */
__I uint32_t RESERVED6[2]; /**< Reserved */
__IO uint32_t PLLFREQ0; /**< PLL Frequency 0 */
__IO uint32_t PLLFREQ1; /**< PLL Frequency 1 */
__I uint32_t PLLSTAT; /**< PLL Frequency Status */
__I uint32_t _RESERVED8[7]; /**< Reserved */
__I uint32_t RESERVED7[7]; /**< Reserved */
__IO uint32_t SLPPWRCFG; /**< Sleep Power Configuration */
__IO uint32_t DSLPPWRCFG; /**< Deep-Sleep Power Configuration */
__I uint32_t _RESERVED9[4]; /**< Reserved */
__I uint32_t RESERVED8[4]; /**< Reserved */
__I uint32_t NVMSTAT; /**< Non-Volatile Memory Information */
__I uint32_t _RESERVED10[4]; /**< Reserved */
__I uint32_t RESERVED9[4]; /**< Reserved */
__IO uint32_t LDOSPCTL; /**< LDO Sleep Power Control */
__I uint32_t LDOSPCAL; /**< LDO Sleep Power Calibration */
__IO uint32_t LDODPCTL; /**< LDO Deep-Sleep Power Control */
__I uint32_t LDODPCAL; /**< LDO Deep-Sleep Power Calibration */
__I uint32_t _RESERVED11[2]; /**< Reserved */
__I uint32_t RESERVED10[2]; /**< Reserved */
__I uint32_t SDPMST; /**< Sleep/Deep-Sleep Power Mode Status */
__I uint32_t _RESERVED12[2]; /**< Reserved */
__I uint32_t RESERVED11[2]; /**< Reserved */
__IO uint32_t RESBEHAVCTL; /**< Reset Behavior Control Register */
__I uint32_t _RESERVED13[6]; /**< Reserved */
__I uint32_t RESERVED12[6]; /**< Reserved */
__IO uint32_t HSSR; /**< Hardware System Service Request */
__I uint32_t _RESERVED14[34];/**< Reserved */
SYSCTL_PDSMPC_t USB; /**< USB PDS/MPC */
SYSCTL_PDSMPC_t EMAC; /**< EMAC PDS/MPC */
SYSCTL_PDSMPC_t LCD; /**< LCD PDS/MPC */
SYSCTL_PDSMPC_t CAN[2]; /**< CAN 0 and 1 PDS/MPC */
__I uint32_t _RESERVED15[22];/**< Reserved */
__I SYSCTL_PERIPH_t PP; /**< Peripheral Present */
__I uint32_t _RESERVED16[60];/**< Reserved */
__IO SYSCTL_PERIPH_t SR; /**< Software Reset */
__IO SYSCTL_PERIPH_t RCGC; /**< Run Mode Clock Gating Control */
__IO SYSCTL_PERIPH_t SCGC; /**< Sleep Mode Clock Gating Control */
__IO SYSCTL_PERIPH_t DCGC; /**< Deep-Sleep Mode Clock Gating Control */
__IO SYSCTL_PERIPH_t PC; /**< Power Control */
__IO SYSCTL_PERIPH_t PR; /**< Peripheral Ready */
__I uint32_t RESERVED[34]; /**< Reserved */
__I uint32_t USBPDS; /**< USB Power Domain Status */
__IO uint32_t USBMPC; /**< USB Memory Power Control */
__I uint32_t EMACPDS; /**< Ethernet MAC Power Domain Status */
__IO uint32_t EMACMPC; /**< Ethernet MAC Memory Power Control */
__I uint32_t RESERVED13[2]; /**< Reserved */
__I uint32_t CAN0PDS; /**< CAN 0 Power Domain Status */
__IO uint32_t CAN0MPC; /**< CAN 0 Memory Power Control */
__I uint32_t CAN1PDS; /**< CAN 1 Power Domain Status */
__IO uint32_t CAN1MPC; /**< CAN 1 Memory Power Control */
__I uint32_t RESERVED14[22]; /**< Reserved */
__I uint32_t PPWD; /**< WDT Peripheral Present */
__I uint32_t PPTIMER; /**< GPT Peripheral Present */
__I uint32_t PPGPIO; /**< GPIO Peripheral Present */
__I uint32_t PPDMA; /**< UDMA Peripheral Present */
__I uint32_t PPEPI; /**< EPI Peripheral Present */
__I uint32_t PPHIB; /**< HIB Peripheral Present */
__I uint32_t PPUART; /**< UART Peripheral Present */
__I uint32_t PPSSI; /**< SSI Peripheral Present */
__I uint32_t PPI2C; /**< I2C Peripheral Present */
__I uint32_t RESERVED15[1]; /**< Reserved */
__I uint32_t PPUSB; /**< USB Peripheral Present */
__I uint32_t RESERVED16[1]; /**< Reserved */
__I uint32_t PPEPHY; /**< Ethernet PHY Peripheral Present */
__I uint32_t PPCAN; /**< CAN Peripheral Present */
__I uint32_t PPADC; /**< ADC Peripheral Present */
__I uint32_t PPACMP; /**< ACMP Peripheral Present */
__I uint32_t PPPWM; /**< PWM Peripheral Present */
__I uint32_t PPQEI; /**< QEI Peripheral Present */
__I uint32_t PPLPC; /**< Low Pin Count Interface Peripheral Present */
__I uint32_t RESERVED17[1]; /**< Reserved */
__I uint32_t PPPECI; /**< Platform Environment Control Interface Peripheral Present */
__I uint32_t PPFAN; /**< Fan Control Peripheral Present */
__I uint32_t PPEEPROM; /**< EEPROM Peripheral Present */
__I uint32_t PPWTIMER; /**< Wide GPT Peripheral Present */
__I uint32_t RESERVED18[4]; /**< Reserved */
__I uint32_t PPRTS; /**< Remote Temperature Sensor Peripheral Present */
__I uint32_t PPCCM; /**< CRC Module Peripheral Present */
__I uint32_t RESERVED19[6]; /**< Reserved */
__I uint32_t PPLCD; /**< LCD Peripheral Present */
__I uint32_t RESERVED20[1]; /**< Reserved */
__I uint32_t PPOWIRE; /**< 1-Wire Peripheral Present */
__I uint32_t PPEMAC; /**< Ethernet MAC Peripheral Present */
__I uint32_t PPPRB; /**< Power Regulator Bus Peripheral Present */
__I uint32_t PPHIM; /**< Human Interface Master Peripheral Present */
__I uint32_t RESERVED21[86]; /**< Reserved */
__IO uint32_t SRWD; /**< WDT Software Reset */
__IO uint32_t SRTIMER; /**< GPT Software Reset */
__IO uint32_t SRGPIO; /**< GPIO Software Reset */
__IO uint32_t SRDMA; /**< UDMA Software Reset */
__IO uint32_t SREPI; /**< EPI Software Reset */
__IO uint32_t SRHIB; /**< HIB Software Reset */
__IO uint32_t SRUART; /**< UART Software Reset */
__IO uint32_t SRSSI; /**< SSI Software Reset */
__IO uint32_t SRI2C; /**< I2C Software Reset */
__I uint32_t RESERVED22[1]; /**< Reserved */
__IO uint32_t SRUSB; /**< USB Software Reset */
__I uint32_t RESERVED23[1]; /**< Reserved */
__IO uint32_t SREPHY; /**< Ethernet PHY Software Reset */
__IO uint32_t SRCAN; /**< CAN Software Reset */
__IO uint32_t SRADC; /**< ADC Software Reset */
__IO uint32_t SRACMP; /**< ACMP Software Reset */
__IO uint32_t SRPWM; /**< PWM Software Reset */
__IO uint32_t SRQEI; /**< QEI Software Reset */
__I uint32_t RESERVED24[4]; /**< Reserved */
__IO uint32_t SREEPROM; /**< EEPROM Software Reset */
__I uint32_t RESERVED25[6]; /**< Reserved */
__IO uint32_t SRCCM; /**< CRC Module Software Reset */
__I uint32_t RESERVED26[9]; /**< Reserved */
__IO uint32_t SREMAC; /**< Ethernet MAC Software Reset */
__I uint32_t RESERVED27[24]; /**< Reserved */
__IO uint32_t RCGCWD; /**< WDT Run Mode Clock Gating Control */
__IO uint32_t RCGCTIMER; /**< GPT Run Mode Clock Gating Control */
__IO uint32_t RCGCGPIO; /**< GPIO Run Mode Clock Gating Control */
__IO uint32_t RCGCDMA; /**< UDMA Run Mode Clock Gating Control */
__IO uint32_t RCGCEPI; /**< EPI Run Mode Clock Gating Control */
__IO uint32_t RCGCHIB; /**< HIB Run Mode Clock Gating Control */
__IO uint32_t RCGCUART; /**< UART Run Mode Control */
__IO uint32_t RCGCSSI; /**< SSI Run Mode Clock Gating Control */
__IO uint32_t RCGCI2C; /**< I2C Run Mode Clock Gating Control */
__I uint32_t RESERVED28[1]; /**< Reserved */
__IO uint32_t RCGCUSB; /**< USB Run Mode Clock Gating Control */
__I uint32_t RESERVED29[1]; /**< Reserved */
__IO uint32_t RCGCEPHY; /**< Ethernet PHY Run Mode Clock Gating Control */
__IO uint32_t RCGCCAN; /**< CAN Run Mode Clock Gating Control */
__IO uint32_t RCGCADC; /**< ADC Run Mode Clock Gating Control */
__IO uint32_t RCGCACMP; /**< ACMP Run Mode Clock Gating Control */
__IO uint32_t RCGCPWM; /**< PWM Run Mode Clock Gating Control */
__IO uint32_t RCGCQEI; /**< QEI Run Mode Clock Gating Control */
__I uint32_t RESERVED30[4]; /**< Reserved */
__IO uint32_t RCGCEEPROM; /**< EEPROM Run Mode Clock Gating Control */
__I uint32_t RESERVED31[6]; /**< Reserved */
__IO uint32_t RCGCCCM; /**< CRC Module Run Mode Clock Gating Control */
__I uint32_t RESERVED32[9]; /**< Reserved */
__IO uint32_t RCGCEMAC; /**< Ethernet MAC Run Mode Clock Gating Control */
__I uint32_t RESERVED33[24]; /**< Reserved */
__IO uint32_t SCGCWD; /**< WDT Sleep Mode Clock Gating Control */
__IO uint32_t SCGCTIMER; /**< GPT Sleep Mode Clock Gating Control */
__IO uint32_t SCGCGPIO; /**< GPIO Sleep Mode Clock Gating Control */
__IO uint32_t SCGCDMA; /**< UDMA Sleep Mode Clock Gating Control */
__IO uint32_t SCGCEPI; /**< EPI Sleep Mode Clock Gating Control */
__IO uint32_t SCGCHIB; /**< HIB Sleep Mode Clock Gating Control */
__IO uint32_t SCGCUART; /**< UART Sleep Mode Clock Gating Control */
__IO uint32_t SCGCSSI; /**< SSI Sleep Mode Clock Gating Control */
__IO uint32_t SCGCI2C; /**< I2C Sleep Mode Clock Gating Control */
__I uint32_t RESERVED34[1]; /**< Reserved */
__IO uint32_t SCGCUSB; /**< USB Sleep Mode Clock Gating Control */
__I uint32_t RESERVED35[1]; /**< Reserved */
__IO uint32_t SCGCEPHY; /**< Ethernet PHY Sleep Mode Clock Gating Control */
__IO uint32_t SCGCCAN; /**< CAN Sleep Mode Clock Gating Control */
__IO uint32_t SCGCADC; /**< ADC Sleep Mode Clock Gating Control */
__IO uint32_t SCGCACMP; /**< ACMP Sleep Mode Clock Gating Control */
__IO uint32_t SCGCPWM; /**< PWM Sleep Mode Clock Gating Control */
__IO uint32_t SCGCQEI; /**< QEI Sleep Mode Clock Gating Control */
__I uint32_t RESERVED36[4]; /**< Reserved */
__IO uint32_t SCGCEEPROM; /**< EEPROM Sleep Mode Clock Gating Control */
__I uint32_t RESERVED37[6]; /**< Reserved */
__IO uint32_t SCGCCCM; /**< CRC Module Sleep Mode Clock Gating Control */
__I uint32_t RESERVED38[9]; /**< Reserved */
__IO uint32_t SCGCEMAC; /**< Ethernet MAC Sleep Mode Clock Gating Control */
__I uint32_t RESERVED39[24]; /**< Reserved */
__IO uint32_t DCGCWD; /**< WDT Deep-Sleep Mode Clock Gating Control*/
__IO uint32_t DCGCTIMER; /**< GPT Deep-Sleep Mode Clock Gating Control*/
__IO uint32_t DCGCGPIO; /**< GPIO Deep-Sleep Mode Clock Gating
Control */
__IO uint32_t DCGCDMA; /**< UDMA Deep-Sleep Mode Clock Gating
Control */
__IO uint32_t DCGCEPI; /**< EPI Deep-Sleep Mode Clock Gating Control */
__IO uint32_t DCGCHIB; /**< HIB Deep-Sleep Mode Clock Gating Control*/
__IO uint32_t DCGCUART; /**< UART Deep-Sleep Mode Clock Gating
Control */
__IO uint32_t DCGCSSI; /**< SSI Deep-Sleep Mode Clock Gating Control*/
__IO uint32_t DCGCI2C; /**< I2C Deep-Sleep Mode Clock Gating Control*/
__I uint32_t RESERVED40[1]; /**< Reserved */
__IO uint32_t DCGCUSB; /**< USB Deep-Sleep Mode Clock Gating Control*/
__I uint32_t RESERVED41[1]; /**< Reserved */
__IO uint32_t DCGCEPHY; /**< Ethernet PHY Deep-Sleep Mode Clock Gating Control */
__IO uint32_t DCGCCAN; /**< CAN Deep-Sleep Mode Clock Gating Control*/
__IO uint32_t DCGCADC; /**< ADC Deep-Sleep Mode Clock Gating Control*/
__IO uint32_t DCGCACMP; /**< ACMP Deep-Sleep Mode Clock Gating
Control */
__IO uint32_t DCGCPWM; /**< PWM Deep-Sleep Mode Clock Gating Control*/
__IO uint32_t DCGCQEI; /**< QEI Deep-Sleep Mode Clock Gating Control*/
__I uint32_t RESERVED42[4]; /**< Reserved */
__IO uint32_t DCGCEEPROM; /**< EEPROM Deep-Sleep Mode Clock Gating
Control */
__I uint32_t RESERVED43[6]; /**< Reserved */
__IO uint32_t DCGCCCM; /**< CRC Module Deep-Sleep Mode Clock Gating Control */
__I uint32_t RESERVED44[9]; /**< Reserved */
__IO uint32_t DCGCEMAC; /**< Ethernet MAC Deep-Sleep Mode Clock Gating Control */
__I uint32_t RESERVED45[24]; /**< Reserved */
__IO uint32_t PCWD; /**< Watchdog Timer Power Control */
__IO uint32_t PCTIMER; /**< 16/32-Bit General-Purpose Timer Power Control */
__IO uint32_t PCGPIO; /**< General-Purpose Input/Output Power Control */
__IO uint32_t PCDMA; /**< Micro Direct Memory Access Power Control */
__IO uint32_t PCEPI; /**< External Peripheral Interface Power Control */
__IO uint32_t PCHIB; /**< Hibernation Power Control */
__IO uint32_t PCUART; /**< Universal Asynchronous Receiver/Transmitter Power Control */
__IO uint32_t PCSSI; /**< Synchronous Serial Interface Power Control */
__IO uint32_t PCI2C; /**< Inter-Integrated Circuit Power Control */
__I uint32_t RESERVED46[1]; /**< Reserved */
__IO uint32_t PCUSB; /**< Universal Serial Bus Power Control */
__I uint32_t RESERVED47[1]; /**< Reserved */
__IO uint32_t PCEPHY; /**< Ethernet PHY Power Control */
__IO uint32_t PCCAN; /**< Controller Area Network Power Control */
__IO uint32_t PCADC; /**< Analog-to-Digital Converter Power Control */
__IO uint32_t PCACMP; /**< Analog Comparator Power Control */
__IO uint32_t PCPWM; /**< Pulse Width Modulator Power Control */
__IO uint32_t PCQEI; /**< Quadrature Encoder Interface Power Control */
__I uint32_t RESERVED48[4]; /**< Reserved */
__IO uint32_t PCEEPROM; /**< EEPROM Power Control */
__I uint32_t RESERVED49[6]; /**< Reserved */
__IO uint32_t PCCCM; /**< CRC Module Power Control */
__I uint32_t RESERVED50[9]; /**< Reserved */
__IO uint32_t PCEMAC; /**< Ethernet MAC Power Control */
__I uint32_t RESERVED51[24]; /**< Reserved */
__IO uint32_t PRWD; /**< WDT Peripheral Ready */
__IO uint32_t PRTIMER; /**< GPT Peripheral Ready */
__IO uint32_t PRGPIO; /**< GPIO Peripheral Ready */
__IO uint32_t PRDMA; /**< UDMA Peripheral Ready */
__IO uint32_t PREPI; /**< EPI Peripheral Ready */
__IO uint32_t PRHIB; /**< HIB Peripheral Ready */
__IO uint32_t PRUART; /**< UART Peripheral Ready */
__IO uint32_t PRSSI; /**< SSI Peripheral Ready */
__IO uint32_t PRI2C; /**< I2C Peripheral Ready */
__I uint32_t RESERVED52[1]; /**< Reserved */
__IO uint32_t PRUSB; /**< USB Peripheral Ready */
__I uint32_t RESERVED53[1]; /**< Reserved */
__IO uint32_t PREPHY; /**< Ethernet PHY Peripheral Ready */
__IO uint32_t PRCAN; /**< CAN Peripheral Ready */
__IO uint32_t PRADC; /**< ADC Peripheral Ready */
__IO uint32_t PRACMP; /**< ACMP Peripheral Ready */
__IO uint32_t PRPWM; /**< PWM Peripheral Ready */
__IO uint32_t PRQEI; /**< QEI Peripheral Ready */
__I uint32_t RESERVED54[4]; /**< Reserved */
__IO uint32_t PREEPROM; /**< EEPROM Peripheral Ready */
__I uint32_t RESERVED55[6]; /**< Reserved */
__IO uint32_t PRCCM; /**< CRC Module Peripheral Ready */
__I uint32_t RESERVED56[9]; /**< Reserved */
__IO uint32_t PREMAC; /**< Ethernet MAC Peripheral Ready */
} SYSCTL_TypeDef;
/**
@ -722,6 +864,106 @@ typedef struct
__IO uint32_t LOCK; /**< Lock */
} WATCHDOG_TypeDef;
/**
* @brief Ethernet peripheral
*/
typedef struct {
__IO uint32_t CFG; /**< Configuration */
__IO uint32_t FRAMEFLTR; /**< Frame Filter */
__IO uint32_t HASHTBLH; /**< Hash Table High */
__IO uint32_t HASHTBLL; /**< Hash Table Low */
__IO uint32_t MIIADDR; /**< MII Address */
__IO uint32_t MIIDATA; /**< MII Data Register */
__IO uint32_t FLOWCTL; /**< Flow Control */
__IO uint32_t VLANTG; /**< VLAN Tag */
__I uint32_t RESERVED0[1]; /**< Reserved */
__IO uint32_t STATUS; /**< Status */
__IO uint32_t RWUFF; /**< Remote Wake-Up Frame Filter */
__IO uint32_t PMTCTLSTAT; /**< PMT Control and Status Register */
__I uint32_t RESERVED1[2]; /**< Reserved */
__IO uint32_t RIS; /**< Raw Interrupt Status */
__IO uint32_t IM; /**< Interrupt Mask */
__IO uint32_t ADDR0H; /**< Address 0 High */
__IO uint32_t ADDR0L; /**< Address 0 Low Register */
__IO uint32_t ADDR1H; /**< Address 1 High */
__IO uint32_t ADDR1L; /**< Address 1 Low */
__IO uint32_t ADDR2H; /**< Address 2 High */
__IO uint32_t ADDR2L; /**< Address 2 Low */
__IO uint32_t ADDR3H; /**< Address 3 High */
__IO uint32_t ADDR3L; /**< Address 3 Low */
__I uint32_t RESERVED2[31]; /**< Reserved */
__IO uint32_t WDOGTO; /**< Watchdog Timeout */
__I uint32_t RESERVED3[8]; /**< Reserved */
__IO uint32_t MMCCTRL; /**< MMC Control */
__IO uint32_t MMCRXRIS; /**< MMC Receive Raw Interrupt Status */
__IO uint32_t MMCTXRIS; /**< MMC Transmit Raw Interrupt Status */
__IO uint32_t MMCRXIM; /**< MMC Receive Interrupt Mask */
__IO uint32_t MMCTXIM; /**< MMC Transmit Interrupt Mask */
__I uint32_t RESERVED4[1]; /**< Reserved */
__IO uint32_t TXCNTGB; /**< Transmit Frame Count for Good and Bad
Frames */
__I uint32_t RESERVED5[12]; /**< Reserved */
__IO uint32_t TXCNTSCOL; /**< Transmit Frame Count for Frames
Transmitted after Single Collision */
__IO uint32_t TXCNTMCOL; /**< Transmit Frame Count for Frames
Transmitted after Multiple Collisions */
__I uint32_t RESERVED6[4]; /**< Reserved */
__IO uint32_t TXOCTCNTG; /**< Transmit Octet Count Good */
__I uint32_t RESERVED7[6]; /**< Reserved */
__IO uint32_t RXCNTGB; /**< Receive Frame Count for Good and Bad
Frames */
__I uint32_t RESERVED8[4]; /**< Reserved */
__IO uint32_t RXCNTCRCERR; /**< Receive Frame Count for CRC Error Frames*/
__IO uint32_t RXCNTALGNERR; /**< Receive Frame Count for Alignment Error
Frames */
__I uint32_t RESERVED9[10]; /**< Reserved */
__IO uint32_t RXCNTGUNI; /**< Receive Frame Count for Good Unicast
Frames */
__I uint32_t RESERVED10[239];/**< Reserved */
__IO uint32_t VLNINCREP; /**< VLAN Tag Inclusion or Replacement */
__IO uint32_t VLANHASH; /**< VLAN Hash Table */
__I uint32_t RESERVED11[93]; /**< Reserved */
__IO uint32_t TIMSTCTRL; /**< Timestamp Control */
__IO uint32_t SUBSECINC; /**< Sub-Second Increment */
__IO uint32_t TIMSEC; /**< System Time - Seconds */
__IO uint32_t TIMNANO; /**< System Time - Nanoseconds */
__IO uint32_t TIMSECU; /**< System Time - Seconds Update */
__IO uint32_t TIMNANOU; /**< System Time - Nanoseconds Update */
__IO uint32_t TIMADD; /**< Timestamp Addend */
__IO uint32_t TARGSEC; /**< Target Time Seconds */
__IO uint32_t TARGNANO; /**< Target Time Nanoseconds */
__IO uint32_t HWORDSEC; /**< System Time-Higher Word Seconds */
__IO uint32_t TIMSTAT; /**< Timestamp Status */
__IO uint32_t PPSCTRL; /**< PPS Control */
__I uint32_t RESERVED12[12]; /**< Reserved */
__IO uint32_t PPS0INTVL; /**< PPS0 Interval */
__IO uint32_t PPS0WIDTH; /**< PPS0 Width */
__I uint32_t RESERVED13[294];/**< Reserved */
__IO uint32_t DMABUSMOD; /**< DMA Bus Mode */
__O uint32_t TXPOLLD; /**< Transmit Poll Demand */
__O uint32_t RXPOLLD; /**< Receive Poll Demand */
__IO uint32_t RXDLADDR; /**< Receive Descriptor List Address */
__IO uint32_t TXDLADDR; /**< Transmit Descriptor List Address */
__IO uint32_t DMARIS; /**< DMA Interrupt Status */
__IO uint32_t DMAOPMODE; /**< DMA Operation Mode */
__IO uint32_t DMAIM; /**< DMA Interrupt Mask Register */
__IO uint32_t MFBOC; /**< Missed Frame and Buffer Overflow Counter*/
__IO uint32_t RXINTWDT; /**< Receive Interrupt Watchdog Timer */
__I uint32_t RESERVED14[8]; /**< Reserved */
__IO uint32_t HOSTXDESC; /**< Current Host Transmit Descriptor */
__IO uint32_t HOSRXDESC; /**< Current Host Receive Descriptor */
__IO uint32_t HOSTXBA; /**< Current Host Transmit Buffer Address */
__IO uint32_t HOSRXBA; /**< Current Host Receive Buffer Address */
__I uint32_t RESERVED15[218];/**< Reserved */
__IO uint32_t PP; /**< Peripheral Property Register */
__IO uint32_t PC; /**< Peripheral Configuration Register */
__IO uint32_t CC; /**< Clock Configuration Register */
__I uint32_t RESERVED16[1]; /**< Reserved */
__I uint32_t PHYRIS; /**< PHY Raw Interrupt Status */
__IO uint32_t PHYIM; /**< PHY Interrupt Mask */
__IO uint32_t PHYMISC; /**< PHY Masked Interrupt Status and Clear */
} ETH_TypeDef;
/**
* @}
*/
@ -796,6 +1038,8 @@ typedef struct
#define QEI0_BASE 0x4002C000
#define QEI1_BASE 0x4002D000
#define ETH_BASE 0x400EC000
/**
* @}
*/
@ -868,6 +1112,8 @@ typedef struct
#define QEI0 ((QEI_TypeDef *) QEI0_BASE)
#define QEI1 ((QEI_TypeDef *) QEI1_BASE)
#define ETH ((ETH_TypeDef *) ETH_BASE)
/**
* @}
*/