From 5f231b6aaf4f3506b462faed77db0b3a5595d918 Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 22 Oct 2014 10:33:02 +0300 Subject: [PATCH] FSMC. SDRAM. Style cleanup --- os/hal/ports/STM32/LLD/FSMCv1/fsmc.c | 16 +- os/hal/ports/STM32/LLD/FSMCv1/fsmc.h | 27 +++- os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c | 63 ++++---- os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.h | 151 ++++++++++--------- os/hal/ports/STM32/STM32F4xx/platform.mk | 3 +- testhal/STM32/STM32F4xx/FSMC_SDRAM/.project | 2 +- testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile | 2 +- testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c | 2 - testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf.h | 2 +- 9 files changed, 156 insertions(+), 112 deletions(-) diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c index 4c1a1977..65f3baf6 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c @@ -28,7 +28,8 @@ #include "hal.h" #include "fsmc.h" -#if HAL_USE_NAND || STM32_USE_FSMC_SRAM || defined(__DOXYGEN__) +#if HAL_USE_NAND || STM32_USE_FSMC_SRAM || STM32_USE_FSMC_SDRAM || \ + defined(__DOXYGEN__) /*===========================================================================*/ /* Driver local definitions. */ @@ -102,6 +103,17 @@ void fsmc_init(void) { #if STM32_USE_FSMC_PCCARD FSMCD1.pccard = (FSMC_PCCARD_TypeDef *)FSMC_Bank4_R_BASE; #endif + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx)) + #if STM32_SDRAM_USE_FSMC_SDRAM1 + FSMCD1.sdram1 = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_R_BASE; + #endif + + #if STM32_SDRAM_USE_FSMC_SDRAM2 + FSMCD1.sdram2 = (FSMC_SDRAM_TypeDef *)FSMC_Bank6_R_BASE; + #endif +#endif } } @@ -183,6 +195,6 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { } #endif /* !STM32_NAND_USE_EXT_INT */ -#endif /* HAL_USE_FSMC || STM32_USE_FSMC_SRAM */ +#endif /* HAL_USE_FSMC || STM32_USE_FSMC_SRAM || STM32_USE_FSMC_SDRAM */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h index 2b579a22..21c58bdb 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h @@ -29,7 +29,7 @@ #ifndef _FSMC_H_ #define _FSMC_H_ -#if HAL_USE_NAND || STM32_USE_FSMC_SRAM || defined(__DOXYGEN__) +#if HAL_USE_NAND || STM32_USE_FSMC_SRAM || STM32_USE_FSMC_SDRAM || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -86,6 +86,11 @@ #define FSMC_Bank2_MAP_BASE ((uint32_t) 0x70000000) #define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000) #define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx)) + #define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000) + #define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000) +#endif /* * Subbunks of bank1 @@ -158,6 +163,15 @@ typedef struct { __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */ } FSMC_SRAM_NOR_TypeDef; +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx)) + typedef struct { + __IO uint32_t SDCR; /**< SDRAM control register */ + uint32_t RESERVED0; /**< Reserved */ + __IO uint32_t SDTR; /**< SDRAM timing register */ + } FSMC_SDRAM_TypeDef; +#endif + /** * @brief PCR register */ @@ -280,6 +294,15 @@ struct FSMCDriver { #if STM32_USE_FSMC_PCCARD FSMC_PCCard_TypeDef *pccard; #endif +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx)) + #if STM32_SDRAM_USE_FSMC_SDRAM1 + FSMC_SDRAM_TypeDef *sdram1; + #endif + #if STM32_SDRAM_USE_FSMC_SDRAM2 + FSMC_SDRAM_TypeDef *sdram2; + #endif +#endif }; /*===========================================================================*/ @@ -304,7 +327,7 @@ extern "C" { } #endif -#endif /* HAL_USE_NAND || STM32_USE_FSMC_SRAM */ +#endif /* HAL_USE_NAND || STM32_USE_FSMC_SRAM || STM32_USE_FSMC_SDRAM */ #endif /* _FSMC_H_ */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c index eca66ea1..b7381851 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c @@ -39,6 +39,17 @@ /* Driver local definitions. */ /*===========================================================================*/ +#define SDCR2_DONTCARE_BITS (FMC_SDClock_Period_Mask | \ + FMC_Read_Burst_Mask | \ + FMC_ReadPipe_Delay_Mask) + +#define SDTR2_DONTCARE_BITS (FMC_RowCycleDelay_Mask | FMC_RPDelay_Mask) + +/* + * FMC SDCRx write protection mask + */ +#define SDCR_WriteProtection_RESET ((uint32_t)0x00007DFF) + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -75,14 +86,14 @@ SDRAMDriver SDRAMD2; * * @notapi */ -static void fsmcSdramInitSequence(uint32_t CommandTarget) { +static void fsmc_sdram_init_sequence(uint32_t command_target) { uint32_t tmpreg; /* Step 3 -----------------------------------------------------------------*/ /* Wait until the SDRAM controller is ready */ while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY); /* Configure a clock configuration enable command */ FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_CLK_Enabled | - CommandTarget | + command_target | ((1 -1) << 5) | // FMC_AutoRefreshNumber = 1 (0 << 9); // FMC_ModeRegisterDefinition = 0 /* Step 4 -----------------------------------------------------------------*/ @@ -93,7 +104,7 @@ static void fsmcSdramInitSequence(uint32_t CommandTarget) { while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY); /* Configure a PALL (precharge all) command */ FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_PALL | - CommandTarget | + command_target | ((1 -1) << 5) | // FMC_AutoRefreshNumber = 1 (0 << 9); // FMC_ModeRegisterDefinition = 0 /* Step 6 -----------------------------------------------------------------*/ @@ -101,14 +112,14 @@ static void fsmcSdramInitSequence(uint32_t CommandTarget) { while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY); /* Configure a Auto-Refresh command: Send the first command */ FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_AutoRefresh | - CommandTarget | + command_target | ((4 -1) << 5) | // FMC_AutoRefreshNumber = 4 (0 << 9); // FMC_ModeRegisterDefinition = 0 /* Wait until the SDRAM controller is ready */ while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY); /* Configure a Auto-Refresh command: Send the second command*/ FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_AutoRefresh | - CommandTarget | + command_target | ((4 -1) << 5) | // FMC_AutoRefreshNumber = 4 (0 << 9); // FMC_ModeRegisterDefinition = 0 /* Step 7 -----------------------------------------------------------------*/ @@ -122,7 +133,7 @@ static void fsmcSdramInitSequence(uint32_t CommandTarget) { FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE; /* Send the command */ FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_LoadMode | - CommandTarget | + command_target | ((1 -1) << 5) | // FMC_AutoRefreshNumber = 1 (tmpreg << 9); /* Step 8 -----------------------------------------------------------------*/ @@ -152,8 +163,6 @@ static void fsmcSdramInitSequence(uint32_t CommandTarget) { /** * @brief Low level SDRAM driver initialization. - * - * @notapi */ void fsmcSdramInit(void) { @@ -168,7 +177,6 @@ void fsmcSdramInit(void) { SDRAMD2.sdram = FSMCD1.sdram2; SDRAMD2.state = SDRAM_STOP; #endif /* STM32_SDRAM_USE_FSMC_SDRAM2 */ - } /** @@ -176,13 +184,7 @@ void fsmcSdramInit(void) { * * @param[in] sdramp pointer to the @p SDRAMDriver object * @param[in] cfgp pointer to the @p SDRAMConfig object - * - * @notapi */ -#define SDCR2_DONTCARE_BITS (FMC_SDClock_Period_Mask | \ - FMC_Read_Burst_Mask | \ - FMC_ReadPipe_Delay_Mask) -#define SDTR2_DONTCARE_BITS (FMC_RowCycleDelay_Mask | FMC_RPDelay_Mask) void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) { if (FSMCD1.state == FSMC_STOP) @@ -196,19 +198,19 @@ void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) { if (sdramp->sdram == (FSMC_SDRAM_TypeDef *)FSMC_Bank5_R_BASE) { sdramp->sdram->SDCR = cfgp->sdcr; sdramp->sdram->SDTR = cfgp->sdtr; - fsmcSdramInitSequence(FMC_Command_Target_bank1); - } else { /* SDCR2 "don't care" bits configuration */ + fsmc_sdram_init_sequence(FMC_Command_Target_bank1); + } + else { /* SDCR2 "don't care" bits configuration */ ((FSMC_SDRAM_TypeDef *)FSMC_Bank5_R_BASE)->SDCR = cfgp->sdcr & SDCR2_DONTCARE_BITS; sdramp->sdram->SDCR = cfgp->sdcr; ((FSMC_SDRAM_TypeDef *)FSMC_Bank5_R_BASE)->SDTR = cfgp->sdtr & SDTR2_DONTCARE_BITS; sdramp->sdram->SDTR = cfgp->sdtr; - fsmcSdramInitSequence(FMC_Command_Target_bank2); + fsmc_sdram_init_sequence(FMC_Command_Target_bank2); } sdramp->state = SDRAM_READY; } - } /** @@ -225,7 +227,6 @@ void fsmcSdramStop(SDRAMDriver *sdramp) { } } - /** * @brief Wait until the SDRAM controller is ready. * @@ -237,25 +238,21 @@ void fsmcSdram_WaitReady(void) { } /** - * @brief Enables or disables write protection to the specified SDRAM Bank. - * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be - * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. - * @param NewState: new state of the write protection flag. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -/* FMC SDCRx write protection Mask*/ -#define SDCR_WriteProtection_RESET ((uint32_t)0x00007DFF) -void fsmcSdram_WriteProtectionConfig(SDRAMDriver *sdramp, int State) { + * @brief Enables or disables write protection to the specified SDRAM Bank. + * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be + * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. + * @param NewState: new state of the write protection flag. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void fsmcSdram_WriteProtectionConfig(SDRAMDriver *sdramp, int state) { - if (State) + if (state) sdramp->sdram->SDCR |= FMC_Write_Protection_Enable; else sdramp->sdram->SDCR &= SDCR_WriteProtection_RESET; - } - #endif /* STM32_USE_FSMC_SDRAM */ #endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.h b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.h index 17fc28de..010fb58e 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.h @@ -40,9 +40,10 @@ /* Driver constants. */ /*===========================================================================*/ -/** @defgroup FMC_ColumnBits_Number - * @{ - */ +/** + * @defgroup FMC_ColumnBits_Number + * @{ + */ #define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) #define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) #define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) @@ -55,12 +56,13 @@ ((COLUMN) == FMC_ColumnBits_Number_11b)) /** - * @} - */ + * @} + */ -/** @defgroup FMC_RowBits_Number - * @{ - */ +/** + * @defgroup FMC_RowBits_Number + * @{ + */ #define FMC_RowBits_Number_11b ((uint32_t)0x00000000) #define FMC_RowBits_Number_12b ((uint32_t)0x00000004) #define FMC_RowBits_Number_13b ((uint32_t)0x00000008) @@ -71,12 +73,13 @@ ((ROW) == FMC_RowBits_Number_13b)) /** - * @} - */ + * @} + */ -/** @defgroup FMC_SDMemory_Data_Width - * @{ - */ +/** + * @defgroup FMC_SDMemory_Data_Width + * @{ + */ #define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) #define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) #define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) @@ -87,12 +90,13 @@ ((WIDTH) == FMC_SDMemory_Width_32b)) /** - * @} - */ + * @} + */ -/** @defgroup FMC_InternalBank_Number - * @{ - */ +/** + * @defgroup FMC_InternalBank_Number + * @{ + */ #define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) #define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) @@ -101,13 +105,14 @@ ((NUMBER) == FMC_InternalBank_Number_4)) /** - * @} - */ + * @} + */ -/** @defgroup FMC_CAS_Latency - * @{ - */ +/** + * @defgroup FMC_CAS_Latency + * @{ + */ #define FMC_CAS_Latency_1 ((uint32_t)0x00000080) #define FMC_CAS_Latency_2 ((uint32_t)0x00000100) #define FMC_CAS_Latency_3 ((uint32_t)0x00000180) @@ -118,12 +123,13 @@ ((LATENCY) == FMC_CAS_Latency_3)) /** - * @} - */ + * @} + */ -/** @defgroup FMC_Write_Protection - * @{ - */ +/** + * @defgroup FMC_Write_Protection + * @{ + */ #define FMC_Write_Protection_Disable ((uint32_t)0x00000000) #define FMC_Write_Protection_Enable ((uint32_t)0x00000200) @@ -132,13 +138,14 @@ ((WRITE) == FMC_Write_Protection_Enable)) /** - * @} - */ + * @} + */ -/** @defgroup FMC_SDClock_Period - * @{ - */ +/** + * @defgroup FMC_SDClock_Period + * @{ + */ #define FMC_SDClock_Disable ((uint32_t)0x00000000) #define FMC_SDClock_Period_2 ((uint32_t)0x00000800) #define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) @@ -150,12 +157,13 @@ ((PERIOD) == FMC_SDClock_Period_3)) /** - * @} - */ + * @} + */ -/** @defgroup FMC_Read_Burst - * @{ - */ +/** + * @defgroup FMC_Read_Burst + * @{ + */ #define FMC_Read_Burst_Disable ((uint32_t)0x00000000) #define FMC_Read_Burst_Enable ((uint32_t)0x00001000) #define FMC_Read_Burst_Mask ((uint32_t)0x00001000) @@ -165,12 +173,13 @@ ((RBURST) == FMC_Read_Burst_Enable)) /** - * @} - */ + * @} + */ -/** @defgroup FMC_ReadPipe_Delay - * @{ - */ +/** + * @defgroup FMC_ReadPipe_Delay + * @{ + */ #define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) #define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) #define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) @@ -182,12 +191,13 @@ ((DELAY) == FMC_ReadPipe_Delay_2)) /** - * @} - */ + * @} + */ -/** @defgroup FMC_Command_Mode - * @{ - */ +/** + * @defgroup FMC_Command_Mode + * @{ + */ #define FMC_Command_Mode_normal ((uint32_t)0x00000000) #define FMC_Command_Mode_CLK_Enabled ((uint32_t)0x00000001) #define FMC_Command_Mode_PALL ((uint32_t)0x00000002) @@ -206,12 +216,13 @@ ((COMMAND) == FMC_Command_Mode_PowerDown)) /** - * @} - */ + * @} + */ -/** @defgroup FMC_Command_Target - * @{ - */ +/** + * @defgroup FMC_Command_Target + * @{ + */ #define FMC_Command_Target_bank2 ((uint32_t)0x00000008) #define FMC_Command_Target_bank1 ((uint32_t)0x00000010) #define FMC_Command_Target_bank1_2 ((uint32_t)0x00000018) @@ -222,31 +233,33 @@ ((TARGET) == FMC_Command_Target_bank1_2)) /** - * @} - */ + * @} + */ -/** @defgroup FMC_AutoRefresh_Number - * @{ - */ +/** + * @defgroup FMC_AutoRefresh_Number + * @{ + */ #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16)) /** - * @} - */ + * @} + */ -/** @defgroup FMC_ModeRegister_Definition - * @{ - */ +/** + * @defgroup FMC_ModeRegister_Definition + * @{ + */ #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191) /** - * @} - */ + * @} + */ /** - * @brief FMC SDRAM Mode definition register defines - */ + * @brief FMC SDRAM Mode definition register defines + */ #define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000) #define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001) #define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002) @@ -342,7 +355,7 @@ struct SDRAMDriver { /** * @brief Pointer to the FMC SDRAM registers block. */ - FSMC_SDRAM_TypeDef *sdram; + FSMC_SDRAM_TypeDef *sdram; }; /*===========================================================================*/ @@ -368,7 +381,7 @@ extern "C" { void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); void fsmcSdramStop(SDRAMDriver *sdramp); void fsmcSdram_WaitReady(void); - void fsmcSdram_WriteProtectionConfig(SDRAMDriver *sdramp, int State); + void fsmcSdram_WriteProtectionConfig(SDRAMDriver *sdramp, int state); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/STM32/STM32F4xx/platform.mk b/os/hal/ports/STM32/STM32F4xx/platform.mk index dc8f1c45..2ede59db 100644 --- a/os/hal/ports/STM32/STM32F4xx/platform.mk +++ b/os/hal/ports/STM32/STM32F4xx/platform.mk @@ -2,6 +2,7 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx/platform.mk PLATFORMSRC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c \ ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c \ - ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c + ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c \ + ${CHIBIOS}/community/os/hal/src/fsmc_sdram.c PLATFORMINC += ${CHIBIOS}/community/os/hal/ports/STM32/LLD/FSMCv1 diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/.project b/testhal/STM32/STM32F4xx/FSMC_SDRAM/.project index dd98b905..120dc0cd 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/.project +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/.project @@ -27,7 +27,7 @@ os 2 - CHIBIOS/os + CHIBIOS diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile b/testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile index 5443c636..7e083fa4 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/Makefile @@ -82,7 +82,7 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../../.. include $(CHIBIOS)/community/os/hal/hal.mk -include $(CHIBIOS)/community/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk +include $(CHIBIOS)/os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk include $(CHIBIOS)/community/os/hal/ports/STM32/STM32F4xx/platform.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk include $(CHIBIOS)/os/rt/rt.mk diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c index 9e107fb0..4a3497db 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c @@ -49,7 +49,6 @@ write memtest function using ideas from http://www.memtest86.com/technical.htm ****************************************************************************** */ -/* /* ****************************************************************************** * GLOBAL VARIABLES @@ -81,7 +80,6 @@ static const SDRAMConfig sdram_cfg = { (2 << 24) // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns) }; - /* benchmarking results in MiB/S */ double memset_speed_ext; double memset_speed_int; diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf.h index f2658343..cc44f87d 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf.h @@ -41,7 +41,7 @@ #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 12 +#define STM32_PLLM_VALUE 8 #define STM32_PLLN_VALUE 336 #define STM32_PLLP_VALUE 2 #define STM32_PLLQ_VALUE 7