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ChibiOS-Contrib
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Merge branch 'master' of github.com:ChibiOS/ChibiOS-Contrib

This commit is contained in:
barthess 2015-03-05 16:00:24 +03:00
parent ae1ce0ea2b 817efe19e0
commit 6518ddaf22
15 changed files with 953 additions and 477 deletions
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48
demos/TIVA/RT-TM4C123G-LAUNCHPAD/main.c
View File

@ -37,6 +37,8 @@ static msg_t blinkLed(void *arg)
chRegSetThreadName("Blinker");
palSetPadMode(ledConfig->port, ledConfig->pin, PAL_MODE_OUTPUT_PUSHPULL);
while (TRUE) {
chThdSleepMilliseconds(ledConfig->sleep);
palTogglePad(ledConfig->port, ledConfig->pin);
@ -62,6 +64,17 @@ int main(void)
halInit();
chSysInit();
/* Configure RX and TX pins for UART0.*/
palSetPadMode(GPIOA, GPIOA_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
palSetPadMode(GPIOA, GPIOA_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
/* Start the serial driver with the default configuration.*/
sdStart(&SD1, NULL);
if (!palReadPad(GPIOF, GPIOF_SW2)) {
TestThread(&SD1);
}
ledRed.port = GPIOF;
ledRed.pin = GPIOF_LED_RED;
ledRed.sleep = 100;
@ -74,39 +87,18 @@ int main(void)
ledBlue.pin = GPIOF_LED_BLUE;
ledBlue.sleep = 102;
/*
* Creating the blinker threads.
*/
chThdCreateStatic(waBlinkLedRed,
sizeof(waBlinkLedRed),
NORMALPRIO,
blinkLed,
/* Creating the blinker threads.*/
chThdCreateStatic(waBlinkLedRed, sizeof(waBlinkLedRed), NORMALPRIO, blinkLed,
&ledRed);
chThdCreateStatic(waBlinkLedGreen,
sizeof(waBlinkLedGreen),
NORMALPRIO,
blinkLed,
&ledGreen);
chThdCreateStatic(waBlinkLedGreen, sizeof(waBlinkLedGreen), NORMALPRIO,
blinkLed, &ledGreen);
chThdCreateStatic(waBlinkLedBlue,
sizeof(waBlinkLedBlue),
NORMALPRIO,
blinkLed,
&ledBlue);
chThdCreateStatic(waBlinkLedBlue, sizeof(waBlinkLedBlue), NORMALPRIO,
blinkLed, &ledBlue);
/*
* Start the serial driver with the default configuration.
*/
sdStart(&SD1, NULL);
/*
* Normal main() thread activity
*/
/* Normal main() thread activity.*/
while (TRUE) {
if (!palReadPad(GPIOF, GPIOF_SW2)) {
TestThread(&SD1);
}
chThdSleepMilliseconds(100);
}

10
demos/TIVA/RT-TM4C123G-LAUNCHPAD/mcuconf.h
View File

@ -24,6 +24,16 @@
#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \
TIVA_RCC_PWMDIV_8)
/*
* GPIO driver system settings.
*/
#define TIVA_GPIO_GPIOA_USE_AHB TRUE
#define TIVA_GPIO_GPIOB_USE_AHB TRUE
#define TIVA_GPIO_GPIOC_USE_AHB TRUE
#define TIVA_GPIO_GPIOD_USE_AHB TRUE
#define TIVA_GPIO_GPIOE_USE_AHB TRUE
#define TIVA_GPIO_GPIOF_USE_AHB TRUE
/*
* GPT driver system settings.
*/

46
demos/TIVA/RT-TM4C1294-LAUNCHPAD/main.c
View File

@ -38,6 +38,9 @@ static msg_t blinkLed(void *arg)
chRegSetThreadName("Blinker");
/* Configure pin as push-pull output.*/
palSetPadMode(ledConfig->port, ledConfig->pin, PAL_MODE_OUTPUT_PUSHPULL);
while (TRUE) {
chThdSleepMilliseconds(ledConfig->sleep);
palTogglePad(ledConfig->port, ledConfig->pin);
@ -63,6 +66,17 @@ int main(void)
halInit();
chSysInit();
/* Configure RX and TX pins for UART0.*/
palSetPadMode(GPIOA, GPIOA_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
palSetPadMode(GPIOA, GPIOA_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
/* Start the serial driver with the default configuration.*/
sdStart(&SD1, NULL);
if (!palReadPad(GPIOJ, GPIOJ_SW1)) {
TestThread(&SD1);
}
led1.port = GPIOF;
led1.pin = GPIOF_LED0;
led1.sleep = 100;
@ -79,45 +93,23 @@ int main(void)
led4.pin = GPION_LED3;
led4.sleep = 103;
/*
* Creating the blinker threads.
*/
chThdCreateStatic(waBlinkLed1,
sizeof(waBlinkLed1),
NORMALPRIO,
blinkLed,
/* Creating the blinker threads.*/
chThdCreateStatic(waBlinkLed1, sizeof(waBlinkLed1), NORMALPRIO, blinkLed,
&led1);
chThdCreateStatic(waBlinkLed2,
sizeof(waBlinkLed2),
NORMALPRIO,
blinkLed,
chThdCreateStatic(waBlinkLed2, sizeof(waBlinkLed2), NORMALPRIO, blinkLed,
&led2);
chThdCreateStatic(waBlinkLed3,
sizeof(waBlinkLed3),
NORMALPRIO,
blinkLed,
chThdCreateStatic(waBlinkLed3, sizeof(waBlinkLed3), NORMALPRIO, blinkLed,
&led3);
chThdCreateStatic(waBlinkLed4,
sizeof(waBlinkLed4),
NORMALPRIO,
blinkLed,
chThdCreateStatic(waBlinkLed4, sizeof(waBlinkLed4), NORMALPRIO, blinkLed,
&led4);
/*
* Start the serial driver with the default configuration.
*/
sdStart(&SD1, NULL);
/*
* Normal main() thread activity
*/
while (TRUE) {
if (!palReadPad(GPIOJ, GPIOJ_SW1)) {
TestThread(&SD1);
}
chThdSleepMilliseconds(100);
}

76
os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h
View File

@ -180,8 +180,8 @@
/*
* GPIOA Setup:
*
* PA0 - UART0 RX (alternate 1)
* PA1 - UART0 TX (alternate 1)
* PA0 - UART0 RX ()
* PA1 - UART0 TX ()
* PA2 - PIN2 ()
* PA3 - PIN3 ()
* PA4 - PIN4 ()
@ -207,8 +207,8 @@
PIN_DIR_IN(GPIOA_PIN6) | \
PIN_DIR_IN(GPIOA_PIN7))
#define VAL_GPIOA_AFSEL (PIN_AFSEL_ALTERNATE(GPIOA_UART0_RX) | \
PIN_AFSEL_ALTERNATE(GPIOA_UART0_TX) | \
#define VAL_GPIOA_AFSEL (PIN_AFSEL_GPIO(GPIOA_UART0_RX) | \
PIN_AFSEL_GPIO(GPIOA_UART0_TX) | \
PIN_AFSEL_GPIO(GPIOA_PIN2) | \
PIN_AFSEL_GPIO(GPIOA_PIN3) | \
PIN_AFSEL_GPIO(GPIOA_PIN4) | \
@ -294,8 +294,8 @@
PIN_SLR_DISABLE(GPIOA_PIN6) | \
PIN_SLR_DISABLE(GPIOA_PIN7))
#define VAL_GPIOA_PCTL (PIN_PCTL_MODE(GPIOA_UART0_RX, 1) | \
PIN_PCTL_MODE(GPIOA_UART0_TX, 1) | \
#define VAL_GPIOA_PCTL (PIN_PCTL_MODE(GPIOA_UART0_RX, 0) | \
PIN_PCTL_MODE(GPIOA_UART0_TX, 0) | \
PIN_PCTL_MODE(GPIOA_PIN2, 0) | \
PIN_PCTL_MODE(GPIOA_PIN3, 0) | \
PIN_PCTL_MODE(GPIOA_PIN4, 0) | \
@ -308,8 +308,8 @@
*
* PB0 - PIN0 ()
* PB1 - PIN1 ()
* PB2 - I2C0_SCL (alternate 3)
* PB3 - I2C0_SDA (alternate 3)
* PB2 - I2C0_SCL ()
* PB3 - I2C0_SDA ()
* PB4 - PIN4 ()
* PB5 - PIN5 ()
* PB6 - PIN6 ()
@ -317,8 +317,8 @@
*/
#define VAL_GPIOB_DATA (PIN_DATA_LOW(GPIOB_PIN0) | \
PIN_DATA_LOW(GPIOB_PIN1) | \
PIN_DATA_LOW(GPIOB_I2C0_SCL) | \
PIN_DATA_LOW(GPIOB_I2C0_SDA) | \
PIN_DATA_LOW(GPIOB_I2C0_SCL) | \
PIN_DATA_LOW(GPIOB_I2C0_SDA) | \
PIN_DATA_LOW(GPIOB_PIN4) | \
PIN_DATA_LOW(GPIOB_PIN5) | \
PIN_DATA_LOW(GPIOB_PIN6) | \
@ -326,8 +326,8 @@
#define VAL_GPIOB_DIR (PIN_DIR_IN(GPIOB_PIN0) | \
PIN_DIR_IN(GPIOB_PIN1) | \
PIN_DIR_IN(GPIOB_I2C0_SCL) | \
PIN_DIR_IN(GPIOB_I2C0_SDA) | \
PIN_DIR_IN(GPIOB_I2C0_SCL) | \
PIN_DIR_IN(GPIOB_I2C0_SDA) | \
PIN_DIR_IN(GPIOB_PIN4) | \
PIN_DIR_IN(GPIOB_PIN5) | \
PIN_DIR_IN(GPIOB_PIN6) | \
@ -335,8 +335,8 @@
#define VAL_GPIOB_AFSEL (PIN_AFSEL_GPIO(GPIOB_PIN0) | \
PIN_AFSEL_GPIO(GPIOB_PIN1) | \
PIN_AFSEL_ALTERNATE(GPIOB_I2C0_SCL) | \
PIN_AFSEL_ALTERNATE(GPIOB_I2C0_SDA) | \
PIN_AFSEL_GPIO(GPIOB_I2C0_SCL) | \
PIN_AFSEL_GPIO(GPIOB_I2C0_SDA) | \
PIN_AFSEL_GPIO(GPIOB_PIN4) | \
PIN_AFSEL_GPIO(GPIOB_PIN5) | \
PIN_AFSEL_GPIO(GPIOB_PIN6) | \
@ -344,8 +344,8 @@
#define VAL_GPIOB_DR2R (PIN_DRxR_ENABLE(GPIOB_PIN0) | \
PIN_DRxR_ENABLE(GPIOB_PIN1) | \
PIN_DRxR_ENABLE(GPIOB_I2C0_SCL) | \
PIN_DRxR_ENABLE(GPIOB_I2C0_SDA) | \
PIN_DRxR_ENABLE(GPIOB_I2C0_SCL) | \
PIN_DRxR_ENABLE(GPIOB_I2C0_SDA) | \
PIN_DRxR_ENABLE(GPIOB_PIN4) | \
PIN_DRxR_ENABLE(GPIOB_PIN5) | \
PIN_DRxR_ENABLE(GPIOB_PIN6) | \
@ -353,8 +353,8 @@
#define VAL_GPIOB_DR4R (PIN_DRxR_DISABLE(GPIOB_PIN0) | \
PIN_DRxR_DISABLE(GPIOB_PIN1) | \
PIN_DRxR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_DRxR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_DRxR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_DRxR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_DRxR_DISABLE(GPIOB_PIN4) | \
PIN_DRxR_DISABLE(GPIOB_PIN5) | \
PIN_DRxR_DISABLE(GPIOB_PIN6) | \
@ -362,8 +362,8 @@
#define VAL_GPIOB_DR8R (PIN_DRxR_DISABLE(GPIOB_PIN0) | \
PIN_DRxR_DISABLE(GPIOB_PIN1) | \
PIN_DRxR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_DRxR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_DRxR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_DRxR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_DRxR_DISABLE(GPIOB_PIN4) | \
PIN_DRxR_DISABLE(GPIOB_PIN5) | \
PIN_DRxR_DISABLE(GPIOB_PIN6) | \
@ -371,8 +371,8 @@
#define VAL_GPIOB_ODR (PIN_ODR_DISABLE(GPIOB_PIN0) | \
PIN_ODR_DISABLE(GPIOB_PIN1) | \
PIN_ODR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_ODR_ENABLE(GPIOB_I2C0_SDA) | \
PIN_ODR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_ODR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_ODR_DISABLE(GPIOB_PIN4) | \
PIN_ODR_DISABLE(GPIOB_PIN5) | \
PIN_ODR_DISABLE(GPIOB_PIN6) | \
@ -380,8 +380,8 @@
#define VAL_GPIOB_PUR (PIN_PxR_DISABLE(GPIOB_PIN0) | \
PIN_PxR_DISABLE(GPIOB_PIN1) | \
PIN_PxR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_PxR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_PxR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_PxR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_PxR_DISABLE(GPIOB_PIN4) | \
PIN_PxR_DISABLE(GPIOB_PIN5) | \
PIN_PxR_DISABLE(GPIOB_PIN6) | \
@ -389,8 +389,8 @@
#define VAL_GPIOB_PDR (PIN_PxR_DISABLE(GPIOB_PIN0) | \
PIN_PxR_DISABLE(GPIOB_PIN1) | \
PIN_PxR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_PxR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_PxR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_PxR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_PxR_DISABLE(GPIOB_PIN4) | \
PIN_PxR_DISABLE(GPIOB_PIN5) | \
PIN_PxR_DISABLE(GPIOB_PIN6) | \
@ -398,8 +398,8 @@
#define VAL_GPIOB_SLR (PIN_SLR_DISABLE(GPIOB_PIN0) | \
PIN_SLR_DISABLE(GPIOB_PIN1) | \
PIN_SLR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_SLR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_SLR_DISABLE(GPIOB_I2C0_SCL) | \
PIN_SLR_DISABLE(GPIOB_I2C0_SDA) | \
PIN_SLR_DISABLE(GPIOB_PIN4) | \
PIN_SLR_DISABLE(GPIOB_PIN5) | \
PIN_SLR_DISABLE(GPIOB_PIN6) | \
@ -407,8 +407,8 @@
#define VAL_GPIOB_DEN (PIN_DEN_ENABLE(GPIOB_PIN0) | \
PIN_DEN_ENABLE(GPIOB_PIN1) | \
PIN_DEN_ENABLE(GPIOB_I2C0_SCL) | \
PIN_DEN_ENABLE(GPIOB_I2C0_SDA) | \
PIN_DEN_ENABLE(GPIOB_I2C0_SCL) | \
PIN_DEN_ENABLE(GPIOB_I2C0_SDA) | \
PIN_DEN_ENABLE(GPIOB_PIN4) | \
PIN_DEN_ENABLE(GPIOB_PIN5) | \
PIN_DEN_ENABLE(GPIOB_PIN6) | \
@ -416,13 +416,13 @@
#define VAL_GPIOB_AMSEL (PIN_AMSEL_DISABLE(GPIOB_PIN0) | \
PIN_AMSEL_DISABLE(GPIOB_PIN1) | \
PIN_AMSEL_DISABLE(GPIOB_I2C0_SCL) | \
PIN_AMSEL_DISABLE(GPIOB_I2C0_SCL) | \
PIN_AMSEL_DISABLE(GPIOB_I2C0_SDA))
#define VAL_GPIOB_PCTL (PIN_PCTL_MODE(GPIOB_PIN0, 0) | \
PIN_PCTL_MODE(GPIOB_PIN1, 0) | \
PIN_PCTL_MODE(GPIOB_I2C0_SCL, 3) | \
PIN_PCTL_MODE(GPIOB_I2C0_SDA, 3) | \
PIN_PCTL_MODE(GPIOB_I2C0_SCL, 0) | \
PIN_PCTL_MODE(GPIOB_I2C0_SDA, 0) | \
PIN_PCTL_MODE(GPIOB_PIN4, 0) | \
PIN_PCTL_MODE(GPIOB_PIN5, 0) | \
PIN_PCTL_MODE(GPIOB_PIN6, 0) | \
@ -827,9 +827,9 @@
PIN_DATA_LOW(GPIOF_PIN7))
#define VAL_GPIOF_DIR (PIN_DIR_IN(GPIOF_SW2) | \
PIN_DIR_OUT(GPIOF_LED_RED) | \
PIN_DIR_OUT(GPIOF_LED_BLUE) | \
PIN_DIR_OUT(GPIOF_LED_GREEN) | \
PIN_DIR_IN(GPIOF_LED_RED) | \
PIN_DIR_IN(GPIOF_LED_BLUE) | \
PIN_DIR_IN(GPIOF_LED_GREEN) | \
PIN_DIR_IN(GPIOF_SW1) | \
PIN_DIR_IN(GPIOF_PIN5) | \
PIN_DIR_IN(GPIOF_PIN6) | \
@ -880,11 +880,11 @@
PIN_ODR_DISABLE(GPIOF_PIN6) | \
PIN_ODR_DISABLE(GPIOF_PIN7))
#define VAL_GPIOF_PUR (PIN_PxR_ENABLE(GPIOF_SW2) | \
#define VAL_GPIOF_PUR (PIN_PxR_DISABLE(GPIOF_SW2) | \
PIN_PxR_DISABLE(GPIOF_LED_RED) | \
PIN_PxR_DISABLE(GPIOF_LED_BLUE) | \
PIN_PxR_DISABLE(GPIOF_LED_GREEN) | \
PIN_PxR_ENABLE(GPIOF_SW1) | \
PIN_PxR_DISABLE(GPIOF_SW1) | \
PIN_PxR_DISABLE(GPIOF_PIN5) | \
PIN_PxR_DISABLE(GPIOF_PIN6) | \
PIN_PxR_DISABLE(GPIOF_PIN7))

18
os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h
View File

@ -208,7 +208,7 @@
*/
#define VAL_GPIOA_DATA 0b00000000
#define VAL_GPIOA_DIR 0b00000000
#define VAL_GPIOA_AFSEL 0b00000011
#define VAL_GPIOA_AFSEL 0b00000000
#define VAL_GPIOA_DR2R 0b11111111
#define VAL_GPIOA_DR4R 0b00000000
#define VAL_GPIOA_DR8R 0b00000000
@ -218,21 +218,21 @@
#define VAL_GPIOA_SLR 0b00000000
#define VAL_GPIOA_DEN 0b11111111
#define VAL_GPIOA_AMSEL 0b0000
#define VAL_GPIOA_PCTL 0x00000011
#define VAL_GPIOA_PCTL 0x00000000
#define VAL_GPIOB_DATA 0b00000000
#define VAL_GPIOB_DIR 0b00000000
#define VAL_GPIOB_AFSEL 0b00001100
#define VAL_GPIOB_AFSEL 0b00000000
#define VAL_GPIOB_DR2R 0b11111111
#define VAL_GPIOB_DR4R 0b00000000
#define VAL_GPIOB_DR8R 0b00000000
#define VAL_GPIOB_ODR 0b00001000
#define VAL_GPIOB_ODR 0b00000000
#define VAL_GPIOB_PUR 0b00000000
#define VAL_GPIOB_PDR 0b00000000
#define VAL_GPIOB_SLR 0b00000000
#define VAL_GPIOB_DEN 0b11111111
#define VAL_GPIOB_AMSEL 0b0000
#define VAL_GPIOB_PCTL 0x00003300
#define VAL_GPIOB_PCTL 0x00000000
#define VAL_GPIOC_DATA 0b00000000
#define VAL_GPIOC_DIR 0b00001000
@ -277,8 +277,8 @@
#define VAL_GPIOE_PCTL 0x00000000
#define VAL_GPIOF_DATA 0b00000000
#define VAL_GPIOF_DIR 0b00010011
#define VAL_GPIOF_AFSEL 0b00010011
#define VAL_GPIOF_DIR 0b00000000
#define VAL_GPIOF_AFSEL 0b00000000
#define VAL_GPIOF_DR2R 0b11111111
#define VAL_GPIOF_DR4R 0b00000000
#define VAL_GPIOF_DR8R 0b00000000
@ -288,7 +288,7 @@
#define VAL_GPIOF_SLR 0b00000000
#define VAL_GPIOF_DEN 0b11111111
#define VAL_GPIOF_AMSEL 0b0000
#define VAL_GPIOF_PCTL 0x00050055
#define VAL_GPIOF_PCTL 0x00000000
#define VAL_GPIOG_DATA 0b00000000
#define VAL_GPIOG_DIR 0b00000000
@ -375,7 +375,7 @@
#define VAL_GPIOM_PCTL 0x00000000
#define VAL_GPION_DATA 0b00000000
#define VAL_GPION_DIR 0b00000011
#define VAL_GPION_DIR 0b00000000
#define VAL_GPION_AFSEL 0b00000000
#define VAL_GPION_DR2R 0b11111111
#define VAL_GPION_DR4R 0b00000000

410
os/hal/ports/TIVA/LLD/pal_lld.c
View File

@ -30,94 +30,206 @@
/* Driver local definitions. */
/*===========================================================================*/
#define RCGCGPIOA (1 << 0)
#define RCGCGPIOB (1 << 1)
#define RCGCGPIOC (1 << 2)
#define RCGCGPIOD (1 << 3)
#define RCGCGPIOE (1 << 4)
#define RCGCGPIOF (1 << 5)
#if TIVA_HAS_GPIOA || defined(__DOXYGEN__)
#define GPIOA_BIT (1 << 0)
#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x)
#define GPIOA_AHB_BIT (1 << 0)
#else
#define GPIOA_AHB_BIT 0
#endif
#else
#define GPIOA_BIT 0
#define GPIOA_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOB || defined(__DOXYGEN__)
#define GPIOB_BIT (1 << 1)
#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x)
#define GPIOB_AHB_BIT (1 << 1)
#else
#define GPIOB_AHB_BIT 0
#endif
#else
#define GPIOB_BIT 0
#define GPIOB_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOC || defined(__DOXYGEN__)
#define GPIOC_BIT (1 << 2)
#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x)
#define GPIOC_AHB_BIT (1 << 2)
#else
#define GPIOC_AHB_BIT 0
#endif
#else
#define GPIOC_BIT 0
#define GPIOC_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOD || defined(__DOXYGEN__)
#define GPIOD_BIT (1 << 3)
#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x)
#define GPIOD_AHB_BIT (1 << 3)
#else
#define GPIOD_AHB_BIT 0
#endif
#else
#define GPIOD_BIT 0
#define GPIOD_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOE || defined(__DOXYGEN__)
#define GPIOE_BIT (1 << 4)
#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x)
#define GPIOE_AHB_BIT (1 << 4)
#else
#define GPIOE_AHB_BIT 0
#endif
#else
#define GPIOE_BIT 0
#define GPIOE_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOF || defined(__DOXYGEN__)
#define GPIOF_BIT (1 << 5)
#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x)
#define GPIOF_AHB_BIT (1 << 5)
#else
#define GPIOF_AHB_BIT 0
#endif
#else
#define GPIOF_BIT 0
#define GPIOF_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
#define RCGCGPIOG (1 << 6)
#define GPIOG_BIT (1 << 6)
#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x)
#define GPIOG_AHB_BIT (1 << 6)
#else
#define RCGCGPIOG 0
#define GPIOG_AHB_BIT 0
#endif
#else
#define GPIOG_BIT 0
#define GPIOG_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
#define RCGCGPIOH (1 << 7)
#define GPIOH_BIT (1 << 7)
#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x)
#define GPIOH_AHB_BIT (1 << 7)
#else
#define RCGCGPIOH 0
#define GPIOH_AHB_BIT 0
#endif
#else
#define GPIOH_BIT 0
#define GPIOH_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
#define RCGCGPIOJ (1 << 8)
#define GPIOJ_BIT (1 << 8)
#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x)
#define GPIOJ_AHB_BIT (1 << 8)
#else
#define RCGCGPIOJ 0
#define GPIOJ_AHB_BIT 0
#endif
#else
#define GPIOJ_BIT 0
#define GPIOJ_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
#define RCGCGPIOK (1 << 9)
#define GPIOK_BIT (1 << 9)
#define GPIOK_AHB_BIT (1 << 9)
#else
#define RCGCGPIOK 0
#define GPIOK_BIT 0
#define GPIOK_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
#define RCGCGPIOL (1 << 10)
#define GPIOL_BIT (1 << 10)
#define GPIOL_AHB_BIT (1 << 10)
#else
#define RCGCGPIOL 0
#define GPIOL_BIT 0
#define GPIOL_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
#define RCGCGPIOM (1 << 11)
#define GPIOM_BIT (1 << 11)
#define GPIOM_AHB_BIT (1 << 11)
#else
#define RCGCGPIOM 0
#define GPIOM_BIT 0
#define GPIOM_AHB_BIT 0
#endif
#if TIVA_HAS_GPION || defined(__DOXYGEN__)
#define RCGCGPION (1 << 12)
#define GPION_BIT (1 << 12)
#define GPION_AHB_BIT (1 << 12)
#else
#define RCGCGPION 0
#define GPION_BIT 0
#define GPION_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
#define RCGCGPIOP (1 << 13)
#define GPIOP_BIT (1 << 13)
#define GPIOP_AHB_BIT (1 << 13)
#else
#define RCGCGPIOP 0
#define GPIOP_BIT 0
#define GPIOP_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
#define RCGCGPIOQ (1 << 14)
#define GPIOQ_BIT (1 << 14)
#define GPIOQ_AHB_BIT (1 << 14)
#else
#define RCGCGPIOQ 0
#define GPIOQ_BIT 0
#define GPIOQ_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
#define RCGCGPIOR (1 << 15)
#define GPIOR_BIT (1 << 15)
#define GPIOR_AHB_BIT (1 << 15)
#else
#define RCGCGPIOR 0
#define GPIOR_BIT 0
#define GPIOR_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
#define RCGCGPIOS (1 << 16)
#define GPIOS_BIT (1 << 16)
#define GPIOS_AHB_BIT (1 << 16)
#else
#define RCGCGPIOS 0
#define GPIOS_BIT 0
#define GPIOS_AHB_BIT 0
#endif
#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
#define RCGCGPIOT (1 << 17)
#define GPIOT_BIT (1 << 17)
#define GPIOT_AHB_BIT (1 << 17)
#else
#define RCGCGPIOT 0
#define GPIOT_BIT 0
#define GPIOT_AHB_BIT 0
#endif
#define RCGCGPIO_VALUE (RCGCGPIOA | RCGCGPIOB | RCGCGPIOC | RCGCGPIOD | \
RCGCGPIOE | RCGCGPIOF | RCGCGPIOG | RCGCGPIOH | \
RCGCGPIOJ | RCGCGPIOK | RCGCGPIOL | RCGCGPIOM | \
RCGCGPION | RCGCGPIOP | RCGCGPIOQ | RCGCGPIOR | \
RCGCGPIOS | RCGCGPIOT)
#define RCGCGPIO_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \
GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \
GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT | \
GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT | \
GPIOS_BIT | GPIOR_BIT)
#define GPIOHBCTL_MASK (GPIOA_AHB_BIT | GPIOB_AHB_BIT | GPIOC_AHB_BIT | \
GPIOD_AHB_BIT | GPIOE_AHB_BIT | GPIOF_AHB_BIT | \
GPIOG_AHB_BIT | GPIOH_AHB_BIT | GPIOJ_AHB_BIT | \
GPIOK_AHB_BIT | GPIOL_AHB_BIT | GPIOM_AHB_BIT | \
GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT | \
GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT)
/* GPIO lock password.*/
#define TIVA_GPIO_LOCK_PWD 0x4C4F434B
#define GPIOC_JTAG_MASK (0x0F)
#define GPIOD_NMI_MASK (0x80)
#define GPIOF_NMI_MASK (0x01)
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@ -130,21 +242,40 @@
/* Driver local functions. */
/*===========================================================================*/
void gpio_init (GPIO_TypeDef *gpiop, const tiva_gpio_setup_t *config)
/**
* @brief Initializes the port with the port configuration.
*
* @param[in] port the port identifier
* @param[in] config the port configuration
*/
static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config)
{
gpiop->DATA = config->data;
gpiop->DIR = config->dir;
gpiop->AFSEL = config->afsel;
gpiop->DR2R = config->dr2r;
gpiop->DR4R = config->dr4r;
gpiop->DR8R = config->dr8r;
gpiop->ODR = config->odr;
gpiop->PUR = config->pur;
gpiop->PDR = config->pdr;
gpiop->SLR = config->slr;
gpiop->DEN = config->den;
gpiop->AMSEL = config->amsel;
gpiop->PCTL = config->pctl;
port->DATA = config->data;
port->DIR = config->dir;
port->AFSEL = config->afsel;
port->DR2R = config->dr2r;
port->DR4R = config->dr4r;
port->DR8R = config->dr8r;
port->ODR = config->odr;
port->PUR = config->pur;
port->PDR = config->pdr;
port->SLR = config->slr;
port->DEN = config->den;
port->AMSEL = config->amsel;
port->PCTL = config->pctl;
}
/**
* @brief Unlocks the masked pins of the GPIO peripheral.
* @note This function is only useful for PORTC0-3, PORTD7 and PORTF0.
*
* @param[in] port the port identifier
* @param[in] mask the pin mask
*/
static void gpio_unlock(ioportid_t port, ioportmask_t mask)
{
port->LOCK = TIVA_GPIO_LOCK_PWD;
port->CR = mask;
}
/*===========================================================================*/
@ -156,86 +287,87 @@ void gpio_init (GPIO_TypeDef *gpiop, const tiva_gpio_setup_t *config)
/*===========================================================================*/
/**
* @brief TIVA I/O ports configuration.
* @brief Tiva I/O ports configuration.
* @details Ports A-F (G, H, J, K, L, M, N, P, Q, R, S, T) clocks enabled.
*
* @param[in] config the TIVA ports configuration
* @param[in] config the Tiva ports configuration
*
* @notapi
*/
void _pal_lld_init(const PALConfig *config)
{
SYSCTL->RCGCGPIO = RCGCGPIO_VALUE;
/*
* Enables all GPIO clocks.
*/
SYSCTL->RCGCGPIO = RCGCGPIO_MASK;
#if defined(TM4C123x)
SYSCTL->GPIOHBCTL = GPIOHBCTL_MASK;
#endif
__NOP();
__NOP();
__NOP();
/* Wait until all GPIO modules are ready */
while (!((SYSCTL->PRGPIO & RCGCGPIO_MASK) == RCGCGPIO_MASK))
;
#if TIVA_HAS_GPIOA
gpio_init(GPIOA, &config->PAData);
#endif
#if TIVA_HAS_GPIOB
gpio_init(GPIOB, &config->PBData);
GPIOC->LOCK = TIVA_GPIO_LOCK_PWD;
GPIOC->CR = 0x01;
#endif
#if TIVA_HAS_GPIOC
/* Unlock JTAG pins.*/
gpio_unlock(GPIOC, GPIOC_JTAG_MASK);
gpio_init(GPIOC, &config->PCData);
GPIOC->LOCK = 0;
#endif
#if TIVA_HAS_GPIOD
/* Unlock NMI pin.*/
gpio_unlock(GPIOD, GPIOD_NMI_MASK);
gpio_init(GPIOD, &config->PDData);
#endif
#if TIVA_HAS_GPIOE
gpio_init(GPIOE, &config->PEData);
GPIOF->LOCK = TIVA_GPIO_LOCK_PWD;
GPIOF->CR = 0x01;
#endif
#if TIVA_HAS_GPIOF
/* Unlock NMI pin.*/
gpio_unlock(GPIOF, GPIOF_NMI_MASK);
gpio_init(GPIOF, &config->PFData);
GPIOF->LOCK = 0;
#endif
#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
gpio_init(GPIOG, &config->PGData);
#endif /* TIVA_HAS_GPIOG.*/
#endif
#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
gpio_init(GPIOH, &config->PHData);
#endif /* TIVA_HAS_GPIOH.*/
#endif
#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
gpio_init(GPIOJ, &config->PJData);
#endif /* TIVA_HAS_GPIOJ.*/
#endif
#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
gpio_init(GPIOK, &config->PKData);
#endif /* TIVA_HAS_GPIOK.*/
#endif
#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
gpio_init(GPIOL, &config->PLData);
#endif /* TIVA_HAS_GPIOL.*/
#endif
#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
gpio_init(GPIOM, &config->PMData);
#endif /* TIVA_HAS_GPIOM.*/
#endif
#if TIVA_HAS_GPION || defined(__DOXYGEN__)
gpio_init(GPION, &config->PNData);
#endif /* TIVA_HAS_GPION.*/
#endif
#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
gpio_init(GPIOP, &config->PPData);
#endif /* TIVA_HAS_GPIOP.*/
#endif
#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
gpio_init(GPIOQ, &config->PQData);
#endif /* TIVA_HAS_GPIOQ.*/
#endif
#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
gpio_init(GPIOR, &config->PRData);
#endif /* TIVA_HAS_GPIOR.*/
#endif
#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
gpio_init(GPIOS, &config->PSData);
#endif /* TIVA_HAS_GPIOS.*/
#endif
#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
gpio_init(GPIOT, &config->PTData);
#endif /* TIVA_HAS_GPIOT.*/
#endif
}
/**
@ -249,61 +381,61 @@ void _pal_lld_init(const PALConfig *config)
*
* @notapi
*/
void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask,
iomode_t mode)
void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode)
{
/* TODO: What does this function exactly do? The pins are already configured
* in board.h and initialized by the pal driver. */
uint32_t dir = (mode & PAL_TIVA_DIR_MASK) >> 0;
uint32_t afsel = (mode & PAL_TIVA_AFSEL_MASK) >> 1;
uint32_t dr2r = (mode & PAL_TIVA_DR2R_MASK) >> 2;
uint32_t dr4r = (mode & PAL_TIVA_DR4R_MASK) >> 3;
uint32_t dr8r = (mode & PAL_TIVA_DR8R_MASK) >> 4;
uint32_t odr = (mode & PAL_TIVA_ODR_MASK) >> 5;
uint32_t pur = (mode & PAL_TIVA_PUR_MASK) >> 6;
uint32_t pdr = (mode & PAL_TIVA_PDR_MASK) >> 7;
uint32_t slr = (mode & PAL_TIVA_SLR_MASK) >> 8;
uint32_t den = (mode & PAL_TIVA_DEN_MASK) >> 9;
uint32_t amsel = (mode & PAL_TIVA_AMSEL_MASK) >> 10;
uint32_t pctl = (mode & PAL_TIVA_PCTL_MASK) >> 11;
uint32_t bit = 0;
(void) port;
(void) mask;
(void) mode;
while(TRUE) {
uint32_t pctl_mask = (7 << (4 * bit));
uint32_t bit_mask = (1 << bit);
/*
switch (mode) {
case PAL_MODE_UNCONNECTED:
case PAL_MODE_INPUT_PULLUP:
port->PUR |= mask;
case PAL_MODE_INPUT:
port->AFSEL &= ~mask;
port->DIR &= ~mask;
port->ODR &= ~mask;
port->DEN |= mask;
break;
if ((mask & 1) != 0) {
port->DIR = (port->DIR & ~bit_mask) | dir;
port->AFSEL = (port->AFSEL & ~bit_mask) | afsel;
port->DR2R = (port->DR2R & ~bit_mask) | dr2r;
port->DR4R = (port->DR4R & ~bit_mask) | dr4r;
port->DR8R = (port->DR8R & ~bit_mask) | dr8r;
port->ODR = (port->ODR & ~bit_mask) | odr;
port->PUR = (port->PUR & ~bit_mask) | pur;
port->PDR = (port->PDR & ~bit_mask) | pdr;
port->SLR = (port->SLR & ~bit_mask) | slr;
port->DEN = (port->DEN & ~bit_mask) | den;
port->AMSEL = (port->AMSEL & ~bit_mask) | amsel;
port->PCTL = (port->PCTL & ~pctl_mask) | pctl;
}
case PAL_MODE_INPUT_PULLDOWN:
port->AFSEL &= ~mask;
port->DIR &= ~mask;
port->ODR &= ~mask;
port->DEN |= mask;
port->PDR |= mask;
break;
mask >>= 1;
if (!mask) {
return;
}
case PAL_MODE_RESET:
case PAL_MODE_INPUT_ANALOG:
port->AFSEL &= ~mask;
port->DIR &= ~mask;
port->ODR &= ~mask;
port->DEN &= ~mask;
port->PUR &= ~mask;
port->PDR &= ~mask;
break;
dir <<= 1;
afsel <<= 1;
dr2r <<= 1;
dr4r <<= 1;
dr8r <<= 1;
odr <<= 1;
pur <<= 1;
pdr <<= 1;
slr <<= 1;
den <<= 1;
amsel <<= 1;
pctl <<= 4;
case PAL_MODE_OUTPUT_PUSHPULL:
port->AFSEL &= ~mask;
port->DIR |= mask;
port->ODR &= ~mask;
port->DEN |= mask;
break;
case PAL_MODE_OUTPUT_OPENDRAIN:
port->AFSEL &= ~mask;
port->DIR |= mask;
port->ODR |= mask;
port->DEN |= mask;
break;
}*/
bit++;
}
}
#endif /* HAL_USE_PAL */

492
os/hal/ports/TIVA/LLD/pal_lld.h
View File

@ -28,14 +28,400 @@
#if HAL_USE_PAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Unsupported modes and specific modes */
/* Driver constants. */
/*===========================================================================*/
#undef PAL_MODE_RESET
#undef PAL_MODE_UNCONNECTED
#undef PAL_MODE_INPUT
#undef PAL_MODE_INPUT_PULLUP
#undef PAL_MODE_INPUT_PULLDOWN
#undef PAL_MODE_INPUT_ANALOG
#undef PAL_MODE_OUTPUT_PUSHPULL
#undef PAL_MODE_OUTPUT_OPENDRAIN
/**
* @name TIVA-specific I/O mode flags
* @{
*/
#define PAL_TIVA_DIR_MASK (1 << 0)
#define PAL_TIVA_DIR_INPUT (0 << 0)
#define PAL_TIVA_DIR_OUTPUT (1 << 0)
#define PAL_TIVA_AFSEL_MASK (1 << 1)
#define PAL_TIVA_AFSEL_GPIO (0 << 1)
#define PAL_TIVA_AFSEL_ALTERNATE (1 << 1)
#define PAL_TIVA_DR2R_MASK (1 << 2)
#define PAL_TIVA_DR2R_DISABLE (0 << 2)
#define PAL_TIVA_DR2R_ENABLE (1 << 2)
#define PAL_TIVA_DR4R_MASK (1 << 3)
#define PAL_TIVA_DR4R_DISABLE (0 << 3)
#define PAL_TIVA_DR4R_ENABLE (1 << 3)
#define PAL_TIVA_DR8R_MASK (1 << 4)
#define PAL_TIVA_DR8R_DISABLE (0 << 4)
#define PAL_TIVA_DR8R_ENABLE (1 << 4)
#define PAL_TIVA_ODR_MASK (1 << 5)
#define PAL_TIVA_ODR_PUSHPULL (0 << 5)
#define PAL_TIVA_ODR_OPENDRAIN (1 << 5)
#define PAL_TIVA_PUR_MASK (1 << 6)
#define PAL_TIVA_PUR_DISABLE (0 << 6)
#define PAL_TIVA_PUR_ENABLE (1 << 6)
#define PAL_TIVA_PDR_MASK (1 << 7)
#define PAL_TIVA_PDR_DISABLE (0 << 7)
#define PAL_TIVA_PDR_ENABLE (1 << 7)
#define PAL_TIVA_SLR_MASK (1 << 8)
#define PAL_TIVA_SLR_DISABLE (0 << 8)
#define PAL_TIVA_SLR_ENABLE (1 << 8)
#define PAL_TIVA_DEN_MASK (1 << 9)
#define PAL_TIVA_DEN_DISABLE (0 << 9)
#define PAL_TIVA_DEN_ENABLE (1 << 9)
#define PAL_TIVA_AMSEL_MASK (1 << 10)
#define PAL_TIVA_AMSEL_DISABLE (0 << 10)
#define PAL_TIVA_AMSEL_ENABLE (1 << 10)
#define PAL_TIVA_PCTL_MASK (7 << 11)
#define PAL_TIVA_PCTL(n) ((n) << 11)
/**
* @brief Alternate function.
*
* @param[in] n alternate function selector
*/
#define PAL_MODE_ALTERNATE(n) (PAL_TIVA_AFSEL_ALTERNATE | \
PAL_TIVA_PCTL(n))
/**
* @}
*/
/**
* @name Standard I/O mode flags
* @{
*/
/**
* @brief This mode is implemented as input.
*/
#define PAL_MODE_RESET PAL_MODE_INPUT
/**
* @brief This mode is implemented as input with pull-up.
*/
#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP
/**
* @brief Regular input high-Z pad.
*/
#define PAL_MODE_INPUT (PAL_TIVA_DEN_ENABLE | \
PAL_TIVA_DIR_INPUT)
/**
* @brief Input pad with weak pull up resistor.
*/
#define PAL_MODE_INPUT_PULLUP (PAL_TIVA_DIR_INPUT | \
PAL_TIVA_PUR_ENABLE | \
PAL_TIVA_DEN_ENABLE)
/**
* @brief Input pad with weak pull down resistor.
*/
#define PAL_MODE_INPUT_PULLDOWN (PAL_TIVA_DIR_INPUT | \
PAL_TIVA_PDR_ENABLE | \
PAL_TIVA_DEN_ENABLE)
/**
* @brief Analog input mode.
*/
#define PAL_MODE_INPUT_ANALOG (PAL_TIVA_DEN_DISABLE | \
PAL_TIVA_AMSEL_ENABLE)
/**
* @brief Push-pull output pad.
*/
#define PAL_MODE_OUTPUT_PUSHPULL (PAL_TIVA_DIR_OUTPUT | \
PAL_TIVA_DR2R_ENABLE | \
PAL_TIVA_ODR_PUSHPULL | \
PAL_TIVA_DEN_ENABLE)
/**
* @brief Open-drain output pad.
*/
#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_TIVA_DIR_OUTPUT | \
PAL_TIVA_DR2R_ENABLE | \
PAL_TIVA_ODR_OPENDRAIN | \
PAL_TIVA_DEN_ENABLE)
/**
* @}
*/
/** @brief GPIOA port identifier.*/
#define IOPORT1 GPIOA
/** @brief GPIOB port identifier.*/
#define IOPORT2 GPIOB
/** @brief GPIOC port identifier.*/
#define IOPORT3 GPIOC
/** @brief GPIOD port identifier.*/
#define IOPORT4 GPIOD
/** @brief GPIOE port identifier.*/
#define IOPORT5 GPIOE
/** @brief GPIOF port identifier.*/
#define IOPORT6 GPIOF
#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
/** @brief Port G setup data.*/
#define IOPORT7 GPIOG
#endif /* TIVA_HAS_GPIOG.*/
#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
/** @brief Port H setup data.*/
#define IOPORT8 GPIOH
#endif /* TIVA_HAS_GPIOH.*/
#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
/** @brief Port J setup data.*/
#define IOPORT9 GPIOJ
#endif /* TIVA_HAS_GPIOJ.*/
#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
/** @brief Port K setup data.*/
#define IOPORT10 GPIOK
#endif /* TIVA_HAS_GPIOK.*/
#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
/** @brief Port L setup data.*/
#define IOPORT11 GPIOL
#endif /* TIVA_HAS_GPIOL.*/
#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
/** @brief Port M setup data.*/
#define IOPORT12 GPIOM
#endif /* TIVA_HAS_GPIOM.*/
#if TIVA_HAS_GPION || defined(__DOXYGEN__)
/** @brief Port N setup data.*/
#define IOPORT13 GPION
#endif /* TIVA_HAS_GPION.*/
#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
/** @brief Port P setup data.*/
#define IOPORT14 GPIOP
#endif /* TIVA_HAS_GPIOP.*/
#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
/** @brief Port Q setup data.*/
#define IOPORT15 GPIOQ
#endif /* TIVA_HAS_GPIOQ.*/
#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
/** @brief Port R setup data.*/
#define IOPORT16 GPIOR
#endif /* TIVA_HAS_GPIOR.*/
#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
/** @brief Port S setup data.*/
#define IOPORT17 GPIOS
#endif /* TIVA_HAS_GPIOS.*/
#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
/** @brief Port T setup data.*/
#define IOPORT18 GPIOT
#endif /* TIVA_HAS_GPIOT.*/
/**
* @brief Width, in bits, of an I/O port.
*/
#define PAL_IOPORTS_WIDTH 8
/**
* @brief Whole port mask.
* @brief This macro specifies all the valid bits into a port.
*/
#define PAL_WHOLE_PORT ((ioportmask_t)0xFF)
/*===========================================================================*/
/* I/O Ports Types and constants. */
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
#if defined(TM4C123x)
/**
* @brief GPIOA AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOA. When set
* to @p FALSE the APB bus is used to access GPIOA.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOA_USE_AHB TRUE
#endif
/**
* @brief GPIOB AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOB. When set
* to @p FALSE the APB bus is used to access GPIOB.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOB_USE_AHB TRUE
#endif
/**
* @brief GPIOC AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOC. When set
* to @p FALSE the APB bus is used to access GPIOC.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOC_USE_AHB TRUE
#endif
/**
* @brief GPIOD AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOD. When set
* to @p FALSE the APB bus is used to access GPIOD.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOD_USE_AHB TRUE
#endif
/**
* @brief GPIOE AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOE. When set
* to @p FALSE the APB bus is used to access GPIOE.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOE_USE_AHB TRUE
#endif
/**
* @brief GPIOF AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOF. When set
* to @p FALSE the APB bus is used to access GPIOF.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOF_USE_AHB TRUE
#endif
/**
* @brief GPIOG AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOG. When set
* to @p FALSE the APB bus is used to access GPIOG.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOG_USE_AHB TRUE
#endif
/**
* @brief GPIOH AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOH. When set
* to @p FALSE the APB bus is used to access GPIOH.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOH_USE_AHB TRUE
#endif
/**
* @brief GPIOJ AHB enable switch.
* @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set
* to @p FALSE the APB bus is used to access GPIOJ.
* @note The default is TRUE.
*/
#if !defined(TIVA_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__)
#define TIVA_GPIO_GPIOJ_USE_AHB TRUE
#endif
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if defined(TM4C123x)
#if TIVA_GPIO_GPIOA_USE_AHB
#define GPIOA GPIOA_AHB
#else
#define GPIOA GPIOA_APB
#endif
#if TIVA_GPIO_GPIOB_USE_AHB
#define GPIOB GPIOB_AHB
#else
#define GPIOB GPIOB_APB
#endif
#if TIVA_GPIO_GPIOC_USE_AHB
#define GPIOC GPIOC_AHB
#else
#define GPIOC GPIOC_APB
#endif
#if TIVA_GPIO_GPIOD_USE_AHB
#define GPIOD GPIOD_AHB
#else
#define GPIOD GPIOD_APB
#endif
#if TIVA_GPIO_GPIOE_USE_AHB
#define GPIOE GPIOE_AHB
#else
#define GPIOE GPIOE_APB
#endif
#if TIVA_GPIO_GPIOF_USE_AHB
#define GPIOF GPIOF_AHB
#else
#define GPIOF GPIOF_APB
#endif
#if TIVA_GPIO_GPIOG_USE_AHB
#define GPIOG GPIOG_AHB
#else
#define GPIOG GPIOG_APB
#endif
#if TIVA_GPIO_GPIOH_USE_AHB
#define GPIOH GPIOH_AHB
#else
#define GPIOH GPIOH_APB
#endif
#if TIVA_GPIO_GPIOJ_USE_AHB
#define GPIOJ GPIOJ_AHB
#else
#define GPIOJ GPIOJ_APB
#endif
#define GPIOK GPIOK_AHB
#define GPIOL GPIOL_AHB
#define GPIOM GPIOM_AHB
#define GPION GPION_AHB
#define GPIOP GPIOP_AHB
#define GPIOQ GPIOQ_AHB
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief GPIO port setup info.
*/
typedef struct
@ -151,17 +537,6 @@ typedef struct
#endif /* TIVA_HAS_GPIOT.*/
} PALConfig;
/**
* @brief Width, in bits, of an I/O port.
*/
#define PAL_IOPORTS_WIDTH 8
/**
* @brief Whole port mask.
* @brief This macro specifies all the valid bits into a port.
*/
#define PAL_WHOLE_PORT ((ioportmask_t)0xFF)
/**
* @brief Digital I/O port sized unsigned type.
*/
@ -178,90 +553,7 @@ typedef uint32_t iomode_t;
typedef GPIO_TypeDef *ioportid_t;
/*===========================================================================*/
/* I/O Ports Identifiers. */
/*===========================================================================*/
/** @brief GPIOA port identifier.*/
#define IOPORT1 GPIOA
/** @brief GPIOB port identifier.*/
#define IOPORT2 GPIOB
/** @brief GPIOC port identifier.*/
#define IOPORT3 GPIOC
/** @brief GPIOD port identifier.*/
#define IOPORT4 GPIOD
/** @brief GPIOE port identifier.*/
#define IOPORT5 GPIOE
/** @brief GPIOF port identifier.*/
#define IOPORT6 GPIOF
#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
/** @brief Port G setup data.*/
#define IOPORT7 GPIOG
#endif /* TIVA_HAS_GPIOG.*/
#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
/** @brief Port H setup data.*/
#define IOPORT8 GPIOH
#endif /* TIVA_HAS_GPIOH.*/
#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
/** @brief Port J setup data.*/
#define IOPORT9 GPIOJ
#endif /* TIVA_HAS_GPIOJ.*/
#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
/** @brief Port K setup data.*/
#define IOPORT10 GPIOK
#endif /* TIVA_HAS_GPIOK.*/
#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
/** @brief Port L setup data.*/
#define IOPORT11 GPIOL
#endif /* TIVA_HAS_GPIOL.*/
#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
/** @brief Port M setup data.*/
#define IOPORT12 GPIOM
#endif /* TIVA_HAS_GPIOM.*/
#if TIVA_HAS_GPION || defined(__DOXYGEN__)
/** @brief Port N setup data.*/
#define IOPORT13 GPION
#endif /* TIVA_HAS_GPION.*/
#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
/** @brief Port P setup data.*/
#define IOPORT14 GPIOP
#endif /* TIVA_HAS_GPIOP.*/
#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
/** @brief Port Q setup data.*/
#define IOPORT15 GPIOQ
#endif /* TIVA_HAS_GPIOQ.*/
#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
/** @brief Port R setup data.*/
#define IOPORT16 GPIOR
#endif /* TIVA_HAS_GPIOR.*/
#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
/** @brief Port S setup data.*/
#define IOPORT17 GPIOS
#endif /* TIVA_HAS_GPIOS.*/
#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
/** @brief Port T setup data.*/
#define IOPORT18 GPIOT
#endif /* TIVA_HAS_GPIOT.*/
/*===========================================================================*/
/* Implementation, some of the following macros could be implemented as */
/* functions, if so please put them in pal_lld.c. */
/* Driver macros. */
/*===========================================================================*/
/**
@ -442,6 +734,10 @@ typedef GPIO_TypeDef *ioportid_t;
#define pal_lld_clearpad(port, pad) \
((port)->MASKED_ACCESS[1 << (pad)] = 0)
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern const PALConfig pal_default_config;
#endif

7
os/hal/ports/TIVA/TM4C123x/tiva_registry.h
View File

@ -58,6 +58,13 @@
#error "No valid device defined."
#endif
/**
* @brief Sub-family identifier.
*/
#if !defined(TM4C123x) || defined(__DOXYGEN__)
#define TM4C123x
#endif
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/

258
os/hal/ports/TIVA/TM4C123x/tm4c123x.h
View File

@ -784,68 +784,77 @@ typedef struct
* @{
*/
#define SYSCTL_BASE 0x400FE000
#define HIB_BASE 0x400FC000
#define FLASH_BASE 0x400FD000
#define EEPROM_BASE 0x400AF000
#define UDMA_BASE 0x400FF000
#define GPIOA_BASE 0x40004000
#define GPIOB_BASE 0x40005000
#define GPIOC_BASE 0x40006000
#define GPIOD_BASE 0x40007000
#define GPIOE_BASE 0x40024000
#define GPIOF_BASE 0x40025000
#define GPIOG_BASE 0x40026000
#define GPIOH_BASE 0x40027000
#define GPIOJ_BASE 0x4003D000
#define GPIOK_BASE 0x40061000
#define GPIOL_BASE 0x40062000
#define GPIOM_BASE 0x40063000
#define GPION_BASE 0x40064000
#define GPIOP_BASE 0x40065000
#define GPIOQ_BASE 0x40066000
#define GPT0_BASE 0x40030000
#define GPT1_BASE 0x40031000
#define GPT2_BASE 0x40032000
#define GPT3_BASE 0x40033000
#define GPT4_BASE 0x40034000
#define GPT5_BASE 0x40035000
#define WGPT0_BASE 0x40036000
#define WGPT1_BASE 0x40037000
#define WGPT2_BASE 0x4004C000
#define WGPT3_BASE 0x4004D000
#define WGPT4_BASE 0x4004E000
#define WGPT5_BASE 0x4004F000
#define WDT0_BASE 0x40000000
#define WDT1_BASE 0x40001000
#define ADC0_BASE 0x40038000
#define ADC1_BASE 0x40039000
#define UART0_BASE 0x4000C000
#define UART1_BASE 0x4000D000
#define UART2_BASE 0x4000E000
#define UART3_BASE 0x4000F000
#define UART4_BASE 0x40010000
#define UART5_BASE 0x40011000
#define UART6_BASE 0x40012000
#define UART7_BASE 0x40013000
#define SSI0_BASE 0x40008000
#define SSI1_BASE 0x40009000
#define SSI2_BASE 0x4000A000
#define SSI3_BASE 0x4000B000
#define I2C0_BASE 0x40020000
#define I2C1_BASE 0x40021000
#define I2C2_BASE 0x40022000
#define I2C3_BASE 0x40023000
#define I2C4_BASE 0x40023000
#define I2C5_BASE 0x40023000
#define CAN0_BASE 0x40040000
#define CAN1_BASE 0x40041000
#define SYSCTL_BASE 0x400FE000
#define HIB_BASE 0x400FC000
#define FLASH_BASE 0x400FD000
#define EEPROM_BASE 0x400AF000
#define UDMA_BASE 0x400FF000
#define GPIOA_APB_BASE 0x40004000
#define GPIOA_AHB_BASE 0x40058000
#define GPIOB_APB_BASE 0x40005000
#define GPIOB_AHB_BASE 0x40059000
#define GPIOC_APB_BASE 0x40006000
#define GPIOC_AHB_BASE 0x4005A000
#define GPIOD_APB_BASE 0x40007000
#define GPIOD_AHB_BASE 0x4005B000
#define GPIOE_APB_BASE 0x40024000
#define GPIOE_AHB_BASE 0x4005C000
#define GPIOF_APB_BASE 0x40025000
#define GPIOF_AHB_BASE 0x4005D000
#define GPIOG_APB_BASE 0x40026000
#define GPIOG_AHB_BASE 0x4005E000
#define GPIOH_APB_BASE 0x40027000
#define GPIOH_AHB_BASE 0x4005F000
#define GPIOJ_APB_BASE 0x4003D000
#define GPIOJ_AHB_BASE 0x40060000
#define GPIOK_AHB_BASE 0x40061000
#define GPIOL_AHB_BASE 0x40062000
#define GPIOM_AHB_BASE 0x40063000
#define GPION_AHB_BASE 0x40064000
#define GPIOP_AHB_BASE 0x40065000
#define GPIOQ_AHB_BASE 0x40066000
#define GPT0_BASE 0x40030000
#define GPT1_BASE 0x40031000
#define GPT2_BASE 0x40032000
#define GPT3_BASE 0x40033000
#define GPT4_BASE 0x40034000
#define GPT5_BASE 0x40035000
#define WGPT0_BASE 0x40036000
#define WGPT1_BASE 0x40037000
#define WGPT2_BASE 0x4004C000
#define WGPT3_BASE 0x4004D000
#define WGPT4_BASE 0x4004E000
#define WGPT5_BASE 0x4004F000
#define WDT0_BASE 0x40000000
#define WDT1_BASE 0x40001000
#define ADC0_BASE 0x40038000
#define ADC1_BASE 0x40039000
#define UART0_BASE 0x4000C000
#define UART1_BASE 0x4000D000
#define UART2_BASE 0x4000E000
#define UART3_BASE 0x4000F000
#define UART4_BASE 0x40010000
#define UART5_BASE 0x40011000
#define UART6_BASE 0x40012000
#define UART7_BASE 0x40013000
#define SSI0_BASE 0x40008000
#define SSI1_BASE 0x40009000
#define SSI2_BASE 0x4000A000
#define SSI3_BASE 0x4000B000
#define I2C0_BASE 0x40020000
#define I2C1_BASE 0x40021000
#define I2C2_BASE 0x40022000
#define I2C3_BASE 0x40023000
#define I2C4_BASE 0x40023000
#define I2C5_BASE 0x40023000
#define CAN0_BASE 0x40040000
#define CAN1_BASE 0x40041000
// usb
#define ACMP_BASE 0x4003C000
#define PWM0_BASE 0x40028000
#define PWM1_BASE 0x40029000
#define QEI0_BASE 0x4002C000
#define QEI1_BASE 0x4002D000
#define ACMP_BASE 0x4003C000
#define PWM0_BASE 0x40028000
#define PWM1_BASE 0x40029000
#define QEI0_BASE 0x4002C000
#define QEI1_BASE 0x4002D000
/**
* @}
@ -856,66 +865,75 @@ typedef struct
* @{
*/
#define SYSCTL ((SYSCTL_TypeDef *) SYSCTL_BASE)
#define HIB ((HIB_TypeDef *) HIB_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_BASE)
#define EEPROM ((EEPROM_TypeDef *) EEPROM_BASE)
#define UDMA ((UDMA_TypeDef *) UDMA_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
#define GPIOL ((GPIO_TypeDef *) GPIOL_BASE)
#define GPIOM ((GPIO_TypeDef *) GPIOM_BASE)
#define GPION ((GPIO_TypeDef *) GPION_BASE)
#define GPIOP ((GPIO_TypeDef *) GPIOP_BASE)
#define GPIOQ ((GPIO_TypeDef *) GPIOQ_BASE)
#define GPT0 ((GPT_TypeDef *) GPT0_BASE)
#define GPT1 ((GPT_TypeDef *) GPT1_BASE)
#define GPT2 ((GPT_TypeDef *) GPT2_BASE)
#define GPT3 ((GPT_TypeDef *) GPT3_BASE)
#define GPT4 ((GPT_TypeDef *) GPT4_BASE)
#define GPT5 ((GPT_TypeDef *) GPT5_BASE)
#define WGPT0 ((GPT_TypeDef *) WGPT0_BASE)
#define WGPT1 ((GPT_TypeDef *) WGPT1_BASE)
#define WGPT2 ((GPT_TypeDef *) WGPT2_BASE)
#define WGPT3 ((GPT_TypeDef *) WGPT3_BASE)
#define WGPT4 ((GPT_TypeDef *) WGPT4_BASE)
#define WGPT5 ((GPT_TypeDef *) WGPT5_BASE)
#define ADC0 ((ADC_TypeDef*) ADC0_BASE)
#define ADC1 ((ADC_TypeDef*) ADC1_BASE)
#define UART0 ((UART_TypeDef *) UART0_BASE)
#define UART1 ((UART_TypeDef *) UART1_BASE)
#define UART2 ((UART_TypeDef *) UART2_BASE)
#define UART3 ((UART_TypeDef *) UART3_BASE)
#define UART4 ((UART_TypeDef *) UART4_BASE)
#define UART5 ((UART_TypeDef *) UART5_BASE)
#define UART6 ((UART_TypeDef *) UART6_BASE)
#define UART7 ((UART_TypeDef *) UART7_BASE)
#define SSI0 ((SSI_TypeDef *) SSI0_BASE)
#define SSI1 ((SSI_TypeDef *) SSI1_BASE)
#define SSI2 ((SSI_TypeDef *) SSI2_BASE)
#define SSI3 ((SSI_TypeDef *) SSI3_BASE)
#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
#define I2C5 ((I2C_TypeDef *) I2C5_BASE)
#define CAN0 ((CAN_TypeDef *) CAN0_BASE)
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define SYSCTL ((SYSCTL_TypeDef *) SYSCTL_BASE)
#define HIB ((HIB_TypeDef *) HIB_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_BASE)
#define EEPROM ((EEPROM_TypeDef *) EEPROM_BASE)
#define UDMA ((UDMA_TypeDef *) UDMA_BASE)
#define GPIOA_APB ((GPIO_TypeDef *) GPIOA_APB_BASE)
#define GPIOA_AHB ((GPIO_TypeDef *) GPIOA_AHB_BASE)
#define GPIOB_APB ((GPIO_TypeDef *) GPIOB_APB_BASE)
#define GPIOB_AHB ((GPIO_TypeDef *) GPIOB_AHB_BASE)
#define GPIOC_APB ((GPIO_TypeDef *) GPIOC_APB_BASE)
#define GPIOC_AHB ((GPIO_TypeDef *) GPIOC_AHB_BASE)
#define GPIOD_APB ((GPIO_TypeDef *) GPIOD_APB_BASE)
#define GPIOD_AHB ((GPIO_TypeDef *) GPIOD_AHB_BASE)
#define GPIOE_APB ((GPIO_TypeDef *) GPIOE_APB_BASE)
#define GPIOE_AHB ((GPIO_TypeDef *) GPIOE_AHB_BASE)
#define GPIOF_APB ((GPIO_TypeDef *) GPIOF_APB_BASE)
#define GPIOF_AHB ((GPIO_TypeDef *) GPIOF_AHB_BASE)
#define GPIOG_APB ((GPIO_TypeDef *) GPIOG_APB_BASE)
#define GPIOG_AHB ((GPIO_TypeDef *) GPIOG_AHB_BASE)
#define GPIOH_APB ((GPIO_TypeDef *) GPIOH_APB_BASE)
#define GPIOH_AHB ((GPIO_TypeDef *) GPIOH_AHB_BASE)
#define GPIOJ_APB ((GPIO_TypeDef *) GPIOJ_APB_BASE)
#define GPIOJ_AHB ((GPIO_TypeDef *) GPIOJ_AHB_BASE)
#define GPIOK_AHB ((GPIO_TypeDef *) GPIOK_AHB_BASE)
#define GPIOL_AHB ((GPIO_TypeDef *) GPIOL_AHB_BASE)
#define GPIOM_AHB ((GPIO_TypeDef *) GPIOM_AHB_BASE)
#define GPION_AHB ((GPIO_TypeDef *) GPION_AHB_BASE)
#define GPIOP_AHB ((GPIO_TypeDef *) GPIOP_AHB_BASE)
#define GPIOQ_AHB ((GPIO_TypeDef *) GPIOQ_AHB_BASE)
#define GPT0 ((GPT_TypeDef *) GPT0_BASE)
#define GPT1 ((GPT_TypeDef *) GPT1_BASE)
#define GPT2 ((GPT_TypeDef *) GPT2_BASE)
#define GPT3 ((GPT_TypeDef *) GPT3_BASE)
#define GPT4 ((GPT_TypeDef *) GPT4_BASE)
#define GPT5 ((GPT_TypeDef *) GPT5_BASE)
#define WGPT0 ((GPT_TypeDef *) WGPT0_BASE)
#define WGPT1 ((GPT_TypeDef *) WGPT1_BASE)
#define WGPT2 ((GPT_TypeDef *) WGPT2_BASE)
#define WGPT3 ((GPT_TypeDef *) WGPT3_BASE)
#define WGPT4 ((GPT_TypeDef *) WGPT4_BASE)
#define WGPT5 ((GPT_TypeDef *) WGPT5_BASE)
#define ADC0 ((ADC_TypeDef*) ADC0_BASE)
#define ADC1 ((ADC_TypeDef*) ADC1_BASE)
#define UART0 ((UART_TypeDef *) UART0_BASE)
#define UART1 ((UART_TypeDef *) UART1_BASE)
#define UART2 ((UART_TypeDef *) UART2_BASE)
#define UART3 ((UART_TypeDef *) UART3_BASE)
#define UART4 ((UART_TypeDef *) UART4_BASE)
#define UART5 ((UART_TypeDef *) UART5_BASE)
#define UART6 ((UART_TypeDef *) UART6_BASE)
#define UART7 ((UART_TypeDef *) UART7_BASE)
#define SSI0 ((SSI_TypeDef *) SSI0_BASE)
#define SSI1 ((SSI_TypeDef *) SSI1_BASE)
#define SSI2 ((SSI_TypeDef *) SSI2_BASE)
#define SSI3 ((SSI_TypeDef *) SSI3_BASE)
#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
#define I2C5 ((I2C_TypeDef *) I2C5_BASE)
#define CAN0 ((CAN_TypeDef *) CAN0_BASE)
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
// usb
#define ACMP ((ACMP_TypeDef *) ACMP_BASE)
#define PWM0 ((PWM_TypeDef *) PWM0_BASE)
#define PWM1 ((PWM_TypeDef *) PWM1_BASE)
#define QEI0 ((QEI_TypeDef *) QEI0_BASE)
#define QEI1 ((QEI_TypeDef *) QEI1_BASE)
#define ACMP ((ACMP_TypeDef *) ACMP_BASE)
#define PWM0 ((PWM_TypeDef *) PWM0_BASE)
#define PWM1 ((PWM_TypeDef *) PWM1_BASE)
#define QEI0 ((QEI_TypeDef *) QEI0_BASE)
#define QEI1 ((QEI_TypeDef *) QEI1_BASE)
/**
* @}

2
testhal/TIVA/TM4C123x/GPT/main.c
View File

@ -71,6 +71,8 @@ int main(void)
halInit();
chSysInit();
palSetPadMode(GPIOF, GPIOF_LED_RED, PAL_MODE_OUTPUT_PUSHPULL);
/*
* Start the gpt drivers with the custom configurations.
*/

10
testhal/TIVA/TM4C123x/GPT/mcuconf.h
View File

@ -24,6 +24,16 @@
#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \
TIVA_RCC_PWMDIV_8)
/*
* GPIO driver system settings.
*/
#define TIVA_GPIO_GPIOA_USE_AHB TRUE
#define TIVA_GPIO_GPIOB_USE_AHB TRUE
#define TIVA_GPIO_GPIOC_USE_AHB TRUE
#define TIVA_GPIO_GPIOD_USE_AHB TRUE
#define TIVA_GPIO_GPIOE_USE_AHB TRUE
#define TIVA_GPIO_GPIOF_USE_AHB TRUE
/*
* GPT driver system settings.
*/

8
testhal/TIVA/TM4C123x/I2C/main.c
View File

@ -69,11 +69,19 @@ int main(void)
halInit();
chSysInit();
/* Configure RX and TX pins for UART0.*/
palSetPadMode(GPIOA, GPIOA_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
palSetPadMode(GPIOA, GPIOA_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
/*
* Start the serial driver with the default configuration.
*/
sdStart(&SD1, NULL);
/* Configure SCK and SCL pins for I2C0.*/
palSetPadMode(GPIOB, GPIOB_I2C0_SCL, PAL_MODE_OUTPUT_PUSHPULL | PAL_MODE_ALTERNATE(3));
palSetPadMode(GPIOB, GPIOB_I2C0_SDA, PAL_MODE_OUTPUT_OPENDRAIN | PAL_MODE_ALTERNATE(3));
/*
* Start the i2c driver with the custom configuration.
*/

10
testhal/TIVA/TM4C123x/I2C/mcuconf.h
View File

@ -24,6 +24,16 @@
#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \
TIVA_RCC_PWMDIV_8)
/*
* GPIO driver system settings.
*/
#define TIVA_GPIO_GPIOA_USE_AHB TRUE
#define TIVA_GPIO_GPIOB_USE_AHB TRUE
#define TIVA_GPIO_GPIOC_USE_AHB TRUE
#define TIVA_GPIO_GPIOD_USE_AHB TRUE
#define TIVA_GPIO_GPIOE_USE_AHB TRUE
#define TIVA_GPIO_GPIOF_USE_AHB TRUE
/*
* GPT driver system settings.
*/

25
testhal/TIVA/TM4C123x/PWM/main.c
View File

@ -74,6 +74,10 @@ int main(void)
halInit();
chSysInit();
palSetPadMode(GPIOF, GPIOF_LED_RED, PAL_MODE_OUTPUT_PUSHPULL);
palSetPadMode(GPIOF, GPIOF_LED_GREEN, PAL_MODE_OUTPUT_PUSHPULL);
palSetPadMode(GPIOF, GPIOF_LED_BLUE, PAL_MODE_OUTPUT_PUSHPULL);
/*
* Start PWM driver
*/
@ -109,24 +113,9 @@ int main(void)
rgbColour[decColour] -= 1;
rgbColour[incColour] += 1;
if (!palReadPad(GPIOF, GPIOF_SW1))
{
pwmEnableChannel(&PWMD1, 0, 0);
pwmEnableChannel(&PWMD1, 1, 1);
pwmEnableChannel(&PWMD1, 2, 2);
}
else if (!palReadPad(GPIOF, GPIOF_SW2))
{
pwmEnableChannel(&PWMD1, 0, pwmcfg.frequency - 2);
pwmEnableChannel(&PWMD1, 1, pwmcfg.frequency - 1);
pwmEnableChannel(&PWMD1, 2, pwmcfg.frequency);
}
else
{
pwmEnableChannel(&PWMD1, 0, rgbColour[0]);
pwmEnableChannel(&PWMD1, 1, rgbColour[1]);
pwmEnableChannel(&PWMD1, 2, rgbColour[2]);
}
pwmEnableChannel(&PWMD1, 0, rgbColour[0]);
pwmEnableChannel(&PWMD1, 1, rgbColour[1]);
pwmEnableChannel(&PWMD1, 2, rgbColour[2]);
chThdSleepMilliseconds(1);
}

10
testhal/TIVA/TM4C123x/PWM/mcuconf.h
View File

@ -24,6 +24,16 @@
#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \
TIVA_RCC_PWMDIV_8)
/*
* GPIO driver system settings.
*/
#define TIVA_GPIO_GPIOA_USE_AHB TRUE
#define TIVA_GPIO_GPIOB_USE_AHB TRUE
#define TIVA_GPIO_GPIOC_USE_AHB TRUE
#define TIVA_GPIO_GPIOD_USE_AHB TRUE
#define TIVA_GPIO_GPIOE_USE_AHB TRUE
#define TIVA_GPIO_GPIOF_USE_AHB TRUE
/*
* GPT driver system settings.
*/