From 6a3caa697aac2f9c5a273d02d8a780c91fc269d1 Mon Sep 17 00:00:00 2001 From: Stefan Kerkmann Date: Mon, 22 Mar 2021 13:18:20 +0100 Subject: [PATCH] GPIO Remove obsolete ports, rename registers --- os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c | 56 ++++++++------------ os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.h | 34 +++--------- os/hal/ports/GD/GD32VF103/stm32f105xc.h | 14 ++--- 3 files changed, 34 insertions(+), 70 deletions(-) diff --git a/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c b/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c index b84e4465..0f9ecd8e 100644 --- a/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c +++ b/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c @@ -30,12 +30,7 @@ /* Driver local definitions. */ /*===========================================================================*/ -#if GD32_HAS_GPIOG -#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ - RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \ - RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN) -#elif GD32_HAS_GPIOE +#if GD32_HAS_GPIOE #define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \ RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \ RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN) @@ -98,32 +93,22 @@ void _pal_lld_init(const PALConfig *config) { /* * Initial GPIO setup. */ - GPIOA->ODR = config->PAData.odr; - GPIOA->CRH = config->PAData.crh; - GPIOA->CRL = config->PAData.crl; - GPIOB->ODR = config->PBData.odr; - GPIOB->CRH = config->PBData.crh; - GPIOB->CRL = config->PBData.crl; - GPIOC->ODR = config->PCData.odr; - GPIOC->CRH = config->PCData.crh; - GPIOC->CRL = config->PCData.crl; - GPIOD->ODR = config->PDData.odr; - GPIOD->CRH = config->PDData.crh; - GPIOD->CRL = config->PDData.crl; + GPIOA->OCTL = config->PAData.odr; + GPIOA->CTL1 = config->PAData.crh; + GPIOA->CTL0 = config->PAData.crl; + GPIOB->OCTL = config->PBData.odr; + GPIOB->CTL1 = config->PBData.crh; + GPIOB->CTL0 = config->PBData.crl; + GPIOC->OCTL = config->PCData.odr; + GPIOC->CTL1 = config->PCData.crh; + GPIOC->CTL0 = config->PCData.crl; + GPIOD->OCTL = config->PDData.odr; + GPIOD->CTL1 = config->PDData.crh; + GPIOD->CTL0 = config->PDData.crl; #if GD32_HAS_GPIOE || defined(__DOXYGEN__) - GPIOE->ODR = config->PEData.odr; - GPIOE->CRH = config->PEData.crh; - GPIOE->CRL = config->PEData.crl; -#if GD32_HAS_GPIOF || defined(__DOXYGEN__) - GPIOF->ODR = config->PFData.odr; - GPIOF->CRH = config->PFData.crh; - GPIOF->CRL = config->PFData.crl; -#if GD32_HAS_GPIOG || defined(__DOXYGEN__) - GPIOG->ODR = config->PGData.odr; - GPIOG->CRH = config->PGData.crh; - GPIOG->CRL = config->PGData.crl; -#endif -#endif + GPIOE->OCTL = config->PEData.odr; + GPIOE->CTL1 = config->PEData.crh; + GPIOE->CTL0 = config->PEData.crl; #endif } @@ -165,13 +150,14 @@ void _pal_lld_setgroupmode(ioportid_t port, 0xB, /* PAL_MODE_GD32_ALTERNATE_PUSHPULL, 50MHz.*/ 0xF, /* PAL_MODE_GD32_ALTERNATE_OPENDRAIN, 50MHz.*/ }; + // TODO RENAME uint32_t mh, ml, crh, crl, cfg; unsigned i; if (mode == PAL_MODE_INPUT_PULLUP) - port->BSRR = mask; + port->BOP = mask; else if (mode == PAL_MODE_INPUT_PULLDOWN) - port->BRR = mask; + port->BC = mask; cfg = cfgtab[mode]; mh = ml = crh = crl = 0; for (i = 0; i < 8; i++) { @@ -189,8 +175,8 @@ void _pal_lld_setgroupmode(ioportid_t port, crh |= cfg; mask <<= 1; } - port->CRH = (port->CRH & mh) | crh; - port->CRL = (port->CRL & ml) | crl; + port->CTL1 = (port->CTL1 & mh) | crh; + port->CTL0 = (port->CTL0 & ml) | crl; } #if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) diff --git a/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.h b/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.h index bc5928fc..ccd61b6b 100644 --- a/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.h +++ b/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.h @@ -129,14 +129,6 @@ typedef struct { #if GD32_HAS_GPIOE || defined(__DOXYGEN__) /** @brief Port E setup data.*/ gd32_gpio_setup_t PEData; -#if GD32_HAS_GPIOF || defined(__DOXYGEN__) - /** @brief Port F setup data.*/ - gd32_gpio_setup_t PFData; -#if GD32_HAS_GPIOG || defined(__DOXYGEN__) - /** @brief Port G setup data.*/ - gd32_gpio_setup_t PGData; -#endif -#endif #endif } PALConfig; @@ -214,20 +206,6 @@ typedef uint32_t iopadid_t; #define IOPORT5 GPIOE #endif -/** - * @brief GPIO port F identifier. - */ -#if GD32_HAS_GPIOF || defined(__DOXYGEN__) -#define IOPORT6 GPIOF -#endif - -/** - * @brief GPIO port G identifier. - */ -#if GD32_HAS_GPIOG || defined(__DOXYGEN__) -#define IOPORT7 GPIOG -#endif - /*===========================================================================*/ /* Implementation, some of the following macros could be implemented as */ /* functions, if so please put them in pal_lld.c. */ @@ -252,7 +230,7 @@ typedef uint32_t iopadid_t; * * @notapi */ -#define pal_lld_readport(port) ((ioportmask_t)((port)->IDR)) +#define pal_lld_readport(port) ((ioportmask_t)((port)->ISTAT)) /** * @brief Reads the output latch. @@ -266,7 +244,7 @@ typedef uint32_t iopadid_t; * * @notapi */ -#define pal_lld_readlatch(port) ((ioportmask_t)((port)->ODR)) +#define pal_lld_readlatch(port) ((ioportmask_t)((port)->OCTL)) /** * @brief Writes on a I/O port. @@ -281,7 +259,7 @@ typedef uint32_t iopadid_t; * * @notapi */ -#define pal_lld_writeport(port, bits) ((port)->ODR = (uint32_t)(bits)) +#define pal_lld_writeport(port, bits) ((port)->OCTL = (uint32_t)(bits)) /** * @brief Sets a bits mask on a I/O port. @@ -296,7 +274,7 @@ typedef uint32_t iopadid_t; * * @notapi */ -#define pal_lld_setport(port, bits) ((port)->BSRR = (uint32_t)(bits)) +#define pal_lld_setport(port, bits) ((port)->BOP = (uint32_t)(bits)) /** * @brief Clears a bits mask on a I/O port. @@ -311,7 +289,7 @@ typedef uint32_t iopadid_t; * * @notapi */ -#define pal_lld_clearport(port, bits) ((port)->BRR = (uint32_t)(bits)) +#define pal_lld_clearport(port, bits) ((port)->BC = (uint32_t)(bits)) /** * @brief Writes a group of bits. @@ -332,7 +310,7 @@ typedef uint32_t iopadid_t; #define pal_lld_writegroup(port, mask, offset, bits) { \ uint32_t w = ((~(uint32_t)(bits) & (uint32_t)(mask)) << (16U + (offset))) | \ ((uint32_t)(bits) & (uint32_t)(mask)) << (offset); \ - (port)->BSRR = w; \ + (port)->BOP = w; \ } /** diff --git a/os/hal/ports/GD/GD32VF103/stm32f105xc.h b/os/hal/ports/GD/GD32VF103/stm32f105xc.h index 17fa2072..49b1b3cb 100644 --- a/os/hal/ports/GD/GD32VF103/stm32f105xc.h +++ b/os/hal/ports/GD/GD32VF103/stm32f105xc.h @@ -358,13 +358,13 @@ typedef struct typedef struct { - __IO uint32_t CRL; - __IO uint32_t CRH; - __IO uint32_t IDR; - __IO uint32_t ODR; - __IO uint32_t BSRR; - __IO uint32_t BRR; - __IO uint32_t LCKR; + __IO uint32_t CTL0; + __IO uint32_t CTL1; + __IO uint32_t ISTAT; + __IO uint32_t OCTL; + __IO uint32_t BOP; + __IO uint32_t BC; + __IO uint32_t LOCK; } GPIO_TypeDef; /**