Merge remote-tracking branch 'upstream/master'
This commit is contained in:
Michael Walker
commit
6d879f58f5
|
|
@ -0,0 +1,16 @@
|
|||
language: c
|
||||
|
||||
sudo: required
|
||||
|
||||
before_install:
|
||||
- chmod +x tools/travis/before_install.sh
|
||||
- ./tools/travis/before_install.sh
|
||||
|
||||
script:
|
||||
- chmod +x tools/travis/script.sh
|
||||
- ./tools/travis/script.sh
|
||||
|
||||
addons:
|
||||
apt:
|
||||
packages:
|
||||
- p7zip-full
|
||||
|
|
@ -19,3 +19,7 @@ https://github.com/mabl
|
|||
|
||||
Andrea Zoppi aka TexZK
|
||||
https://github.com/TexZK
|
||||
|
||||
Diego Ismirlian aka dismirlian
|
||||
https://github.com/dismirlian
|
||||
USB Host stack author
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#define _CHCONF_H_
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#define _CHCONF_H_
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#define _CHCONF_H_
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#define CHCONF_H
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#define _CHCONF_H_
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#define _CHCONF_H_
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#define _CHCONF_H_
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#define _CHCONF_H_
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#define CHCONF_H
|
||||
|
||||
#define _CHIBIOS_NIL_CONF_
|
||||
#define _CHIBIOS_NIL_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#define CHCONF_H
|
||||
|
||||
#define _CHIBIOS_NIL_CONF_
|
||||
#define _CHIBIOS_NIL_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -0,0 +1,223 @@
|
|||
##############################################################################
|
||||
# Build global options
|
||||
# NOTE: Can be overridden externally.
|
||||
#
|
||||
|
||||
# Compiler options here.
|
||||
ifeq ($(USE_OPT),)
|
||||
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -std=c11
|
||||
endif
|
||||
|
||||
# C specific options here (added to USE_OPT).
|
||||
ifeq ($(USE_COPT),)
|
||||
USE_COPT =
|
||||
endif
|
||||
|
||||
# C++ specific options here (added to USE_OPT).
|
||||
ifeq ($(USE_CPPOPT),)
|
||||
USE_CPPOPT = -fno-rtti
|
||||
endif
|
||||
|
||||
# Enable this if you want the linker to remove unused code and data
|
||||
ifeq ($(USE_LINK_GC),)
|
||||
USE_LINK_GC = yes
|
||||
endif
|
||||
|
||||
# Linker extra options here.
|
||||
ifeq ($(USE_LDOPT),)
|
||||
USE_LDOPT =
|
||||
endif
|
||||
|
||||
# Enable this if you want link time optimizations (LTO)
|
||||
ifeq ($(USE_LTO),)
|
||||
USE_LTO = yes
|
||||
endif
|
||||
|
||||
# If enabled, this option allows to compile the application in THUMB mode.
|
||||
ifeq ($(USE_THUMB),)
|
||||
USE_THUMB = yes
|
||||
endif
|
||||
|
||||
# Enable this if you want to see the full log while compiling.
|
||||
ifeq ($(USE_VERBOSE_COMPILE),)
|
||||
USE_VERBOSE_COMPILE = no
|
||||
endif
|
||||
|
||||
# If enabled, this option makes the build process faster by not compiling
|
||||
# modules not used in the current configuration.
|
||||
ifeq ($(USE_SMART_BUILD),)
|
||||
USE_SMART_BUILD = yes
|
||||
endif
|
||||
|
||||
#
|
||||
# Build global options
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Architecture or project specific options
|
||||
#
|
||||
|
||||
# Stack size to be allocated to the Cortex-M process stack. This stack is
|
||||
# the stack used by the main() thread.
|
||||
ifeq ($(USE_PROCESS_STACKSIZE),)
|
||||
USE_PROCESS_STACKSIZE = 0x200
|
||||
endif
|
||||
|
||||
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
|
||||
# stack is used for processing interrupts and exceptions.
|
||||
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
|
||||
USE_EXCEPTIONS_STACKSIZE = 0x400
|
||||
endif
|
||||
|
||||
# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
|
||||
ifeq ($(USE_FPU),)
|
||||
USE_FPU = no
|
||||
endif
|
||||
|
||||
#
|
||||
# Architecture or project specific options
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Project, sources and paths
|
||||
#
|
||||
|
||||
# Define project name here
|
||||
PROJECT = ch
|
||||
|
||||
# Imported source files and paths
|
||||
CHIBIOS = ../../../../ChibiOS-RT
|
||||
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
|
||||
# Startup files.
|
||||
include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk
|
||||
# HAL-OSAL files (optional).
|
||||
include $(CHIBIOS)/os/hal/hal.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF5/NRF51822/platform.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/boards/MICROBIT/board.mk
|
||||
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
|
||||
include $(CHIBIOS)/os/hal/lib/streams/streams.mk
|
||||
# RTOS files (optional).
|
||||
include $(CHIBIOS)/os/rt/rt.mk
|
||||
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
|
||||
# Other files (optional).
|
||||
include $(CHIBIOS)/test/rt/test.mk
|
||||
|
||||
# Define linker script file here
|
||||
LDSCRIPT= $(STARTUPLD)/NRF51822.ld
|
||||
|
||||
# C sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CSRC = $(STARTUPSRC) \
|
||||
$(KERNSRC) \
|
||||
$(PORTSRC) \
|
||||
$(OSALSRC) \
|
||||
$(HALSRC) \
|
||||
$(PLATFORMSRC) \
|
||||
$(BOARDSRC) \
|
||||
$(STREAMSSRC) \
|
||||
$(TESTSRC) \
|
||||
main.c
|
||||
|
||||
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CPPSRC =
|
||||
|
||||
# C sources to be compiled in ARM mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
# option that results in lower performance and larger code size.
|
||||
ACSRC =
|
||||
|
||||
# C++ sources to be compiled in ARM mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
# option that results in lower performance and larger code size.
|
||||
ACPPSRC =
|
||||
|
||||
# C sources to be compiled in THUMB mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
# option that results in lower performance and larger code size.
|
||||
TCSRC =
|
||||
|
||||
# C sources to be compiled in THUMB mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
# option that results in lower performance and larger code size.
|
||||
TCPPSRC =
|
||||
|
||||
# List ASM source files here
|
||||
ASMSRC =
|
||||
ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
|
||||
|
||||
INCDIR = $(CHIBIOS)/os/license \
|
||||
$(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
|
||||
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
|
||||
$(STREAMSINC) \
|
||||
$(CHIBIOS)/os/various
|
||||
|
||||
#
|
||||
# Project, sources and paths
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Compiler settings
|
||||
#
|
||||
|
||||
MCU = cortex-m0
|
||||
|
||||
TRGT = arm-none-eabi-
|
||||
CC = $(TRGT)gcc
|
||||
CPPC = $(TRGT)g++
|
||||
# Enable loading with g++ only if you need C++ runtime support.
|
||||
# NOTE: You can use C++ even without C++ support if you are careful. C++
|
||||
# runtime support makes code size explode.
|
||||
LD = $(TRGT)gcc
|
||||
#LD = $(TRGT)g++
|
||||
CP = $(TRGT)objcopy
|
||||
AS = $(TRGT)gcc -x assembler-with-cpp
|
||||
AR = $(TRGT)ar
|
||||
OD = $(TRGT)objdump
|
||||
SZ = $(TRGT)size
|
||||
HEX = $(CP) -O ihex
|
||||
BIN = $(CP) -O binary
|
||||
SREC = $(CP) -O srec
|
||||
|
||||
# ARM-specific options here
|
||||
AOPT =
|
||||
|
||||
# THUMB-specific options here
|
||||
TOPT = -mthumb -DTHUMB
|
||||
|
||||
# Define C warning options here
|
||||
CWARN = -Wall -Wextra -Wstrict-prototypes
|
||||
|
||||
# Define C++ warning options here
|
||||
CPPWARN = -Wall -Wextra
|
||||
|
||||
#
|
||||
# Compiler settings
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Start of user section
|
||||
#
|
||||
|
||||
# List all user C define here, like -D_DEBUG=1
|
||||
UDEFS =
|
||||
|
||||
# Define ASM defines here
|
||||
UADEFS =
|
||||
|
||||
# List all user directories here
|
||||
UINCDIR =
|
||||
|
||||
# List the user directory to look for the libraries here
|
||||
ULIBDIR =
|
||||
|
||||
# List all user libraries here
|
||||
ULIBS =
|
||||
|
||||
#
|
||||
# End of user defines
|
||||
##############################################################################
|
||||
|
||||
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
|
||||
include $(RULESPATH)/rules.mk
|
||||
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
Copyright (C) 2015 Fabio Utzig
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -14,10 +14,22 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file templates/chconf.h
|
||||
* @brief Configuration file template.
|
||||
* @details A copy of this file must be placed in each project directory, it
|
||||
* contains the application specific kernel settings.
|
||||
*
|
||||
* @addtogroup config
|
||||
* @details Kernel related settings and hooks.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _CHCONF_H_
|
||||
#define _CHCONF_H_
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
@ -49,13 +61,6 @@
|
|||
*/
|
||||
#define CH_CFG_ST_TIMEDELTA 0
|
||||
|
||||
/**
|
||||
* @brief Realtime Counter frequency.
|
||||
* @details Frequency of the system counter used for realtime delays and
|
||||
* measurements.
|
||||
*/
|
||||
#define CH_CFG_RTC_FREQUENCY 80000000
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -77,7 +82,7 @@
|
|||
* @note The round robin preemption is not supported in tickless mode and
|
||||
* must be set to zero in that case.
|
||||
*/
|
||||
#define CH_CFG_TIME_QUANTUM 0
|
||||
#define CH_CFG_TIME_QUANTUM 20
|
||||
|
||||
/**
|
||||
* @brief Managed RAM size.
|
||||
|
|
@ -97,7 +102,8 @@
|
|||
* @details When this option is activated the function @p chSysInit()
|
||||
* does not spawn the idle thread. The application @p main()
|
||||
* function becomes the idle thread and must implement an
|
||||
* infinite loop. */
|
||||
* infinite loop.
|
||||
*/
|
||||
#define CH_CFG_NO_IDLE_THREAD FALSE
|
||||
|
||||
/** @} */
|
||||
|
|
@ -135,7 +141,7 @@
|
|||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_TM TRUE
|
||||
#define CH_CFG_USE_TM FALSE
|
||||
|
||||
/**
|
||||
* @brief Threads registry APIs.
|
||||
|
|
@ -181,6 +187,16 @@
|
|||
*/
|
||||
#define CH_CFG_USE_MUTEXES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables recursive behavior on mutexes.
|
||||
* @note Recursive mutexes are heavier and have an increased
|
||||
* memory footprint.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||
*/
|
||||
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
|
||||
|
||||
/**
|
||||
* @brief Conditional Variables APIs.
|
||||
* @details If enabled then the conditional variables APIs are included
|
||||
|
|
@ -428,7 +444,7 @@
|
|||
* @details This hook is invoked just before switching between threads.
|
||||
*/
|
||||
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
|
||||
/* System halt code here.*/ \
|
||||
/* Context switch code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
Copyright (C) 2015 Fabio Utzig
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -14,6 +14,17 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file templates/halconf.h
|
||||
* @brief HAL configuration header.
|
||||
* @details HAL configuration file, this file allows to enable or disable the
|
||||
* various device drivers from your application. You may also use
|
||||
* this file in order to override the device drivers default settings.
|
||||
*
|
||||
* @addtogroup HAL_CONF
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _HALCONF_H_
|
||||
#define _HALCONF_H_
|
||||
|
||||
|
|
@ -44,7 +55,7 @@
|
|||
* @brief Enables the EXT subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_EXT TRUE
|
||||
#define HAL_USE_EXT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -61,6 +72,13 @@
|
|||
#define HAL_USE_I2C FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the I2S subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_I2S FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ICU subsystem.
|
||||
*/
|
||||
|
|
@ -107,7 +125,7 @@
|
|||
* @brief Enables the SERIAL subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SERIAL FALSE
|
||||
#define HAL_USE_SERIAL TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -269,6 +287,21 @@
|
|||
#define SERIAL_BUFFERS_SIZE 16
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SERIAL_USB driver related setting. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Serial over USB buffers size.
|
||||
* @details Configuration parameter, the buffer size must be a multiple of
|
||||
* the USB data endpoint maximum packet size.
|
||||
* @note The default is 64 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_SIZE 256
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
Copyright (C) 2016 Stephane D'Alu
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
#include "ch_test.h"
|
||||
|
||||
/* See: https://lancaster-university.github.io/microbit-docs/ubit/display/
|
||||
*/
|
||||
|
||||
static THD_WORKING_AREA(waThread1, 64);
|
||||
static THD_FUNCTION(Thread1, arg) {
|
||||
(void)arg;
|
||||
chRegSetThreadName("Blinker");
|
||||
|
||||
ioline_t cols[] = {
|
||||
LINE_LED_COL_1, LINE_LED_COL_2, LINE_LED_COL_3,
|
||||
LINE_LED_COL_4, LINE_LED_COL_5, LINE_LED_COL_6,
|
||||
LINE_LED_COL_7, LINE_LED_COL_8, LINE_LED_COL_9,
|
||||
PAL_NOLINE
|
||||
};
|
||||
for (ioline_t *col = cols ; *col != PAL_NOLINE ; col++)
|
||||
palClearLine(col);
|
||||
|
||||
while (1) {
|
||||
palSetLine(LINE_LED_ROW_2);
|
||||
chThdSleepMilliseconds(100);
|
||||
palClearLine(LINE_LED_ROW_2);
|
||||
chThdSleepMilliseconds(500);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Application entry point.
|
||||
*/
|
||||
int main(void) {
|
||||
|
||||
SerialConfig serial_config = {
|
||||
.speed = 115200,
|
||||
.tx_pad = IOPORT1_UART_TX,
|
||||
.rx_pad = IOPORT1_UART_RX,
|
||||
};
|
||||
|
||||
/*
|
||||
* System initializations.
|
||||
* - HAL initialization, this also initializes the configured device drivers
|
||||
* and performs the board-specific initializations.
|
||||
* - Kernel initialization, the main() function becomes a thread and the
|
||||
* RTOS is active.
|
||||
*/
|
||||
halInit();
|
||||
chSysInit();
|
||||
|
||||
/*
|
||||
* Activates UART0 using the driver default configuration.
|
||||
*/
|
||||
sdStart(&SD1, &serial_config);
|
||||
|
||||
/*
|
||||
* Creates the blinker thread.
|
||||
*/
|
||||
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
|
||||
|
||||
|
||||
test_execute((BaseSequentialStream *)&SD1);
|
||||
while (1) {
|
||||
chThdSleepMilliseconds(500);
|
||||
}
|
||||
}
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
|
||||
Copyright (C) 2015 Fabio Utzig
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -14,15 +14,15 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef ONEWIRE_TEST_H_
|
||||
#define ONEWIRE_TEST_H_
|
||||
#ifndef _MCUCONF_H_
|
||||
#define _MCUCONF_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void onewireTest(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define NRF5_SERIAL_USE_UART0 TRUE
|
||||
#define NRF5_ST_USE_RTC0 TRUE
|
||||
#define NRF5_ST_USE_RTC1 FALSE
|
||||
#define NRF5_ST_USE_TIMER0 FALSE
|
||||
|
||||
#endif /* ONEWIRE_TEST_H_ */
|
||||
#endif /* _MCUCONF_H_ */
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
*****************************************************************************
|
||||
** ChibiOS/RT port for ARM-Cortex-M0 BBC micro:bit (nRF51822). **
|
||||
*****************************************************************************
|
||||
|
||||
** TARGET **
|
||||
|
||||
The demo runs on a BBC micro:bit board. This board is powered by a Nordic
|
||||
Semiconductor nRF51822 processor which is an ARM Cortex-M0 with bluetooth radio
|
||||
hardware. Information about this board can be found on:
|
||||
https://www.microbit.co.uk
|
||||
|
||||
** The Demo **
|
||||
|
||||
This demo will print the standard TestThread output and blink 7 LEDs
|
||||
|
||||
** Build Procedure **
|
||||
|
||||
The demo has been tested using the freely available GCC ARM Embedded toolchain.
|
||||
|
|
@ -92,7 +92,7 @@ CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
|
|||
include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk
|
||||
# HAL-OSAL files (optional).
|
||||
include $(CHIBIOS)/os/hal/hal.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF51/NRF51822/platform.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF5/NRF51822/platform.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/boards/OSHCHIP_V1.0/board.mk
|
||||
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
|
||||
# RTOS files (optional).
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#define _CHCONF_H_
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -17,15 +17,15 @@
|
|||
#ifndef _MCUCONF_H_
|
||||
#define _MCUCONF_H_
|
||||
|
||||
/* Possible value for NRF51_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth */
|
||||
#define NRF51_LFCLK_SOURCE 0
|
||||
/* Possible value for NRF5_LFCLK_SOURCE are 0=RC, 1=XTAL, 2=Synth */
|
||||
#define NRF5_LFCLK_SOURCE 0
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define NRF51_SERIAL_USE_UART0 TRUE
|
||||
#define NRF51_ST_USE_RTC0 TRUE
|
||||
#define NRF51_ST_USE_RTC1 FALSE
|
||||
#define NRF51_ST_USE_TIMER0 FALSE
|
||||
#define NRF5_SERIAL_USE_UART0 TRUE
|
||||
#define NRF5_ST_USE_RTC0 TRUE
|
||||
#define NRF5_ST_USE_RTC1 FALSE
|
||||
#define NRF5_ST_USE_TIMER0 FALSE
|
||||
|
||||
#endif /* _MCUCONF_H_ */
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@ CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
|
|||
include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk
|
||||
# HAL-OSAL files (optional).
|
||||
include $(CHIBIOS)/os/hal/hal.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF51/NRF51822/platform.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF5/NRF51822/platform.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/boards/WVSHARE_BLE400/board.mk
|
||||
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
|
||||
# RTOS files (optional).
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#define _CHCONF_H_
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -20,9 +20,9 @@
|
|||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define NRF51_SERIAL_USE_UART0 TRUE
|
||||
#define NRF51_ST_USE_RTC0 TRUE
|
||||
#define NRF51_ST_USE_RTC1 FALSE
|
||||
#define NRF51_ST_USE_TIMER0 FALSE
|
||||
#define NRF5_SERIAL_USE_UART0 TRUE
|
||||
#define NRF5_ST_USE_RTC0 TRUE
|
||||
#define NRF5_ST_USE_RTC1 FALSE
|
||||
#define NRF5_ST_USE_TIMER0 FALSE
|
||||
|
||||
#endif /* _MCUCONF_H_ */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,250 @@
|
|||
##############################################################################
|
||||
# Build global options
|
||||
# NOTE: Can be overridden externally.
|
||||
#
|
||||
|
||||
PLATFORM=NRF5/NRF52832
|
||||
BOARD=NRF52-DK
|
||||
|
||||
# Compiler options here.
|
||||
ifeq ($(USE_OPT),)
|
||||
USE_OPT = -Os -ggdb -fomit-frame-pointer -falign-functions=16 -std=c11
|
||||
endif
|
||||
|
||||
# C specific options here (added to USE_OPT).
|
||||
ifeq ($(USE_COPT),)
|
||||
USE_COPT =
|
||||
endif
|
||||
|
||||
# C++ specific options here (added to USE_OPT).
|
||||
ifeq ($(USE_CPPOPT),)
|
||||
USE_CPPOPT = -fno-rtti
|
||||
endif
|
||||
|
||||
# Enable this if you want the linker to remove unused code and data
|
||||
ifeq ($(USE_LINK_GC),)
|
||||
USE_LINK_GC = yes
|
||||
endif
|
||||
|
||||
# Linker extra options here.
|
||||
ifeq ($(USE_LDOPT),)
|
||||
USE_LDOPT =
|
||||
endif
|
||||
|
||||
# Enable this if you want link time optimizations (LTO)
|
||||
ifeq ($(USE_LTO),)
|
||||
USE_LTO = yes
|
||||
endif
|
||||
|
||||
# If enabled, this option allows to compile the application in THUMB mode.
|
||||
ifeq ($(USE_THUMB),)
|
||||
USE_THUMB = yes
|
||||
endif
|
||||
|
||||
# Enable this if you want to see the full log while compiling.
|
||||
ifeq ($(USE_VERBOSE_COMPILE),)
|
||||
USE_VERBOSE_COMPILE = no
|
||||
endif
|
||||
|
||||
# If enabled, this option makes the build process faster by not compiling
|
||||
# modules not used in the current configuration.
|
||||
ifeq ($(USE_SMART_BUILD),)
|
||||
USE_SMART_BUILD = no
|
||||
endif
|
||||
|
||||
#
|
||||
# Build global options
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Architecture or project specific options
|
||||
#
|
||||
|
||||
# Stack size to be allocated to the Cortex-M process stack. This stack is
|
||||
# the stack used by the main() thread.
|
||||
ifeq ($(USE_PROCESS_STACKSIZE),)
|
||||
USE_PROCESS_STACKSIZE = 0x400
|
||||
endif
|
||||
|
||||
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
|
||||
# stack is used for processing interrupts and exceptions.
|
||||
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
|
||||
USE_EXCEPTIONS_STACKSIZE = 0x400
|
||||
endif
|
||||
|
||||
# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
|
||||
ifeq ($(USE_FPU),)
|
||||
USE_FPU = no
|
||||
endif
|
||||
|
||||
#
|
||||
# Architecture or project specific options
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Project, sources and paths
|
||||
#
|
||||
|
||||
# Define project name here
|
||||
PROJECT = ch
|
||||
|
||||
# Imported source files and paths
|
||||
CHIBIOS = ../../../../ChibiOS-RT
|
||||
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
|
||||
# Startup files.
|
||||
include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk
|
||||
# HAL-OSAL files (optional).
|
||||
include $(CHIBIOS)/os/hal/hal.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/hal.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/$(PLATFORM)/platform.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/boards/$(BOARD)/board.mk
|
||||
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
|
||||
# RTOS files (optional).
|
||||
include $(CHIBIOS)/os/rt/rt.mk
|
||||
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
|
||||
# Other files (optional).
|
||||
include $(CHIBIOS)/test/rt/test.mk
|
||||
include $(CHIBIOS)/os/various/shell/shell.mk
|
||||
|
||||
# Define linker script file here
|
||||
LDSCRIPT= $(STARTUPLD)/NRF52832.ld
|
||||
|
||||
# C sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CSRC = $(STARTUPSRC) \
|
||||
$(KERNSRC) \
|
||||
$(PORTSRC) \
|
||||
$(OSALSRC) \
|
||||
$(HALSRC) \
|
||||
$(PLATFORMSRC) \
|
||||
$(BOARDSRC) \
|
||||
$(TESTSRC) \
|
||||
$(SHELLSRC) \
|
||||
$(CHIBIOS)/os/hal/lib/streams/memstreams.c \
|
||||
$(CHIBIOS)/os/hal/lib/streams/chprintf.c
|
||||
|
||||
CSRC += main.c
|
||||
|
||||
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CPPSRC =
|
||||
|
||||
# C sources to be compiled in ARM mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
# option that results in lower performance and larger code size.
|
||||
ACSRC =
|
||||
|
||||
# C++ sources to be compiled in ARM mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
# option that results in lower performance and larger code size.
|
||||
ACPPSRC =
|
||||
|
||||
# C sources to be compiled in THUMB mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
# option that results in lower performance and larger code size.
|
||||
TCSRC =
|
||||
|
||||
# C++ sources to be compiled in THUMB mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
# option that results in lower performance and larger code size.
|
||||
TCPPSRC =
|
||||
|
||||
# List ASM source files here
|
||||
ASMSRC =
|
||||
ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
|
||||
|
||||
|
||||
INCDIR = $(CHIBIOS)/os/license \
|
||||
$(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
|
||||
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
|
||||
$(SHELLINC) \
|
||||
$(CHIBIOS)/os/hal/lib/streams $(CHIBIOS)/os/various
|
||||
|
||||
|
||||
INCDIR += $(CHIBIOS_CONTRIB)/os/various
|
||||
|
||||
#
|
||||
# Project, sources and paths
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Compiler settings
|
||||
#
|
||||
|
||||
MCU = cortex-m4
|
||||
|
||||
TRGT = arm-none-eabi-
|
||||
CC = $(TRGT)gcc
|
||||
CPPC = $(TRGT)g++
|
||||
# Enable loading with g++ only if you need C++ runtime support.
|
||||
# NOTE: You can use C++ even without C++ support if you are careful. C++
|
||||
# runtime support makes code size explode.
|
||||
LD = $(TRGT)gcc
|
||||
#LD = $(TRGT)g++
|
||||
CP = $(TRGT)objcopy
|
||||
AS = $(TRGT)gcc -x assembler-with-cpp
|
||||
AR = $(TRGT)ar
|
||||
OD = $(TRGT)objdump
|
||||
SZ = $(TRGT)size
|
||||
HEX = $(CP) -O ihex
|
||||
BIN = $(CP) -O binary
|
||||
SREC = $(CP) -O srec
|
||||
|
||||
# ARM-specific options here
|
||||
AOPT =
|
||||
|
||||
# THUMB-specific options here
|
||||
TOPT = -mthumb -DTHUMB
|
||||
|
||||
# Define C warning options here
|
||||
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes -Wno-unused-parameter
|
||||
|
||||
# Define C++ warning options here
|
||||
CPPWARN = -Wall -Wextra -Wundef
|
||||
|
||||
#
|
||||
# Compiler settings
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Start of user section
|
||||
#
|
||||
|
||||
# List all user C define here, like -D_DEBUG=1
|
||||
UDEFS =
|
||||
|
||||
# Define ASM defines here
|
||||
UADEFS =
|
||||
|
||||
# List all user directories here
|
||||
UINCDIR =
|
||||
|
||||
# List the user directory to look for the libraries here
|
||||
ULIBDIR =
|
||||
|
||||
# List all user libraries here
|
||||
ULIBS =
|
||||
|
||||
#
|
||||
# End of user defines
|
||||
##############################################################################
|
||||
|
||||
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/
|
||||
include $(RULESPATH)/rules.mk
|
||||
|
||||
OHEX = $(BUILDDIR)/$(PROJECT).hex
|
||||
OELF = $(BUILDDIR)/$(PROJECT).elf
|
||||
OBIN = $(BUILDDIR)/$(PROJECT).bin
|
||||
|
||||
|
||||
|
||||
include $(CHIBIOS_CONTRIB)/os/various/jlink.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/various/gdb.mk
|
||||
|
||||
|
||||
pin-reset: jlink-pin-reset
|
||||
flash: all jlink-flash
|
||||
debug: gdb-debug
|
||||
erase-all: jlink-erase-all
|
||||
debug-server: jlink-debug-server
|
||||
|
||||
|
|
@ -0,0 +1,530 @@
|
|||
/*
|
||||
Copyright (C) 2016 Stephane D'Alu
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file templates/chconf.h
|
||||
* @brief Configuration file template.
|
||||
* @details A copy of this file must be placed in each project directory, it
|
||||
* contains the application specific kernel settings.
|
||||
*
|
||||
* @addtogroup config
|
||||
* @details Kernel related settings and hooks.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _CHCONF_H_
|
||||
#define _CHCONF_H_
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name System timers settings
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System time counter resolution.
|
||||
* @note Allowed values are 16 or 32 bits.
|
||||
*/
|
||||
#define CH_CFG_ST_RESOLUTION 32
|
||||
|
||||
/**
|
||||
* @brief System tick frequency.
|
||||
* @details Frequency of the system timer that drives the system ticks. This
|
||||
* setting also defines the system tick time unit.
|
||||
*/
|
||||
#define CH_CFG_ST_FREQUENCY 1000
|
||||
|
||||
/**
|
||||
* @brief Time delta constant for the tick-less mode.
|
||||
* @note If this value is zero then the system uses the classic
|
||||
* periodic tick. This value represents the minimum number
|
||||
* of ticks that is safe to specify in a timeout directive.
|
||||
* The value one is not valid, timeouts are rounded up to
|
||||
* this value.
|
||||
*/
|
||||
#define CH_CFG_ST_TIMEDELTA 0
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Kernel parameters and options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Round robin interval.
|
||||
* @details This constant is the number of system ticks allowed for the
|
||||
* threads before preemption occurs. Setting this value to zero
|
||||
* disables the preemption for threads with equal priority and the
|
||||
* round robin becomes cooperative. Note that higher priority
|
||||
* threads can still preempt, the kernel is always preemptive.
|
||||
* @note Disabling the round robin preemption makes the kernel more compact
|
||||
* and generally faster.
|
||||
* @note The round robin preemption is not supported in tickless mode and
|
||||
* must be set to zero in that case.
|
||||
*/
|
||||
#define CH_CFG_TIME_QUANTUM 0
|
||||
|
||||
/**
|
||||
* @brief Managed RAM size.
|
||||
* @details Size of the RAM area to be managed by the OS. If set to zero
|
||||
* then the whole available RAM is used. The core memory is made
|
||||
* available to the heap allocator and/or can be used directly through
|
||||
* the simplified core memory allocator.
|
||||
*
|
||||
* @note In order to let the OS manage the whole RAM the linker script must
|
||||
* provide the @p __heap_base__ and @p __heap_end__ symbols.
|
||||
* @note Requires @p CH_CFG_USE_MEMCORE.
|
||||
*/
|
||||
#define CH_CFG_MEMCORE_SIZE 0
|
||||
|
||||
/**
|
||||
* @brief Idle thread automatic spawn suppression.
|
||||
* @details When this option is activated the function @p chSysInit()
|
||||
* does not spawn the idle thread. The application @p main()
|
||||
* function becomes the idle thread and must implement an
|
||||
* infinite loop.
|
||||
*/
|
||||
#define CH_CFG_NO_IDLE_THREAD FALSE
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Performance options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief OS optimization.
|
||||
* @details If enabled then time efficient rather than space efficient code
|
||||
* is used when two possible implementations exist.
|
||||
*
|
||||
* @note This is not related to the compiler optimization options.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_OPTIMIZE_SPEED TRUE
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Subsystem options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Time Measurement APIs.
|
||||
* @details If enabled then the time measurement APIs are included in
|
||||
* the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_TM FALSE
|
||||
|
||||
/**
|
||||
* @brief Threads registry APIs.
|
||||
* @details If enabled then the registry APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_REGISTRY TRUE
|
||||
|
||||
/**
|
||||
* @brief Threads synchronization APIs.
|
||||
* @details If enabled then the @p chThdWait() function is included in
|
||||
* the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_WAITEXIT TRUE
|
||||
|
||||
/**
|
||||
* @brief Semaphores APIs.
|
||||
* @details If enabled then the Semaphores APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_SEMAPHORES TRUE
|
||||
|
||||
/**
|
||||
* @brief Semaphores queuing mode.
|
||||
* @details If enabled then the threads are enqueued on semaphores by
|
||||
* priority rather than in FIFO order.
|
||||
*
|
||||
* @note The default is @p FALSE. Enable this if you have special
|
||||
* requirements.
|
||||
* @note Requires @p CH_CFG_USE_SEMAPHORES.
|
||||
*/
|
||||
#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
|
||||
|
||||
/**
|
||||
* @brief Mutexes APIs.
|
||||
* @details If enabled then the mutexes APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_MUTEXES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables recursive behavior on mutexes.
|
||||
* @note Recursive mutexes are heavier and have an increased
|
||||
* memory footprint.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||
*/
|
||||
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
|
||||
|
||||
/**
|
||||
* @brief Conditional Variables APIs.
|
||||
* @details If enabled then the conditional variables APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||
*/
|
||||
#define CH_CFG_USE_CONDVARS TRUE
|
||||
|
||||
/**
|
||||
* @brief Conditional Variables APIs with timeout.
|
||||
* @details If enabled then the conditional variables APIs with timeout
|
||||
* specification are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_CONDVARS.
|
||||
*/
|
||||
#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
|
||||
|
||||
/**
|
||||
* @brief Events Flags APIs.
|
||||
* @details If enabled then the event flags APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_EVENTS TRUE
|
||||
|
||||
/**
|
||||
* @brief Events Flags APIs with timeout.
|
||||
* @details If enabled then the events APIs with timeout specification
|
||||
* are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_EVENTS.
|
||||
*/
|
||||
#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
|
||||
|
||||
/**
|
||||
* @brief Synchronous Messages APIs.
|
||||
* @details If enabled then the synchronous messages APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_MESSAGES TRUE
|
||||
|
||||
/**
|
||||
* @brief Synchronous Messages queuing mode.
|
||||
* @details If enabled then messages are served by priority rather than in
|
||||
* FIFO order.
|
||||
*
|
||||
* @note The default is @p FALSE. Enable this if you have special
|
||||
* requirements.
|
||||
* @note Requires @p CH_CFG_USE_MESSAGES.
|
||||
*/
|
||||
#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
|
||||
|
||||
/**
|
||||
* @brief Mailboxes APIs.
|
||||
* @details If enabled then the asynchronous messages (mailboxes) APIs are
|
||||
* included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_SEMAPHORES.
|
||||
*/
|
||||
#define CH_CFG_USE_MAILBOXES TRUE
|
||||
|
||||
/**
|
||||
* @brief I/O Queues APIs.
|
||||
* @details If enabled then the I/O queues APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_QUEUES TRUE
|
||||
|
||||
/**
|
||||
* @brief Core Memory Manager APIs.
|
||||
* @details If enabled then the core memory manager APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_MEMCORE TRUE
|
||||
|
||||
/**
|
||||
* @brief Heap Allocator APIs.
|
||||
* @details If enabled then the memory heap allocator APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
|
||||
* @p CH_CFG_USE_SEMAPHORES.
|
||||
* @note Mutexes are recommended.
|
||||
*/
|
||||
#define CH_CFG_USE_HEAP TRUE
|
||||
|
||||
/**
|
||||
* @brief Memory Pools Allocator APIs.
|
||||
* @details If enabled then the memory pools allocator APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_MEMPOOLS TRUE
|
||||
|
||||
/**
|
||||
* @brief Dynamic Threads APIs.
|
||||
* @details If enabled then the dynamic threads creation APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_WAITEXIT.
|
||||
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
|
||||
*/
|
||||
#define CH_CFG_USE_DYNAMIC TRUE
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Debug options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Debug option, kernel statistics.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_STATISTICS FALSE
|
||||
|
||||
/**
|
||||
* @brief Debug option, system state check.
|
||||
* @details If enabled the correct call protocol for system APIs is checked
|
||||
* at runtime.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_SYSTEM_STATE_CHECK TRUE
|
||||
|
||||
/**
|
||||
* @brief Debug option, parameters checks.
|
||||
* @details If enabled then the checks on the API functions input
|
||||
* parameters are activated.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_ENABLE_CHECKS FALSE
|
||||
|
||||
/**
|
||||
* @brief Debug option, consistency checks.
|
||||
* @details If enabled then all the assertions in the kernel code are
|
||||
* activated. This includes consistency checks inside the kernel,
|
||||
* runtime anomalies and port-defined checks.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_ENABLE_ASSERTS FALSE
|
||||
|
||||
/**
|
||||
* @brief Debug option, trace buffer.
|
||||
* @details If enabled then the context switch circular trace buffer is
|
||||
* activated.
|
||||
*
|
||||
* @note The default is @p CH_DBG_TRACE_MASK_NONE.
|
||||
*/
|
||||
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_NONE
|
||||
|
||||
/**
|
||||
* @brief Trace buffer entries.
|
||||
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
|
||||
* different from @p CH_DBG_TRACE_MASK_NONE.
|
||||
*/
|
||||
#define CH_DBG_TRACE_BUFFER_SIZE 128
|
||||
|
||||
/**
|
||||
* @brief Debug option, stack checks.
|
||||
* @details If enabled then a runtime stack check is performed.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note The stack check is performed in a architecture/port dependent way.
|
||||
* It may not be implemented or some ports.
|
||||
* @note The default failure mode is to halt the system with the global
|
||||
* @p panic_msg variable set to @p NULL.
|
||||
*/
|
||||
#define CH_DBG_ENABLE_STACK_CHECK FALSE
|
||||
|
||||
/**
|
||||
* @brief Debug option, stacks initialization.
|
||||
* @details If enabled then the threads working area is filled with a byte
|
||||
* value when a thread is created. This can be useful for the
|
||||
* runtime measurement of the used stack.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_FILL_THREADS FALSE
|
||||
|
||||
/**
|
||||
* @brief Debug option, threads profiling.
|
||||
* @details If enabled then a field is added to the @p thread_t structure that
|
||||
* counts the system ticks occurred while executing the thread.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note This debug option is not currently compatible with the
|
||||
* tickless mode.
|
||||
*/
|
||||
#define CH_DBG_THREADS_PROFILING FALSE
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Kernel hooks
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Threads descriptor structure extension.
|
||||
* @details User fields added to the end of the @p thread_t structure.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXTRA_FIELDS \
|
||||
/* Add threads custom fields here.*/
|
||||
|
||||
/**
|
||||
* @brief Threads initialization hook.
|
||||
* @details User initialization code added to the @p chThdInit() API.
|
||||
*
|
||||
* @note It is invoked from within @p chThdInit() and implicitly from all
|
||||
* the threads creation APIs.
|
||||
*/
|
||||
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
|
||||
/* Add threads initialization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Threads finalization hook.
|
||||
* @details User finalization code added to the @p chThdExit() API.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
|
||||
/* Add threads finalization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Context switch hook.
|
||||
* @details This hook is invoked just before switching between threads.
|
||||
*/
|
||||
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
|
||||
/* Context switch code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ISR enter hook.
|
||||
*/
|
||||
#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
|
||||
/* IRQ prologue code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ISR exit hook.
|
||||
*/
|
||||
#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
|
||||
/* IRQ epilogue code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Idle thread enter hook.
|
||||
* @note This hook is invoked within a critical zone, no OS functions
|
||||
* should be invoked from here.
|
||||
* @note This macro can be used to activate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_ENTER_HOOK() { \
|
||||
/* Idle-enter code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Idle thread leave hook.
|
||||
* @note This hook is invoked within a critical zone, no OS functions
|
||||
* should be invoked from here.
|
||||
* @note This macro can be used to deactivate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_LEAVE_HOOK() { \
|
||||
/* Idle-leave code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Idle Loop hook.
|
||||
* @details This hook is continuously invoked by the idle thread loop.
|
||||
*/
|
||||
#define CH_CFG_IDLE_LOOP_HOOK() { \
|
||||
/* Idle loop code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System tick event hook.
|
||||
* @details This hook is invoked in the system tick handler immediately
|
||||
* after processing the virtual timers queue.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_TICK_HOOK() { \
|
||||
/* System tick event code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System halt hook.
|
||||
* @details This hook is invoked in case to a system halting error before
|
||||
* the system is halted.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
|
||||
/* System halt code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Trace hook.
|
||||
* @details This hook is invoked each time a new record is written in the
|
||||
* trace buffer.
|
||||
*/
|
||||
#define CH_CFG_TRACE_HOOK(tep) { \
|
||||
/* Trace code here.*/ \
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Port-specific settings (override port settings defaulted in chcore.h). */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _CHCONF_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,340 @@
|
|||
/*
|
||||
Copyright (C) 2016 Stephane D'Alu
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file templates/halconf.h
|
||||
* @brief HAL configuration header.
|
||||
* @details HAL configuration file, this file allows to enable or disable the
|
||||
* various device drivers from your application. You may also use
|
||||
* this file in order to override the device drivers default settings.
|
||||
*
|
||||
* @addtogroup HAL_CONF
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _HALCONF_H_
|
||||
#define _HALCONF_H_
|
||||
|
||||
#include "mcuconf.h"
|
||||
|
||||
/**
|
||||
* @brief Enables the PAL subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_PAL TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ADC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_ADC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the CAN subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CAN FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the EXT subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_EXT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the GPT subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_GPT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the I2C subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_I2C FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the I2S subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_I2S FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ICU subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_ICU FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the MAC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_MAC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the MMC_SPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_MMC_SPI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the PWM subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_PWM FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the RTC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_RTC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SDC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SDC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SERIAL subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SERIAL TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SERIAL over USB subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SERIAL_USB FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SPI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the UART subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_UART FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the USB subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_USB FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the WDG subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_WDG TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* ADC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define ADC_USE_WAIT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define ADC_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* CAN driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Sleep mode related APIs inclusion switch.
|
||||
*/
|
||||
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
|
||||
#define CAN_USE_SLEEP_MODE TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I2C driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the mutual exclusion APIs on the I2C bus.
|
||||
*/
|
||||
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define I2C_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* MAC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables an event sources for incoming packets.
|
||||
*/
|
||||
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
|
||||
#define MAC_USE_ZERO_COPY FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables an event sources for incoming packets.
|
||||
*/
|
||||
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
|
||||
#define MAC_USE_EVENTS TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* MMC_SPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Delays insertions.
|
||||
* @details If enabled this options inserts delays into the MMC waiting
|
||||
* routines releasing some extra CPU time for the threads with
|
||||
* lower priority, this may slow down the driver a bit however.
|
||||
* This option is recommended also if the SPI driver does not
|
||||
* use a DMA channel and heavily loads the CPU.
|
||||
*/
|
||||
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||
#define MMC_NICE_WAITING TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SDC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Number of initialization attempts before rejecting the card.
|
||||
* @note Attempts are performed at 10mS intervals.
|
||||
*/
|
||||
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
|
||||
#define SDC_INIT_RETRY 100
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Include support for MMC cards.
|
||||
* @note MMC support is not yet implemented so this option must be kept
|
||||
* at @p FALSE.
|
||||
*/
|
||||
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
|
||||
#define SDC_MMC_SUPPORT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Delays insertions.
|
||||
* @details If enabled this options inserts delays into the MMC waiting
|
||||
* routines releasing some extra CPU time for the threads with
|
||||
* lower priority, this may slow down the driver a bit however.
|
||||
*/
|
||||
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||
#define SDC_NICE_WAITING TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SERIAL driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Default bit rate.
|
||||
* @details Configuration parameter, this is the baud rate selected for the
|
||||
* default configuration.
|
||||
*/
|
||||
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_DEFAULT_BITRATE 38400
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Serial buffers size.
|
||||
* @details Configuration parameter, you can change the depth of the queue
|
||||
* buffers depending on the requirements of your application.
|
||||
* @note The default is 64 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_BUFFERS_SIZE 16
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SERIAL_USB driver related setting. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Serial over USB buffers size.
|
||||
* @details Configuration parameter, the buffer size must be a multiple of
|
||||
* the USB data endpoint maximum packet size.
|
||||
* @note The default is 64 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_SIZE 256
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define SPI_USE_WAIT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define SPI_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Community drivers's includes */
|
||||
/*===========================================================================*/
|
||||
|
||||
#include "halconf_community.h"
|
||||
|
||||
#endif /* _HALCONF_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2016 Stéphane D'Alu
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _HALCONF_COMMUNITY_H_
|
||||
#define _HALCONF_COMMUNITY_H_
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables the community overlay.
|
||||
*/
|
||||
#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_COMMUNITY TRUE
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables the community subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_RNG TRUE
|
||||
#endif
|
||||
|
||||
|
||||
#define HAL_USE_QEI TRUE
|
||||
|
||||
|
||||
/*===========================================================================*/
|
||||
/* QEI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables discard of overlow
|
||||
*/
|
||||
#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__)
|
||||
#define QEI_USE_OVERFLOW_DISCARD TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables discard of overlow
|
||||
*/
|
||||
#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__)
|
||||
#define QEI_USE_OVERFLOW_MINMAX TRUE
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//#define HAL_USE_SOFTDEVICE TRUE
|
||||
|
||||
#define HAL_USE_CAPSENSE TRUE
|
||||
#define CAPSENSE_USE_WAIT TRUE
|
||||
#define CAPSENSE_USE_MUTUAL_EXCLUSION TRUE
|
||||
|
||||
|
||||
|
||||
#endif /* _HALCONF_COMMUNITY_H_ */
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
#include "chprintf.h"
|
||||
#include "shell.h"
|
||||
#include "ch_test.h"
|
||||
|
||||
#define LED_EXT 14
|
||||
|
||||
|
||||
bool watchdog_started = false;
|
||||
|
||||
void watchdog_callback(void) {
|
||||
palTogglePad(IOPORT1, LED2);
|
||||
palTogglePad(IOPORT1, LED3);
|
||||
palTogglePad(IOPORT1, LED4);
|
||||
}
|
||||
|
||||
WDGConfig WDG_config = {
|
||||
.pause_on_sleep = 0,
|
||||
.pause_on_halt = 0,
|
||||
.timeout_ms = 5000,
|
||||
.callback = watchdog_callback,
|
||||
};
|
||||
|
||||
|
||||
void gpt_callback(GPTDriver *gptp) {
|
||||
palTogglePad(IOPORT1, LED2);
|
||||
}
|
||||
|
||||
/*
|
||||
* GPT configuration
|
||||
* Frequency: 31250Hz (32us period)
|
||||
* Resolution: 16 bits
|
||||
*/
|
||||
static const GPTConfig gpt_config = {
|
||||
.frequency = 31250,
|
||||
.callback = gpt_callback,
|
||||
.resolution = 16,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Command Random
|
||||
*/
|
||||
#define RANDOM_BUFFER_SIZE 1024
|
||||
static uint8_t random_buffer[RANDOM_BUFFER_SIZE];
|
||||
|
||||
static void cmd_random(BaseSequentialStream *chp, int argc, char *argv[]) {
|
||||
uint16_t size = 16;
|
||||
uint16_t i = 0;
|
||||
uint8_t nl = 0;
|
||||
|
||||
if (argc > 0) {
|
||||
size = atoi(argv[0]);
|
||||
}
|
||||
|
||||
if (size > RANDOM_BUFFER_SIZE) {
|
||||
chprintf(chp, "random: maximum size is %d.\r\n", RANDOM_BUFFER_SIZE);
|
||||
return;
|
||||
}
|
||||
|
||||
chprintf(chp, "Fetching %d random byte(s):\r\n", size);
|
||||
|
||||
rngStart(&RNGD1, NULL);
|
||||
rngWrite(&RNGD1, random_buffer, size, TIME_INFINITE);
|
||||
rngStop(&RNGD1);
|
||||
|
||||
for (i = 0 ; i < size ; i++) {
|
||||
chprintf(chp, "%02x ", random_buffer[i]);
|
||||
if ((nl = (((i+1) % 20)) == 0))
|
||||
chprintf(chp, "\r\n");
|
||||
}
|
||||
if (!nl)
|
||||
chprintf(chp, "\r\n");
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
static void cmd_watchdog(BaseSequentialStream *chp, int argc, char *argv[]) {
|
||||
if ((argc != 2) || (strcmp(argv[0], "start"))) {
|
||||
usage:
|
||||
chprintf(chp, "Usage: watchdog start <timeout>\r\n"
|
||||
" <timeout> = 0..%d seconds\r\n",
|
||||
WDG_MAX_TIMEOUT_MS/1000);
|
||||
return;
|
||||
}
|
||||
int timeout = atoi(argv[1]);
|
||||
if ((timeout < 0) || (timeout > (WDG_MAX_TIMEOUT_MS/1000)))
|
||||
goto usage;
|
||||
|
||||
if (watchdog_started) {
|
||||
chprintf(chp, "Watchdog already started."
|
||||
" Can't be modified once activated.\r\n");
|
||||
return;
|
||||
}
|
||||
|
||||
chprintf(chp,
|
||||
"Watchdog started\r\n"
|
||||
"You need to push BTN1 every %d second(s)\r\n", timeout);
|
||||
|
||||
WDG_config.timeout_ms = timeout * 1000;
|
||||
wdgStart(&WDGD1, &WDG_config);
|
||||
watchdog_started = true;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
static void cmd_info(BaseSequentialStream *chp, int argc, char *argv[]) {
|
||||
chprintf(chp, "Watchdog max = %d ms\r\n", WDG_MAX_TIMEOUT_MS);
|
||||
}
|
||||
|
||||
|
||||
static THD_WORKING_AREA(shell_wa, 1024);
|
||||
|
||||
static const ShellCommand commands[] = {
|
||||
{"info", cmd_info },
|
||||
{"random", cmd_random },
|
||||
{"watchdog", cmd_watchdog },
|
||||
{NULL, NULL}
|
||||
};
|
||||
|
||||
static const ShellConfig shell_cfg1 = {
|
||||
(BaseSequentialStream *)&SD1,
|
||||
commands
|
||||
};
|
||||
|
||||
static SerialConfig serial_config = {
|
||||
.speed = 115200,
|
||||
.tx_pad = UART_TX,
|
||||
.rx_pad = UART_RX,
|
||||
#if NRF5_SERIAL_USE_HWFLOWCTRL == TRUE
|
||||
.rts_pad = UART_RTS,
|
||||
.cts_pad = UART_CTS,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
static THD_WORKING_AREA(waThread1, 64);
|
||||
static THD_FUNCTION(Thread1, arg) {
|
||||
|
||||
(void)arg;
|
||||
uint8_t led = LED4;
|
||||
|
||||
chRegSetThreadName("blinker");
|
||||
|
||||
|
||||
while (1) {
|
||||
palTogglePad(IOPORT1, led);
|
||||
chThdSleepMilliseconds(100);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#define printf(fmt, ...) \
|
||||
chprintf((BaseSequentialStream*)&SD1, fmt, ##__VA_ARGS__)
|
||||
|
||||
|
||||
|
||||
|
||||
/**@brief Function for application main entry.
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
|
||||
halInit();
|
||||
chSysInit();
|
||||
shellInit();
|
||||
|
||||
sdStart(&SD1, &serial_config);
|
||||
|
||||
palSetPad(IOPORT1, LED1);
|
||||
palClearPad(IOPORT1, LED2);
|
||||
palClearPad(IOPORT1, LED3);
|
||||
palSetPad(IOPORT1, LED4);
|
||||
|
||||
gptStart(&GPTD1, &gpt_config);
|
||||
gptStartContinuous(&GPTD1, 31250);
|
||||
|
||||
|
||||
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO+1,
|
||||
Thread1, NULL);
|
||||
|
||||
|
||||
|
||||
chThdCreateStatic(shell_wa, sizeof(shell_wa), NORMALPRIO+1,
|
||||
shellThread, (void *)&shell_cfg1);
|
||||
|
||||
|
||||
|
||||
|
||||
printf(PORT_INFO "\r\n");
|
||||
chThdSleep(2);
|
||||
|
||||
|
||||
|
||||
printf("Priority levels %d\r\n", CORTEX_PRIORITY_LEVELS);
|
||||
|
||||
//test_execute((BaseSequentialStream *)&SD1);
|
||||
|
||||
NRF_P0->DETECTMODE = 0;
|
||||
|
||||
while (true) {
|
||||
if (watchdog_started &&
|
||||
(palReadPad(IOPORT1, BTN1) == 0)) {
|
||||
palTogglePad(IOPORT1, LED1);
|
||||
wdgReset(&WDGD1);
|
||||
printf("Watchdog reseted\r\n");
|
||||
}
|
||||
chThdSleepMilliseconds(250);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
Copyright (C) 2016 Stephane D'Alu
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _MCUCONF_H_
|
||||
#define _MCUCONF_H_
|
||||
|
||||
/*
|
||||
* Board setting
|
||||
*/
|
||||
|
||||
|
||||
#define NRF5_SOFTDEVICE_THREAD_WA_SIZE 128
|
||||
|
||||
#define SHELL_CMD_TEST_ENABLED FALSE
|
||||
#define SHELL_CMD_ECHO_ENABLED FALSE
|
||||
#define SHELL_CMD_INFO_ENABLED FALSE
|
||||
|
||||
|
||||
|
||||
|
||||
#define NRF5_SOFTDEVICE_LFCLK_SOURCE NRF_CLOCK_LF_SRC_XTAL
|
||||
#define NRF5_SOFTDEVICE_LFCLK_ACCURACY NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM
|
||||
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define NRF5_SERIAL_USE_UART0 TRUE
|
||||
#define NRF5_SERIAL_USE_HWFLOWCTRL TRUE
|
||||
#define NRF5_RNG_USE_RNG0 TRUE
|
||||
#define NRF5_GPT_USE_TIMER0 TRUE
|
||||
|
||||
#define NRF5_QEI_USE_QDEC0 TRUE
|
||||
#define NRF5_QEI_USE_LED FALSE
|
||||
|
||||
#define WDG_USE_TIMEOUT_CALLBACK TRUE
|
||||
|
||||
|
||||
#endif /* _MCUCONF_H_ */
|
||||
|
|
@ -1,56 +1,147 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
<cconfiguration id="0.1306240181">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.1306240181" moduleId="org.eclipse.cdt.core.settings" name="Default">
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration buildProperties="" description="" id="0.1306240181" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
|
||||
<folderInfo id="0.1306240181." name="/" resourcePath="">
|
||||
<toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.1809487124" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
|
||||
<targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.1809487124.82130379" name=""/>
|
||||
<builder id="org.eclipse.cdt.build.core.settings.default.builder.1978195842" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
|
||||
<tool id="org.eclipse.cdt.build.core.settings.holder.libs.1542188159" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
|
||||
<tool id="org.eclipse.cdt.build.core.settings.holder.1536899570" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
|
||||
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.878634277" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
|
||||
</tool>
|
||||
<tool id="org.eclipse.cdt.build.core.settings.holder.508046483" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
|
||||
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1664032194" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
|
||||
</tool>
|
||||
<tool id="org.eclipse.cdt.build.core.settings.holder.87282723" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
|
||||
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.430808546" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="RT-STM32F429-DISCOVERY-DMA2D.null.1705354114" name="RT-STM32F429-DISCOVERY-DMA2D"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="0.2113576648">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="0.1306240181">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="0.114656749">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="refreshScope"/>
|
||||
</cproject>
|
||||
/*
|
||||
ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* FSMC driver system settings.
|
||||
*/
|
||||
#define STM32_FSMC_USE_FSMC1 FALSE
|
||||
#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10
|
||||
|
||||
/*
|
||||
* FSMC NAND driver system settings.
|
||||
*/
|
||||
#define STM32_NAND_USE_FSMC_NAND1 FALSE
|
||||
#define STM32_NAND_USE_FSMC_NAND2 FALSE
|
||||
#define STM32_NAND_USE_EXT_INT FALSE
|
||||
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_NAND_DMA_PRIORITY 0
|
||||
#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* FSMC SRAM driver system settings.
|
||||
*/
|
||||
#define STM32_USE_FSMC_SRAM FALSE
|
||||
#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
|
||||
#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
|
||||
#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
|
||||
#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
|
||||
|
||||
/*
|
||||
* FSMC SDRAM driver system settings.
|
||||
*/
|
||||
#define STM32_USE_FSMC_SDRAM FALSE
|
||||
|
||||
/*
|
||||
* TIMCAP driver system settings.
|
||||
*/
|
||||
#define STM32_TIMCAP_USE_TIM1 FALSE
|
||||
#define STM32_TIMCAP_USE_TIM2 FALSE
|
||||
#define STM32_TIMCAP_USE_TIM3 FALSE
|
||||
#define STM32_TIMCAP_USE_TIM4 FALSE
|
||||
#define STM32_TIMCAP_USE_TIM5 FALSE
|
||||
#define STM32_TIMCAP_USE_TIM8 FALSE
|
||||
#define STM32_TIMCAP_USE_TIM9 FALSE
|
||||
#define STM32_TIMCAP_TIM1_IRQ_PRIORITY 3
|
||||
#define STM32_TIMCAP_TIM2_IRQ_PRIORITY 3
|
||||
#define STM32_TIMCAP_TIM3_IRQ_PRIORITY 3
|
||||
#define STM32_TIMCAP_TIM4_IRQ_PRIORITY 3
|
||||
#define STM32_TIMCAP_TIM5_IRQ_PRIORITY 3
|
||||
#define STM32_TIMCAP_TIM8_IRQ_PRIORITY 3
|
||||
#define STM32_TIMCAP_TIM9_IRQ_PRIORITY 3
|
||||
|
||||
/*
|
||||
* COMP driver system settings.
|
||||
*/
|
||||
#define STM32_COMP_USE_COMP1 FALSE
|
||||
#define STM32_COMP_USE_COMP2 FALSE
|
||||
#define STM32_COMP_USE_COMP3 FALSE
|
||||
#define STM32_COMP_USE_COMP4 FALSE
|
||||
#define STM32_COMP_USE_COMP5 FALSE
|
||||
#define STM32_COMP_USE_COMP6 FALSE
|
||||
#define STM32_COMP_USE_COMP7 FALSE
|
||||
|
||||
#define STM32_COMP_USE_INTERRUPTS TRUE
|
||||
#define STM32_COMP_1_2_3_IRQ_PRIORITY 5
|
||||
#define STM32_COMP_4_5_6_IRQ_PRIORITY 5
|
||||
#define STM32_COMP_7_IRQ_PRIORITY 5
|
||||
|
||||
#if STM32_COMP_USE_INTERRUPTS
|
||||
#define STM32_DISABLE_EXTI21_22_29_HANDLER
|
||||
#define STM32_DISABLE_EXTI30_32_HANDLER
|
||||
#define STM32_DISABLE_EXTI33_HANDLER
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USBH driver system settings.
|
||||
*/
|
||||
#define STM32_OTG1_CHANNELS_NUMBER 8
|
||||
#define STM32_OTG2_CHANNELS_NUMBER 12
|
||||
|
||||
#define STM32_USBH_USE_OTG1 1
|
||||
#define STM32_OTG1_RXFIFO_SIZE 1024
|
||||
#define STM32_OTG1_PTXFIFO_SIZE 128
|
||||
#define STM32_OTG1_NPTXFIFO_SIZE 128
|
||||
|
||||
#define STM32_USBH_USE_OTG2 0
|
||||
#define STM32_OTG2_RXFIFO_SIZE 2048
|
||||
#define STM32_OTG2_PTXFIFO_SIZE 1024
|
||||
#define STM32_OTG2_NPTXFIFO_SIZE 1024
|
||||
|
||||
#define STM32_USBH_MIN_QSPACE 4
|
||||
#define STM32_USBH_CHANNELS_NP 4
|
||||
|
||||
/*
|
||||
* CRC driver system settings.
|
||||
*/
|
||||
#define STM32_CRC_USE_CRC1 TRUE
|
||||
#define STM32_CRC_CRC1_DMA_IRQ_PRIORITY 1
|
||||
#define STM32_CRC_CRC1_DMA_PRIORITY 2
|
||||
#define STM32_CRC_CRC1_DMA_STREAM STM32_DMA1_STREAM2
|
||||
|
||||
#define CRCSW_USE_CRC1 FALSE
|
||||
#define CRCSW_CRC32_TABLE TRUE
|
||||
#define CRCSW_CRC16_TABLE TRUE
|
||||
#define CRCSW_PROGRAMMABLE TRUE
|
||||
|
||||
/*
|
||||
* EICU driver system settings.
|
||||
*/
|
||||
#define STM32_EICU_USE_TIM1 FALSE
|
||||
#define STM32_EICU_USE_TIM2 FALSE
|
||||
#define STM32_EICU_USE_TIM3 TRUE
|
||||
#define STM32_EICU_USE_TIM4 FALSE
|
||||
#define STM32_EICU_USE_TIM5 FALSE
|
||||
#define STM32_EICU_USE_TIM8 FALSE
|
||||
#define STM32_EICU_USE_TIM9 FALSE
|
||||
#define STM32_EICU_USE_TIM10 FALSE
|
||||
#define STM32_EICU_USE_TIM11 FALSE
|
||||
#define STM32_EICU_USE_TIM12 FALSE
|
||||
#define STM32_EICU_USE_TIM13 FALSE
|
||||
#define STM32_EICU_USE_TIM14 FALSE
|
||||
#define STM32_EICU_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_EICU_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_EICU_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_EICU_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_EICU_TIM5_IRQ_PRIORITY 7
|
||||
#define STM32_EICU_TIM8_IRQ_PRIORITY 7
|
||||
#define STM32_EICU_TIM9_IRQ_PRIORITY 7
|
||||
#define STM32_EICU_TIM10_IRQ_PRIORITY 7
|
||||
#define STM32_EICU_TIM11_IRQ_PRIORITY 7
|
||||
#define STM32_EICU_TIM12_IRQ_PRIORITY 7
|
||||
#define STM32_EICU_TIM13_IRQ_PRIORITY 7
|
||||
#define STM32_EICU_TIM14_IRQ_PRIORITY 7
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
|
||||
# Compiler options here.
|
||||
ifeq ($(USE_OPT),)
|
||||
USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
|
||||
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
|
||||
endif
|
||||
|
||||
# C specific options here (added to USE_OPT).
|
||||
|
|
@ -30,7 +30,7 @@ endif
|
|||
|
||||
# Enable this if you want link time optimizations (LTO)
|
||||
ifeq ($(USE_LTO),)
|
||||
USE_LTO = no
|
||||
USE_LTO = yes
|
||||
endif
|
||||
|
||||
# If enabled, this option allows to compile the application in THUMB mode.
|
||||
|
|
@ -99,7 +99,9 @@ include $(CHIBIOS)/os/hal/osal/rt/osal.mk
|
|||
include $(CHIBIOS)/os/rt/rt.mk
|
||||
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
|
||||
# Other files (optional).
|
||||
include $(CHIBIOS)/test/rt/test.mk
|
||||
include $(CHIBIOS)/test/lib/test.mk
|
||||
include $(CHIBIOS)/test/rt/rt_test.mk
|
||||
include $(CHIBIOS)/test/oslib/oslib_test.mk
|
||||
include $(CHIBIOS)/os/hal/lib/streams/streams.mk
|
||||
include $(CHIBIOS)/os/various/shell/shell.mk
|
||||
|
||||
|
|
@ -119,7 +121,7 @@ CSRC = $(STARTUPSRC) \
|
|||
$(STREAMSSRC) \
|
||||
$(SHELLSRC) \
|
||||
$(CHIBIOS_CONTRIB)/os/various/devices_lib/lcd/ili9341.c \
|
||||
main.c \
|
||||
main.c usbcfg.c \
|
||||
wolf3d_palette.c \
|
||||
res/wolf3d_vgagraph_chunk87.c
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -29,6 +29,7 @@
|
|||
#define CHCONF_H
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
@ -48,7 +49,19 @@
|
|||
* @details Frequency of the system timer that drives the system ticks. This
|
||||
* setting also defines the system tick time unit.
|
||||
*/
|
||||
#define CH_CFG_ST_FREQUENCY 1000
|
||||
#define CH_CFG_ST_FREQUENCY 10000
|
||||
|
||||
/**
|
||||
* @brief Time intervals data size.
|
||||
* @note Allowed values are 16, 32 or 64 bits.
|
||||
*/
|
||||
#define CH_CFG_INTERVALS_SIZE 32
|
||||
|
||||
/**
|
||||
* @brief Time types data size.
|
||||
* @note Allowed values are 16 or 32 bits.
|
||||
*/
|
||||
#define CH_CFG_TIME_TYPES_SIZE 32
|
||||
|
||||
/**
|
||||
* @brief Time delta constant for the tick-less mode.
|
||||
|
|
@ -294,6 +307,15 @@
|
|||
*/
|
||||
#define CH_CFG_USE_MEMPOOLS TRUE
|
||||
|
||||
/**
|
||||
* @brief Objects FIFOs APIs.
|
||||
* @details If enabled then the objects FIFOs APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_OBJ_FIFOS TRUE
|
||||
|
||||
/**
|
||||
* @brief Dynamic Threads APIs.
|
||||
* @details If enabled then the dynamic threads creation APIs are included
|
||||
|
|
@ -307,6 +329,56 @@
|
|||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Objects factory options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Objects Factory APIs.
|
||||
* @details If enabled then the objects factory APIs are included in the
|
||||
* kernel.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_CFG_USE_FACTORY FALSE
|
||||
|
||||
/**
|
||||
* @brief Maximum length for object names.
|
||||
* @details If the specified length is zero then the name is stored by
|
||||
* pointer but this could have unintended side effects.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
|
||||
|
||||
/**
|
||||
* @brief Enables the registry of generic objects.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for generic buffers.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for semaphores.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_SEMAPHORES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for mailboxes.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_MAILBOXES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for objects FIFOs.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Debug options
|
||||
|
|
@ -406,6 +478,22 @@
|
|||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System structure extension.
|
||||
* @details User fields added to the end of the @p ch_system_t structure.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_EXTRA_FIELDS \
|
||||
/* Add threads custom fields here.*/
|
||||
|
||||
/**
|
||||
* @brief System initialization hook.
|
||||
* @details User initialization code added to the @p chSysInit() function
|
||||
* just before interrupts are enabled globally.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_INIT_HOOK(tp) { \
|
||||
/* Add threads initialization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Threads descriptor structure extension.
|
||||
* @details User fields added to the end of the @p thread_t structure.
|
||||
|
|
@ -415,9 +503,9 @@
|
|||
|
||||
/**
|
||||
* @brief Threads initialization hook.
|
||||
* @details User initialization code added to the @p chThdInit() API.
|
||||
* @details User initialization code added to the @p _thread_init() function.
|
||||
*
|
||||
* @note It is invoked from within @p chThdInit() and implicitly from all
|
||||
* @note It is invoked from within @p _thread_init() and implicitly from all
|
||||
* the threads creation APIs.
|
||||
*/
|
||||
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -51,6 +51,13 @@
|
|||
#define HAL_USE_CAN FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the cryptographic subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CRY FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the DAC subsystem.
|
||||
*/
|
||||
|
|
@ -114,6 +121,13 @@
|
|||
#define HAL_USE_PWM FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the QSPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_QSPI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the RTC subsystem.
|
||||
*/
|
||||
|
|
@ -139,7 +153,7 @@
|
|||
* @brief Enables the SERIAL over USB subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SERIAL_USB FALSE
|
||||
#define HAL_USE_SERIAL_USB TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -160,7 +174,7 @@
|
|||
* @brief Enables the USB subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_USB FALSE
|
||||
#define HAL_USE_USB TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -201,6 +215,28 @@
|
|||
#define CAN_USE_SLEEP_MODE TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* CRY driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the SW fall-back of the cryptographic driver.
|
||||
* @details When enabled, this option, activates a fall-back software
|
||||
* implementation for algorithms not supported by the underlying
|
||||
* hardware.
|
||||
* @note Fall-back implementations may not be present for all algorithms.
|
||||
*/
|
||||
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_USE_FALLBACK FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Makes the driver forcibly use the fall-back implementations.
|
||||
*/
|
||||
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_ENFORCE_FALLBACK FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I2C driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
|
|||
|
|
@ -14,8 +14,8 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _HALCONF_COMMUNITY_H_
|
||||
#define _HALCONF_COMMUNITY_H_
|
||||
#ifndef HALCONF_COMMUNITY_H
|
||||
#define HALCONF_COMMUNITY_H
|
||||
|
||||
/**
|
||||
* @brief Enables the community overlay.
|
||||
|
|
@ -66,7 +66,6 @@
|
|||
#define HAL_USE_RNG FALSE
|
||||
#endif
|
||||
|
||||
|
||||
/*===========================================================================*/
|
||||
/* FSMCNAND driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -94,6 +93,6 @@
|
|||
*/
|
||||
#define ONEWIRE_USE_SEARCH_ROM TRUE
|
||||
|
||||
#endif /* _HALCONF_COMMUNITY_H_ */
|
||||
#endif /* HALCONF_COMMUNITY_H */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -284,10 +284,12 @@ static const LTDCConfig ltdc_cfg = {
|
|||
extern LTDCDriver LTDCD1;
|
||||
|
||||
const SPIConfig spi_cfg5 = {
|
||||
false,
|
||||
NULL,
|
||||
GPIOC,
|
||||
GPIOC_SPI5_LCD_CS,
|
||||
(((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR),
|
||||
0
|
||||
};
|
||||
|
||||
extern SPIDriver SPID5;
|
||||
|
|
@ -473,10 +475,6 @@ static void dma2d_test(void) {
|
|||
/* Command line related. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if (HAL_USE_SERIAL_USB == TRUE)
|
||||
/* Virtual serial port over USB.*/
|
||||
SerialUSBDriver SDU1;
|
||||
#endif
|
||||
|
||||
#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
|
||||
#define TEST_WA_SIZE THD_WORKING_AREA_SIZE(256)
|
||||
|
|
@ -500,7 +498,7 @@ static const ShellCommand commands[] = {
|
|||
|
||||
static const ShellConfig shell_cfg1 = {
|
||||
#if (HAL_USE_SERIAL_USB == TRUE)
|
||||
(BaseSequentialStream *)&SDU1,
|
||||
(BaseSequentialStream *)&SDU2,
|
||||
#else
|
||||
(BaseSequentialStream *)&SD1,
|
||||
#endif
|
||||
|
|
@ -536,8 +534,8 @@ int main(void) {
|
|||
/*
|
||||
* Initializes a serial-over-USB CDC driver.
|
||||
*/
|
||||
sduObjectInit(&SDU1);
|
||||
sduStart(&SDU1, &serusbcfg);
|
||||
sduObjectInit(&SDU2);
|
||||
sduStart(&SDU2, &serusbcfg);
|
||||
|
||||
/*
|
||||
* Activates the USB driver and then the USB bus pull-up on D+.
|
||||
|
|
@ -594,7 +592,7 @@ int main(void) {
|
|||
while (true) {
|
||||
if (!shelltp) {
|
||||
#if (HAL_USE_SERIAL_USB == TRUE)
|
||||
if (SDU1.config->usbp->state == USB_ACTIVE) {
|
||||
if (SDU2.config->usbp->state == USB_ACTIVE) {
|
||||
/* Spawns a new shell.*/
|
||||
shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, "shell", NORMALPRIO, shellThread, (void *) &shell_cfg1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -69,6 +69,24 @@
|
|||
#define STM32_PLLSAIR_VALUE 4
|
||||
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI1_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI2_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI3_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI4_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI16_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI17_PRIORITY 15
|
||||
#define STM32_IRQ_EXTI18_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI19_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI20_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI21_PRIORITY 15
|
||||
#define STM32_IRQ_EXTI22_PRIORITY 15
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
|
|
@ -108,24 +126,6 @@
|
|||
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
*/
|
||||
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
|
||||
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
|
||||
#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
|
|
@ -243,8 +243,8 @@
|
|||
*/
|
||||
#define STM32_SDC_SDIO_DMA_PRIORITY 3
|
||||
#define STM32_SDC_SDIO_IRQ_PRIORITY 9
|
||||
#define STM32_SDC_WRITE_TIMEOUT_MS 250
|
||||
#define STM32_SDC_READ_TIMEOUT_MS 25
|
||||
#define STM32_SDC_WRITE_TIMEOUT_MS 1000
|
||||
#define STM32_SDC_READ_TIMEOUT_MS 1000
|
||||
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
|
||||
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
|
||||
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||||
|
|
@ -258,12 +258,16 @@
|
|||
#define STM32_SERIAL_USE_UART4 FALSE
|
||||
#define STM32_SERIAL_USE_UART5 FALSE
|
||||
#define STM32_SERIAL_USE_USART6 FALSE
|
||||
#define STM32_SERIAL_USE_UART7 FALSE
|
||||
#define STM32_SERIAL_USE_UART8 FALSE
|
||||
#define STM32_SERIAL_USART1_PRIORITY 12
|
||||
#define STM32_SERIAL_USART2_PRIORITY 12
|
||||
#define STM32_SERIAL_USART3_PRIORITY 12
|
||||
#define STM32_SERIAL_UART4_PRIORITY 12
|
||||
#define STM32_SERIAL_UART5_PRIORITY 12
|
||||
#define STM32_SERIAL_USART6_PRIORITY 12
|
||||
#define STM32_SERIAL_UART7_PRIORITY 12
|
||||
#define STM32_SERIAL_UART8_PRIORITY 12
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
|
|
@ -345,7 +349,7 @@
|
|||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 FALSE
|
||||
#define STM32_USB_USE_OTG2 FALSE
|
||||
#define STM32_USB_USE_OTG2 TRUE
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY 14
|
||||
#define STM32_USB_OTG2_IRQ_PRIORITY 14
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -17,6 +17,9 @@
|
|||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
|
||||
/* Virtual serial port over USB.*/
|
||||
SerialUSBDriver SDU2;
|
||||
|
||||
/*
|
||||
* Endpoints to be used for USBD2.
|
||||
*/
|
||||
|
|
@ -262,11 +265,9 @@ static const USBEndpointConfig ep2config = {
|
|||
* Handles the USB driver global events.
|
||||
*/
|
||||
static void usb_event(USBDriver *usbp, usbevent_t event) {
|
||||
extern SerialUSBDriver SDU1;
|
||||
extern SerialUSBDriver SDU2;
|
||||
|
||||
switch (event) {
|
||||
case USB_EVENT_RESET:
|
||||
return;
|
||||
case USB_EVENT_ADDRESS:
|
||||
return;
|
||||
case USB_EVENT_CONFIGURED:
|
||||
|
|
@ -279,13 +280,29 @@ static void usb_event(USBDriver *usbp, usbevent_t event) {
|
|||
usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config);
|
||||
|
||||
/* Resetting the state of the CDC subsystem.*/
|
||||
sduConfigureHookI(&SDU1);
|
||||
sduConfigureHookI(&SDU2);
|
||||
|
||||
chSysUnlockFromISR();
|
||||
return;
|
||||
case USB_EVENT_RESET:
|
||||
/* Falls into.*/
|
||||
case USB_EVENT_UNCONFIGURED:
|
||||
/* Falls into.*/
|
||||
case USB_EVENT_SUSPEND:
|
||||
chSysLockFromISR();
|
||||
|
||||
/* Disconnection event on suspend.*/
|
||||
sduSuspendHookI(&SDU2);
|
||||
|
||||
chSysUnlockFromISR();
|
||||
return;
|
||||
case USB_EVENT_WAKEUP:
|
||||
chSysLockFromISR();
|
||||
|
||||
/* Disconnection event on suspend.*/
|
||||
sduWakeupHookI(&SDU2);
|
||||
|
||||
chSysUnlockFromISR();
|
||||
return;
|
||||
case USB_EVENT_STALLED:
|
||||
return;
|
||||
|
|
@ -293,6 +310,18 @@ static void usb_event(USBDriver *usbp, usbevent_t event) {
|
|||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Handles the USB driver global events.
|
||||
*/
|
||||
static void sof_handler(USBDriver *usbp) {
|
||||
|
||||
(void)usbp;
|
||||
|
||||
osalSysLockFromISR();
|
||||
sduSOFHookI(&SDU2);
|
||||
osalSysUnlockFromISR();
|
||||
}
|
||||
|
||||
/*
|
||||
* USB driver configuration.
|
||||
*/
|
||||
|
|
@ -300,7 +329,7 @@ const USBConfig usbcfg = {
|
|||
usb_event,
|
||||
get_descriptor,
|
||||
sduRequestsHook,
|
||||
NULL
|
||||
sof_handler
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -14,12 +14,13 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _USBCFG_H_
|
||||
#define _USBCFG_H_
|
||||
#ifndef USBCFG_H
|
||||
#define USBCFG_H
|
||||
|
||||
extern const USBConfig usbcfg;
|
||||
extern SerialUSBConfig serusbcfg;
|
||||
extern SerialUSBDriver SDU2;
|
||||
|
||||
#endif /* _USBCFG_H_ */
|
||||
#endif /* USBCFG_H */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
|
||||
# Compiler options here.
|
||||
ifeq ($(USE_OPT),)
|
||||
USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
|
||||
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
|
||||
endif
|
||||
|
||||
# C specific options here (added to USE_OPT).
|
||||
|
|
@ -30,7 +30,7 @@ endif
|
|||
|
||||
# Enable this if you want link time optimizations (LTO)
|
||||
ifeq ($(USE_LTO),)
|
||||
USE_LTO = no
|
||||
USE_LTO = yes
|
||||
endif
|
||||
|
||||
# If enabled, this option allows to compile the application in THUMB mode.
|
||||
|
|
@ -99,7 +99,9 @@ include $(CHIBIOS)/os/hal/osal/rt/osal.mk
|
|||
include $(CHIBIOS)/os/rt/rt.mk
|
||||
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
|
||||
# Other files (optional).
|
||||
include $(CHIBIOS)/test/rt/test.mk
|
||||
include $(CHIBIOS)/test/lib/test.mk
|
||||
include $(CHIBIOS)/test/rt/rt_test.mk
|
||||
include $(CHIBIOS)/test/oslib/oslib_test.mk
|
||||
include $(CHIBIOS)/os/hal/lib/streams/streams.mk
|
||||
include $(CHIBIOS)/os/various/shell/shell.mk
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -29,6 +29,7 @@
|
|||
#define CHCONF_H
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
@ -48,7 +49,19 @@
|
|||
* @details Frequency of the system timer that drives the system ticks. This
|
||||
* setting also defines the system tick time unit.
|
||||
*/
|
||||
#define CH_CFG_ST_FREQUENCY 1000
|
||||
#define CH_CFG_ST_FREQUENCY 10000
|
||||
|
||||
/**
|
||||
* @brief Time intervals data size.
|
||||
* @note Allowed values are 16, 32 or 64 bits.
|
||||
*/
|
||||
#define CH_CFG_INTERVALS_SIZE 32
|
||||
|
||||
/**
|
||||
* @brief Time types data size.
|
||||
* @note Allowed values are 16 or 32 bits.
|
||||
*/
|
||||
#define CH_CFG_TIME_TYPES_SIZE 32
|
||||
|
||||
/**
|
||||
* @brief Time delta constant for the tick-less mode.
|
||||
|
|
@ -294,6 +307,15 @@
|
|||
*/
|
||||
#define CH_CFG_USE_MEMPOOLS FALSE
|
||||
|
||||
/**
|
||||
* @brief Objects FIFOs APIs.
|
||||
* @details If enabled then the objects FIFOs APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_OBJ_FIFOS FALSE
|
||||
|
||||
/**
|
||||
* @brief Dynamic Threads APIs.
|
||||
* @details If enabled then the dynamic threads creation APIs are included
|
||||
|
|
@ -307,6 +329,56 @@
|
|||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Objects factory options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Objects Factory APIs.
|
||||
* @details If enabled then the objects factory APIs are included in the
|
||||
* kernel.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_CFG_USE_FACTORY FALSE
|
||||
|
||||
/**
|
||||
* @brief Maximum length for object names.
|
||||
* @details If the specified length is zero then the name is stored by
|
||||
* pointer but this could have unintended side effects.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
|
||||
|
||||
/**
|
||||
* @brief Enables the registry of generic objects.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for generic buffers.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for semaphores.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_SEMAPHORES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for mailboxes.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_MAILBOXES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for objects FIFOs.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Debug options
|
||||
|
|
@ -406,6 +478,22 @@
|
|||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System structure extension.
|
||||
* @details User fields added to the end of the @p ch_system_t structure.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_EXTRA_FIELDS \
|
||||
/* Add threads custom fields here.*/
|
||||
|
||||
/**
|
||||
* @brief System initialization hook.
|
||||
* @details User initialization code added to the @p chSysInit() function
|
||||
* just before interrupts are enabled globally.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_INIT_HOOK(tp) { \
|
||||
/* Add threads initialization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Threads descriptor structure extension.
|
||||
* @details User fields added to the end of the @p thread_t structure.
|
||||
|
|
@ -415,9 +503,9 @@
|
|||
|
||||
/**
|
||||
* @brief Threads initialization hook.
|
||||
* @details User initialization code added to the @p chThdInit() API.
|
||||
* @details User initialization code added to the @p _thread_init() function.
|
||||
*
|
||||
* @note It is invoked from within @p chThdInit() and implicitly from all
|
||||
* @note It is invoked from within @p _thread_init() and implicitly from all
|
||||
* the threads creation APIs.
|
||||
*/
|
||||
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -51,6 +51,13 @@
|
|||
#define HAL_USE_CAN FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the cryptographic subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CRY FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the DAC subsystem.
|
||||
*/
|
||||
|
|
@ -114,6 +121,13 @@
|
|||
#define HAL_USE_PWM FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the QSPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_QSPI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the RTC subsystem.
|
||||
*/
|
||||
|
|
@ -201,6 +215,28 @@
|
|||
#define CAN_USE_SLEEP_MODE TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* CRY driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the SW fall-back of the cryptographic driver.
|
||||
* @details When enabled, this option, activates a fall-back software
|
||||
* implementation for algorithms not supported by the underlying
|
||||
* hardware.
|
||||
* @note Fall-back implementations may not be present for all algorithms.
|
||||
*/
|
||||
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_USE_FALLBACK FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Makes the driver forcibly use the fall-back implementations.
|
||||
*/
|
||||
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_ENFORCE_FALLBACK FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I2C driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
|
|||
|
|
@ -14,8 +14,8 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _HALCONF_COMMUNITY_H_
|
||||
#define _HALCONF_COMMUNITY_H_
|
||||
#ifndef HALCONF_COMMUNITY_H
|
||||
#define HALCONF_COMMUNITY_H
|
||||
|
||||
/**
|
||||
* @brief Enables the community overlay.
|
||||
|
|
@ -66,7 +66,6 @@
|
|||
#define HAL_USE_RNG FALSE
|
||||
#endif
|
||||
|
||||
|
||||
/*===========================================================================*/
|
||||
/* FSMCNAND driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -94,6 +93,6 @@
|
|||
*/
|
||||
#define ONEWIRE_USE_SEARCH_ROM TRUE
|
||||
|
||||
#endif /* _HALCONF_COMMUNITY_H_ */
|
||||
#endif /* HALCONF_COMMUNITY_H */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -28,8 +28,6 @@
|
|||
#include <stdlib.h>
|
||||
|
||||
#if (HAL_USE_SERIAL_USB == TRUE)
|
||||
/* Virtual serial port over USB.*/
|
||||
SerialUSBDriver SDU1;
|
||||
static BaseSequentialStream *const chout = (BaseSequentialStream *)&SDU1;
|
||||
#else
|
||||
static BaseSequentialStream *const chout = (BaseSequentialStream *)&SD1;
|
||||
|
|
@ -141,7 +139,7 @@ static THD_FUNCTION(reader_thread, arg) {
|
|||
osalThreadSuspendS(&thread_ref);
|
||||
reader_suspend = false;
|
||||
} else {
|
||||
osalThreadSleepS(MS2ST(reader_delay));
|
||||
osalThreadSleepS(TIME_MS2I(reader_delay));
|
||||
}
|
||||
old_priority = chThdGetPriorityX();
|
||||
osalSysUnlock();
|
||||
|
|
@ -180,7 +178,7 @@ static THD_FUNCTION(writer_thread, arg) {
|
|||
osalThreadSuspendS(&thread_ref);
|
||||
writer_suspend = false;
|
||||
} else {
|
||||
osalThreadSleepS(MS2ST(writer_delay));
|
||||
osalThreadSleepS(TIME_MS2I(writer_delay));
|
||||
}
|
||||
osalSysUnlock();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -69,6 +69,24 @@
|
|||
#define STM32_PLLSAIR_VALUE 4
|
||||
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI1_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI2_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI3_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI4_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI16_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI17_PRIORITY 15
|
||||
#define STM32_IRQ_EXTI18_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI19_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI20_PRIORITY 6
|
||||
#define STM32_IRQ_EXTI21_PRIORITY 15
|
||||
#define STM32_IRQ_EXTI22_PRIORITY 15
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
|
|
@ -108,24 +126,6 @@
|
|||
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
*/
|
||||
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
|
||||
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
|
||||
#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
|
|
@ -258,12 +258,16 @@
|
|||
#define STM32_SERIAL_USE_UART4 FALSE
|
||||
#define STM32_SERIAL_USE_UART5 FALSE
|
||||
#define STM32_SERIAL_USE_USART6 FALSE
|
||||
#define STM32_SERIAL_USE_UART7 FALSE
|
||||
#define STM32_SERIAL_USE_UART8 FALSE
|
||||
#define STM32_SERIAL_USART1_PRIORITY 12
|
||||
#define STM32_SERIAL_USART2_PRIORITY 12
|
||||
#define STM32_SERIAL_USART3_PRIORITY 12
|
||||
#define STM32_SERIAL_UART4_PRIORITY 12
|
||||
#define STM32_SERIAL_UART5_PRIORITY 12
|
||||
#define STM32_SERIAL_USART6_PRIORITY 12
|
||||
#define STM32_SERIAL_UART7_PRIORITY 12
|
||||
#define STM32_SERIAL_UART8_PRIORITY 12
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -14,9 +14,11 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
|
||||
/* Virtual serial port over USB.*/
|
||||
SerialUSBDriver SDU1;
|
||||
|
||||
/*
|
||||
* Endpoints to be used for USBD2.
|
||||
*/
|
||||
|
|
@ -265,8 +267,6 @@ static void usb_event(USBDriver *usbp, usbevent_t event) {
|
|||
extern SerialUSBDriver SDU1;
|
||||
|
||||
switch (event) {
|
||||
case USB_EVENT_RESET:
|
||||
return;
|
||||
case USB_EVENT_ADDRESS:
|
||||
return;
|
||||
case USB_EVENT_CONFIGURED:
|
||||
|
|
@ -283,9 +283,25 @@ static void usb_event(USBDriver *usbp, usbevent_t event) {
|
|||
|
||||
chSysUnlockFromISR();
|
||||
return;
|
||||
case USB_EVENT_RESET:
|
||||
/* Falls into.*/
|
||||
case USB_EVENT_UNCONFIGURED:
|
||||
/* Falls into.*/
|
||||
case USB_EVENT_SUSPEND:
|
||||
chSysLockFromISR();
|
||||
|
||||
/* Disconnection event on suspend.*/
|
||||
sduSuspendHookI(&SDU1);
|
||||
|
||||
chSysUnlockFromISR();
|
||||
return;
|
||||
case USB_EVENT_WAKEUP:
|
||||
chSysLockFromISR();
|
||||
|
||||
/* Disconnection event on suspend.*/
|
||||
sduWakeupHookI(&SDU1);
|
||||
|
||||
chSysUnlockFromISR();
|
||||
return;
|
||||
case USB_EVENT_STALLED:
|
||||
return;
|
||||
|
|
@ -293,6 +309,18 @@ static void usb_event(USBDriver *usbp, usbevent_t event) {
|
|||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Handles the USB driver global events.
|
||||
*/
|
||||
static void sof_handler(USBDriver *usbp) {
|
||||
|
||||
(void)usbp;
|
||||
|
||||
osalSysLockFromISR();
|
||||
sduSOFHookI(&SDU1);
|
||||
osalSysUnlockFromISR();
|
||||
}
|
||||
|
||||
/*
|
||||
* USB driver configuration.
|
||||
*/
|
||||
|
|
@ -300,7 +328,7 @@ const USBConfig usbcfg = {
|
|||
usb_event,
|
||||
get_descriptor,
|
||||
sduRequestsHook,
|
||||
NULL
|
||||
sof_handler
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -14,12 +14,13 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _USBCFG_H_
|
||||
#define _USBCFG_H_
|
||||
#ifndef USBCFG_H
|
||||
#define USBCFG_H
|
||||
|
||||
extern const USBConfig usbcfg;
|
||||
extern SerialUSBConfig serusbcfg;
|
||||
extern SerialUSBDriver SDU1;
|
||||
|
||||
#endif /* _USBCFG_H_ */
|
||||
#endif /* USBCFG_H */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -49,4 +49,5 @@
|
|||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="refreshScope"/>
|
||||
</cproject>
|
||||
|
|
|
|||
|
|
@ -80,17 +80,22 @@
|
|||
<link>
|
||||
<name>board</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS3/community/os/hal/boards/TI_TM4C123G_LAUNCHPAD</locationURI>
|
||||
<locationURI>PARENT-1-CHIBIOS/ChibiOS-Contrib/os/hal/boards/TI_TM4C123G_LAUNCHPAD</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>community_os</name>
|
||||
<type>2</type>
|
||||
<locationURI>PARENT-1-CHIBIOS/ChibiOS-Contrib/os</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>os</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS3/os</locationURI>
|
||||
<locationURI>CHIBIOS/os</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>test</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS3/test</locationURI>
|
||||
<locationURI>CHIBIOS/test</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
<variableList>
|
||||
|
|
|
|||
|
|
@ -43,6 +43,12 @@ ifeq ($(USE_VERBOSE_COMPILE),)
|
|||
USE_VERBOSE_COMPILE = no
|
||||
endif
|
||||
|
||||
# If enabled, this option makes the build process faster by not compiling
|
||||
# modules not used in the current configuration.
|
||||
ifeq ($(USE_SMART_BUILD),)
|
||||
USE_SMART_BUILD = yes
|
||||
endif
|
||||
|
||||
#
|
||||
# Build global options
|
||||
##############################################################################
|
||||
|
|
@ -65,7 +71,7 @@ endif
|
|||
|
||||
# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
|
||||
ifeq ($(USE_FPU),)
|
||||
USE_FPU = hard
|
||||
USE_FPU = no
|
||||
endif
|
||||
|
||||
#
|
||||
|
|
@ -82,6 +88,9 @@ PROJECT = ch
|
|||
# Imported source files and paths
|
||||
CHIBIOS = ../../../../ChibiOS-RT
|
||||
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
|
||||
|
||||
# Licensing files.
|
||||
include $(CHIBIOS)/os/license/license.mk
|
||||
# Startup files.
|
||||
include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
|
||||
# HAL-OSAL files (optional).
|
||||
|
|
@ -93,26 +102,22 @@ include $(CHIBIOS)/os/hal/osal/rt/osal.mk
|
|||
include $(CHIBIOS)/os/rt/rt.mk
|
||||
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
|
||||
# Other files (optional).
|
||||
include $(CHIBIOS)/test/rt/test.mk
|
||||
include $(CHIBIOS)/test/lib/test.mk
|
||||
include $(CHIBIOS)/test/rt/rt_test.mk
|
||||
include $(CHIBIOS)/test/oslib/oslib_test.mk
|
||||
|
||||
# Define linker script file here
|
||||
LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld
|
||||
|
||||
# C sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CSRC = $(STARTUPSRC) \
|
||||
$(KERNSRC) \
|
||||
$(PORTSRC) \
|
||||
$(OSALSRC) \
|
||||
$(HALSRC) \
|
||||
$(PLATFORMSRC) \
|
||||
$(BOARDSRC) \
|
||||
CSRC = $(ALLCSRC) \
|
||||
$(TESTSRC) \
|
||||
main.c
|
||||
|
||||
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CPPSRC =
|
||||
CPPSRC = $(ALLCPPSRC)
|
||||
|
||||
# C sources to be compiled in ARM mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
|
|
@ -135,13 +140,10 @@ TCSRC =
|
|||
TCPPSRC =
|
||||
|
||||
# List ASM source files here
|
||||
ASMSRC =
|
||||
ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
|
||||
ASMSRC = $(ALLASMSRC)
|
||||
ASMXSRC = $(ALLXASMSRC)
|
||||
|
||||
INCDIR = $(CHIBIOS)/os/license \
|
||||
$(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
|
||||
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
|
||||
$(CHIBIOS)/os/various
|
||||
INCDIR = $(ALLINC) $(TESTINC)
|
||||
|
||||
#
|
||||
# Project, sources and paths
|
||||
|
|
@ -177,10 +179,10 @@ AOPT =
|
|||
TOPT = -mthumb -DTHUMB
|
||||
|
||||
# Define C warning options here
|
||||
CWARN = -Wall -Wextra -Wstrict-prototypes
|
||||
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
|
||||
|
||||
# Define C++ warning options here
|
||||
CPPWARN = -Wall -Wextra
|
||||
CPPWARN = -Wall -Wextra -Wundef
|
||||
|
||||
#
|
||||
# Compiler settings
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -14,10 +14,22 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _CHCONF_H_
|
||||
#define _CHCONF_H_
|
||||
/**
|
||||
* @file templates/chconf.h
|
||||
* @brief Configuration file template.
|
||||
* @details A copy of this file must be placed in each project directory, it
|
||||
* contains the application specific kernel settings.
|
||||
*
|
||||
* @addtogroup config
|
||||
* @details Kernel related settings and hooks.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef CHCONF_H
|
||||
#define CHCONF_H
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
@ -39,6 +51,18 @@
|
|||
*/
|
||||
#define CH_CFG_ST_FREQUENCY 10000
|
||||
|
||||
/**
|
||||
* @brief Time intervals data size.
|
||||
* @note Allowed values are 16, 32 or 64 bits.
|
||||
*/
|
||||
#define CH_CFG_INTERVALS_SIZE 32
|
||||
|
||||
/**
|
||||
* @brief Time types data size.
|
||||
* @note Allowed values are 16 or 32 bits.
|
||||
*/
|
||||
#define CH_CFG_TIME_TYPES_SIZE 32
|
||||
|
||||
/**
|
||||
* @brief Time delta constant for the tick-less mode.
|
||||
* @note If this value is zero then the system uses the classic
|
||||
|
|
@ -47,14 +71,7 @@
|
|||
* The value one is not valid, timeouts are rounded up to
|
||||
* this value.
|
||||
*/
|
||||
#define CH_CFG_ST_TIMEDELTA 0
|
||||
|
||||
/**
|
||||
* @brief Realtime Counter frequency.
|
||||
* @details Frequency of the system counter used for realtime delays and
|
||||
* measurements.
|
||||
*/
|
||||
#define CH_CFG_RTC_FREQUENCY 80000000
|
||||
#define CH_CFG_ST_TIMEDELTA 2
|
||||
|
||||
/** @} */
|
||||
|
||||
|
|
@ -97,7 +114,8 @@
|
|||
* @details When this option is activated the function @p chSysInit()
|
||||
* does not spawn the idle thread. The application @p main()
|
||||
* function becomes the idle thread and must implement an
|
||||
* infinite loop. */
|
||||
* infinite loop.
|
||||
*/
|
||||
#define CH_CFG_NO_IDLE_THREAD FALSE
|
||||
|
||||
/** @} */
|
||||
|
|
@ -181,6 +199,16 @@
|
|||
*/
|
||||
#define CH_CFG_USE_MUTEXES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables recursive behavior on mutexes.
|
||||
* @note Recursive mutexes are heavier and have an increased
|
||||
* memory footprint.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||
*/
|
||||
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
|
||||
|
||||
/**
|
||||
* @brief Conditional Variables APIs.
|
||||
* @details If enabled then the conditional variables APIs are included
|
||||
|
|
@ -249,14 +277,6 @@
|
|||
*/
|
||||
#define CH_CFG_USE_MAILBOXES TRUE
|
||||
|
||||
/**
|
||||
* @brief I/O Queues APIs.
|
||||
* @details If enabled then the I/O queues APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_QUEUES TRUE
|
||||
|
||||
/**
|
||||
* @brief Core Memory Manager APIs.
|
||||
* @details If enabled then the core memory manager APIs are included
|
||||
|
|
@ -287,6 +307,15 @@
|
|||
*/
|
||||
#define CH_CFG_USE_MEMPOOLS TRUE
|
||||
|
||||
/**
|
||||
* @brief Objects FIFOs APIs.
|
||||
* @details If enabled then the objects FIFOs APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_OBJ_FIFOS TRUE
|
||||
|
||||
/**
|
||||
* @brief Dynamic Threads APIs.
|
||||
* @details If enabled then the dynamic threads creation APIs are included
|
||||
|
|
@ -300,6 +329,56 @@
|
|||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Objects factory options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Objects Factory APIs.
|
||||
* @details If enabled then the objects factory APIs are included in the
|
||||
* kernel.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_CFG_USE_FACTORY TRUE
|
||||
|
||||
/**
|
||||
* @brief Maximum length for object names.
|
||||
* @details If the specified length is zero then the name is stored by
|
||||
* pointer but this could have unintended side effects.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
|
||||
|
||||
/**
|
||||
* @brief Enables the registry of generic objects.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for generic buffers.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for semaphores.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_SEMAPHORES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for mailboxes.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_MAILBOXES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for objects FIFOs.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Debug options
|
||||
|
|
@ -344,12 +423,18 @@
|
|||
|
||||
/**
|
||||
* @brief Debug option, trace buffer.
|
||||
* @details If enabled then the context switch circular trace buffer is
|
||||
* activated.
|
||||
* @details If enabled then the trace buffer is activated.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
|
||||
*/
|
||||
#define CH_DBG_ENABLE_TRACE FALSE
|
||||
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
|
||||
|
||||
/**
|
||||
* @brief Trace buffer entries.
|
||||
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
|
||||
* different from @p CH_DBG_TRACE_MASK_DISABLED.
|
||||
*/
|
||||
#define CH_DBG_TRACE_BUFFER_SIZE 128
|
||||
|
||||
/**
|
||||
* @brief Debug option, stack checks.
|
||||
|
|
@ -393,6 +478,22 @@
|
|||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System structure extension.
|
||||
* @details User fields added to the end of the @p ch_system_t structure.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_EXTRA_FIELDS \
|
||||
/* Add threads custom fields here.*/
|
||||
|
||||
/**
|
||||
* @brief System initialization hook.
|
||||
* @details User initialization code added to the @p chSysInit() function
|
||||
* just before interrupts are enabled globally.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_INIT_HOOK(tp) { \
|
||||
/* Add threads initialization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Threads descriptor structure extension.
|
||||
* @details User fields added to the end of the @p thread_t structure.
|
||||
|
|
@ -402,9 +503,9 @@
|
|||
|
||||
/**
|
||||
* @brief Threads initialization hook.
|
||||
* @details User initialization code added to the @p chThdInit() API.
|
||||
* @details User initialization code added to the @p _thread_init() function.
|
||||
*
|
||||
* @note It is invoked from within @p chThdInit() and implicitly from all
|
||||
* @note It is invoked from within @p _thread_init() and implicitly from all
|
||||
* the threads creation APIs.
|
||||
*/
|
||||
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
|
||||
|
|
@ -414,10 +515,6 @@
|
|||
/**
|
||||
* @brief Threads finalization hook.
|
||||
* @details User finalization code added to the @p chThdExit() API.
|
||||
*
|
||||
* @note It is inserted into lock zone.
|
||||
* @note It is also invoked when the threads simply return in order to
|
||||
* terminate.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
|
||||
/* Add threads finalization code here.*/ \
|
||||
|
|
@ -428,7 +525,7 @@
|
|||
* @details This hook is invoked just before switching between threads.
|
||||
*/
|
||||
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
|
||||
/* System halt code here.*/ \
|
||||
/* Context switch code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -452,6 +549,7 @@
|
|||
* @note This macro can be used to activate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_ENTER_HOOK() { \
|
||||
/* Idle-enter code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -461,6 +559,7 @@
|
|||
* @note This macro can be used to deactivate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_LEAVE_HOOK() { \
|
||||
/* Idle-leave code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -504,6 +603,6 @@
|
|||
/* Port-specific settings (override port settings defaulted in chcore.h). */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _CHCONF_H_ */
|
||||
#endif /* CHCONF_H */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -1,10 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="org.eclipse.ui.externaltools.ProgramLaunchConfigurationType">
|
||||
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
|
||||
<listEntry value="org.eclipse.ui.externaltools.launchGroup"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.ui.externaltools.ATTR_LAUNCH_CONFIGURATION_BUILD_SCOPE" value="${none}"/>
|
||||
<stringAttribute key="org.eclipse.ui.externaltools.ATTR_LOCATION" value="${eclipse_home}\..\tools\openocd\bin\openocd.exe"/>
|
||||
<stringAttribute key="org.eclipse.ui.externaltools.ATTR_TOOL_ARGUMENTS" value="-c "telnet_port 4444" -f "interface/ti-icdi.cfg" -f "${file_prompt}""/>
|
||||
<stringAttribute key="org.eclipse.ui.externaltools.ATTR_WORKING_DIRECTORY" value="${eclipse_home}\..\tools\openocd\bin\"/>
|
||||
</launchConfiguration>
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -14,8 +14,19 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _HALCONF_H_
|
||||
#define _HALCONF_H_
|
||||
/**
|
||||
* @file templates/halconf.h
|
||||
* @brief HAL configuration header.
|
||||
* @details HAL configuration file, this file allows to enable or disable the
|
||||
* various device drivers from your application. You may also use
|
||||
* this file in order to override the device drivers default settings.
|
||||
*
|
||||
* @addtogroup HAL_CONF
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef HALCONF_H
|
||||
#define HALCONF_H
|
||||
|
||||
#include "mcuconf.h"
|
||||
|
||||
|
|
@ -40,6 +51,20 @@
|
|||
#define HAL_USE_CAN FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the cryptographic subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CRY FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the DAC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_DAC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the EXT subsystem.
|
||||
*/
|
||||
|
|
@ -61,6 +86,13 @@
|
|||
#define HAL_USE_I2C FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the I2S subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_I2S FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ICU subsystem.
|
||||
*/
|
||||
|
|
@ -89,6 +121,13 @@
|
|||
#define HAL_USE_PWM FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the QSPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_QSPI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the RTC subsystem.
|
||||
*/
|
||||
|
|
@ -138,6 +177,13 @@
|
|||
#define HAL_USE_USB FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the WDG subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_WDG FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* ADC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -169,6 +215,28 @@
|
|||
#define CAN_USE_SLEEP_MODE TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* CRY driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the SW fall-back of the cryptographic driver.
|
||||
* @details When enabled, this option, activates a fall-back software
|
||||
* implementation for algorithms not supported by the underlying
|
||||
* hardware.
|
||||
* @note Fall-back implementations may not be present for all algorithms.
|
||||
*/
|
||||
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_USE_FALLBACK FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Makes the driver forcibly use the fall-back implementations.
|
||||
*/
|
||||
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_ENFORCE_FALLBACK FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I2C driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -262,13 +330,36 @@
|
|||
* @brief Serial buffers size.
|
||||
* @details Configuration parameter, you can change the depth of the queue
|
||||
* buffers depending on the requirements of your application.
|
||||
* @note The default is 64 bytes for both the transmission and receive
|
||||
* @note The default is 16 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_BUFFERS_SIZE 16
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SERIAL_USB driver related setting. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Serial over USB buffers size.
|
||||
* @details Configuration parameter, the buffer size must be a multiple of
|
||||
* the USB data endpoint maximum packet size.
|
||||
* @note The default is 256 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_SIZE 256
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Serial over USB number of buffers.
|
||||
* @note The default is 2 buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_NUMBER 2
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -289,6 +380,38 @@
|
|||
#define SPI_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
#endif /* _HALCONF_H_ */
|
||||
/*===========================================================================*/
|
||||
/* UART driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define UART_USE_WAIT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define UART_USE_MUTUAL_EXCLUSION FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* USB driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define USB_USE_WAIT FALSE
|
||||
#endif
|
||||
|
||||
#endif /* HALCONF_H */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
Copyright (C) 2014..2016 Marco Veeneman
|
||||
Copyright (C) 2014..2017 Marco Veeneman
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -16,13 +16,13 @@
|
|||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
#include "ch_test.h"
|
||||
#include "rt_test_root.h"
|
||||
#include "oslib_test_root.h"
|
||||
|
||||
typedef struct led_config
|
||||
{
|
||||
ioportid_t port;
|
||||
ioline_t line;
|
||||
uint32_t sleep;
|
||||
uint8_t pin;
|
||||
} led_config_t;
|
||||
|
||||
/*
|
||||
|
|
@ -36,11 +36,11 @@ static THD_FUNCTION(blinkLed, arg) {
|
|||
|
||||
chRegSetThreadName("Blinker");
|
||||
|
||||
palSetPadMode(ledConfig->port, ledConfig->pin, PAL_MODE_OUTPUT_PUSHPULL);
|
||||
palSetLineMode(ledConfig->line, PAL_MODE_OUTPUT_PUSHPULL);
|
||||
|
||||
while (TRUE) {
|
||||
chThdSleepMilliseconds(ledConfig->sleep);
|
||||
palTogglePad(ledConfig->port, ledConfig->pin);
|
||||
palToggleLine(ledConfig->line);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -62,37 +62,44 @@ int main(void)
|
|||
chSysInit();
|
||||
|
||||
/* Configure RX and TX pins for UART0.*/
|
||||
palSetPadMode(GPIOA, GPIOA_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
|
||||
palSetPadMode(GPIOA, GPIOA_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
|
||||
palSetLineMode(LINE_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
|
||||
palSetLineMode(LINE_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
|
||||
|
||||
/* Start the serial driver with the default configuration.*/
|
||||
sdStart(&SD1, NULL);
|
||||
|
||||
if (!palReadPad(GPIOF, GPIOF_SW2)) {
|
||||
test_execute((BaseSequentialStream *)&SD1);
|
||||
if (!palReadLine(LINE_SW2)) {
|
||||
test_execute((BaseSequentialStream *)&SD1, &rt_test_suite);
|
||||
test_execute((BaseSequentialStream *)&SD1, &oslib_test_suite);
|
||||
}
|
||||
|
||||
ledRed.port = GPIOF;
|
||||
ledRed.pin = GPIOF_LED_RED;
|
||||
ledRed.line = LINE_LED_RED;
|
||||
ledRed.sleep = 100;
|
||||
|
||||
ledGreen.port = GPIOF;
|
||||
ledGreen.pin = GPIOF_LED_GREEN;
|
||||
ledGreen.line = LINE_LED_GREEN;
|
||||
ledGreen.sleep = 101;
|
||||
|
||||
ledBlue.port = GPIOF;
|
||||
ledBlue.pin = GPIOF_LED_BLUE;
|
||||
ledBlue.line = LINE_LED_BLUE;
|
||||
ledBlue.sleep = 102;
|
||||
|
||||
/* Creating the blinker threads.*/
|
||||
chThdCreateStatic(waBlinkLedRed, sizeof(waBlinkLedRed), NORMALPRIO, blinkLed,
|
||||
chThdCreateStatic(waBlinkLedRed,
|
||||
sizeof(waBlinkLedRed),
|
||||
NORMALPRIO,
|
||||
blinkLed,
|
||||
&ledRed);
|
||||
|
||||
chThdCreateStatic(waBlinkLedGreen, sizeof(waBlinkLedGreen), NORMALPRIO,
|
||||
blinkLed, &ledGreen);
|
||||
chThdCreateStatic(waBlinkLedGreen,
|
||||
sizeof(waBlinkLedGreen),
|
||||
NORMALPRIO,
|
||||
blinkLed,
|
||||
&ledGreen);
|
||||
|
||||
chThdCreateStatic(waBlinkLedBlue, sizeof(waBlinkLedBlue), NORMALPRIO,
|
||||
blinkLed, &ledBlue);
|
||||
chThdCreateStatic(waBlinkLedBlue,
|
||||
sizeof(waBlinkLedBlue),
|
||||
NORMALPRIO,
|
||||
blinkLed,
|
||||
&ledBlue);
|
||||
|
||||
/* Normal main() thread activity.*/
|
||||
while (TRUE) {
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
Copyright (C) 2014..2016 Marco Veeneman
|
||||
Copyright (C) 2014..2017 Marco Veeneman
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -30,25 +30,25 @@
|
|||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC
|
||||
#define TIVA_OSCSRC SYSCTL_RCC2_OSCSRC2_MO
|
||||
#define TIVA_MOSC_ENABLE TRUE
|
||||
#define TIVA_DIV400_VALUE 1
|
||||
#define TIVA_SYSDIV_VALUE 2
|
||||
#define TIVA_USESYSDIV_ENABLE FALSE
|
||||
#define TIVA_SYSDIV2LSB_ENABLE FALSE
|
||||
#define TIVA_BYPASS_VALUE 0
|
||||
#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \
|
||||
TIVA_RCC_PWMDIV_8)
|
||||
#define TIVA_PWM_FIELDS (SYSCTL_RCC_USEPWMDIV | \
|
||||
SYSCTL_RCC_PWMDIV_8)
|
||||
|
||||
/*
|
||||
* GPIO driver system settings.
|
||||
* PAL driver system settings.
|
||||
*/
|
||||
#define TIVA_GPIO_GPIOA_USE_AHB TRUE
|
||||
#define TIVA_GPIO_GPIOB_USE_AHB TRUE
|
||||
#define TIVA_GPIO_GPIOC_USE_AHB TRUE
|
||||
#define TIVA_GPIO_GPIOD_USE_AHB TRUE
|
||||
#define TIVA_GPIO_GPIOE_USE_AHB TRUE
|
||||
#define TIVA_GPIO_GPIOF_USE_AHB TRUE
|
||||
#define TIVA_PAL_GPIOA_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOB_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOC_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOD_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOE_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOF_IRQ_PRIORITY 3
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
|
|
|
|||
|
|
@ -22,22 +22,79 @@
|
|||
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<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/TM4C129x"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/boards/TI_TM4C1294_LAUNCHPAD"/>
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|
||||
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
|
||||
</tool>
|
||||
|
|
|
|||
|
|
@ -27,22 +27,17 @@
|
|||
<link>
|
||||
<name>board</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS3/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD</locationURI>
|
||||
<locationURI>PARENT-1-CHIBIOS/ChibiOS-Contrib/os/hal/boards/TI_TM4C1294_LAUNCHPAD</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>community_os</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS3/community</locationURI>
|
||||
<locationURI>PARENT-1-CHIBIOS/ChibiOS-Contrib/os</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>os</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS3/os</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>test</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS3/test</locationURI>
|
||||
<locationURI>CHIBIOS/os</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
<variableList>
|
||||
|
|
|
|||
|
|
@ -43,6 +43,12 @@ ifeq ($(USE_VERBOSE_COMPILE),)
|
|||
USE_VERBOSE_COMPILE = no
|
||||
endif
|
||||
|
||||
# If enabled, this option makes the build process faster by not compiling
|
||||
# modules not used in the current configuration.
|
||||
ifeq ($(USE_SMART_BUILD),)
|
||||
USE_SMART_BUILD = yes
|
||||
endif
|
||||
|
||||
#
|
||||
# Build global options
|
||||
##############################################################################
|
||||
|
|
@ -65,7 +71,7 @@ endif
|
|||
|
||||
# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
|
||||
ifeq ($(USE_FPU),)
|
||||
USE_FPU = hard
|
||||
USE_FPU = no
|
||||
endif
|
||||
|
||||
#
|
||||
|
|
@ -82,6 +88,9 @@ PROJECT = ch
|
|||
# Imported source files and paths
|
||||
CHIBIOS = ../../../../ChibiOS-RT
|
||||
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
|
||||
|
||||
# Licensing files.
|
||||
include $(CHIBIOS)/os/license/license.mk
|
||||
# Startup files.
|
||||
include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
|
||||
# HAL-OSAL files (optional).
|
||||
|
|
@ -100,22 +109,13 @@ LDSCRIPT= $(STARTUPLD)/TM4C129xNC.ld
|
|||
|
||||
# C sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CSRC = $(STARTUPSRC) \
|
||||
$(KERNSRC) \
|
||||
$(PORTSRC) \
|
||||
$(OSALSRC) \
|
||||
$(HALSRC) \
|
||||
$(PLATFORMSRC) \
|
||||
$(BOARDSRC) \
|
||||
$(TESTSRC) \
|
||||
$(LWSRC) \
|
||||
CSRC = $(ALLCSRC) \
|
||||
$(CHIBIOS)/os/various/evtimer.c \
|
||||
main.c \
|
||||
web/web.c \
|
||||
main.c
|
||||
|
||||
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CPPSRC =
|
||||
CPPSRC = $(ALLCPPSRC)
|
||||
|
||||
# C sources to be compiled in ARM mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
|
|
@ -138,13 +138,10 @@ TCSRC =
|
|||
TCPPSRC =
|
||||
|
||||
# List ASM source files here
|
||||
ASMSRC =
|
||||
ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
|
||||
ASMSRC = $(ALLASMSRC)
|
||||
ASMXSRC = $(ALLXASMSRC)
|
||||
|
||||
INCDIR = $(CHIBIOS)/os/license \
|
||||
$(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
|
||||
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
|
||||
$(CHIBIOS)/os/various $(LWINC)
|
||||
INCDIR = $(ALLINC) $(CHIBIOS)/os/various
|
||||
|
||||
#
|
||||
# Project, sources and paths
|
||||
|
|
@ -180,10 +177,10 @@ AOPT =
|
|||
TOPT = -mthumb -DTHUMB
|
||||
|
||||
# Define C warning options here
|
||||
CWARN = -Wall -Wextra -Wstrict-prototypes
|
||||
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
|
||||
|
||||
# Define C++ warning options here
|
||||
CPPWARN = -Wall -Wextra
|
||||
CPPWARN = -Wall -Wextra -Wundef
|
||||
|
||||
#
|
||||
# Compiler settings
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -14,10 +14,22 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _CHCONF_H_
|
||||
#define _CHCONF_H_
|
||||
/**
|
||||
* @file templates/chconf.h
|
||||
* @brief Configuration file template.
|
||||
* @details A copy of this file must be placed in each project directory, it
|
||||
* contains the application specific kernel settings.
|
||||
*
|
||||
* @addtogroup config
|
||||
* @details Kernel related settings and hooks.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef CHCONF_H
|
||||
#define CHCONF_H
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
@ -39,6 +51,18 @@
|
|||
*/
|
||||
#define CH_CFG_ST_FREQUENCY 10000
|
||||
|
||||
/**
|
||||
* @brief Time intervals data size.
|
||||
* @note Allowed values are 16, 32 or 64 bits.
|
||||
*/
|
||||
#define CH_CFG_INTERVALS_SIZE 32
|
||||
|
||||
/**
|
||||
* @brief Time types data size.
|
||||
* @note Allowed values are 16 or 32 bits.
|
||||
*/
|
||||
#define CH_CFG_TIME_TYPES_SIZE 32
|
||||
|
||||
/**
|
||||
* @brief Time delta constant for the tick-less mode.
|
||||
* @note If this value is zero then the system uses the classic
|
||||
|
|
@ -49,13 +73,6 @@
|
|||
*/
|
||||
#define CH_CFG_ST_TIMEDELTA 0
|
||||
|
||||
/**
|
||||
* @brief Realtime Counter frequency.
|
||||
* @details Frequency of the system counter used for realtime delays and
|
||||
* measurements.
|
||||
*/
|
||||
#define CH_CFG_RTC_FREQUENCY 80000000
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -97,7 +114,8 @@
|
|||
* @details When this option is activated the function @p chSysInit()
|
||||
* does not spawn the idle thread. The application @p main()
|
||||
* function becomes the idle thread and must implement an
|
||||
* infinite loop. */
|
||||
* infinite loop.
|
||||
*/
|
||||
#define CH_CFG_NO_IDLE_THREAD FALSE
|
||||
|
||||
/** @} */
|
||||
|
|
@ -181,6 +199,16 @@
|
|||
*/
|
||||
#define CH_CFG_USE_MUTEXES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables recursive behavior on mutexes.
|
||||
* @note Recursive mutexes are heavier and have an increased
|
||||
* memory footprint.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||
*/
|
||||
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
|
||||
|
||||
/**
|
||||
* @brief Conditional Variables APIs.
|
||||
* @details If enabled then the conditional variables APIs are included
|
||||
|
|
@ -249,14 +277,6 @@
|
|||
*/
|
||||
#define CH_CFG_USE_MAILBOXES TRUE
|
||||
|
||||
/**
|
||||
* @brief I/O Queues APIs.
|
||||
* @details If enabled then the I/O queues APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_QUEUES TRUE
|
||||
|
||||
/**
|
||||
* @brief Core Memory Manager APIs.
|
||||
* @details If enabled then the core memory manager APIs are included
|
||||
|
|
@ -287,6 +307,15 @@
|
|||
*/
|
||||
#define CH_CFG_USE_MEMPOOLS TRUE
|
||||
|
||||
/**
|
||||
* @brief Objects FIFOs APIs.
|
||||
* @details If enabled then the objects FIFOs APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_OBJ_FIFOS TRUE
|
||||
|
||||
/**
|
||||
* @brief Dynamic Threads APIs.
|
||||
* @details If enabled then the dynamic threads creation APIs are included
|
||||
|
|
@ -300,6 +329,56 @@
|
|||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Objects factory options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Objects Factory APIs.
|
||||
* @details If enabled then the objects factory APIs are included in the
|
||||
* kernel.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_CFG_USE_FACTORY TRUE
|
||||
|
||||
/**
|
||||
* @brief Maximum length for object names.
|
||||
* @details If the specified length is zero then the name is stored by
|
||||
* pointer but this could have unintended side effects.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
|
||||
|
||||
/**
|
||||
* @brief Enables the registry of generic objects.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for generic buffers.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for semaphores.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_SEMAPHORES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for mailboxes.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_MAILBOXES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for objects FIFOs.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Debug options
|
||||
|
|
@ -312,7 +391,7 @@
|
|||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_STATISTICS TRUE
|
||||
#define CH_DBG_STATISTICS FALSE
|
||||
|
||||
/**
|
||||
* @brief Debug option, system state check.
|
||||
|
|
@ -321,7 +400,7 @@
|
|||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_SYSTEM_STATE_CHECK TRUE
|
||||
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
|
||||
|
||||
/**
|
||||
* @brief Debug option, parameters checks.
|
||||
|
|
@ -330,7 +409,7 @@
|
|||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_ENABLE_CHECKS TRUE
|
||||
#define CH_DBG_ENABLE_CHECKS FALSE
|
||||
|
||||
/**
|
||||
* @brief Debug option, consistency checks.
|
||||
|
|
@ -340,16 +419,22 @@
|
|||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_ENABLE_ASSERTS TRUE
|
||||
#define CH_DBG_ENABLE_ASSERTS FALSE
|
||||
|
||||
/**
|
||||
* @brief Debug option, trace buffer.
|
||||
* @details If enabled then the context switch circular trace buffer is
|
||||
* activated.
|
||||
* @details If enabled then the trace buffer is activated.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
|
||||
*/
|
||||
#define CH_DBG_ENABLE_TRACE TRUE
|
||||
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
|
||||
|
||||
/**
|
||||
* @brief Trace buffer entries.
|
||||
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
|
||||
* different from @p CH_DBG_TRACE_MASK_DISABLED.
|
||||
*/
|
||||
#define CH_DBG_TRACE_BUFFER_SIZE 128
|
||||
|
||||
/**
|
||||
* @brief Debug option, stack checks.
|
||||
|
|
@ -361,7 +446,7 @@
|
|||
* @note The default failure mode is to halt the system with the global
|
||||
* @p panic_msg variable set to @p NULL.
|
||||
*/
|
||||
#define CH_DBG_ENABLE_STACK_CHECK TRUE
|
||||
#define CH_DBG_ENABLE_STACK_CHECK FALSE
|
||||
|
||||
/**
|
||||
* @brief Debug option, stacks initialization.
|
||||
|
|
@ -371,7 +456,7 @@
|
|||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_FILL_THREADS TRUE
|
||||
#define CH_DBG_FILL_THREADS FALSE
|
||||
|
||||
/**
|
||||
* @brief Debug option, threads profiling.
|
||||
|
|
@ -382,7 +467,7 @@
|
|||
* @note This debug option is not currently compatible with the
|
||||
* tickless mode.
|
||||
*/
|
||||
#define CH_DBG_THREADS_PROFILING TRUE
|
||||
#define CH_DBG_THREADS_PROFILING FALSE
|
||||
|
||||
/** @} */
|
||||
|
||||
|
|
@ -393,6 +478,22 @@
|
|||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System structure extension.
|
||||
* @details User fields added to the end of the @p ch_system_t structure.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_EXTRA_FIELDS \
|
||||
/* Add threads custom fields here.*/
|
||||
|
||||
/**
|
||||
* @brief System initialization hook.
|
||||
* @details User initialization code added to the @p chSysInit() function
|
||||
* just before interrupts are enabled globally.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_INIT_HOOK(tp) { \
|
||||
/* Add threads initialization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Threads descriptor structure extension.
|
||||
* @details User fields added to the end of the @p thread_t structure.
|
||||
|
|
@ -402,9 +503,9 @@
|
|||
|
||||
/**
|
||||
* @brief Threads initialization hook.
|
||||
* @details User initialization code added to the @p chThdInit() API.
|
||||
* @details User initialization code added to the @p _thread_init() function.
|
||||
*
|
||||
* @note It is invoked from within @p chThdInit() and implicitly from all
|
||||
* @note It is invoked from within @p _thread_init() and implicitly from all
|
||||
* the threads creation APIs.
|
||||
*/
|
||||
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
|
||||
|
|
@ -414,10 +515,6 @@
|
|||
/**
|
||||
* @brief Threads finalization hook.
|
||||
* @details User finalization code added to the @p chThdExit() API.
|
||||
*
|
||||
* @note It is inserted into lock zone.
|
||||
* @note It is also invoked when the threads simply return in order to
|
||||
* terminate.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
|
||||
/* Add threads finalization code here.*/ \
|
||||
|
|
@ -428,7 +525,7 @@
|
|||
* @details This hook is invoked just before switching between threads.
|
||||
*/
|
||||
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
|
||||
/* System halt code here.*/ \
|
||||
/* Context switch code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -452,6 +549,7 @@
|
|||
* @note This macro can be used to activate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_ENTER_HOOK() { \
|
||||
/* Idle-enter code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -461,6 +559,7 @@
|
|||
* @note This macro can be used to deactivate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_LEAVE_HOOK() { \
|
||||
/* Idle-leave code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -504,6 +603,6 @@
|
|||
/* Port-specific settings (override port settings defaulted in chcore.h). */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _CHCONF_H_ */
|
||||
#endif /* CHCONF_H */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -14,8 +14,19 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _HALCONF_H_
|
||||
#define _HALCONF_H_
|
||||
/**
|
||||
* @file templates/halconf.h
|
||||
* @brief HAL configuration header.
|
||||
* @details HAL configuration file, this file allows to enable or disable the
|
||||
* various device drivers from your application. You may also use
|
||||
* this file in order to override the device drivers default settings.
|
||||
*
|
||||
* @addtogroup HAL_CONF
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef HALCONF_H
|
||||
#define HALCONF_H
|
||||
|
||||
#include "mcuconf.h"
|
||||
|
||||
|
|
@ -40,6 +51,20 @@
|
|||
#define HAL_USE_CAN FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the cryptographic subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CRY FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the DAC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_DAC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the EXT subsystem.
|
||||
*/
|
||||
|
|
@ -61,6 +86,13 @@
|
|||
#define HAL_USE_I2C FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the I2S subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_I2S FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ICU subsystem.
|
||||
*/
|
||||
|
|
@ -89,6 +121,13 @@
|
|||
#define HAL_USE_PWM FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the QSPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_QSPI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the RTC subsystem.
|
||||
*/
|
||||
|
|
@ -138,6 +177,13 @@
|
|||
#define HAL_USE_USB FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the WDG subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_WDG FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* ADC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -169,6 +215,28 @@
|
|||
#define CAN_USE_SLEEP_MODE TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* CRY driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the SW fall-back of the cryptographic driver.
|
||||
* @details When enabled, this option, activates a fall-back software
|
||||
* implementation for algorithms not supported by the underlying
|
||||
* hardware.
|
||||
* @note Fall-back implementations may not be present for all algorithms.
|
||||
*/
|
||||
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_USE_FALLBACK FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Makes the driver forcibly use the fall-back implementations.
|
||||
*/
|
||||
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_ENFORCE_FALLBACK FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I2C driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -262,11 +330,34 @@
|
|||
* @brief Serial buffers size.
|
||||
* @details Configuration parameter, you can change the depth of the queue
|
||||
* buffers depending on the requirements of your application.
|
||||
* @note The default is 64 bytes for both the transmission and receive
|
||||
* @note The default is 16 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_BUFFERS_SIZE 64
|
||||
#define SERIAL_BUFFERS_SIZE 16
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SERIAL_USB driver related setting. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Serial over USB buffers size.
|
||||
* @details Configuration parameter, the buffer size must be a multiple of
|
||||
* the USB data endpoint maximum packet size.
|
||||
* @note The default is 256 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_SIZE 256
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Serial over USB number of buffers.
|
||||
* @note The default is 2 buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_NUMBER 2
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -289,6 +380,38 @@
|
|||
#define SPI_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
#endif /* _HALCONF_H_ */
|
||||
/*===========================================================================*/
|
||||
/* UART driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define UART_USE_WAIT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define UART_USE_MUTUAL_EXCLUSION FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* USB driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define USB_USE_WAIT FALSE
|
||||
#endif
|
||||
|
||||
#endif /* HALCONF_H */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,323 @@
|
|||
/**
|
||||
* @file
|
||||
* HTTP server options list
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the lwIP TCP/IP stack.
|
||||
*
|
||||
* Author: Adam Dunkels <adam@sics.se>
|
||||
*
|
||||
* This version of the file has been modified by Texas Instruments to offer
|
||||
* simple server-side-include (SSI) and Common Gateway Interface (CGI)
|
||||
* capability.
|
||||
*/
|
||||
|
||||
#ifndef LWIP_HDR_APPS_HTTPD_OPTS_H
|
||||
#define LWIP_HDR_APPS_HTTPD_OPTS_H
|
||||
|
||||
#include "lwip/opt.h"
|
||||
|
||||
/**
|
||||
* @defgroup httpd_opts Options
|
||||
* @ingroup httpd
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Set this to 1 to support CGI (old style) */
|
||||
#if !defined LWIP_HTTPD_CGI || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_CGI 0
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to support CGI (new style) */
|
||||
#if !defined LWIP_HTTPD_CGI_SSI || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_CGI_SSI 0
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to support SSI (Server-Side-Includes) */
|
||||
#if !defined LWIP_HTTPD_SSI || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_SSI 0
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to implement an SSI tag handler callback that gets a const char*
|
||||
* to the tag (instead of an index into a pre-registered array of known tags) */
|
||||
#if !defined LWIP_HTTPD_SSI_RAW || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_SSI_RAW 0
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to support HTTP POST */
|
||||
#if !defined LWIP_HTTPD_SUPPORT_POST || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_SUPPORT_POST 0
|
||||
#endif
|
||||
|
||||
/* The maximum number of parameters that the CGI handler can be sent. */
|
||||
#if !defined LWIP_HTTPD_MAX_CGI_PARAMETERS || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_MAX_CGI_PARAMETERS 16
|
||||
#endif
|
||||
|
||||
/** LWIP_HTTPD_SSI_MULTIPART==1: SSI handler function is called with 2 more
|
||||
* arguments indicating a counter for insert string that are too long to be
|
||||
* inserted at once: the SSI handler function must then set 'next_tag_part'
|
||||
* which will be passed back to it in the next call. */
|
||||
#if !defined LWIP_HTTPD_SSI_MULTIPART || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_SSI_MULTIPART 0
|
||||
#endif
|
||||
|
||||
/* The maximum length of the string comprising the tag name */
|
||||
#if !defined LWIP_HTTPD_MAX_TAG_NAME_LEN || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_MAX_TAG_NAME_LEN 8
|
||||
#endif
|
||||
|
||||
/* The maximum length of string that can be returned to replace any given tag */
|
||||
#if !defined LWIP_HTTPD_MAX_TAG_INSERT_LEN || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_MAX_TAG_INSERT_LEN 192
|
||||
#endif
|
||||
|
||||
#if !defined LWIP_HTTPD_POST_MANUAL_WND || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_POST_MANUAL_WND 0
|
||||
#endif
|
||||
|
||||
/** This string is passed in the HTTP header as "Server: " */
|
||||
#if !defined HTTPD_SERVER_AGENT || defined __DOXYGEN__
|
||||
#define HTTPD_SERVER_AGENT "lwIP/" LWIP_VERSION_STRING " (http://savannah.nongnu.org/projects/lwip)"
|
||||
#endif
|
||||
|
||||
/** Set this to 1 if you want to include code that creates HTTP headers
|
||||
* at runtime. Default is off: HTTP headers are then created statically
|
||||
* by the makefsdata tool. Static headers mean smaller code size, but
|
||||
* the (readonly) fsdata will grow a bit as every file includes the HTTP
|
||||
* header. */
|
||||
#if !defined LWIP_HTTPD_DYNAMIC_HEADERS || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_DYNAMIC_HEADERS 0
|
||||
#endif
|
||||
|
||||
#if !defined HTTPD_DEBUG || defined __DOXYGEN__
|
||||
#define HTTPD_DEBUG LWIP_DBG_OFF
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to use a memp pool for allocating
|
||||
* struct http_state instead of the heap.
|
||||
*/
|
||||
#if !defined HTTPD_USE_MEM_POOL || defined __DOXYGEN__
|
||||
#define HTTPD_USE_MEM_POOL 0
|
||||
#endif
|
||||
|
||||
/** The server port for HTTPD to use */
|
||||
#if !defined HTTPD_SERVER_PORT || defined __DOXYGEN__
|
||||
#define HTTPD_SERVER_PORT 80
|
||||
#endif
|
||||
|
||||
/** Maximum retries before the connection is aborted/closed.
|
||||
* - number of times pcb->poll is called -> default is 4*500ms = 2s;
|
||||
* - reset when pcb->sent is called
|
||||
*/
|
||||
#if !defined HTTPD_MAX_RETRIES || defined __DOXYGEN__
|
||||
#define HTTPD_MAX_RETRIES 4
|
||||
#endif
|
||||
|
||||
/** The poll delay is X*500ms */
|
||||
#if !defined HTTPD_POLL_INTERVAL || defined __DOXYGEN__
|
||||
#define HTTPD_POLL_INTERVAL 4
|
||||
#endif
|
||||
|
||||
/** Priority for tcp pcbs created by HTTPD (very low by default).
|
||||
* Lower priorities get killed first when running out of memory.
|
||||
*/
|
||||
#if !defined HTTPD_TCP_PRIO || defined __DOXYGEN__
|
||||
#define HTTPD_TCP_PRIO TCP_PRIO_MIN
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to enable timing each file sent */
|
||||
#if !defined LWIP_HTTPD_TIMING || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_TIMING 0
|
||||
#endif
|
||||
/** Set this to 1 to enable timing each file sent */
|
||||
#if !defined HTTPD_DEBUG_TIMING || defined __DOXYGEN__
|
||||
#define HTTPD_DEBUG_TIMING LWIP_DBG_OFF
|
||||
#endif
|
||||
|
||||
/** Set this to one to show error pages when parsing a request fails instead
|
||||
of simply closing the connection. */
|
||||
#if !defined LWIP_HTTPD_SUPPORT_EXTSTATUS || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_SUPPORT_EXTSTATUS 0
|
||||
#endif
|
||||
|
||||
/** Set this to 0 to drop support for HTTP/0.9 clients (to save some bytes) */
|
||||
#if !defined LWIP_HTTPD_SUPPORT_V09 || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_SUPPORT_V09 1
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to enable HTTP/1.1 persistent connections.
|
||||
* ATTENTION: If the generated file system includes HTTP headers, these must
|
||||
* include the "Connection: keep-alive" header (pass argument "-11" to makefsdata).
|
||||
*/
|
||||
#if !defined LWIP_HTTPD_SUPPORT_11_KEEPALIVE || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_SUPPORT_11_KEEPALIVE 0
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to support HTTP request coming in in multiple packets/pbufs */
|
||||
#if !defined LWIP_HTTPD_SUPPORT_REQUESTLIST || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_SUPPORT_REQUESTLIST 1
|
||||
#endif
|
||||
|
||||
#if LWIP_HTTPD_SUPPORT_REQUESTLIST
|
||||
/** Number of rx pbufs to enqueue to parse an incoming request (up to the first
|
||||
newline) */
|
||||
#if !defined LWIP_HTTPD_REQ_QUEUELEN || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_REQ_QUEUELEN 5
|
||||
#endif
|
||||
|
||||
/** Number of (TCP payload-) bytes (in pbufs) to enqueue to parse and incoming
|
||||
request (up to the first double-newline) */
|
||||
#if !defined LWIP_HTTPD_REQ_BUFSIZE || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_REQ_BUFSIZE LWIP_HTTPD_MAX_REQ_LENGTH
|
||||
#endif
|
||||
|
||||
/** Defines the maximum length of a HTTP request line (up to the first CRLF,
|
||||
copied from pbuf into this a global buffer when pbuf- or packet-queues
|
||||
are received - otherwise the input pbuf is used directly) */
|
||||
#if !defined LWIP_HTTPD_MAX_REQ_LENGTH || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_MAX_REQ_LENGTH LWIP_MIN(1023, (LWIP_HTTPD_REQ_QUEUELEN * PBUF_POOL_BUFSIZE))
|
||||
#endif
|
||||
#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
|
||||
|
||||
/** This is the size of a static buffer used when URIs end with '/'.
|
||||
* In this buffer, the directory requested is concatenated with all the
|
||||
* configured default file names.
|
||||
* Set to 0 to disable checking default filenames on non-root directories.
|
||||
*/
|
||||
#if !defined LWIP_HTTPD_MAX_REQUEST_URI_LEN || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_MAX_REQUEST_URI_LEN 63
|
||||
#endif
|
||||
|
||||
/** Maximum length of the filename to send as response to a POST request,
|
||||
* filled in by the application when a POST is finished.
|
||||
*/
|
||||
#if !defined LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN 63
|
||||
#endif
|
||||
|
||||
/** Set this to 0 to not send the SSI tag (default is on, so the tag will
|
||||
* be sent in the HTML page */
|
||||
#if !defined LWIP_HTTPD_SSI_INCLUDE_TAG || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_SSI_INCLUDE_TAG 1
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to call tcp_abort when tcp_close fails with memory error.
|
||||
* This can be used to prevent consuming all memory in situations where the
|
||||
* HTTP server has low priority compared to other communication. */
|
||||
#if !defined LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR 0
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to kill the oldest connection when running out of
|
||||
* memory for 'struct http_state' or 'struct http_ssi_state'.
|
||||
* ATTENTION: This puts all connections on a linked list, so may be kind of slow.
|
||||
*/
|
||||
#if !defined LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED 0
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to send URIs without extension without headers
|
||||
* (who uses this at all??) */
|
||||
#if !defined LWIP_HTTPD_OMIT_HEADER_FOR_EXTENSIONLESS_URI || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_OMIT_HEADER_FOR_EXTENSIONLESS_URI 0
|
||||
#endif
|
||||
|
||||
/** Default: Tags are sent from struct http_state and are therefore volatile */
|
||||
#if !defined HTTP_IS_TAG_VOLATILE || defined __DOXYGEN__
|
||||
#define HTTP_IS_TAG_VOLATILE(ptr) TCP_WRITE_FLAG_COPY
|
||||
#endif
|
||||
|
||||
/* By default, the httpd is limited to send 2*pcb->mss to keep resource usage low
|
||||
when http is not an important protocol in the device. */
|
||||
#if !defined HTTPD_LIMIT_SENDING_TO_2MSS || defined __DOXYGEN__
|
||||
#define HTTPD_LIMIT_SENDING_TO_2MSS 1
|
||||
#endif
|
||||
|
||||
/* Define this to a function that returns the maximum amount of data to enqueue.
|
||||
The function have this signature: u16_t fn(struct tcp_pcb* pcb); */
|
||||
#if !defined HTTPD_MAX_WRITE_LEN || defined __DOXYGEN__
|
||||
#if HTTPD_LIMIT_SENDING_TO_2MSS
|
||||
#define HTTPD_MAX_WRITE_LEN(pcb) (2 * tcp_mss(pcb))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*------------------- FS OPTIONS -------------------*/
|
||||
|
||||
/** Set this to 1 and provide the functions:
|
||||
* - "int fs_open_custom(struct fs_file *file, const char *name)"
|
||||
* Called first for every opened file to allow opening files
|
||||
* that are not included in fsdata(_custom).c
|
||||
* - "void fs_close_custom(struct fs_file *file)"
|
||||
* Called to free resources allocated by fs_open_custom().
|
||||
*/
|
||||
#if !defined LWIP_HTTPD_CUSTOM_FILES || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_CUSTOM_FILES 0
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to support fs_read() to dynamically read file data.
|
||||
* Without this (default=off), only one-block files are supported,
|
||||
* and the contents must be ready after fs_open().
|
||||
*/
|
||||
#if !defined LWIP_HTTPD_DYNAMIC_FILE_READ || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_DYNAMIC_FILE_READ 0
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to include an application state argument per file
|
||||
* that is opened. This allows to keep a state per connection/file.
|
||||
*/
|
||||
#if !defined LWIP_HTTPD_FILE_STATE || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_FILE_STATE 0
|
||||
#endif
|
||||
|
||||
/** HTTPD_PRECALCULATED_CHECKSUM==1: include precompiled checksums for
|
||||
* predefined (MSS-sized) chunks of the files to prevent having to calculate
|
||||
* the checksums at runtime. */
|
||||
#if !defined HTTPD_PRECALCULATED_CHECKSUM || defined __DOXYGEN__
|
||||
#define HTTPD_PRECALCULATED_CHECKSUM 0
|
||||
#endif
|
||||
|
||||
/** LWIP_HTTPD_FS_ASYNC_READ==1: support asynchronous read operations
|
||||
* (fs_read_async returns FS_READ_DELAYED and calls a callback when finished).
|
||||
*/
|
||||
#if !defined LWIP_HTTPD_FS_ASYNC_READ || defined __DOXYGEN__
|
||||
#define LWIP_HTTPD_FS_ASYNC_READ 0
|
||||
#endif
|
||||
|
||||
/** Set this to 1 to include "fsdata_custom.c" instead of "fsdata.c" for the
|
||||
* file system (to prevent changing the file included in CVS) */
|
||||
#if !defined HTTPD_USE_CUSTOM_FSDATA || defined __DOXYGEN__
|
||||
#define HTTPD_USE_CUSTOM_FSDATA 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LWIP_HDR_APPS_HTTPD_OPTS_H */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
Copyright (C) 2014..2016 Marco Veeneman
|
||||
Copyright (C) 2014..2017 Marco Veeneman
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -17,7 +17,7 @@
|
|||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
#include "lwipthread.h"
|
||||
#include "web/web.h"
|
||||
#include "lwip/apps/httpd.h"
|
||||
|
||||
/*
|
||||
* Application entry point.
|
||||
|
|
@ -43,10 +43,9 @@ int main(void)
|
|||
sdStart(&SD1, NULL);
|
||||
|
||||
/*
|
||||
* Creates the HTTP thread (it changes priority internally).
|
||||
* Creates the LwIP HTTP server.
|
||||
*/
|
||||
chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1,
|
||||
http_server, NULL);
|
||||
httpd_init();
|
||||
|
||||
while (1) {
|
||||
osalThreadSleepMilliseconds(500);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
Copyright (C) 2014..2016 Marco Veeneman
|
||||
Copyright (C) 2014..2017 Marco Veeneman
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -31,7 +31,7 @@
|
|||
* HAL driver system settings.
|
||||
*/
|
||||
#define TIVA_MOSC_SINGLE_ENDED FALSE
|
||||
#define TIVA_RSCLKCFG_OSCSRC RSCLKCFG_OSCSRC_MOSC
|
||||
#define TIVA_RSCLKCFG_OSCSRC SYSCTL_RSCLKCFG_OSCSRC_MOSC
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
|
|
@ -53,6 +53,42 @@
|
|||
#define TIVA_GPT_GPT6A_IRQ_PRIORITY 7
|
||||
#define TIVA_GPT_GPT7A_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* PAL driver system settings.
|
||||
*/
|
||||
#define TIVA_PAL_GPIOA_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOB_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOC_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOD_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOE_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOF_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOG_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOH_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOJ_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOK_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOL_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOM_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPION_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP0_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP1_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP2_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP3_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP4_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP5_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP6_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP7_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ0_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ1_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ2_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ3_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ4_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ5_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ6_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ7_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOR_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOS_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOT_IRQ_PRIORITY 3
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,120 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is a modified version of the lwIP web server demo. The original
|
||||
* author is unknown because the file didn't contain any license information.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file web.c
|
||||
* @brief HTTP server wrapper thread code.
|
||||
* @addtogroup WEB_THREAD
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
|
||||
#include "lwip/opt.h"
|
||||
#include "lwip/arch.h"
|
||||
#include "lwip/api.h"
|
||||
|
||||
#include "web.h"
|
||||
|
||||
#if LWIP_NETCONN
|
||||
|
||||
static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n";
|
||||
static const char http_index_html[] = "<html><head><title>Congrats!</title></head><body><h1>Welcome to our lwIP HTTP server!</h1><p>This is a small test page.</body></html>";
|
||||
|
||||
static void http_server_serve(struct netconn *conn) {
|
||||
struct netbuf *inbuf;
|
||||
char *buf;
|
||||
u16_t buflen;
|
||||
err_t err;
|
||||
|
||||
/* Read the data from the port, blocking if nothing yet there.
|
||||
We assume the request (the part we care about) is in one netbuf */
|
||||
err = netconn_recv(conn, &inbuf);
|
||||
|
||||
if (err == ERR_OK) {
|
||||
netbuf_data(inbuf, (void **)&buf, &buflen);
|
||||
|
||||
/* Is this an HTTP GET command? (only check the first 5 chars, since
|
||||
there are other formats for GET, and we're keeping it very simple )*/
|
||||
if (buflen>=5 &&
|
||||
buf[0]=='G' &&
|
||||
buf[1]=='E' &&
|
||||
buf[2]=='T' &&
|
||||
buf[3]==' ' &&
|
||||
buf[4]=='/' ) {
|
||||
|
||||
/* Send the HTML header
|
||||
* subtract 1 from the size, since we dont send the \0 in the string
|
||||
* NETCONN_NOCOPY: our data is const static, so no need to copy it
|
||||
*/
|
||||
netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY);
|
||||
|
||||
/* Send our HTML page */
|
||||
netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY);
|
||||
}
|
||||
}
|
||||
/* Close the connection (server closes in HTTP) */
|
||||
netconn_close(conn);
|
||||
|
||||
/* Delete the buffer (netconn_recv gives us ownership,
|
||||
so we have to make sure to deallocate the buffer) */
|
||||
netbuf_delete(inbuf);
|
||||
}
|
||||
|
||||
/**
|
||||
* Stack area for the http thread.
|
||||
*/
|
||||
THD_WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
|
||||
|
||||
/**
|
||||
* HTTP server thread.
|
||||
*/
|
||||
THD_FUNCTION(http_server, p) {
|
||||
struct netconn *conn, *newconn;
|
||||
err_t err;
|
||||
|
||||
(void)p;
|
||||
|
||||
/* Create a new TCP connection handle */
|
||||
conn = netconn_new(NETCONN_TCP);
|
||||
LWIP_ERROR("http_server: invalid conn", (conn != NULL), return;);
|
||||
|
||||
/* Bind to port 80 (HTTP) with default IP address */
|
||||
netconn_bind(conn, NULL, WEB_THREAD_PORT);
|
||||
|
||||
/* Put the connection into LISTEN state */
|
||||
netconn_listen(conn);
|
||||
|
||||
/* Goes to the final priority after initialization.*/
|
||||
chThdSetPriority(WEB_THREAD_PRIORITY);
|
||||
|
||||
while(1) {
|
||||
err = netconn_accept(conn, &newconn);
|
||||
if (err != ERR_OK)
|
||||
continue;
|
||||
http_server_serve(newconn);
|
||||
netconn_delete(newconn);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* LWIP_NETCONN */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file web.h
|
||||
* @brief HTTP server wrapper thread macros and structures.
|
||||
* @addtogroup WEB_THREAD
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _WEB_H_
|
||||
#define _WEB_H_
|
||||
|
||||
#ifndef WEB_THREAD_STACK_SIZE
|
||||
#define WEB_THREAD_STACK_SIZE 1024
|
||||
#endif
|
||||
|
||||
#ifndef WEB_THREAD_PORT
|
||||
#define WEB_THREAD_PORT 80
|
||||
#endif
|
||||
|
||||
#ifndef WEB_THREAD_PRIORITY
|
||||
#define WEB_THREAD_PRIORITY (LOWPRIO + 2)
|
||||
#endif
|
||||
|
||||
extern THD_WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
THD_FUNCTION(http_server, p);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _WEB_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -21,12 +21,159 @@
|
|||
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|
||||
<tool id="org.eclipse.cdt.build.core.settings.holder.libs.2143276802" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
|
||||
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|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/osal/rt"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ext/TivaWare"/>
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||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/common/oslib/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/various"/>
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||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/>
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||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/hal/osal/rt"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/hal/include"/>
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||||
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||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/ext/CMSIS/include"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/include"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/TM4C129x"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/rt/include"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/GPTM"/>
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||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/demos/TIVA/RT-TM4C1294-LAUNCHPAD"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/uDMA"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/rt/ports/ARMCMx"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/test/rt"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/include"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/test/lib"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C129x"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/WDT"/>
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||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/test/rt"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/GPIO"/>
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||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/common/ext/CMSIS/include"/>
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||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/>
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||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/common/ports/ARMCMx/compilers/GCC"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/MAC"/>
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||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/I2C"/>
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<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/test/rt/source/test"/>
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||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD"/>
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||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/SSI"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/boards/TI_TM4C1294_LAUNCHPAD"/>
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||||
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||||
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||||
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|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/various"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/hal/osal/rt"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/hal/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/license"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/startup/ARMCMx/devices/TM4C129x"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/ext/CMSIS/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/UART"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/ports/common/ARMCMx"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/TM4C129x"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/rt/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/GPTM"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/demos/TIVA/RT-TM4C1294-LAUNCHPAD"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/various"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/uDMA"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/common/ports/ARMCMx"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/hal/ports/common/ARMCMx"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/rt/ports/ARMCMx"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/test/rt"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/test/lib"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C129x"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/WDT"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/test/rt"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/GPIO"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/common/ext/CMSIS/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/common/ports/ARMCMx/compilers/GCC"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/MAC"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/I2C"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/test/rt/source/test"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/common/startup/ARMCMx/compilers/GCC"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/PWM"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/rt/ports/ARMCMx/compilers/GCC"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/SSI"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/boards/TI_TM4C1294_LAUNCHPAD"/>
|
||||
</option>
|
||||
<option id="org.eclipse.cdt.build.core.settings.holder.undef.symbols.625344253" name="Undefined Symbols" superClass="org.eclipse.cdt.build.core.settings.holder.undef.symbols" valueType="undefDefinedSymbols">
|
||||
<listOptionValue builtIn="false" value="THUMB_PRESENT"/>
|
||||
<listOptionValue builtIn="false" value="CORTEX_USE_FPU"/>
|
||||
<listOptionValue builtIn="false" value="THUMB_NO_INTERWORKING"/>
|
||||
</option>
|
||||
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.338985256" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
|
||||
</tool>
|
||||
<tool id="org.eclipse.cdt.build.core.settings.holder.1165165914" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
|
||||
<option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.289466379" name="Undefined Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath">
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/osal/rt"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ext/TivaWare"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/common/oslib/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/various"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/hal/osal/rt"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/hal/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/license"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/startup/ARMCMx/devices/TM4C129x"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/ext/CMSIS/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/UART"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/ports/common/ARMCMx"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/TM4C129x"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/rt/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/GPTM"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/demos/TIVA/RT-TM4C1294-LAUNCHPAD"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/various"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/uDMA"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/common/ports/ARMCMx"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/hal/ports/common/ARMCMx"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/rt/ports/ARMCMx"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/test/rt"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/test/lib"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C129x"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/WDT"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/test/rt"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/GPIO"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/common/ext/CMSIS/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/common/ports/ARMCMx/compilers/GCC"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/MAC"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/I2C"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/test/rt/source/test"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/common/startup/ARMCMx/compilers/GCC"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/PWM"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/chibios30/os/rt/ports/ARMCMx/compilers/GCC"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD/SSI"/>
|
||||
<listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/boards/TI_TM4C1294_LAUNCHPAD"/>
|
||||
</option>
|
||||
<option id="org.eclipse.cdt.build.core.settings.holder.undef.symbols.324974813" name="Undefined Symbols" superClass="org.eclipse.cdt.build.core.settings.holder.undef.symbols" valueType="undefDefinedSymbols">
|
||||
<listOptionValue builtIn="false" value="THUMB_PRESENT"/>
|
||||
<listOptionValue builtIn="false" value="CORTEX_USE_FPU"/>
|
||||
<listOptionValue builtIn="false" value="THUMB_NO_INTERWORKING"/>
|
||||
</option>
|
||||
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
|
|
|
|||
|
|
@ -27,22 +27,22 @@
|
|||
<link>
|
||||
<name>board</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS3/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD</locationURI>
|
||||
<locationURI>PARENT-1-CHIBIOS/ChibiOS-Contrib/os/hal/boards/TI_TM4C1294_LAUNCHPAD</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>community_os</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS3/community/os</locationURI>
|
||||
<locationURI>PARENT-1-CHIBIOS/ChibiOS-Contrib/os</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>os</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS3/os</locationURI>
|
||||
<locationURI>CHIBIOS/os</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>test</name>
|
||||
<type>2</type>
|
||||
<locationURI>CHIBIOS3/test</locationURI>
|
||||
<locationURI>CHIBIOS/test</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
<variableList>
|
||||
|
|
|
|||
|
|
@ -43,6 +43,12 @@ ifeq ($(USE_VERBOSE_COMPILE),)
|
|||
USE_VERBOSE_COMPILE = no
|
||||
endif
|
||||
|
||||
# If enabled, this option makes the build process faster by not compiling
|
||||
# modules not used in the current configuration.
|
||||
ifeq ($(USE_SMART_BUILD),)
|
||||
USE_SMART_BUILD = yes
|
||||
endif
|
||||
|
||||
#
|
||||
# Build global options
|
||||
##############################################################################
|
||||
|
|
@ -65,7 +71,7 @@ endif
|
|||
|
||||
# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
|
||||
ifeq ($(USE_FPU),)
|
||||
USE_FPU = hard
|
||||
USE_FPU = no
|
||||
endif
|
||||
|
||||
#
|
||||
|
|
@ -82,6 +88,9 @@ PROJECT = ch
|
|||
# Imported source files and paths
|
||||
CHIBIOS = ../../../../ChibiOS-RT
|
||||
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
|
||||
|
||||
# Licensing files.
|
||||
include $(CHIBIOS)/os/license/license.mk
|
||||
# Startup files.
|
||||
include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
|
||||
# HAL-OSAL files (optional).
|
||||
|
|
@ -93,26 +102,22 @@ include $(CHIBIOS)/os/hal/osal/rt/osal.mk
|
|||
include $(CHIBIOS)/os/rt/rt.mk
|
||||
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
|
||||
# Other files (optional).
|
||||
include $(CHIBIOS)/test/rt/test.mk
|
||||
include $(CHIBIOS)/test/lib/test.mk
|
||||
include $(CHIBIOS)/test/rt/rt_test.mk
|
||||
include $(CHIBIOS)/test/oslib/oslib_test.mk
|
||||
|
||||
# Define linker script file here
|
||||
LDSCRIPT= $(STARTUPLD)/TM4C129xNC.ld
|
||||
|
||||
# C sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CSRC = $(STARTUPSRC) \
|
||||
$(KERNSRC) \
|
||||
$(PORTSRC) \
|
||||
$(OSALSRC) \
|
||||
$(HALSRC) \
|
||||
$(PLATFORMSRC) \
|
||||
$(BOARDSRC) \
|
||||
CSRC = $(ALLCSRC) \
|
||||
$(TESTSRC) \
|
||||
main.c
|
||||
|
||||
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CPPSRC =
|
||||
CPPSRC = $(ALLCPPSRC)
|
||||
|
||||
# C sources to be compiled in ARM mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
|
|
@ -135,13 +140,10 @@ TCSRC =
|
|||
TCPPSRC =
|
||||
|
||||
# List ASM source files here
|
||||
ASMSRC =
|
||||
ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
|
||||
ASMSRC = $(ALLASMSRC)
|
||||
ASMXSRC = $(ALLXASMSRC)
|
||||
|
||||
INCDIR = $(CHIBIOS)/os/license \
|
||||
$(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
|
||||
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
|
||||
$(CHIBIOS)/os/various
|
||||
INCDIR = $(ALLINC) $(TESTINC)
|
||||
|
||||
#
|
||||
# Project, sources and paths
|
||||
|
|
@ -153,6 +155,7 @@ INCDIR = $(CHIBIOS)/os/license \
|
|||
|
||||
MCU = cortex-m4
|
||||
|
||||
#TRGT = arm-elf-
|
||||
TRGT = arm-none-eabi-
|
||||
CC = $(TRGT)gcc
|
||||
CPPC = $(TRGT)g++
|
||||
|
|
@ -176,10 +179,10 @@ AOPT =
|
|||
TOPT = -mthumb -DTHUMB
|
||||
|
||||
# Define C warning options here
|
||||
CWARN = -Wall -Wextra -Wstrict-prototypes
|
||||
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
|
||||
|
||||
# Define C++ warning options here
|
||||
CPPWARN = -Wall -Wextra
|
||||
CPPWARN = -Wall -Wextra -Wundef
|
||||
|
||||
#
|
||||
# Compiler settings
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -14,10 +14,22 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _CHCONF_H_
|
||||
#define _CHCONF_H_
|
||||
/**
|
||||
* @file templates/chconf.h
|
||||
* @brief Configuration file template.
|
||||
* @details A copy of this file must be placed in each project directory, it
|
||||
* contains the application specific kernel settings.
|
||||
*
|
||||
* @addtogroup config
|
||||
* @details Kernel related settings and hooks.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef CHCONF_H
|
||||
#define CHCONF_H
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
|
|
@ -39,6 +51,18 @@
|
|||
*/
|
||||
#define CH_CFG_ST_FREQUENCY 10000
|
||||
|
||||
/**
|
||||
* @brief Time intervals data size.
|
||||
* @note Allowed values are 16, 32 or 64 bits.
|
||||
*/
|
||||
#define CH_CFG_INTERVALS_SIZE 32
|
||||
|
||||
/**
|
||||
* @brief Time types data size.
|
||||
* @note Allowed values are 16 or 32 bits.
|
||||
*/
|
||||
#define CH_CFG_TIME_TYPES_SIZE 32
|
||||
|
||||
/**
|
||||
* @brief Time delta constant for the tick-less mode.
|
||||
* @note If this value is zero then the system uses the classic
|
||||
|
|
@ -49,13 +73,6 @@
|
|||
*/
|
||||
#define CH_CFG_ST_TIMEDELTA 0
|
||||
|
||||
/**
|
||||
* @brief Realtime Counter frequency.
|
||||
* @details Frequency of the system counter used for realtime delays and
|
||||
* measurements.
|
||||
*/
|
||||
#define CH_CFG_RTC_FREQUENCY 120000000
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -97,7 +114,8 @@
|
|||
* @details When this option is activated the function @p chSysInit()
|
||||
* does not spawn the idle thread. The application @p main()
|
||||
* function becomes the idle thread and must implement an
|
||||
* infinite loop. */
|
||||
* infinite loop.
|
||||
*/
|
||||
#define CH_CFG_NO_IDLE_THREAD FALSE
|
||||
|
||||
/** @} */
|
||||
|
|
@ -181,6 +199,16 @@
|
|||
*/
|
||||
#define CH_CFG_USE_MUTEXES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables recursive behavior on mutexes.
|
||||
* @note Recursive mutexes are heavier and have an increased
|
||||
* memory footprint.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||
*/
|
||||
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
|
||||
|
||||
/**
|
||||
* @brief Conditional Variables APIs.
|
||||
* @details If enabled then the conditional variables APIs are included
|
||||
|
|
@ -249,14 +277,6 @@
|
|||
*/
|
||||
#define CH_CFG_USE_MAILBOXES TRUE
|
||||
|
||||
/**
|
||||
* @brief I/O Queues APIs.
|
||||
* @details If enabled then the I/O queues APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_QUEUES TRUE
|
||||
|
||||
/**
|
||||
* @brief Core Memory Manager APIs.
|
||||
* @details If enabled then the core memory manager APIs are included
|
||||
|
|
@ -287,6 +307,15 @@
|
|||
*/
|
||||
#define CH_CFG_USE_MEMPOOLS TRUE
|
||||
|
||||
/**
|
||||
* @brief Objects FIFOs APIs.
|
||||
* @details If enabled then the objects FIFOs APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_OBJ_FIFOS TRUE
|
||||
|
||||
/**
|
||||
* @brief Dynamic Threads APIs.
|
||||
* @details If enabled then the dynamic threads creation APIs are included
|
||||
|
|
@ -300,6 +329,56 @@
|
|||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Objects factory options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Objects Factory APIs.
|
||||
* @details If enabled then the objects factory APIs are included in the
|
||||
* kernel.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_CFG_USE_FACTORY TRUE
|
||||
|
||||
/**
|
||||
* @brief Maximum length for object names.
|
||||
* @details If the specified length is zero then the name is stored by
|
||||
* pointer but this could have unintended side effects.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
|
||||
|
||||
/**
|
||||
* @brief Enables the registry of generic objects.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for generic buffers.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for semaphores.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_SEMAPHORES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for mailboxes.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_MAILBOXES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables factory for objects FIFOs.
|
||||
*/
|
||||
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Debug options
|
||||
|
|
@ -344,12 +423,18 @@
|
|||
|
||||
/**
|
||||
* @brief Debug option, trace buffer.
|
||||
* @details If enabled then the context switch circular trace buffer is
|
||||
* activated.
|
||||
* @details If enabled then the trace buffer is activated.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
|
||||
*/
|
||||
#define CH_DBG_ENABLE_TRACE FALSE
|
||||
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
|
||||
|
||||
/**
|
||||
* @brief Trace buffer entries.
|
||||
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
|
||||
* different from @p CH_DBG_TRACE_MASK_DISABLED.
|
||||
*/
|
||||
#define CH_DBG_TRACE_BUFFER_SIZE 128
|
||||
|
||||
/**
|
||||
* @brief Debug option, stack checks.
|
||||
|
|
@ -393,6 +478,22 @@
|
|||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System structure extension.
|
||||
* @details User fields added to the end of the @p ch_system_t structure.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_EXTRA_FIELDS \
|
||||
/* Add threads custom fields here.*/
|
||||
|
||||
/**
|
||||
* @brief System initialization hook.
|
||||
* @details User initialization code added to the @p chSysInit() function
|
||||
* just before interrupts are enabled globally.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_INIT_HOOK(tp) { \
|
||||
/* Add threads initialization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Threads descriptor structure extension.
|
||||
* @details User fields added to the end of the @p thread_t structure.
|
||||
|
|
@ -402,9 +503,9 @@
|
|||
|
||||
/**
|
||||
* @brief Threads initialization hook.
|
||||
* @details User initialization code added to the @p chThdInit() API.
|
||||
* @details User initialization code added to the @p _thread_init() function.
|
||||
*
|
||||
* @note It is invoked from within @p chThdInit() and implicitly from all
|
||||
* @note It is invoked from within @p _thread_init() and implicitly from all
|
||||
* the threads creation APIs.
|
||||
*/
|
||||
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
|
||||
|
|
@ -414,10 +515,6 @@
|
|||
/**
|
||||
* @brief Threads finalization hook.
|
||||
* @details User finalization code added to the @p chThdExit() API.
|
||||
*
|
||||
* @note It is inserted into lock zone.
|
||||
* @note It is also invoked when the threads simply return in order to
|
||||
* terminate.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
|
||||
/* Add threads finalization code here.*/ \
|
||||
|
|
@ -428,7 +525,7 @@
|
|||
* @details This hook is invoked just before switching between threads.
|
||||
*/
|
||||
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
|
||||
/* System halt code here.*/ \
|
||||
/* Context switch code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -452,6 +549,7 @@
|
|||
* @note This macro can be used to activate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_ENTER_HOOK() { \
|
||||
/* Idle-enter code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -461,6 +559,7 @@
|
|||
* @note This macro can be used to deactivate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_LEAVE_HOOK() { \
|
||||
/* Idle-leave code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -504,6 +603,6 @@
|
|||
/* Port-specific settings (override port settings defaulted in chcore.h). */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _CHCONF_H_ */
|
||||
#endif /* CHCONF_H */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,52 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
|
||||
<stringAttribute key="bad_container_name" value="\TM4C129x-ETH\debu"/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="monitor reset halt monitor reset init cortex_m maskisr auto"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="dmaris-VectorE0-(format)" val="2"/></contentList>"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-TM4C1294-LAUNCHPAD"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.114656749"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/RT-TM4C1294-LAUNCHPAD"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
|
||||
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
|
||||
</listAttribute>
|
||||
</launchConfiguration>
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -14,8 +14,19 @@
|
|||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _HALCONF_H_
|
||||
#define _HALCONF_H_
|
||||
/**
|
||||
* @file templates/halconf.h
|
||||
* @brief HAL configuration header.
|
||||
* @details HAL configuration file, this file allows to enable or disable the
|
||||
* various device drivers from your application. You may also use
|
||||
* this file in order to override the device drivers default settings.
|
||||
*
|
||||
* @addtogroup HAL_CONF
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef HALCONF_H
|
||||
#define HALCONF_H
|
||||
|
||||
#include "mcuconf.h"
|
||||
|
||||
|
|
@ -40,6 +51,20 @@
|
|||
#define HAL_USE_CAN FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the cryptographic subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CRY FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the DAC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_DAC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the EXT subsystem.
|
||||
*/
|
||||
|
|
@ -61,6 +86,13 @@
|
|||
#define HAL_USE_I2C FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the I2S subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_I2S FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ICU subsystem.
|
||||
*/
|
||||
|
|
@ -89,6 +121,13 @@
|
|||
#define HAL_USE_PWM FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the QSPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_QSPI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the RTC subsystem.
|
||||
*/
|
||||
|
|
@ -138,6 +177,13 @@
|
|||
#define HAL_USE_USB FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the WDG subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_WDG FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* ADC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -169,6 +215,28 @@
|
|||
#define CAN_USE_SLEEP_MODE TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* CRY driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the SW fall-back of the cryptographic driver.
|
||||
* @details When enabled, this option, activates a fall-back software
|
||||
* implementation for algorithms not supported by the underlying
|
||||
* hardware.
|
||||
* @note Fall-back implementations may not be present for all algorithms.
|
||||
*/
|
||||
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_USE_FALLBACK FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Makes the driver forcibly use the fall-back implementations.
|
||||
*/
|
||||
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_ENFORCE_FALLBACK FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I2C driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -262,13 +330,36 @@
|
|||
* @brief Serial buffers size.
|
||||
* @details Configuration parameter, you can change the depth of the queue
|
||||
* buffers depending on the requirements of your application.
|
||||
* @note The default is 64 bytes for both the transmission and receive
|
||||
* @note The default is 16 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_BUFFERS_SIZE 16
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SERIAL_USB driver related setting. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Serial over USB buffers size.
|
||||
* @details Configuration parameter, the buffer size must be a multiple of
|
||||
* the USB data endpoint maximum packet size.
|
||||
* @note The default is 256 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_SIZE 256
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Serial over USB number of buffers.
|
||||
* @note The default is 2 buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_NUMBER 2
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -289,6 +380,38 @@
|
|||
#define SPI_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
#endif /* _HALCONF_H_ */
|
||||
/*===========================================================================*/
|
||||
/* UART driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define UART_USE_WAIT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define UART_USE_MUTUAL_EXCLUSION FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* USB driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define USB_USE_WAIT FALSE
|
||||
#endif
|
||||
|
||||
#endif /* HALCONF_H */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
Copyright (C) 2014..2016 Marco Veeneman
|
||||
Copyright (C) 2014..2017 Marco Veeneman
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -16,13 +16,13 @@
|
|||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
#include "ch_test.h"
|
||||
#include "rt_test_root.h"
|
||||
#include "oslib_test_root.h"
|
||||
|
||||
typedef struct led_config
|
||||
{
|
||||
ioportid_t port;
|
||||
ioline_t line;
|
||||
uint32_t sleep;
|
||||
uint8_t pin;
|
||||
} led_config_t;
|
||||
|
||||
/*
|
||||
|
|
@ -38,11 +38,11 @@ static THD_FUNCTION(blinkLed, arg) {
|
|||
chRegSetThreadName("Blinker");
|
||||
|
||||
/* Configure pin as push-pull output.*/
|
||||
palSetPadMode(ledConfig->port, ledConfig->pin, PAL_MODE_OUTPUT_PUSHPULL);
|
||||
palSetLineMode(ledConfig->line, PAL_MODE_OUTPUT_PUSHPULL);
|
||||
|
||||
while (TRUE) {
|
||||
chThdSleepMilliseconds(ledConfig->sleep);
|
||||
palTogglePad(ledConfig->port, ledConfig->pin);
|
||||
palToggleLine(ledConfig->line);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -64,43 +64,52 @@ int main(void)
|
|||
chSysInit();
|
||||
|
||||
/* Configure RX and TX pins for UART0.*/
|
||||
palSetPadMode(GPIOA, GPIOA_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
|
||||
palSetPadMode(GPIOA, GPIOA_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
|
||||
palSetLineMode(LINE_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
|
||||
palSetLineMode(LINE_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1));
|
||||
|
||||
/* Start the serial driver with the default configuration.*/
|
||||
sdStart(&SD1, NULL);
|
||||
|
||||
if (!palReadPad(GPIOJ, GPIOJ_SW1)) {
|
||||
test_execute((BaseSequentialStream *)&SD1);
|
||||
if (!palReadLine(LINE_SW1)) {
|
||||
test_execute((BaseSequentialStream *)&SD1, &rt_test_suite);
|
||||
test_execute((BaseSequentialStream *)&SD1, &oslib_test_suite);
|
||||
}
|
||||
|
||||
led1.port = GPIOF;
|
||||
led1.pin = GPIOF_LED0;
|
||||
led1.line = LINE_LED0;
|
||||
led1.sleep = 100;
|
||||
|
||||
led2.port = GPIOF;
|
||||
led2.pin = GPIOF_LED1;
|
||||
led2.line = LINE_LED1;
|
||||
led2.sleep = 101;
|
||||
|
||||
led3.port = GPION;
|
||||
led3.pin = GPION_LED2;
|
||||
led3.line = LINE_LED2;
|
||||
led3.sleep = 102;
|
||||
|
||||
led4.port = GPION;
|
||||
led4.pin = GPION_LED3;
|
||||
led4.line = LINE_LED3;
|
||||
led4.sleep = 103;
|
||||
|
||||
/* Creating the blinker threads.*/
|
||||
chThdCreateStatic(waBlinkLed1, sizeof(waBlinkLed1), NORMALPRIO, blinkLed,
|
||||
chThdCreateStatic(waBlinkLed1,
|
||||
sizeof(waBlinkLed1),
|
||||
NORMALPRIO,
|
||||
blinkLed,
|
||||
&led1);
|
||||
|
||||
chThdCreateStatic(waBlinkLed2, sizeof(waBlinkLed2), NORMALPRIO, blinkLed,
|
||||
chThdCreateStatic(waBlinkLed2,
|
||||
sizeof(waBlinkLed2),
|
||||
NORMALPRIO,
|
||||
blinkLed,
|
||||
&led2);
|
||||
|
||||
chThdCreateStatic(waBlinkLed3, sizeof(waBlinkLed3), NORMALPRIO, blinkLed,
|
||||
chThdCreateStatic(waBlinkLed3,
|
||||
sizeof(waBlinkLed3),
|
||||
NORMALPRIO,
|
||||
blinkLed,
|
||||
&led3);
|
||||
|
||||
chThdCreateStatic(waBlinkLed4, sizeof(waBlinkLed4), NORMALPRIO, blinkLed,
|
||||
chThdCreateStatic(waBlinkLed4,
|
||||
sizeof(waBlinkLed4),
|
||||
NORMALPRIO,
|
||||
blinkLed,
|
||||
&led4);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
Copyright (C) 2014..2016 Marco Veeneman
|
||||
Copyright (C) 2014..2017 Marco Veeneman
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
|
|
@ -31,7 +31,7 @@
|
|||
* HAL driver system settings.
|
||||
*/
|
||||
#define TIVA_MOSC_SINGLE_ENDED FALSE
|
||||
#define TIVA_RSCLKCFG_OSCSRC RSCLKCFG_OSCSRC_MOSC
|
||||
#define TIVA_RSCLKCFG_OSCSRC SYSCTL_RSCLKCFG_OSCSRC_MOSC
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
|
|
@ -53,6 +53,42 @@
|
|||
#define TIVA_GPT_GPT6A_IRQ_PRIORITY 7
|
||||
#define TIVA_GPT_GPT7A_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* PAL driver system settings.
|
||||
*/
|
||||
#define TIVA_PAL_GPIOA_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOB_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOC_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOD_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOE_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOF_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOG_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOH_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOJ_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOK_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOL_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOM_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPION_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP0_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP1_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP2_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP3_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP4_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP5_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP6_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOP7_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ0_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ1_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ2_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ3_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ4_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ5_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ6_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOQ7_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOR_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOS_IRQ_PRIORITY 3
|
||||
#define TIVA_PAL_GPIOT_IRQ_PRIORITY 3
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@ include $(CHIBIOS)/os/hal/boards/simulator/board.mk
|
|||
include $(CHIBIOS)/os/hal/hal.mk
|
||||
include $(CHIBIOS)/os/hal/ports/simulator/win32/platform.mk
|
||||
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
|
||||
include $(CHIBIOS)/os/rt/ports/SIMIA32/compilers/GCC/port.mk
|
||||
include $(CHIBIOS)/os/common/ports/SIMIA32/compilers/GCC/port.mk
|
||||
include $(CHIBIOS)/os/rt/rt.mk
|
||||
include $(CHIBIOS)/test/rt/test.mk
|
||||
|
||||
|
|
|
|||
|
|
@ -28,6 +28,9 @@
|
|||
#ifndef _CHCONF_H_
|
||||
#define _CHCONF_H_
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_5_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name System timers settings
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ static char read_front(void) {
|
|||
msg_t error;
|
||||
|
||||
/* Wait until a new front buffer gets available with prepared data */
|
||||
error = tribufWaitReadyTimeout(&tribuf, MS2ST(1000));
|
||||
error = tribufWaitReadyTimeout(&tribuf, TIME_MS2I(1000));
|
||||
if (error == MSG_TIMEOUT)
|
||||
chSysHalt("ERROR: read_front() timed out");
|
||||
|
||||
|
|
|
|||
|
|
@ -2242,7 +2242,7 @@ typedef struct
|
|||
/******** Bits definition for USBx_CTL register *****************/
|
||||
#define USBx_CTL_JSTATE ((uint8_t)0x80) /*!< Live USB differential receiver JSTATE signal */
|
||||
#define USBx_CTL_SE0 ((uint8_t)0x40) /*!< Live USB single ended zero signal */
|
||||
#define USBx_CTL_TXSUSPENDTOKENBUS ((uint8_t)0x20) /*!< */
|
||||
#define USBx_CTL_TXSUSPENDTOKENBUSY ((uint8_t)0x20) /*!< */
|
||||
#define USBx_CTL_RESET ((uint8_t)0x10) /*!< Generates an USB reset signal (host mode) */
|
||||
#define USBx_CTL_HOSTMODEEN ((uint8_t)0x08) /*!< Operate in Host mode */
|
||||
#define USBx_CTL_RESUME ((uint8_t)0x04) /*!< Executes resume signaling */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,343 @@
|
|||
/*******************************************************************************
|
||||
* in430.h -
|
||||
*
|
||||
* Copyright (C) 2003-2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __IN430_H__
|
||||
#define __IN430_H__
|
||||
|
||||
/* Definitions for projects using the GNU C/C++ compiler */
|
||||
#if !defined(__ASSEMBLER__)
|
||||
|
||||
/* Definitions of things which are intrinsics with IAR and CCS, but which don't
|
||||
appear to be intrinsics with the RedHat GCC compiler */
|
||||
|
||||
/* The data type used to hold interrupt state */
|
||||
typedef unsigned int __istate_t;
|
||||
|
||||
#define _no_operation() __asm__ __volatile__ ("nop")
|
||||
|
||||
#define _get_interrupt_state() \
|
||||
({ \
|
||||
unsigned int __x; \
|
||||
__asm__ __volatile__( \
|
||||
"mov SR, %0" \
|
||||
: "=r" ((unsigned int) __x) \
|
||||
:); \
|
||||
__x; \
|
||||
})
|
||||
|
||||
#if defined(__MSP430_HAS_MSP430XV2_CPU__) || defined(__MSP430_HAS_MSP430X_CPU__)
|
||||
#define _set_interrupt_state(x) \
|
||||
({ \
|
||||
__asm__ __volatile__ ("mov %0, SR { nop" \
|
||||
: : "ri"((unsigned int) x) \
|
||||
);\
|
||||
})
|
||||
|
||||
#define _enable_interrupts() __asm__ __volatile__ ("nop { eint { nop")
|
||||
|
||||
#define _bis_SR_register(x) \
|
||||
__asm__ __volatile__ ("bis.w %0, SR { nop" \
|
||||
: : "ri"((unsigned int) x) \
|
||||
)
|
||||
#else
|
||||
|
||||
#define _set_interrupt_state(x) \
|
||||
({ \
|
||||
__asm__ __volatile__ ("mov %0, SR" \
|
||||
: : "ri"((unsigned int) x) \
|
||||
);\
|
||||
})
|
||||
|
||||
#define _enable_interrupts() __asm__ __volatile__ ("eint { nop")
|
||||
|
||||
#define _bis_SR_register(x) \
|
||||
__asm__ __volatile__ ("bis.w %0, SR" \
|
||||
: : "ri"((unsigned int) x) \
|
||||
)
|
||||
|
||||
#endif
|
||||
|
||||
#define _disable_interrupts() __asm__ __volatile__ ("dint { nop")
|
||||
|
||||
#define _bic_SR_register(x) \
|
||||
__asm__ __volatile__ ("bic.w %0, SR { nop" \
|
||||
: : "ri"((unsigned int) x) \
|
||||
)
|
||||
|
||||
#define _get_SR_register() \
|
||||
({ \
|
||||
unsigned int __x; \
|
||||
__asm__ __volatile__( \
|
||||
"mov SR, %0" \
|
||||
: "=r" ((unsigned int) __x) \
|
||||
:); \
|
||||
__x; \
|
||||
})
|
||||
|
||||
#define _swap_bytes(x) \
|
||||
({ \
|
||||
unsigned int __dst = x; \
|
||||
__asm__ __volatile__( \
|
||||
"swpb %0" \
|
||||
: "+r" ((unsigned int) __dst) \
|
||||
:); \
|
||||
__dst; \
|
||||
})
|
||||
|
||||
/* Alternative names for GCC built-ins */
|
||||
#define _bic_SR_register_on_exit(x) __bic_SR_register_on_exit(x)
|
||||
#define _bis_SR_register_on_exit(x) __bis_SR_register_on_exit(x)
|
||||
|
||||
/* Additional intrinsics provided for IAR/CCS compatibility */
|
||||
#define _bcd_add_short(x,y) \
|
||||
({ \
|
||||
unsigned short __z = ((unsigned short) y); \
|
||||
__asm__ __volatile__( \
|
||||
"clrc \n\t" \
|
||||
"dadd.w %1, %0" \
|
||||
: "+r" ((unsigned short) __z) \
|
||||
: "ri" ((unsigned short) x) \
|
||||
); \
|
||||
__z; \
|
||||
})
|
||||
|
||||
#define __bcd_add_short(x,y) _bcd_add_short(x,y)
|
||||
|
||||
#define _bcd_add_long(x,y) \
|
||||
({ \
|
||||
unsigned long __z = ((unsigned long) y); \
|
||||
__asm__ __volatile__( \
|
||||
"clrc \n\t" \
|
||||
"dadd.w %L1, %L0 \n\t" \
|
||||
"dadd.w %H1, %H0" \
|
||||
: "+r" ((unsigned long) __z) \
|
||||
: "ri" ((unsigned long) x) \
|
||||
); \
|
||||
__z; \
|
||||
})
|
||||
|
||||
#define __bcd_add_long(x,y) _bcd_add_long(x,y)
|
||||
|
||||
#define _get_SP_register() \
|
||||
({ \
|
||||
unsigned int __x; \
|
||||
__asm__ __volatile__( \
|
||||
"mov SP, %0" \
|
||||
: "=r" ((unsigned int) __x) \
|
||||
:); \
|
||||
__x; \
|
||||
})
|
||||
|
||||
#define __get_SP_register() _get_SP_register()
|
||||
|
||||
#define _set_SP_register(x) \
|
||||
({ \
|
||||
__asm__ __volatile__ ("mov %0, SP" \
|
||||
: : "ri"((unsigned int) x) \
|
||||
);\
|
||||
})
|
||||
|
||||
#define __set_SP_register(x) _set_SP_register(x)
|
||||
|
||||
#define _data16_write_addr(addr,src) \
|
||||
({ \
|
||||
unsigned long __src = src; \
|
||||
__asm__ __volatile__ ( \
|
||||
"movx.a %1, 0(%0)" \
|
||||
: : "r"((unsigned int) addr), "m"((unsigned long) __src) \
|
||||
); \
|
||||
})
|
||||
|
||||
#define __data16_write_addr(addr,src) _data16_write_addr(addr,src)
|
||||
|
||||
#define _data16_read_addr(addr) \
|
||||
({ \
|
||||
unsigned long __dst; \
|
||||
__asm__ __volatile__ ( \
|
||||
"movx.a @%1, %0" \
|
||||
: "=m"((unsigned long) __dst) \
|
||||
: "r"((unsigned int) addr) \
|
||||
); \
|
||||
__dst; \
|
||||
})
|
||||
|
||||
#define __data16_read_addr(addr) _data16_read_addr(addr)
|
||||
|
||||
#define _data20_write_char(addr,src) \
|
||||
({ \
|
||||
unsigned int __tmp; \
|
||||
unsigned long __addr = addr; \
|
||||
__asm__ __volatile__ ( \
|
||||
"movx.a %1, %0 \n\t" \
|
||||
"mov.b %2, 0(%0)" \
|
||||
: "=&r"((unsigned int) __tmp) \
|
||||
: "m"((unsigned long) __addr), "ri"((char) src) \
|
||||
); \
|
||||
})
|
||||
|
||||
#define __data20_write_char(addr,src) _data20_write_char(addr,src)
|
||||
|
||||
#define _data20_read_char(addr) \
|
||||
({ \
|
||||
char __dst; \
|
||||
unsigned int __tmp; \
|
||||
unsigned long __addr = addr; \
|
||||
__asm__ __volatile__ ( \
|
||||
"movx.a %2, %1 \n\t" \
|
||||
"mov.b 0(%1), %0" \
|
||||
: "=r"((char) __dst), "=&r"((unsigned int) __tmp) \
|
||||
: "m"((unsigned long) __addr) \
|
||||
); \
|
||||
__dst ; \
|
||||
})
|
||||
|
||||
#define __data20_read_char(addr) _data20_read_char(addr)
|
||||
|
||||
#define _data20_write_short(addr,src) \
|
||||
({ \
|
||||
unsigned int __tmp; \
|
||||
unsigned long __addr = addr; \
|
||||
__asm__ __volatile__ ( \
|
||||
"movx.a %1, %0 \n\t" \
|
||||
"mov.w %2, 0(%0)" \
|
||||
: "=&r"((unsigned int) __tmp) \
|
||||
: "m"((unsigned long) __addr), "ri"((short) src) \
|
||||
); \
|
||||
})
|
||||
|
||||
#define __data20_write_short(addr,src) _data20_write_short(addr,src)
|
||||
|
||||
#define _data20_read_short(addr) \
|
||||
({ \
|
||||
short __dst; \
|
||||
unsigned int __tmp; \
|
||||
unsigned long __addr = addr; \
|
||||
__asm__ __volatile__ ( \
|
||||
"movx.a %2, %1 \n\t" \
|
||||
"mov.w 0(%1), %0" \
|
||||
: "=r"((short) __dst), "=&r"((unsigned int) __tmp) \
|
||||
: "m"((unsigned long) __addr) \
|
||||
); \
|
||||
__dst ; \
|
||||
})
|
||||
|
||||
#define __data20_read_short(addr) _data20_read_short(addr)
|
||||
|
||||
#define _data20_write_long(addr,src) \
|
||||
({ \
|
||||
unsigned int __tmp; \
|
||||
unsigned long __addr = addr; \
|
||||
__asm__ __volatile__ ( \
|
||||
"movx.a %1, %0 \n\t" \
|
||||
"mov.w %L2, 0(%0) \n\t" \
|
||||
"mov.w %H2, 2(%0)" \
|
||||
: "=&r"((unsigned int) __tmp) \
|
||||
: "m"((unsigned long) __addr), "ri"((long) src) \
|
||||
); \
|
||||
})
|
||||
|
||||
#define __data20_write_long(addr,src) _data20_write_long(addr,src)
|
||||
|
||||
#define _data20_read_long(addr) \
|
||||
({ \
|
||||
long __dst; \
|
||||
unsigned int __tmp; \
|
||||
unsigned long __addr = addr; \
|
||||
__asm__ __volatile__ ( \
|
||||
"movx.a %2, %1 \n\t" \
|
||||
"mov.w 0(%1), %L0 \n\t" \
|
||||
"mov.w 2(%1), %H0" \
|
||||
: "=r"((long) __dst), "=&r"((unsigned int) __tmp) \
|
||||
: "m"((unsigned long) __addr) \
|
||||
); \
|
||||
__dst ; \
|
||||
})
|
||||
|
||||
#define __data20_read_long(addr) _data20_read_long(addr)
|
||||
|
||||
#define _low_power_mode_0() _bis_SR_register(0x18)
|
||||
#define _low_power_mode_1() _bis_SR_register(0x58)
|
||||
#define _low_power_mode_2() _bis_SR_register(0x98)
|
||||
#define _low_power_mode_3() _bis_SR_register(0xD8)
|
||||
#define _low_power_mode_4() _bis_SR_register(0xF8)
|
||||
#define _low_power_mode_off_on_exit() _bic_SR_register_on_exit(0xF0)
|
||||
|
||||
#define __low_power_mode_0() _low_power_mode_0()
|
||||
#define __low_power_mode_1() _low_power_mode_1()
|
||||
#define __low_power_mode_2() _low_power_mode_2()
|
||||
#define __low_power_mode_3() _low_power_mode_3()
|
||||
#define __low_power_mode_4() _low_power_mode_4()
|
||||
#define __low_power_mode_off_on_exit() _low_power_mode_off_on_exit()
|
||||
|
||||
#define _even_in_range(x,y) (x)
|
||||
#define __even_in_range(x,y) _even_in_range(x,y)
|
||||
|
||||
/* Define some alternative names for the intrinsics, which have been used
|
||||
in the various versions of IAR and GCC */
|
||||
#define __no_operation() _no_operation()
|
||||
|
||||
#define __get_interrupt_state() _get_interrupt_state()
|
||||
#define __set_interrupt_state(x) _set_interrupt_state(x)
|
||||
#define __enable_interrupt() _enable_interrupts()
|
||||
#define __disable_interrupt() _disable_interrupts()
|
||||
|
||||
#define __bic_SR_register(x) _bic_SR_register(x)
|
||||
#define __bis_SR_register(x) _bis_SR_register(x)
|
||||
#define __get_SR_register() _get_SR_register()
|
||||
|
||||
#define __swap_bytes(x) _swap_bytes(x)
|
||||
|
||||
#define __nop() _no_operation()
|
||||
|
||||
#define __eint() _enable_interrupts()
|
||||
#define __dint() _disable_interrupts()
|
||||
|
||||
#define _NOP() _no_operation()
|
||||
#define _EINT() _enable_interrupts()
|
||||
#define _DINT() _disable_interrupts()
|
||||
|
||||
#define _BIC_SR(x) _bic_SR_register(x)
|
||||
#define _BIC_SR_IRQ(x) _bic_SR_register_on_exit(x)
|
||||
#define _BIS_SR(x) _bis_SR_register(x)
|
||||
#define _BIS_SR_IRQ(x) _bis_SR_register_on_exit(x)
|
||||
#define _BIS_NMI_IE1(x) _bis_nmi_ie1(x)
|
||||
|
||||
#define _SWAP_BYTES(x) _swap_bytes(x)
|
||||
|
||||
#define __no_init __attribute__ ((section (".noinit")))
|
||||
|
||||
#endif /* !defined _GNU_ASSEMBLER_ */
|
||||
|
||||
#endif /* __IN430_H__ */
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/*******************************************************************************
|
||||
* iomacros.h -
|
||||
*
|
||||
* Copyright (C) 2003-2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#if !defined(_IOMACROS_H_)
|
||||
#define _IOMACROS_H_
|
||||
|
||||
|
||||
#if defined(__ASSEMBLER__)
|
||||
|
||||
/* Definitions for assembly compilation using the GNU assembler */
|
||||
#define sfrb(x,x_) x=x_
|
||||
#define sfrw(x,x_) x=x_
|
||||
#define sfra(x,x_) x=x_
|
||||
#define sfrl(x,x_) x=x_
|
||||
|
||||
#define const_sfrb(x,x_) x=x_
|
||||
#define const_sfrw(x,x_) x=x_
|
||||
#define const_sfra(x,x_) x=x_
|
||||
#define const_sfrl(x,x_) x=x_
|
||||
|
||||
#define sfr_b(x)
|
||||
#define sfr_w(x)
|
||||
#define sfr_a(x)
|
||||
#define sfr_l(x)
|
||||
|
||||
#else
|
||||
|
||||
#define sfr_b(x) extern volatile unsigned char x
|
||||
#define sfr_w(x) extern volatile unsigned int x
|
||||
#define sfr_a(x) extern volatile unsigned long int x
|
||||
#define sfr_l(x) extern volatile unsigned long int x
|
||||
|
||||
#define sfrb_(x,x_) extern volatile unsigned char x __asm__(#x_)
|
||||
#define sfrw_(x,x_) extern volatile unsigned int x __asm__(#x_)
|
||||
#define sfra_(x,x_) extern volatile unsigned long int x __asm__(#x_)
|
||||
#define sfrl_(x,x_) extern volatile unsigned long int x __asm__(#x_)
|
||||
|
||||
#define sfrb(x,x_) sfrb_(x,x_)
|
||||
#define sfrw(x,x_) sfrw_(x,x_)
|
||||
#define sfra(x,x_) sfra_(x,x_)
|
||||
#define sfrl(x,x_) sfrl_(x,x_)
|
||||
|
||||
#define const_sfrb(x,x_) const sfrb_(x,x_)
|
||||
#define const_sfrw(x,x_) const sfrw_(x,x_)
|
||||
#define const_sfra(x,x_) const sfra_(x,x_)
|
||||
#define const_sfrl(x,x_) const sfrl_(x,x_)
|
||||
|
||||
#define __interrupt __attribute__((__interrupt__))
|
||||
#define __interrupt_vec(vec) __attribute__((interrupt(vec)))
|
||||
|
||||
#endif /* defined(__ASSEMBLER__) */
|
||||
|
||||
#endif /* _IOMACROS_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,227 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// asmdefs.h - Macros to allow assembly code be portable among toolchains.
|
||||
//
|
||||
// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __ASMDEFS_H__
|
||||
#define __ASMDEFS_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The defines required for code_red.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef codered
|
||||
|
||||
//
|
||||
// The assembly code preamble required to put the assembler into the correct
|
||||
// configuration.
|
||||
//
|
||||
.syntax unified
|
||||
.thumb
|
||||
|
||||
//
|
||||
// Section headers.
|
||||
//
|
||||
#define __LIBRARY__ @
|
||||
#define __TEXT__ .text
|
||||
#define __DATA__ .data
|
||||
#define __BSS__ .bss
|
||||
#define __TEXT_NOROOT__ .text
|
||||
|
||||
//
|
||||
// Assembler nmenonics.
|
||||
//
|
||||
#define __ALIGN__ .balign 4
|
||||
#define __END__ .end
|
||||
#define __EXPORT__ .globl
|
||||
#define __IMPORT__ .extern
|
||||
#define __LABEL__ :
|
||||
#define __STR__ .ascii
|
||||
#define __THUMB_LABEL__ .thumb_func
|
||||
#define __WORD__ .word
|
||||
#define __INLINE_DATA__
|
||||
|
||||
#endif // codered
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The defines required for EW-ARM.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef ewarm
|
||||
|
||||
//
|
||||
// Section headers.
|
||||
//
|
||||
#define __LIBRARY__ module
|
||||
#define __TEXT__ rseg CODE:CODE(2)
|
||||
#define __DATA__ rseg DATA:DATA(2)
|
||||
#define __BSS__ rseg DATA:DATA(2)
|
||||
#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2)
|
||||
|
||||
//
|
||||
// Assembler nmenonics.
|
||||
//
|
||||
#define __ALIGN__ alignrom 2
|
||||
#define __END__ end
|
||||
#define __EXPORT__ export
|
||||
#define __IMPORT__ import
|
||||
#define __LABEL__
|
||||
#define __STR__ dcb
|
||||
#define __THUMB_LABEL__ thumb
|
||||
#define __WORD__ dcd
|
||||
#define __INLINE_DATA__ data
|
||||
|
||||
#endif // ewarm
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The defines required for GCC.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined(gcc)
|
||||
|
||||
//
|
||||
// The assembly code preamble required to put the assembler into the correct
|
||||
// configuration.
|
||||
//
|
||||
.syntax unified
|
||||
.thumb
|
||||
|
||||
//
|
||||
// Section headers.
|
||||
//
|
||||
#define __LIBRARY__ @
|
||||
#define __TEXT__ .text
|
||||
#define __DATA__ .data
|
||||
#define __BSS__ .bss
|
||||
#define __TEXT_NOROOT__ .text
|
||||
|
||||
//
|
||||
// Assembler nmenonics.
|
||||
//
|
||||
#define __ALIGN__ .balign 4
|
||||
#define __END__ .end
|
||||
#define __EXPORT__ .globl
|
||||
#define __IMPORT__ .extern
|
||||
#define __LABEL__ :
|
||||
#define __STR__ .ascii
|
||||
#define __THUMB_LABEL__ .thumb_func
|
||||
#define __WORD__ .word
|
||||
#define __INLINE_DATA__
|
||||
|
||||
#endif // gcc
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The defines required for RV-MDK.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef rvmdk
|
||||
|
||||
//
|
||||
// The assembly code preamble required to put the assembler into the correct
|
||||
// configuration.
|
||||
//
|
||||
thumb
|
||||
require8
|
||||
preserve8
|
||||
|
||||
//
|
||||
// Section headers.
|
||||
//
|
||||
#define __LIBRARY__ ;
|
||||
#define __TEXT__ area ||.text||, code, readonly, align=2
|
||||
#define __DATA__ area ||.data||, data, align=2
|
||||
#define __BSS__ area ||.bss||, noinit, align=2
|
||||
#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2
|
||||
|
||||
//
|
||||
// Assembler nmenonics.
|
||||
//
|
||||
#define __ALIGN__ align 4
|
||||
#define __END__ end
|
||||
#define __EXPORT__ export
|
||||
#define __IMPORT__ import
|
||||
#define __LABEL__
|
||||
#define __STR__ dcb
|
||||
#define __THUMB_LABEL__
|
||||
#define __WORD__ dcd
|
||||
#define __INLINE_DATA__
|
||||
|
||||
#endif // rvmdk
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The defines required for Sourcery G++.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined(sourcerygxx)
|
||||
|
||||
//
|
||||
// The assembly code preamble required to put the assembler into the correct
|
||||
// configuration.
|
||||
//
|
||||
.syntax unified
|
||||
.thumb
|
||||
|
||||
//
|
||||
// Section headers.
|
||||
//
|
||||
#define __LIBRARY__ @
|
||||
#define __TEXT__ .text
|
||||
#define __DATA__ .data
|
||||
#define __BSS__ .bss
|
||||
#define __TEXT_NOROOT__ .text
|
||||
|
||||
//
|
||||
// Assembler nmenonics.
|
||||
//
|
||||
#define __ALIGN__ .balign 4
|
||||
#define __END__ .end
|
||||
#define __EXPORT__ .globl
|
||||
#define __IMPORT__ .extern
|
||||
#define __LABEL__ :
|
||||
#define __STR__ .ascii
|
||||
#define __THUMB_LABEL__ .thumb_func
|
||||
#define __WORD__ .word
|
||||
#define __INLINE_DATA__
|
||||
|
||||
#endif // sourcerygxx
|
||||
|
||||
#endif // __ASMDEF_H__
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,545 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_aes.h - Macros used when accessing the AES hardware.
|
||||
//
|
||||
// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_AES_H__
|
||||
#define __HW_AES_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the AES register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_O_KEY2_6 0x00000000 // AES Key 2_6
|
||||
#define AES_O_KEY2_7 0x00000004 // AES Key 2_7
|
||||
#define AES_O_KEY2_4 0x00000008 // AES Key 2_4
|
||||
#define AES_O_KEY2_5 0x0000000C // AES Key 2_5
|
||||
#define AES_O_KEY2_2 0x00000010 // AES Key 2_2
|
||||
#define AES_O_KEY2_3 0x00000014 // AES Key 2_3
|
||||
#define AES_O_KEY2_0 0x00000018 // AES Key 2_0
|
||||
#define AES_O_KEY2_1 0x0000001C // AES Key 2_1
|
||||
#define AES_O_KEY1_6 0x00000020 // AES Key 1_6
|
||||
#define AES_O_KEY1_7 0x00000024 // AES Key 1_7
|
||||
#define AES_O_KEY1_4 0x00000028 // AES Key 1_4
|
||||
#define AES_O_KEY1_5 0x0000002C // AES Key 1_5
|
||||
#define AES_O_KEY1_2 0x00000030 // AES Key 1_2
|
||||
#define AES_O_KEY1_3 0x00000034 // AES Key 1_3
|
||||
#define AES_O_KEY1_0 0x00000038 // AES Key 1_0
|
||||
#define AES_O_KEY1_1 0x0000003C // AES Key 1_1
|
||||
#define AES_O_IV_IN_0 0x00000040 // AES Initialization Vector Input
|
||||
// 0
|
||||
#define AES_O_IV_IN_1 0x00000044 // AES Initialization Vector Input
|
||||
// 1
|
||||
#define AES_O_IV_IN_2 0x00000048 // AES Initialization Vector Input
|
||||
// 2
|
||||
#define AES_O_IV_IN_3 0x0000004C // AES Initialization Vector Input
|
||||
// 3
|
||||
#define AES_O_CTRL 0x00000050 // AES Control
|
||||
#define AES_O_C_LENGTH_0 0x00000054 // AES Crypto Data Length 0
|
||||
#define AES_O_C_LENGTH_1 0x00000058 // AES Crypto Data Length 1
|
||||
#define AES_O_AUTH_LENGTH 0x0000005C // AES Authentication Data Length
|
||||
#define AES_O_DATA_IN_0 0x00000060 // AES Data RW Plaintext/Ciphertext
|
||||
// 0
|
||||
#define AES_O_DATA_IN_1 0x00000064 // AES Data RW Plaintext/Ciphertext
|
||||
// 1
|
||||
#define AES_O_DATA_IN_2 0x00000068 // AES Data RW Plaintext/Ciphertext
|
||||
// 2
|
||||
#define AES_O_DATA_IN_3 0x0000006C // AES Data RW Plaintext/Ciphertext
|
||||
// 3
|
||||
#define AES_O_TAG_OUT_0 0x00000070 // AES Hash Tag Out 0
|
||||
#define AES_O_TAG_OUT_1 0x00000074 // AES Hash Tag Out 1
|
||||
#define AES_O_TAG_OUT_2 0x00000078 // AES Hash Tag Out 2
|
||||
#define AES_O_TAG_OUT_3 0x0000007C // AES Hash Tag Out 3
|
||||
#define AES_O_REVISION 0x00000080 // AES IP Revision Identifier
|
||||
#define AES_O_SYSCONFIG 0x00000084 // AES System Configuration
|
||||
#define AES_O_SYSSTATUS 0x00000088 // AES System Status
|
||||
#define AES_O_IRQSTATUS 0x0000008C // AES Interrupt Status
|
||||
#define AES_O_IRQENABLE 0x00000090 // AES Interrupt Enable
|
||||
#define AES_O_DIRTYBITS 0x00000094 // AES Dirty Bits
|
||||
#define AES_O_DMAIM 0xFFFFA020 // AES DMA Interrupt Mask
|
||||
#define AES_O_DMARIS 0xFFFFA024 // AES DMA Raw Interrupt Status
|
||||
#define AES_O_DMAMIS 0xFFFFA028 // AES DMA Masked Interrupt Status
|
||||
#define AES_O_DMAIC 0xFFFFA02C // AES DMA Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY2_6 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY2_6_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY2_6_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY2_7 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY2_7_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY2_7_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY2_4 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY2_4_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY2_4_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY2_5 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY2_5_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY2_5_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY2_2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY2_2_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY2_2_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY2_3 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY2_3_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY2_3_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY2_0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY2_0_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY2_0_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY2_1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY2_1_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY2_1_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY1_6 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY1_6_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY1_6_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY1_7 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY1_7_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY1_7_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY1_4 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY1_4_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY1_4_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY1_5 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY1_5_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY1_5_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY1_2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY1_2_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY1_2_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY1_3 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY1_3_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY1_3_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY1_0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY1_0_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY1_0_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_KEY1_1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_KEY1_1_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define AES_KEY1_1_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_IV_IN_0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // Initialization Vector Input
|
||||
#define AES_IV_IN_0_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_IV_IN_1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // Initialization Vector Input
|
||||
#define AES_IV_IN_1_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_IV_IN_2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // Initialization Vector Input
|
||||
#define AES_IV_IN_2_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_IV_IN_3 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // Initialization Vector Input
|
||||
#define AES_IV_IN_3_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_CTRL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_CTRL_CTXTRDY 0x80000000 // Context Data Registers Ready
|
||||
#define AES_CTRL_SVCTXTRDY 0x40000000 // AES TAG/IV Block(s) Ready
|
||||
#define AES_CTRL_SAVE_CONTEXT 0x20000000 // TAG or Result IV Save
|
||||
#define AES_CTRL_CCM_M_M 0x01C00000 // Counter with CBC-MAC (CCM)
|
||||
#define AES_CTRL_CCM_L_M 0x00380000 // L Value
|
||||
#define AES_CTRL_CCM_L_2 0x00080000 // width = 2
|
||||
#define AES_CTRL_CCM_L_4 0x00180000 // width = 4
|
||||
#define AES_CTRL_CCM_L_8 0x00380000 // width = 8
|
||||
#define AES_CTRL_CCM 0x00040000 // AES-CCM Mode Enable
|
||||
#define AES_CTRL_GCM_M 0x00030000 // AES-GCM Mode Enable
|
||||
#define AES_CTRL_GCM_NOP 0x00000000 // No operation
|
||||
#define AES_CTRL_GCM_HLY0ZERO 0x00010000 // GHASH with H loaded and
|
||||
// Y0-encrypted forced to zero
|
||||
#define AES_CTRL_GCM_HLY0CALC 0x00020000 // GHASH with H loaded and
|
||||
// Y0-encrypted calculated
|
||||
// internally
|
||||
#define AES_CTRL_GCM_HY0CALC 0x00030000 // Autonomous GHASH (both H and
|
||||
// Y0-encrypted calculated
|
||||
// internally)
|
||||
#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC Enable
|
||||
#define AES_CTRL_F9 0x00004000 // AES f9 Mode Enable
|
||||
#define AES_CTRL_F8 0x00002000 // AES f8 Mode Enable
|
||||
#define AES_CTRL_XTS_M 0x00001800 // AES-XTS Operation Enabled
|
||||
#define AES_CTRL_XTS_NOP 0x00000000 // No operation
|
||||
#define AES_CTRL_XTS_TWEAKJL 0x00000800 // Previous/intermediate tweak
|
||||
// value and j loaded (value is
|
||||
// loaded via IV, j is loaded via
|
||||
// the AAD length register)
|
||||
#define AES_CTRL_XTS_K2IJL 0x00001000 // Key2, n and j are loaded (n is
|
||||
// loaded via IV, j is loaded via
|
||||
// the AAD length register)
|
||||
#define AES_CTRL_XTS_K2ILJ0 0x00001800 // Key2 and n are loaded; j=0 (n is
|
||||
// loaded via IV)
|
||||
#define AES_CTRL_CFB 0x00000400 // Full block AES cipher feedback
|
||||
// mode (CFB128) Enable
|
||||
#define AES_CTRL_ICM 0x00000200 // AES Integer Counter Mode (ICM)
|
||||
// Enable
|
||||
#define AES_CTRL_CTR_WIDTH_M 0x00000180 // AES-CTR Mode Counter Width
|
||||
#define AES_CTRL_CTR_WIDTH_32 0x00000000 // Counter is 32 bits
|
||||
#define AES_CTRL_CTR_WIDTH_64 0x00000080 // Counter is 64 bits
|
||||
#define AES_CTRL_CTR_WIDTH_96 0x00000100 // Counter is 96 bits
|
||||
#define AES_CTRL_CTR_WIDTH_128 0x00000180 // Counter is 128 bits
|
||||
#define AES_CTRL_CTR 0x00000040 // Counter Mode
|
||||
#define AES_CTRL_MODE 0x00000020 // ECB/CBC Mode
|
||||
#define AES_CTRL_KEY_SIZE_M 0x00000018 // Key Size
|
||||
#define AES_CTRL_KEY_SIZE_128 0x00000008 // Key is 128 bits
|
||||
#define AES_CTRL_KEY_SIZE_192 0x00000010 // Key is 192 bits
|
||||
#define AES_CTRL_KEY_SIZE_256 0x00000018 // Key is 256 bits
|
||||
#define AES_CTRL_DIRECTION 0x00000004 // Encryption/Decryption Selection
|
||||
#define AES_CTRL_INPUT_READY 0x00000002 // Input Ready Status
|
||||
#define AES_CTRL_OUTPUT_READY 0x00000001 // Output Ready Status
|
||||
#define AES_CTRL_CCM_M_S 22
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_C_LENGTH_0
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_C_LENGTH_0_LENGTH_M 0xFFFFFFFF // Data Length
|
||||
#define AES_C_LENGTH_0_LENGTH_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_C_LENGTH_1
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_C_LENGTH_1_LENGTH_M 0xFFFFFFFF // Data Length
|
||||
#define AES_C_LENGTH_1_LENGTH_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_AUTH_LENGTH
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_AUTH_LENGTH_AUTH_M 0xFFFFFFFF // Authentication Data Length
|
||||
#define AES_AUTH_LENGTH_AUTH_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_DATA_IN_0
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Secure Data RW
|
||||
// Plaintext/Ciphertext
|
||||
#define AES_DATA_IN_0_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_DATA_IN_1
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Secure Data RW
|
||||
// Plaintext/Ciphertext
|
||||
#define AES_DATA_IN_1_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_DATA_IN_2
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Secure Data RW
|
||||
// Plaintext/Ciphertext
|
||||
#define AES_DATA_IN_2_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_DATA_IN_3
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Secure Data RW
|
||||
// Plaintext/Ciphertext
|
||||
#define AES_DATA_IN_3_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_TAG_OUT_0
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash Result
|
||||
#define AES_TAG_OUT_0_HASH_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_TAG_OUT_1
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash Result
|
||||
#define AES_TAG_OUT_1_HASH_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_TAG_OUT_2
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash Result
|
||||
#define AES_TAG_OUT_2_HASH_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_TAG_OUT_3
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash Result
|
||||
#define AES_TAG_OUT_3_HASH_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_REVISION register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_REVISION_M 0xFFFFFFFF // Revision number
|
||||
#define AES_REVISION_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_SYSCONFIG
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_SYSCONFIG_K3 0x00001000 // K3 Select
|
||||
#define AES_SYSCONFIG_KEYENC 0x00000800 // Key Encoding
|
||||
#define AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT \
|
||||
0x00000200 // Map Context Out on Data Out
|
||||
// Enable
|
||||
#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \
|
||||
0x00000100 // DMA Request Context Out Enable
|
||||
#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
|
||||
0x00000080 // DMA Request Context In Enable
|
||||
#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
|
||||
0x00000040 // DMA Request Data Out Enable
|
||||
#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
|
||||
0x00000020 // DMA Request Data In Enable
|
||||
#define AES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_SYSSTATUS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_IRQSTATUS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_IRQSTATUS_CONTEXT_OUT \
|
||||
0x00000008 // Context Output Interrupt Status
|
||||
#define AES_IRQSTATUS_DATA_OUT 0x00000004 // Data Out Interrupt Status
|
||||
#define AES_IRQSTATUS_DATA_IN 0x00000002 // Data In Interrupt Status
|
||||
#define AES_IRQSTATUS_CONTEXT_IN \
|
||||
0x00000001 // Context In Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_IRQENABLE
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_IRQENABLE_CONTEXT_OUT \
|
||||
0x00000008 // Context Out Interrupt Enable
|
||||
#define AES_IRQENABLE_DATA_OUT 0x00000004 // Data Out Interrupt Enable
|
||||
#define AES_IRQENABLE_DATA_IN 0x00000002 // Data In Interrupt Enable
|
||||
#define AES_IRQENABLE_CONTEXT_IN \
|
||||
0x00000001 // Context In Interrupt Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_DIRTYBITS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_DIRTYBITS_S_DIRTY 0x00000002 // AES Dirty Bit
|
||||
#define AES_DIRTYBITS_S_ACCESS 0x00000001 // AES Access Bit
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_DMAIM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_DMAIM_DOUT 0x00000008 // Data Out DMA Done Interrupt Mask
|
||||
#define AES_DMAIM_DIN 0x00000004 // Data In DMA Done Interrupt Mask
|
||||
#define AES_DMAIM_COUT 0x00000002 // Context Out DMA Done Interrupt
|
||||
// Mask
|
||||
#define AES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt
|
||||
// Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_DMARIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_DMARIS_DOUT 0x00000008 // Data Out DMA Done Raw Interrupt
|
||||
// Status
|
||||
#define AES_DMARIS_DIN 0x00000004 // Data In DMA Done Raw Interrupt
|
||||
// Status
|
||||
#define AES_DMARIS_COUT 0x00000002 // Context Out DMA Done Raw
|
||||
// Interrupt Status
|
||||
#define AES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_DMAMIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_DMAMIS_DOUT 0x00000008 // Data Out DMA Done Masked
|
||||
// Interrupt Status
|
||||
#define AES_DMAMIS_DIN 0x00000004 // Data In DMA Done Masked
|
||||
// Interrupt Status
|
||||
#define AES_DMAMIS_COUT 0x00000002 // Context Out DMA Done Masked
|
||||
// Interrupt Status
|
||||
#define AES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the AES_O_DMAIC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define AES_DMAIC_DOUT 0x00000008 // Data Out DMA Done Interrupt
|
||||
// Clear
|
||||
#define AES_DMAIC_DIN 0x00000004 // Data In DMA Done Interrupt Clear
|
||||
#define AES_DMAIC_COUT 0x00000002 // Context Out DMA Done Masked
|
||||
// Interrupt Status
|
||||
#define AES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw
|
||||
// Interrupt Status
|
||||
|
||||
#endif // __HW_AES_H__
|
||||
|
|
@ -0,0 +1,462 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_can.h - Defines and macros used when accessing the CAN controllers.
|
||||
//
|
||||
// Copyright (c) 2006-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_CAN_H__
|
||||
#define __HW_CAN_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the CAN register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_O_CTL 0x00000000 // CAN Control
|
||||
#define CAN_O_STS 0x00000004 // CAN Status
|
||||
#define CAN_O_ERR 0x00000008 // CAN Error Counter
|
||||
#define CAN_O_BIT 0x0000000C // CAN Bit Timing
|
||||
#define CAN_O_INT 0x00000010 // CAN Interrupt
|
||||
#define CAN_O_TST 0x00000014 // CAN Test
|
||||
#define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler
|
||||
// Extension
|
||||
#define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request
|
||||
#define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask
|
||||
#define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1
|
||||
#define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2
|
||||
#define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1
|
||||
#define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2
|
||||
#define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control
|
||||
#define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1
|
||||
#define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2
|
||||
#define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1
|
||||
#define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2
|
||||
#define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request
|
||||
#define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask
|
||||
#define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1
|
||||
#define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2
|
||||
#define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1
|
||||
#define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2
|
||||
#define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control
|
||||
#define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1
|
||||
#define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2
|
||||
#define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1
|
||||
#define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2
|
||||
#define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1
|
||||
#define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2
|
||||
#define CAN_O_NWDA1 0x00000120 // CAN New Data 1
|
||||
#define CAN_O_NWDA2 0x00000124 // CAN New Data 2
|
||||
#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending
|
||||
#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending
|
||||
#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid
|
||||
#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
|
||||
#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
|
||||
#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
|
||||
#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
|
||||
#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
|
||||
#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable
|
||||
#define CAN_CTL_INIT 0x00000001 // Initialization
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_STS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_STS_BOFF 0x00000080 // Bus-Off Status
|
||||
#define CAN_STS_EWARN 0x00000040 // Warning Status
|
||||
#define CAN_STS_EPASS 0x00000020 // Error Passive
|
||||
#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully
|
||||
#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
|
||||
// Successfully
|
||||
#define CAN_STS_LEC_M 0x00000007 // Last Error Code
|
||||
#define CAN_STS_LEC_NONE 0x00000000 // No Error
|
||||
#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
|
||||
#define CAN_STS_LEC_FORM 0x00000002 // Format Error
|
||||
#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
|
||||
#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
|
||||
#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
|
||||
#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
|
||||
#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_ERR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_ERR_RP 0x00008000 // Received Error Passive
|
||||
#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter
|
||||
#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter
|
||||
#define CAN_ERR_REC_S 8
|
||||
#define CAN_ERR_TEC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_BIT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point
|
||||
#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point
|
||||
#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width
|
||||
#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler
|
||||
#define CAN_BIT_TSEG2_S 12
|
||||
#define CAN_BIT_TSEG1_S 8
|
||||
#define CAN_BIT_SJW_S 6
|
||||
#define CAN_BIT_BRP_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_INT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier
|
||||
#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
|
||||
#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_TST register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_TST_RX 0x00000080 // Receive Observation
|
||||
#define CAN_TST_TX_M 0x00000060 // Transmit Control
|
||||
#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control
|
||||
#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point
|
||||
#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low
|
||||
#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High
|
||||
#define CAN_TST_LBACK 0x00000010 // Loopback Mode
|
||||
#define CAN_TST_SILENT 0x00000008 // Silent Mode
|
||||
#define CAN_TST_BASIC 0x00000004 // Basic Mode
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_BRPE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension
|
||||
#define CAN_BRPE_BRPE_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag
|
||||
#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number
|
||||
#define CAN_IF1CRQ_MNUM_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read
|
||||
#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits
|
||||
#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits
|
||||
#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits
|
||||
#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
|
||||
#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data
|
||||
#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request
|
||||
#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
|
||||
#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
|
||||
#define CAN_IF1MSK1_IDMSK_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier
|
||||
#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction
|
||||
#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask
|
||||
#define CAN_IF1MSK2_IDMSK_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier
|
||||
#define CAN_IF1ARB1_ID_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid
|
||||
#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier
|
||||
#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction
|
||||
#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier
|
||||
#define CAN_IF1ARB2_ID_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data
|
||||
#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost
|
||||
#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending
|
||||
#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask
|
||||
#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
|
||||
#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable
|
||||
#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable
|
||||
#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request
|
||||
#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer
|
||||
#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code
|
||||
#define CAN_IF1MCTL_DLC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF1DA1_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF1DA2_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF1DB1_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF1DB2_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag
|
||||
#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number
|
||||
#define CAN_IF2CRQ_MNUM_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read
|
||||
#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits
|
||||
#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits
|
||||
#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits
|
||||
#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
|
||||
#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data
|
||||
#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request
|
||||
#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
|
||||
#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
|
||||
#define CAN_IF2MSK1_IDMSK_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier
|
||||
#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction
|
||||
#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask
|
||||
#define CAN_IF2MSK2_IDMSK_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier
|
||||
#define CAN_IF2ARB1_ID_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid
|
||||
#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier
|
||||
#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction
|
||||
#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier
|
||||
#define CAN_IF2ARB2_ID_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data
|
||||
#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost
|
||||
#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending
|
||||
#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask
|
||||
#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
|
||||
#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable
|
||||
#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable
|
||||
#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request
|
||||
#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer
|
||||
#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code
|
||||
#define CAN_IF2MCTL_DLC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF2DA1_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF2DA2_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF2DB1_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data
|
||||
#define CAN_IF2DB2_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits
|
||||
#define CAN_TXRQ1_TXRQST_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits
|
||||
#define CAN_TXRQ2_TXRQST_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_NWDA1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits
|
||||
#define CAN_NWDA1_NEWDAT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_NWDA2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits
|
||||
#define CAN_NWDA2_NEWDAT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_MSG1INT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
|
||||
#define CAN_MSG1INT_INTPND_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_MSG2INT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
|
||||
#define CAN_MSG2INT_INTPND_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
|
||||
#define CAN_MSG1VAL_MSGVAL_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
|
||||
#define CAN_MSG2VAL_MSGVAL_S 0
|
||||
|
||||
#endif // __HW_CAN_H__
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_ccm.h - Macros used when accessing the CCM hardware.
|
||||
//
|
||||
// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_CCM_H__
|
||||
#define __HW_CCM_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the EC register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CCM_O_CRCCTRL 0x00000400 // CRC Control
|
||||
#define CCM_O_CRCSEED 0x00000410 // CRC SEED/Context
|
||||
#define CCM_O_CRCDIN 0x00000414 // CRC Data Input
|
||||
#define CCM_O_CRCRSLTPP 0x00000418 // CRC Post Processing Result
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CCM_O_CRCCTRL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CCM_CRCCTRL_INIT_M 0x00006000 // CRC Initialization
|
||||
#define CCM_CRCCTRL_INIT_SEED 0x00000000 // Use the CRCSEED register context
|
||||
// as the starting value
|
||||
#define CCM_CRCCTRL_INIT_0 0x00004000 // Initialize to all '0s'
|
||||
#define CCM_CRCCTRL_INIT_1 0x00006000 // Initialize to all '1s'
|
||||
#define CCM_CRCCTRL_SIZE 0x00001000 // Input Data Size
|
||||
#define CCM_CRCCTRL_RESINV 0x00000200 // Result Inverse Enable
|
||||
#define CCM_CRCCTRL_OBR 0x00000100 // Output Reverse Enable
|
||||
#define CCM_CRCCTRL_BR 0x00000080 // Bit reverse enable
|
||||
#define CCM_CRCCTRL_ENDIAN_M 0x00000030 // Endian Control
|
||||
#define CCM_CRCCTRL_ENDIAN_SBHW 0x00000000 // Configuration unchanged. (B3,
|
||||
// B2, B1, B0)
|
||||
#define CCM_CRCCTRL_ENDIAN_SHW 0x00000010 // Bytes are swapped in half-words
|
||||
// but half-words are not swapped
|
||||
// (B2, B3, B0, B1)
|
||||
#define CCM_CRCCTRL_ENDIAN_SHWNB \
|
||||
0x00000020 // Half-words are swapped but bytes
|
||||
// are not swapped in half-word.
|
||||
// (B1, B0, B3, B2)
|
||||
#define CCM_CRCCTRL_ENDIAN_SBSW 0x00000030 // Bytes are swapped in half-words
|
||||
// and half-words are swapped. (B0,
|
||||
// B1, B2, B3)
|
||||
#define CCM_CRCCTRL_TYPE_M 0x0000000F // Operation Type
|
||||
#define CCM_CRCCTRL_TYPE_P8055 0x00000000 // Polynomial 0x8005
|
||||
#define CCM_CRCCTRL_TYPE_P1021 0x00000001 // Polynomial 0x1021
|
||||
#define CCM_CRCCTRL_TYPE_P4C11DB7 \
|
||||
0x00000002 // Polynomial 0x4C11DB7
|
||||
#define CCM_CRCCTRL_TYPE_P1EDC6F41 \
|
||||
0x00000003 // Polynomial 0x1EDC6F41
|
||||
#define CCM_CRCCTRL_TYPE_TCPCHKSUM \
|
||||
0x00000008 // TCP checksum
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CCM_O_CRCSEED register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CCM_CRCSEED_SEED_M 0xFFFFFFFF // SEED/Context Value
|
||||
#define CCM_CRCSEED_SEED_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CCM_O_CRCDIN register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CCM_CRCDIN_DATAIN_M 0xFFFFFFFF // Data Input
|
||||
#define CCM_CRCDIN_DATAIN_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the CCM_O_CRCRSLTPP
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define CCM_CRCRSLTPP_RSLTPP_M 0xFFFFFFFF // Post Processing Result
|
||||
#define CCM_CRCRSLTPP_RSLTPP_S 0
|
||||
|
||||
#endif // __HW_CCM_H__
|
||||
|
|
@ -0,0 +1,211 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_comp.h - Macros used when accessing the comparator hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_COMP_H__
|
||||
#define __HW_COMP_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Comparator register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked
|
||||
// Interrupt Status
|
||||
#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt
|
||||
// Status
|
||||
#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt
|
||||
// Enable
|
||||
#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference
|
||||
// Voltage Control
|
||||
#define COMP_O_ACSTAT0 0x00000020 // Analog Comparator Status 0
|
||||
#define COMP_O_ACCTL0 0x00000024 // Analog Comparator Control 0
|
||||
#define COMP_O_ACSTAT1 0x00000040 // Analog Comparator Status 1
|
||||
#define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1
|
||||
#define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2
|
||||
#define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2
|
||||
#define COMP_O_PP 0x00000FC0 // Analog Comparator Peripheral
|
||||
// Properties
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACMIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt
|
||||
// Status
|
||||
#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
|
||||
// Status
|
||||
#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
|
||||
// Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACRIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status
|
||||
#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status
|
||||
#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACINTEN register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable
|
||||
#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable
|
||||
#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACREFCTL
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable
|
||||
#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range
|
||||
#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref
|
||||
#define COMP_ACREFCTL_VREF_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable
|
||||
#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive
|
||||
#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+
|
||||
#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
|
||||
#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
|
||||
#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value
|
||||
#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense
|
||||
#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
|
||||
#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
|
||||
#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
|
||||
#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
|
||||
#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value
|
||||
#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense
|
||||
#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
|
||||
#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
|
||||
#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
|
||||
#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
|
||||
#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable
|
||||
#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive
|
||||
#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+
|
||||
#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
|
||||
#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
|
||||
#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value
|
||||
#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense
|
||||
#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
|
||||
#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
|
||||
#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
|
||||
#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
|
||||
#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value
|
||||
#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense
|
||||
#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
|
||||
#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
|
||||
#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
|
||||
#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
|
||||
#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable
|
||||
#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive
|
||||
#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+
|
||||
#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+
|
||||
#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference
|
||||
#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value
|
||||
#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense
|
||||
#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
|
||||
#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge
|
||||
#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge
|
||||
#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge
|
||||
#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value
|
||||
#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense
|
||||
#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
|
||||
#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge
|
||||
#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge
|
||||
#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
|
||||
#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the COMP_O_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present
|
||||
#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present
|
||||
#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present
|
||||
#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present
|
||||
#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present
|
||||
#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present
|
||||
|
||||
#endif // __HW_COMP_H__
|
||||
|
|
@ -0,0 +1,310 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_des.h - Macros used when accessing the DES hardware.
|
||||
//
|
||||
// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_DES_H__
|
||||
#define __HW_DES_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the DES register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_O_KEY3_L 0x00000000 // DES Key 3 LSW for 192-Bit Key
|
||||
#define DES_O_KEY3_H 0x00000004 // DES Key 3 MSW for 192-Bit Key
|
||||
#define DES_O_KEY2_L 0x00000008 // DES Key 2 LSW for 128-Bit Key
|
||||
#define DES_O_KEY2_H 0x0000000C // DES Key 2 MSW for 128-Bit Key
|
||||
#define DES_O_KEY1_L 0x00000010 // DES Key 1 LSW for 64-Bit Key
|
||||
#define DES_O_KEY1_H 0x00000014 // DES Key 1 MSW for 64-Bit Key
|
||||
#define DES_O_IV_L 0x00000018 // DES Initialization Vector
|
||||
#define DES_O_IV_H 0x0000001C // DES Initialization Vector
|
||||
#define DES_O_CTRL 0x00000020 // DES Control
|
||||
#define DES_O_LENGTH 0x00000024 // DES Cryptographic Data Length
|
||||
#define DES_O_DATA_L 0x00000028 // DES LSW Data RW
|
||||
#define DES_O_DATA_H 0x0000002C // DES MSW Data RW
|
||||
#define DES_O_REVISION 0x00000030 // DES Revision Number
|
||||
#define DES_O_SYSCONFIG 0x00000034 // DES System Configuration
|
||||
#define DES_O_SYSSTATUS 0x00000038 // DES System Status
|
||||
#define DES_O_IRQSTATUS 0x0000003C // DES Interrupt Status
|
||||
#define DES_O_IRQENABLE 0x00000040 // DES Interrupt Enable
|
||||
#define DES_O_DIRTYBITS 0x00000044 // DES Dirty Bits
|
||||
#define DES_O_DMAIM 0xFFFF8030 // DES DMA Interrupt Mask
|
||||
#define DES_O_DMARIS 0xFFFF8034 // DES DMA Raw Interrupt Status
|
||||
#define DES_O_DMAMIS 0xFFFF8038 // DES DMA Masked Interrupt Status
|
||||
#define DES_O_DMAIC 0xFFFF803C // DES DMA Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_KEY3_L register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_KEY3_L_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define DES_KEY3_L_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_KEY3_H register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_KEY3_H_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define DES_KEY3_H_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_KEY2_L register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_KEY2_L_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define DES_KEY2_L_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_KEY2_H register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_KEY2_H_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define DES_KEY2_H_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_KEY1_L register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_KEY1_L_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define DES_KEY1_L_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_KEY1_H register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_KEY1_H_KEY_M 0xFFFFFFFF // Key Data
|
||||
#define DES_KEY1_H_KEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_IV_L register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_IV_L_M 0xFFFFFFFF // Initialization vector for CBC,
|
||||
// CFB modes (LSW)
|
||||
#define DES_IV_L_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_IV_H register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_IV_H_M 0xFFFFFFFF // Initialization vector for CBC,
|
||||
// CFB modes (MSW)
|
||||
#define DES_IV_H_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_CTRL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_CTRL_CONTEXT 0x80000000 // If 1, this read-only status bit
|
||||
// indicates that the context data
|
||||
// registers can be overwritten and
|
||||
// the host is permitted to write
|
||||
// the next context
|
||||
#define DES_CTRL_MODE_M 0x00000030 // Select CBC, ECB or CFB mode0x0:
|
||||
// ECB mode0x1: CBC mode0x2: CFB
|
||||
// mode0x3: reserved
|
||||
#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES
|
||||
// encryption/decryption
|
||||
#define DES_CTRL_DIRECTION 0x00000004 // Select encryption/decryption
|
||||
// 0x0: decryption is selected0x1:
|
||||
// Encryption is selected
|
||||
#define DES_CTRL_INPUT_READY 0x00000002 // When 1, ready to encrypt/decrypt
|
||||
// data
|
||||
#define DES_CTRL_OUTPUT_READY 0x00000001 // When 1, Data decrypted/encrypted
|
||||
// ready
|
||||
#define DES_CTRL_MODE_S 4
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_LENGTH register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_LENGTH_M 0xFFFFFFFF // Cryptographic data length in
|
||||
// bytes for all modes
|
||||
#define DES_LENGTH_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_DATA_L register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_DATA_L_M 0xFFFFFFFF // Data for encryption/decryption,
|
||||
// LSW
|
||||
#define DES_DATA_L_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_DATA_H register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_DATA_H_M 0xFFFFFFFF // Data for encryption/decryption,
|
||||
// MSW
|
||||
#define DES_DATA_H_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_REVISION register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_REVISION_M 0xFFFFFFFF // Revision number
|
||||
#define DES_REVISION_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_SYSCONFIG
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
|
||||
0x00000080 // DMA Request Context In Enable
|
||||
#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
|
||||
0x00000040 // DMA Request Data Out Enable
|
||||
#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
|
||||
0x00000020 // DMA Request Data In Enable
|
||||
#define DES_SYSCONFIG_SIDLE_M 0x0000000C // Sidle mode
|
||||
#define DES_SYSCONFIG_SIDLE_FORCE \
|
||||
0x00000000 // Force-idle mode
|
||||
#define DES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_SYSSTATUS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_IRQSTATUS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_IRQSTATUS_DATA_OUT 0x00000004 // This bit indicates data output
|
||||
// interrupt is active and triggers
|
||||
// the interrupt output
|
||||
#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input
|
||||
// interrupt is active and triggers
|
||||
// the interrupt output
|
||||
#define DES_IRQSTATUS_CONTEX_IN 0x00000001 // This bit indicates context
|
||||
// interrupt is active and triggers
|
||||
// the interrupt output
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_IRQENABLE
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_IRQENABLE_M_DATA_OUT \
|
||||
0x00000004 // If this bit is set to 1 the data
|
||||
// output interrupt is enabled
|
||||
#define DES_IRQENABLE_M_DATA_IN 0x00000002 // If this bit is set to 1 the data
|
||||
// input interrupt is enabled
|
||||
#define DES_IRQENABLE_M_CONTEX_IN \
|
||||
0x00000001 // If this bit is set to 1 the
|
||||
// context interrupt is enabled
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_DIRTYBITS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_DIRTYBITS_S_DIRTY 0x00000002 // This bit is set to 1 by the
|
||||
// module if any of the DES_*
|
||||
// registers is written
|
||||
#define DES_DIRTYBITS_S_ACCESS 0x00000001 // This bit is set to 1 by the
|
||||
// module if any of the DES_*
|
||||
// registers is read
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_DMAIM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_DMAIM_DOUT 0x00000004 // Data Out DMA Done Interrupt Mask
|
||||
#define DES_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask
|
||||
#define DES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt
|
||||
// Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_DMARIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_DMARIS_DOUT 0x00000004 // Data Out DMA Done Raw Interrupt
|
||||
// Status
|
||||
#define DES_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt
|
||||
// Status
|
||||
#define DES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_DMAMIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_DMAMIS_DOUT 0x00000004 // Data Out DMA Done Masked
|
||||
// Interrupt Status
|
||||
#define DES_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked
|
||||
// Interrupt Status
|
||||
#define DES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the DES_O_DMAIC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define DES_DMAIC_DOUT 0x00000004 // Data Out DMA Done Interrupt
|
||||
// Clear
|
||||
#define DES_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear
|
||||
#define DES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw
|
||||
// Interrupt Status
|
||||
|
||||
#endif // __HW_DES_H__
|
||||
|
|
@ -0,0 +1,251 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_eeprom.h - Macros used when accessing the EEPROM controller.
|
||||
//
|
||||
// Copyright (c) 2011-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_EEPROM_H__
|
||||
#define __HW_EEPROM_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the EEPROM register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information
|
||||
#define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block
|
||||
#define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset
|
||||
#define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write
|
||||
#define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment
|
||||
#define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status
|
||||
#define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and
|
||||
// Status
|
||||
#define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock
|
||||
#define EEPROM_EEPROT 0x400AF030 // EEPROM Protection
|
||||
#define EEPROM_EEPASS0 0x400AF034 // EEPROM Password
|
||||
#define EEPROM_EEPASS1 0x400AF038 // EEPROM Password
|
||||
#define EEPROM_EEPASS2 0x400AF03C // EEPROM Password
|
||||
#define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt
|
||||
#define EEPROM_EEHIDE0 0x400AF050 // EEPROM Block Hide 0
|
||||
#define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide
|
||||
#define EEPROM_EEHIDE1 0x400AF054 // EEPROM Block Hide 1
|
||||
#define EEPROM_EEHIDE2 0x400AF058 // EEPROM Block Hide 2
|
||||
#define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase
|
||||
#define EEPROM_PP 0x400AFFC0 // EEPROM Peripheral Properties
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EESIZE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words
|
||||
#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks
|
||||
#define EEPROM_EESIZE_WORDCNT_S 0
|
||||
#define EEPROM_EESIZE_BLKCNT_S 16
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block
|
||||
#define EEPROM_EEBLOCK_BLOCK_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEOFFSET
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEOFFSET_OFFSET_M \
|
||||
0x0000000F // Current Address Offset
|
||||
#define EEPROM_EEOFFSET_OFFSET_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EERDWR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data
|
||||
#define EEPROM_EERDWR_VALUE_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EERDWRINC
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EERDWRINC_VALUE_M \
|
||||
0xFFFFFFFF // EEPROM Read or Write Data with
|
||||
// Increment
|
||||
#define EEPROM_EERDWRINC_VALUE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEDONE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working
|
||||
#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase
|
||||
#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy
|
||||
#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission
|
||||
#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EESUPP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried
|
||||
#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEUNLOCK
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEUNLOCK_UNLOCK_M \
|
||||
0xFFFFFFFF // EEPROM Unlock
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEPROT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control
|
||||
#define EEPROM_EEPROT_PROT_RWNPW \
|
||||
0x00000000 // This setting is the default. If
|
||||
// there is no password, the block
|
||||
// is not protected and is readable
|
||||
// and writable
|
||||
#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the
|
||||
// block is readable or writable
|
||||
// only when unlocked
|
||||
#define EEPROM_EEPROT_PROT_RONPW \
|
||||
0x00000002 // If there is no password, the
|
||||
// block is readable, not writable
|
||||
#define EEPROM_EEPROT_ACC 0x00000008 // Access Control
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password
|
||||
#define EEPROM_EEPASS0_PASS_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password
|
||||
#define EEPROM_EEPASS1_PASS_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password
|
||||
#define EEPROM_EEPASS2_PASS_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEINT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEHIDE0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEHIDE0_HN_M 0xFFFFFFFE // Hide Block
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEHIDE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEHIDE1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEHIDE1_HN_M 0xFFFFFFFF // Hide Block
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEHIDE2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEHIDE2_HN_M 0xFFFFFFFF // Hide Block
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_EEDBGME register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase
|
||||
#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key
|
||||
#define EEPROM_EEDBGME_KEY_S 16
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EEPROM_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EEPROM_PP_SIZE_M 0x0000FFFF // EEPROM Size
|
||||
#define EEPROM_PP_SIZE_64 0x00000000 // 64 bytes of EEPROM
|
||||
#define EEPROM_PP_SIZE_128 0x00000001 // 128 bytes of EEPROM
|
||||
#define EEPROM_PP_SIZE_256 0x00000003 // 256 bytes of EEPROM
|
||||
#define EEPROM_PP_SIZE_512 0x00000007 // 512 bytes of EEPROM
|
||||
#define EEPROM_PP_SIZE_1K 0x0000000F // 1 KB of EEPROM
|
||||
#define EEPROM_PP_SIZE_2K 0x0000001F // 2 KB of EEPROM
|
||||
#define EEPROM_PP_SIZE_3K 0x0000003F // 3 KB of EEPROM
|
||||
#define EEPROM_PP_SIZE_4K 0x0000007F // 4 KB of EEPROM
|
||||
#define EEPROM_PP_SIZE_5K 0x000000FF // 5 KB of EEPROM
|
||||
#define EEPROM_PP_SIZE_6K 0x000001FF // 6 KB of EEPROM
|
||||
#define EEPROM_PP_SIZE_S 0
|
||||
|
||||
#endif // __HW_EEPROM_H__
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,933 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_epi.h - Macros for use in accessing the EPI registers.
|
||||
//
|
||||
// Copyright (c) 2008-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_EPI_H__
|
||||
#define __HW_EPI_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the External Peripheral Interface register
|
||||
// offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_O_CFG 0x00000000 // EPI Configuration
|
||||
#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate
|
||||
#define EPI_O_BAUD2 0x00000008 // EPI Main Baud Rate
|
||||
#define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration
|
||||
#define EPI_O_GPCFG 0x00000010 // EPI General-Purpose
|
||||
// Configuration
|
||||
#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration
|
||||
#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration
|
||||
#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2
|
||||
#define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2
|
||||
#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map
|
||||
#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0
|
||||
#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0
|
||||
#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0
|
||||
#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1
|
||||
#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1
|
||||
#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1
|
||||
#define EPI_O_STAT 0x00000060 // EPI Status
|
||||
#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count
|
||||
#define EPI_O_READFIFO0 0x00000070 // EPI Read FIFO
|
||||
#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1
|
||||
#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2
|
||||
#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3
|
||||
#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4
|
||||
#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5
|
||||
#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6
|
||||
#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7
|
||||
#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects
|
||||
#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count
|
||||
#define EPI_O_DMATXCNT 0x00000208 // EPI DMA Transmit Count
|
||||
#define EPI_O_IM 0x00000210 // EPI Interrupt Mask
|
||||
#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status
|
||||
#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status
|
||||
#define EPI_O_EISC 0x0000021C // EPI Error and Interrupt Status
|
||||
// and Clear
|
||||
#define EPI_O_HB8CFG3 0x00000308 // EPI Host-Bus 8 Configuration 3
|
||||
#define EPI_O_HB16CFG3 0x00000308 // EPI Host-Bus 16 Configuration 3
|
||||
#define EPI_O_HB16CFG4 0x0000030C // EPI Host-Bus 16 Configuration 4
|
||||
#define EPI_O_HB8CFG4 0x0000030C // EPI Host-Bus 8 Configuration 4
|
||||
#define EPI_O_HB8TIME 0x00000310 // EPI Host-Bus 8 Timing Extension
|
||||
#define EPI_O_HB16TIME 0x00000310 // EPI Host-Bus 16 Timing Extension
|
||||
#define EPI_O_HB8TIME2 0x00000314 // EPI Host-Bus 8 Timing Extension
|
||||
#define EPI_O_HB16TIME2 0x00000314 // EPI Host-Bus 16 Timing Extension
|
||||
#define EPI_O_HB16TIME3 0x00000318 // EPI Host-Bus 16 Timing Extension
|
||||
#define EPI_O_HB8TIME3 0x00000318 // EPI Host-Bus 8 Timing Extension
|
||||
#define EPI_O_HB8TIME4 0x0000031C // EPI Host-Bus 8 Timing Extension
|
||||
#define EPI_O_HB16TIME4 0x0000031C // EPI Host-Bus 16 Timing Extension
|
||||
#define EPI_O_HBPSRAM 0x00000360 // EPI Host-Bus PSRAM
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_CFG register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_CFG_INTDIV 0x00000100 // Integer Clock Divider Enable
|
||||
#define EPI_CFG_BLKEN 0x00000010 // Block Enable
|
||||
#define EPI_CFG_MODE_M 0x0000000F // Mode Select
|
||||
#define EPI_CFG_MODE_NONE 0x00000000 // General Purpose
|
||||
#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM
|
||||
#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8)
|
||||
#define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_BAUD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1
|
||||
#define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0
|
||||
#define EPI_BAUD_COUNT1_S 16
|
||||
#define EPI_BAUD_COUNT0_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_BAUD2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_BAUD2_COUNT1_M 0xFFFF0000 // CS3n Baud Rate Counter 1
|
||||
#define EPI_BAUD2_COUNT0_M 0x0000FFFF // CS2n Baud Rate Counter 0
|
||||
#define EPI_BAUD2_COUNT1_S 16
|
||||
#define EPI_BAUD2_COUNT0_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB16CFG register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB16CFG_CLKGATE 0x80000000 // Clock Gated
|
||||
#define EPI_HB16CFG_CLKGATEI 0x40000000 // Clock Gated Idle
|
||||
#define EPI_HB16CFG_CLKINV 0x20000000 // Invert Output Clock Enable
|
||||
#define EPI_HB16CFG_RDYEN 0x10000000 // Input Ready Enable
|
||||
#define EPI_HB16CFG_IRDYINV 0x08000000 // Input Ready Invert
|
||||
#define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable
|
||||
#define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable
|
||||
#define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity
|
||||
#define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity
|
||||
#define EPI_HB16CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity
|
||||
#define EPI_HB16CFG_WRCRE 0x00040000 // PSRAM Configuration Register
|
||||
// Write
|
||||
#define EPI_HB16CFG_RDCRE 0x00020000 // PSRAM Configuration Register
|
||||
// Read
|
||||
#define EPI_HB16CFG_BURST 0x00010000 // Burst Mode
|
||||
#define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
|
||||
#define EPI_HB16CFG_WRWS_M 0x000000C0 // Write Wait States
|
||||
#define EPI_HB16CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
|
||||
#define EPI_HB16CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
|
||||
#define EPI_HB16CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
|
||||
#define EPI_HB16CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
|
||||
#define EPI_HB16CFG_RDWS_M 0x00000030 // Read Wait States
|
||||
#define EPI_HB16CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
|
||||
#define EPI_HB16CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
|
||||
#define EPI_HB16CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
|
||||
#define EPI_HB16CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
|
||||
#define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration
|
||||
#define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode
|
||||
#define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
|
||||
#define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0]
|
||||
#define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0]
|
||||
#define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0]
|
||||
#define EPI_HB16CFG_MAXWAIT_S 8
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_GPCFG register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin
|
||||
#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated
|
||||
#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame
|
||||
#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count
|
||||
#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes
|
||||
#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size
|
||||
#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address
|
||||
#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide
|
||||
#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size
|
||||
// cannot be used with 24-bit data
|
||||
#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size
|
||||
// cannot be used with data sizes
|
||||
// other than 8
|
||||
#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus
|
||||
#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7)
|
||||
#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15)
|
||||
#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23)
|
||||
#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31)
|
||||
#define EPI_GPCFG_FRMCNT_S 22
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // EPI Frequency Range
|
||||
#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz
|
||||
#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz
|
||||
#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz
|
||||
#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter
|
||||
#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode
|
||||
#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM
|
||||
#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB)
|
||||
#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB)
|
||||
#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB)
|
||||
#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB)
|
||||
#define EPI_SDRAMCFG_RFSH_S 16
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB8CFG register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB8CFG_CLKGATE 0x80000000 // Clock Gated
|
||||
#define EPI_HB8CFG_CLKGATEI 0x40000000 // Clock Gated when Idle
|
||||
#define EPI_HB8CFG_CLKINV 0x20000000 // Invert Output Clock Enable
|
||||
#define EPI_HB8CFG_RDYEN 0x10000000 // Input Ready Enable
|
||||
#define EPI_HB8CFG_IRDYINV 0x08000000 // Input Ready Invert
|
||||
#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable
|
||||
#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable
|
||||
#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity
|
||||
#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity
|
||||
#define EPI_HB8CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity
|
||||
#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
|
||||
#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States
|
||||
#define EPI_HB8CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
|
||||
#define EPI_HB8CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
|
||||
#define EPI_HB8CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
|
||||
#define EPI_HB8CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
|
||||
#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States
|
||||
#define EPI_HB8CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
|
||||
#define EPI_HB8CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
|
||||
#define EPI_HB8CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
|
||||
#define EPI_HB8CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
|
||||
#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode
|
||||
#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0]
|
||||
#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0]
|
||||
#define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0]
|
||||
#define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0]
|
||||
#define EPI_HB8CFG_MAXWAIT_S 8
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB8CFG2_CSCFGEXT 0x08000000 // Chip Select Extended
|
||||
// Configuration
|
||||
#define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and
|
||||
// Multiple Sub-Mode Configuration
|
||||
// enable
|
||||
#define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration
|
||||
#define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration
|
||||
#define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration
|
||||
#define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
|
||||
#define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
|
||||
#define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity
|
||||
#define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity
|
||||
#define EPI_HB8CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity
|
||||
#define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States
|
||||
#define EPI_HB8CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
|
||||
#define EPI_HB8CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
|
||||
#define EPI_HB8CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
|
||||
#define EPI_HB8CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
|
||||
#define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States
|
||||
#define EPI_HB8CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
|
||||
#define EPI_HB8CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
|
||||
#define EPI_HB8CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
|
||||
#define EPI_HB8CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
|
||||
#define EPI_HB8CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode
|
||||
#define EPI_HB8CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0]
|
||||
#define EPI_HB8CFG2_MODE_AD 0x00000001 // ADNONMUX - D[7:0]
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB16CFG2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB16CFG2_CSCFGEXT 0x08000000 // Chip Select Extended
|
||||
// Configuration
|
||||
#define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and
|
||||
// Multiple Sub-Mode Configuration
|
||||
// enable
|
||||
#define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration
|
||||
#define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration
|
||||
#define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration
|
||||
#define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
|
||||
#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
|
||||
#define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity
|
||||
#define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity
|
||||
#define EPI_HB16CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity
|
||||
#define EPI_HB16CFG2_WRCRE 0x00040000 // CS1n PSRAM Configuration
|
||||
// Register Write
|
||||
#define EPI_HB16CFG2_RDCRE 0x00020000 // CS1n PSRAM Configuration
|
||||
// Register Read
|
||||
#define EPI_HB16CFG2_BURST 0x00010000 // CS1n Burst Mode
|
||||
#define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States
|
||||
#define EPI_HB16CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
|
||||
#define EPI_HB16CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
|
||||
#define EPI_HB16CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
|
||||
#define EPI_HB16CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
|
||||
#define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States
|
||||
#define EPI_HB16CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
|
||||
#define EPI_HB16CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
|
||||
#define EPI_HB16CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
|
||||
#define EPI_HB16CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
|
||||
#define EPI_HB16CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode
|
||||
#define EPI_HB16CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
|
||||
#define EPI_HB16CFG2_MODE_AD 0x00000001 // ADNONMUX - D[15:0]
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_ADDRMAP_ECSZ_M 0x00000C00 // External Code Size
|
||||
#define EPI_ADDRMAP_ECSZ_256B 0x00000000 // 256 bytes; lower address range:
|
||||
// 0x00 to 0xFF
|
||||
#define EPI_ADDRMAP_ECSZ_64KB 0x00000400 // 64 KB; lower address range:
|
||||
// 0x0000 to 0xFFFF
|
||||
#define EPI_ADDRMAP_ECSZ_16MB 0x00000800 // 16 MB; lower address range:
|
||||
// 0x00.0000 to 0xFF.FFFF
|
||||
#define EPI_ADDRMAP_ECSZ_256MB 0x00000C00 // 256MB; lower address range:
|
||||
// 0x000.0000 to 0x0FFF.FFFF
|
||||
#define EPI_ADDRMAP_ECADR_M 0x00000300 // External Code Address
|
||||
#define EPI_ADDRMAP_ECADR_NONE 0x00000000 // Not mapped
|
||||
#define EPI_ADDRMAP_ECADR_1000 0x00000100 // At 0x1000.0000
|
||||
#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size
|
||||
#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range:
|
||||
// 0x00 to 0xFF
|
||||
#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range:
|
||||
// 0x0000 to 0xFFFF
|
||||
#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range:
|
||||
// 0x00.0000 to 0xFF.FFFF
|
||||
#define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range:
|
||||
// 0x000.0000 to 0xFFF.FFFF
|
||||
#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address
|
||||
#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped
|
||||
#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000
|
||||
#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000
|
||||
#define EPI_ADDRMAP_EPADR_HBQS 0x00000030 // Only to be used with Host Bus
|
||||
// quad chip select. In quad chip
|
||||
// select mode, CS2n maps to
|
||||
// 0xA000.0000 and CS3n maps to
|
||||
// 0xC000.0000
|
||||
#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size
|
||||
#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range:
|
||||
// 0x00 to 0xFF
|
||||
#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range:
|
||||
// 0x0000 to 0xFFFF
|
||||
#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range:
|
||||
// 0x00.0000 to 0xFF.FFFF
|
||||
#define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range:
|
||||
// 0x000.0000 to 0xFFF.FFFF
|
||||
#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address
|
||||
#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped
|
||||
#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000
|
||||
#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000
|
||||
#define EPI_ADDRMAP_ERADR_HBQS 0x00000003 // Only to be used with Host Bus
|
||||
// quad chip select. In quad chip
|
||||
// select mode, CS0n maps to
|
||||
// 0x6000.0000 and CS1n maps to
|
||||
// 0x8000.0000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size
|
||||
#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits)
|
||||
#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits)
|
||||
#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_RADDR0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_RADDR0_ADDR_M 0xFFFFFFFF // Current Address
|
||||
#define EPI_RADDR0_ADDR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count
|
||||
#define EPI_RPSTD0_POSTCNT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size
|
||||
#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits)
|
||||
#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits)
|
||||
#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_RADDR1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_RADDR1_ADDR_M 0xFFFFFFFF // Current Address
|
||||
#define EPI_RADDR1_ADDR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count
|
||||
#define EPI_RPSTD1_POSTCNT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_STAT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full
|
||||
#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty
|
||||
#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence
|
||||
#define EPI_STAT_WBUSY 0x00000020 // Write Busy
|
||||
#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy
|
||||
#define EPI_STAT_ACTIVE 0x00000001 // Register Active
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_RFIFOCNT_COUNT_M 0x0000000F // FIFO Count
|
||||
#define EPI_RFIFOCNT_COUNT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_READFIFO0
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_READFIFO0_DATA_M 0xFFFFFFFF // Reads Data
|
||||
#define EPI_READFIFO0_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_READFIFO1
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data
|
||||
#define EPI_READFIFO1_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_READFIFO2
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data
|
||||
#define EPI_READFIFO2_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_READFIFO3
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data
|
||||
#define EPI_READFIFO3_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_READFIFO4
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data
|
||||
#define EPI_READFIFO4_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_READFIFO5
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data
|
||||
#define EPI_READFIFO5_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_READFIFO6
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data
|
||||
#define EPI_READFIFO6_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_READFIFO7
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data
|
||||
#define EPI_READFIFO7_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error
|
||||
#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error
|
||||
#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO
|
||||
#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Interrupt is triggered while
|
||||
// WRFIFO is empty.
|
||||
#define EPI_FIFOLVL_WRFIFO_2 0x00000020 // Interrupt is triggered until
|
||||
// there are only two slots
|
||||
// available. Thus, trigger is
|
||||
// deasserted when there are two
|
||||
// WRFIFO entries present. This
|
||||
// configuration is optimized for
|
||||
// bursts of 2
|
||||
#define EPI_FIFOLVL_WRFIFO_1 0x00000030 // Interrupt is triggered until
|
||||
// there is one WRFIFO entry
|
||||
// available. This configuration
|
||||
// expects only single writes
|
||||
#define EPI_FIFOLVL_WRFIFO_NFULL \
|
||||
0x00000040 // Trigger interrupt when WRFIFO is
|
||||
// not full, meaning trigger will
|
||||
// continue to assert until there
|
||||
// are four entries in the WRFIFO
|
||||
#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO
|
||||
#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty
|
||||
#define EPI_FIFOLVL_RDFIFO_1 0x00000001 // Trigger when there are 1 or more
|
||||
// entries in the NBRFIFO
|
||||
#define EPI_FIFOLVL_RDFIFO_2 0x00000002 // Trigger when there are 2 or more
|
||||
// entries in the NBRFIFO
|
||||
#define EPI_FIFOLVL_RDFIFO_4 0x00000003 // Trigger when there are 4 or more
|
||||
// entries in the NBRFIFO
|
||||
#define EPI_FIFOLVL_RDFIFO_6 0x00000004 // Trigger when there are 6 or more
|
||||
// entries in the NBRFIFO
|
||||
#define EPI_FIFOLVL_RDFIFO_7 0x00000005 // Trigger when there are 7 or more
|
||||
// entries in the NBRFIFO
|
||||
#define EPI_FIFOLVL_RDFIFO_8 0x00000006 // Trigger when there are 8 entries
|
||||
// in the NBRFIFO
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions
|
||||
#define EPI_WFIFOCNT_WTAV_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_DMATXCNT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_DMATXCNT_TXCNT_M 0x0000FFFF // DMA Count
|
||||
#define EPI_DMATXCNT_TXCNT_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_IM_DMAWRIM 0x00000010 // Write uDMA Interrupt Mask
|
||||
#define EPI_IM_DMARDIM 0x00000008 // Read uDMA Interrupt Mask
|
||||
#define EPI_IM_WRIM 0x00000004 // Write FIFO Empty Interrupt Mask
|
||||
#define EPI_IM_RDIM 0x00000002 // Read FIFO Full Interrupt Mask
|
||||
#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_RIS_DMAWRRIS 0x00000010 // Write uDMA Raw Interrupt Status
|
||||
#define EPI_RIS_DMARDRIS 0x00000008 // Read uDMA Raw Interrupt Status
|
||||
#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status
|
||||
#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status
|
||||
#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_MIS_DMAWRMIS 0x00000010 // Write uDMA Masked Interrupt
|
||||
// Status
|
||||
#define EPI_MIS_DMARDMIS 0x00000008 // Read uDMA Masked Interrupt
|
||||
// Status
|
||||
#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status
|
||||
#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status
|
||||
#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_EISC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_EISC_DMAWRIC 0x00000010 // Write uDMA Interrupt Clear
|
||||
#define EPI_EISC_DMARDIC 0x00000008 // Read uDMA Interrupt Clear
|
||||
#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error
|
||||
#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error
|
||||
#define EPI_EISC_TOUT 0x00000001 // Timeout Error
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB8CFG3 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB8CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity
|
||||
#define EPI_HB8CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity
|
||||
#define EPI_HB8CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity
|
||||
#define EPI_HB8CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States
|
||||
#define EPI_HB8CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
|
||||
#define EPI_HB8CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
|
||||
#define EPI_HB8CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
|
||||
#define EPI_HB8CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
|
||||
#define EPI_HB8CFG3_RDWS_M 0x00000030 // CS2n Read Wait States
|
||||
#define EPI_HB8CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
|
||||
#define EPI_HB8CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
|
||||
#define EPI_HB8CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
|
||||
#define EPI_HB8CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
|
||||
#define EPI_HB8CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode
|
||||
#define EPI_HB8CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0]
|
||||
#define EPI_HB8CFG3_MODE_AD 0x00000001 // ADNONMUX - D[7:0]
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB16CFG3 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB16CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity
|
||||
#define EPI_HB16CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity
|
||||
#define EPI_HB16CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity
|
||||
#define EPI_HB16CFG3_WRCRE 0x00040000 // CS2n PSRAM Configuration
|
||||
// Register Write
|
||||
#define EPI_HB16CFG3_RDCRE 0x00020000 // CS2n PSRAM Configuration
|
||||
// Register Read
|
||||
#define EPI_HB16CFG3_BURST 0x00010000 // CS2n Burst Mode
|
||||
#define EPI_HB16CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States
|
||||
#define EPI_HB16CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
|
||||
#define EPI_HB16CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
|
||||
#define EPI_HB16CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
|
||||
#define EPI_HB16CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
|
||||
#define EPI_HB16CFG3_RDWS_M 0x00000030 // CS2n Read Wait States
|
||||
#define EPI_HB16CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
|
||||
#define EPI_HB16CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
|
||||
#define EPI_HB16CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
|
||||
#define EPI_HB16CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
|
||||
#define EPI_HB16CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode
|
||||
#define EPI_HB16CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
|
||||
#define EPI_HB16CFG3_MODE_AD 0x00000001 // ADNONMUX - D[15:0]
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB16CFG4 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB16CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity
|
||||
#define EPI_HB16CFG4_RDHIGH 0x00100000 // CS3n READ Strobe Polarity
|
||||
#define EPI_HB16CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity
|
||||
#define EPI_HB16CFG4_WRCRE 0x00040000 // CS3n PSRAM Configuration
|
||||
// Register Write
|
||||
#define EPI_HB16CFG4_RDCRE 0x00020000 // CS3n PSRAM Configuration
|
||||
// Register Read
|
||||
#define EPI_HB16CFG4_BURST 0x00010000 // CS3n Burst Mode
|
||||
#define EPI_HB16CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States
|
||||
#define EPI_HB16CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
|
||||
#define EPI_HB16CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
|
||||
#define EPI_HB16CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
|
||||
#define EPI_HB16CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
|
||||
#define EPI_HB16CFG4_RDWS_M 0x00000030 // CS3n Read Wait States
|
||||
#define EPI_HB16CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
|
||||
#define EPI_HB16CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
|
||||
#define EPI_HB16CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
|
||||
#define EPI_HB16CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
|
||||
#define EPI_HB16CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode
|
||||
#define EPI_HB16CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
|
||||
#define EPI_HB16CFG4_MODE_AD 0x00000001 // ADNONMUX - D[15:0]
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB8CFG4 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB8CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity
|
||||
#define EPI_HB8CFG4_RDHIGH 0x00100000 // CS2n READ Strobe Polarity
|
||||
#define EPI_HB8CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity
|
||||
#define EPI_HB8CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States
|
||||
#define EPI_HB8CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
|
||||
#define EPI_HB8CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
|
||||
#define EPI_HB8CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
|
||||
#define EPI_HB8CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
|
||||
#define EPI_HB8CFG4_RDWS_M 0x00000030 // CS3n Read Wait States
|
||||
#define EPI_HB8CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
|
||||
#define EPI_HB8CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
|
||||
#define EPI_HB8CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
|
||||
#define EPI_HB8CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
|
||||
#define EPI_HB8CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode
|
||||
#define EPI_HB8CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0]
|
||||
#define EPI_HB8CFG4_MODE_AD 0x00000001 // ADNONMUX - D[7:0]
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB8TIME register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB8TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay
|
||||
#define EPI_HB8TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture
|
||||
// Width
|
||||
#define EPI_HB8TIME_WRWSM 0x00000010 // Write Wait State Minus One
|
||||
#define EPI_HB8TIME_RDWSM 0x00000001 // Read Wait State Minus One
|
||||
#define EPI_HB8TIME_IRDYDLY_S 24
|
||||
#define EPI_HB8TIME_CAPWIDTH_S 12
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB16TIME register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB16TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay
|
||||
#define EPI_HB16TIME_PSRAMSZ_M 0x00070000 // PSRAM Row Size
|
||||
#define EPI_HB16TIME_PSRAMSZ_0 0x00000000 // No row size limitation
|
||||
#define EPI_HB16TIME_PSRAMSZ_128B \
|
||||
0x00010000 // 128 B
|
||||
#define EPI_HB16TIME_PSRAMSZ_256B \
|
||||
0x00020000 // 256 B
|
||||
#define EPI_HB16TIME_PSRAMSZ_512B \
|
||||
0x00030000 // 512 B
|
||||
#define EPI_HB16TIME_PSRAMSZ_1KB \
|
||||
0x00040000 // 1024 B
|
||||
#define EPI_HB16TIME_PSRAMSZ_2KB \
|
||||
0x00050000 // 2048 B
|
||||
#define EPI_HB16TIME_PSRAMSZ_4KB \
|
||||
0x00060000 // 4096 B
|
||||
#define EPI_HB16TIME_PSRAMSZ_8KB \
|
||||
0x00070000 // 8192 B
|
||||
#define EPI_HB16TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture
|
||||
// Width
|
||||
#define EPI_HB16TIME_WRWSM 0x00000010 // Write Wait State Minus One
|
||||
#define EPI_HB16TIME_RDWSM 0x00000001 // Read Wait State Minus One
|
||||
#define EPI_HB16TIME_IRDYDLY_S 24
|
||||
#define EPI_HB16TIME_CAPWIDTH_S 12
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB8TIME2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB8TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay
|
||||
#define EPI_HB8TIME2_CAPWIDTH_M 0x00003000 // CS1n Inter-transfer Capture
|
||||
// Width
|
||||
#define EPI_HB8TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One
|
||||
#define EPI_HB8TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One
|
||||
#define EPI_HB8TIME2_IRDYDLY_S 24
|
||||
#define EPI_HB8TIME2_CAPWIDTH_S 12
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB16TIME2
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB16TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay
|
||||
#define EPI_HB16TIME2_PSRAMSZ_M 0x00070000 // PSRAM Row Size
|
||||
#define EPI_HB16TIME2_PSRAMSZ_0 0x00000000 // No row size limitation
|
||||
#define EPI_HB16TIME2_PSRAMSZ_128B \
|
||||
0x00010000 // 128 B
|
||||
#define EPI_HB16TIME2_PSRAMSZ_256B \
|
||||
0x00020000 // 256 B
|
||||
#define EPI_HB16TIME2_PSRAMSZ_512B \
|
||||
0x00030000 // 512 B
|
||||
#define EPI_HB16TIME2_PSRAMSZ_1KB \
|
||||
0x00040000 // 1024 B
|
||||
#define EPI_HB16TIME2_PSRAMSZ_2KB \
|
||||
0x00050000 // 2048 B
|
||||
#define EPI_HB16TIME2_PSRAMSZ_4KB \
|
||||
0x00060000 // 4096 B
|
||||
#define EPI_HB16TIME2_PSRAMSZ_8KB \
|
||||
0x00070000 // 8192 B
|
||||
#define EPI_HB16TIME2_CAPWIDTH_M \
|
||||
0x00003000 // CS1n Inter-transfer Capture
|
||||
// Width
|
||||
#define EPI_HB16TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One
|
||||
#define EPI_HB16TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One
|
||||
#define EPI_HB16TIME2_IRDYDLY_S 24
|
||||
#define EPI_HB16TIME2_CAPWIDTH_S \
|
||||
12
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB16TIME3
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB16TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay
|
||||
#define EPI_HB16TIME3_PSRAMSZ_M 0x00070000 // PSRAM Row Size
|
||||
#define EPI_HB16TIME3_PSRAMSZ_0 0x00000000 // No row size limitation
|
||||
#define EPI_HB16TIME3_PSRAMSZ_128B \
|
||||
0x00010000 // 128 B
|
||||
#define EPI_HB16TIME3_PSRAMSZ_256B \
|
||||
0x00020000 // 256 B
|
||||
#define EPI_HB16TIME3_PSRAMSZ_512B \
|
||||
0x00030000 // 512 B
|
||||
#define EPI_HB16TIME3_PSRAMSZ_1KB \
|
||||
0x00040000 // 1024 B
|
||||
#define EPI_HB16TIME3_PSRAMSZ_2KB \
|
||||
0x00050000 // 2048 B
|
||||
#define EPI_HB16TIME3_PSRAMSZ_4KB \
|
||||
0x00060000 // 4096 B
|
||||
#define EPI_HB16TIME3_PSRAMSZ_8KB \
|
||||
0x00070000 // 8192 B
|
||||
#define EPI_HB16TIME3_CAPWIDTH_M \
|
||||
0x00003000 // CS2n Inter-transfer Capture
|
||||
// Width
|
||||
#define EPI_HB16TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One
|
||||
#define EPI_HB16TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One
|
||||
#define EPI_HB16TIME3_IRDYDLY_S 24
|
||||
#define EPI_HB16TIME3_CAPWIDTH_S \
|
||||
12
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB8TIME3 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB8TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay
|
||||
#define EPI_HB8TIME3_CAPWIDTH_M 0x00003000 // CS2n Inter-transfer Capture
|
||||
// Width
|
||||
#define EPI_HB8TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One
|
||||
#define EPI_HB8TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One
|
||||
#define EPI_HB8TIME3_IRDYDLY_S 24
|
||||
#define EPI_HB8TIME3_CAPWIDTH_S 12
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB8TIME4 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB8TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay
|
||||
#define EPI_HB8TIME4_CAPWIDTH_M 0x00003000 // CS3n Inter-transfer Capture
|
||||
// Width
|
||||
#define EPI_HB8TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One
|
||||
#define EPI_HB8TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One
|
||||
#define EPI_HB8TIME4_IRDYDLY_S 24
|
||||
#define EPI_HB8TIME4_CAPWIDTH_S 12
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HB16TIME4
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HB16TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay
|
||||
#define EPI_HB16TIME4_PSRAMSZ_M 0x00070000 // PSRAM Row Size
|
||||
#define EPI_HB16TIME4_PSRAMSZ_0 0x00000000 // No row size limitation
|
||||
#define EPI_HB16TIME4_PSRAMSZ_128B \
|
||||
0x00010000 // 128 B
|
||||
#define EPI_HB16TIME4_PSRAMSZ_256B \
|
||||
0x00020000 // 256 B
|
||||
#define EPI_HB16TIME4_PSRAMSZ_512B \
|
||||
0x00030000 // 512 B
|
||||
#define EPI_HB16TIME4_PSRAMSZ_1KB \
|
||||
0x00040000 // 1024 B
|
||||
#define EPI_HB16TIME4_PSRAMSZ_2KB \
|
||||
0x00050000 // 2048 B
|
||||
#define EPI_HB16TIME4_PSRAMSZ_4KB \
|
||||
0x00060000 // 4096 B
|
||||
#define EPI_HB16TIME4_PSRAMSZ_8KB \
|
||||
0x00070000 // 8192 B
|
||||
#define EPI_HB16TIME4_CAPWIDTH_M \
|
||||
0x00003000 // CS3n Inter-transfer Capture
|
||||
// Width
|
||||
#define EPI_HB16TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One
|
||||
#define EPI_HB16TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One
|
||||
#define EPI_HB16TIME4_IRDYDLY_S 24
|
||||
#define EPI_HB16TIME4_CAPWIDTH_S \
|
||||
12
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the EPI_O_HBPSRAM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_HBPSRAM_CR_M 0x001FFFFF // PSRAM Config Register
|
||||
#define EPI_HBPSRAM_CR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the EPI_O_FIFOLVL
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are up to 3
|
||||
// spaces available in the WFIFO
|
||||
#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are up to 2
|
||||
// spaces available in the WFIFO
|
||||
#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space
|
||||
// available in the WFIFO
|
||||
#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more
|
||||
// entries in the NBRFIFO
|
||||
#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more
|
||||
// entries in the NBRFIFO
|
||||
#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more
|
||||
// entries in the NBRFIFO
|
||||
#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more
|
||||
// entries in the NBRFIFO
|
||||
#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more
|
||||
// entries in the NBRFIFO
|
||||
#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries
|
||||
// in the NBRFIFO
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_EPI_H__
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_fan.h - Macros used when accessing the fan control hardware.
|
||||
//
|
||||
// Copyright (c) 2010-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_FAN_H__
|
||||
#define __HW_FAN_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Fan Control register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#endif // __HW_FAN_H__
|
||||
|
|
@ -0,0 +1,625 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_flash.h - Macros used when accessing the flash controller.
|
||||
//
|
||||
// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_FLASH_H__
|
||||
#define __HW_FLASH_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the FLASH register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMA 0x400FD000 // Flash Memory Address
|
||||
#define FLASH_FMD 0x400FD004 // Flash Memory Data
|
||||
#define FLASH_FMC 0x400FD008 // Flash Memory Control
|
||||
#define FLASH_FCRIS 0x400FD00C // Flash Controller Raw Interrupt
|
||||
// Status
|
||||
#define FLASH_FCIM 0x400FD010 // Flash Controller Interrupt Mask
|
||||
#define FLASH_FCMISC 0x400FD014 // Flash Controller Masked
|
||||
// Interrupt Status and Clear
|
||||
#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2
|
||||
#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid
|
||||
#define FLASH_FLPEKEY 0x400FD03C // Flash Program/Erase Key
|
||||
#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n
|
||||
#define FLASH_PP 0x400FDFC0 // Flash Peripheral Properties
|
||||
#define FLASH_FSIZE 0x400FDFC0 // Flash Size
|
||||
#define FLASH_SSIZE 0x400FDFC4 // SRAM Size
|
||||
#define FLASH_CONF 0x400FDFC8 // Flash Configuration Register
|
||||
#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map
|
||||
#define FLASH_DMASZ 0x400FDFD0 // Flash DMA Address Size
|
||||
#define FLASH_DMAST 0x400FDFD4 // Flash DMA Starting Address
|
||||
#define FLASH_RVP 0x400FE0D4 // Reset Vector Pointer
|
||||
#define FLASH_RMCTL 0x400FE0F0 // ROM Control
|
||||
#define FLASH_BOOTCFG 0x400FE1D0 // Boot Configuration
|
||||
#define FLASH_USERREG0 0x400FE1E0 // User Register 0
|
||||
#define FLASH_USERREG1 0x400FE1E4 // User Register 1
|
||||
#define FLASH_USERREG2 0x400FE1E8 // User Register 2
|
||||
#define FLASH_USERREG3 0x400FE1EC // User Register 3
|
||||
#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read
|
||||
// Enable 0
|
||||
#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read
|
||||
// Enable 1
|
||||
#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read
|
||||
// Enable 2
|
||||
#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read
|
||||
// Enable 3
|
||||
#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read
|
||||
// Enable 4
|
||||
#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read
|
||||
// Enable 5
|
||||
#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read
|
||||
// Enable 6
|
||||
#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read
|
||||
// Enable 7
|
||||
#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read
|
||||
// Enable 8
|
||||
#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read
|
||||
// Enable 9
|
||||
#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read
|
||||
// Enable 10
|
||||
#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read
|
||||
// Enable 11
|
||||
#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read
|
||||
// Enable 12
|
||||
#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read
|
||||
// Enable 13
|
||||
#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read
|
||||
// Enable 14
|
||||
#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read
|
||||
// Enable 15
|
||||
#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program
|
||||
// Enable 0
|
||||
#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program
|
||||
// Enable 1
|
||||
#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program
|
||||
// Enable 2
|
||||
#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program
|
||||
// Enable 3
|
||||
#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program
|
||||
// Enable 4
|
||||
#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program
|
||||
// Enable 5
|
||||
#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program
|
||||
// Enable 6
|
||||
#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program
|
||||
// Enable 7
|
||||
#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program
|
||||
// Enable 8
|
||||
#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program
|
||||
// Enable 9
|
||||
#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program
|
||||
// Enable 10
|
||||
#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program
|
||||
// Enable 11
|
||||
#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program
|
||||
// Enable 12
|
||||
#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program
|
||||
// Enable 13
|
||||
#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program
|
||||
// Enable 14
|
||||
#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program
|
||||
// Enable 15
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMA_OFFSET_M 0x000FFFFF // Address Offset
|
||||
#define FLASH_FMA_OFFSET_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
|
||||
#define FLASH_FMD_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
|
||||
#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
|
||||
#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
|
||||
#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
|
||||
#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FCRIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FCRIS_PROGRIS 0x00002000 // Program Verify Error Raw
|
||||
// Interrupt Status
|
||||
#define FLASH_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt
|
||||
// Status
|
||||
#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt
|
||||
// Status
|
||||
#define FLASH_FCRIS_VOLTRIS 0x00000200 // Pump Voltage Raw Interrupt
|
||||
// Status
|
||||
#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status
|
||||
#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
|
||||
#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FCIM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask
|
||||
#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask
|
||||
#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask
|
||||
#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask
|
||||
#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask
|
||||
#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
|
||||
#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FCMISC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status
|
||||
// and Clear
|
||||
#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status
|
||||
// and Clear
|
||||
#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt
|
||||
// Status and Clear
|
||||
#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and
|
||||
// Clear
|
||||
#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
|
||||
// and Clear
|
||||
#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
|
||||
// Status and Clear
|
||||
#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
|
||||
// and Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMC2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
|
||||
#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FWBVAL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FLPEKEY register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FLPEKEY_PEKEY_M 0x0000FFFF // Key Value
|
||||
#define FLASH_FLPEKEY_PEKEY_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FWBN register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_PP_PFC 0x40000000 // Prefetch Buffer Mode
|
||||
#define FLASH_PP_FMM 0x20000000 // Flash Mirror Mode
|
||||
#define FLASH_PP_DFA 0x10000000 // DMA Flash Access
|
||||
#define FLASH_PP_EESS_M 0x00780000 // EEPROM Sector Size of the
|
||||
// physical bank
|
||||
#define FLASH_PP_EESS_1KB 0x00000000 // 1 KB
|
||||
#define FLASH_PP_EESS_2KB 0x00080000 // 2 KB
|
||||
#define FLASH_PP_EESS_4KB 0x00100000 // 4 KB
|
||||
#define FLASH_PP_EESS_8KB 0x00180000 // 8 KB
|
||||
#define FLASH_PP_MAINSS_M 0x00070000 // Flash Sector Size of the
|
||||
// physical bank
|
||||
#define FLASH_PP_MAINSS_1KB 0x00000000 // 1 KB
|
||||
#define FLASH_PP_MAINSS_2KB 0x00010000 // 2 KB
|
||||
#define FLASH_PP_MAINSS_4KB 0x00020000 // 4 KB
|
||||
#define FLASH_PP_MAINSS_8KB 0x00030000 // 8 KB
|
||||
#define FLASH_PP_MAINSS_16KB 0x00040000 // 16 KB
|
||||
#define FLASH_PP_SIZE_M 0x0000FFFF // Flash Size
|
||||
#define FLASH_PP_SIZE_512KB 0x000000FF // 512 KB of Flash
|
||||
#define FLASH_PP_SIZE_1MB 0x000001FF // 1024 KB of Flash
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FSIZE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size
|
||||
#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash
|
||||
#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash
|
||||
#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash
|
||||
#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_SSIZE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size
|
||||
#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM
|
||||
#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM
|
||||
#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM
|
||||
#define FLASH_SSIZE_SIZE_256KB 0x000003FF // 256 KB of SRAM
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_CONF register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_CONF_FMME 0x40000000 // Flash Mirror Mode Enable
|
||||
#define FLASH_CONF_SPFE 0x20000000 // Single Prefetch Mode Enable
|
||||
#define FLASH_CONF_CLRTV 0x00100000 // Clear Valid Tags
|
||||
#define FLASH_CONF_FPFON 0x00020000 // Force Prefetch On
|
||||
#define FLASH_CONF_FPFOFF 0x00010000 // Force Prefetch Off
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present
|
||||
#define FLASH_ROMSWMAP_SW0EN_M 0x00000003 // ROM SW Region 0 Availability
|
||||
#define FLASH_ROMSWMAP_SW0EN_NOTVIS \
|
||||
0x00000000 // Software region not available to
|
||||
// the core
|
||||
#define FLASH_ROMSWMAP_SW0EN_CORE \
|
||||
0x00000001 // Region available to core
|
||||
#define FLASH_ROMSWMAP_SW1EN_M 0x0000000C // ROM SW Region 1 Availability
|
||||
#define FLASH_ROMSWMAP_SW1EN_NOTVIS \
|
||||
0x00000000 // Software region not available to
|
||||
// the core
|
||||
#define FLASH_ROMSWMAP_SW1EN_CORE \
|
||||
0x00000004 // Region available to core
|
||||
#define FLASH_ROMSWMAP_SW2EN_M 0x00000030 // ROM SW Region 2 Availability
|
||||
#define FLASH_ROMSWMAP_SW2EN_NOTVIS \
|
||||
0x00000000 // Software region not available to
|
||||
// the core
|
||||
#define FLASH_ROMSWMAP_SW2EN_CORE \
|
||||
0x00000010 // Region available to core
|
||||
#define FLASH_ROMSWMAP_SW3EN_M 0x000000C0 // ROM SW Region 3 Availability
|
||||
#define FLASH_ROMSWMAP_SW3EN_NOTVIS \
|
||||
0x00000000 // Software region not available to
|
||||
// the core
|
||||
#define FLASH_ROMSWMAP_SW3EN_CORE \
|
||||
0x00000040 // Region available to core
|
||||
#define FLASH_ROMSWMAP_SW4EN_M 0x00000300 // ROM SW Region 4 Availability
|
||||
#define FLASH_ROMSWMAP_SW4EN_NOTVIS \
|
||||
0x00000000 // Software region not available to
|
||||
// the core
|
||||
#define FLASH_ROMSWMAP_SW4EN_CORE \
|
||||
0x00000100 // Region available to core
|
||||
#define FLASH_ROMSWMAP_SW5EN_M 0x00000C00 // ROM SW Region 5 Availability
|
||||
#define FLASH_ROMSWMAP_SW5EN_NOTVIS \
|
||||
0x00000000 // Software region not available to
|
||||
// the core
|
||||
#define FLASH_ROMSWMAP_SW5EN_CORE \
|
||||
0x00000400 // Region available to core
|
||||
#define FLASH_ROMSWMAP_SW6EN_M 0x00003000 // ROM SW Region 6 Availability
|
||||
#define FLASH_ROMSWMAP_SW6EN_NOTVIS \
|
||||
0x00000000 // Software region not available to
|
||||
// the core
|
||||
#define FLASH_ROMSWMAP_SW6EN_CORE \
|
||||
0x00001000 // Region available to core
|
||||
#define FLASH_ROMSWMAP_SW7EN_M 0x0000C000 // ROM SW Region 7 Availability
|
||||
#define FLASH_ROMSWMAP_SW7EN_NOTVIS \
|
||||
0x00000000 // Software region not available to
|
||||
// the core
|
||||
#define FLASH_ROMSWMAP_SW7EN_CORE \
|
||||
0x00004000 // Region available to core
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_DMASZ register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_DMASZ_SIZE_M 0x0003FFFF // uDMA-accessible Memory Size
|
||||
#define FLASH_DMASZ_SIZE_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_DMAST register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_DMAST_ADDR_M 0x1FFFF800 // Contains the starting address of
|
||||
// the flash region accessible by
|
||||
// uDMA if the FLASHPP register DFA
|
||||
// bit is set
|
||||
#define FLASH_DMAST_ADDR_S 11
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_RVP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_RVP_RV_M 0xFFFFFFFF // Reset Vector Pointer Address
|
||||
#define FLASH_RVP_RV_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_RMCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_BOOTCFG register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_BOOTCFG_NW 0x80000000 // Not Written
|
||||
#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port
|
||||
#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A
|
||||
#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B
|
||||
#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C
|
||||
#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D
|
||||
#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E
|
||||
#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F
|
||||
#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G
|
||||
#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H
|
||||
#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin
|
||||
#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0
|
||||
#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1
|
||||
#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2
|
||||
#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3
|
||||
#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4
|
||||
#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5
|
||||
#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6
|
||||
#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7
|
||||
#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity
|
||||
#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable
|
||||
#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select
|
||||
#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1
|
||||
#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_USERREG0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data
|
||||
#define FLASH_USERREG0_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_USERREG1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data
|
||||
#define FLASH_USERREG1_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_USERREG2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data
|
||||
#define FLASH_USERREG2_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_USERREG3 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data
|
||||
#define FLASH_USERREG3_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPRE8 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPRE8_READ_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Read Enable
|
||||
#define FLASH_FMPRE8_READ_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPRE9 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPRE9_READ_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Read Enable
|
||||
#define FLASH_FMPRE9_READ_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPRE10 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPRE10_READ_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Read Enable
|
||||
#define FLASH_FMPRE10_READ_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPRE11 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPRE11_READ_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Read Enable
|
||||
#define FLASH_FMPRE11_READ_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPRE12 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPRE12_READ_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Read Enable
|
||||
#define FLASH_FMPRE12_READ_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPRE13 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPRE13_READ_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Read Enable
|
||||
#define FLASH_FMPRE13_READ_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPRE14 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPRE14_READ_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Read Enable
|
||||
#define FLASH_FMPRE14_READ_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPRE15 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPRE15_READ_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Read Enable
|
||||
#define FLASH_FMPRE15_READ_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPPE8 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPPE8_PROG_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Programming Enable
|
||||
#define FLASH_FMPPE8_PROG_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPPE9 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPPE9_PROG_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Programming Enable
|
||||
#define FLASH_FMPPE9_PROG_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPPE10 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPPE10_PROG_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Programming Enable
|
||||
#define FLASH_FMPPE10_PROG_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPPE11 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPPE11_PROG_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Programming Enable
|
||||
#define FLASH_FMPPE11_PROG_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPPE12 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPPE12_PROG_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Programming Enable
|
||||
#define FLASH_FMPPE12_PROG_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPPE13 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPPE13_PROG_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Programming Enable
|
||||
#define FLASH_FMPPE13_PROG_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPPE14 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPPE14_PROG_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Programming Enable
|
||||
#define FLASH_FMPPE14_PROG_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the FLASH_FMPPE15 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_FMPPE15_PROG_ENABLE_M \
|
||||
0xFFFFFFFF // Flash Programming Enable
|
||||
#define FLASH_FMPPE15_PROG_ENABLE_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the erase size of the FLASH block that is
|
||||
// erased by an erase operation, and the protect size is the size of the FLASH
|
||||
// block that is protected by each protection register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_PROTECT_SIZE 0x00000800
|
||||
#define FLASH_ERASE_SIZE 0x00000400
|
||||
|
||||
#endif // __HW_FLASH_H__
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_gpio.h - Defines and Macros for GPIO hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_GPIO_H__
|
||||
#define __HW_GPIO_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the GPIO register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_O_DATA 0x00000000 // GPIO Data
|
||||
#define GPIO_O_DIR 0x00000400 // GPIO Direction
|
||||
#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
|
||||
#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
|
||||
#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
|
||||
#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
|
||||
#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
|
||||
#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
|
||||
#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
|
||||
#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
|
||||
#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
|
||||
#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
|
||||
#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
|
||||
#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
|
||||
#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
|
||||
#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
|
||||
#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
|
||||
#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
|
||||
#define GPIO_O_LOCK 0x00000520 // GPIO Lock
|
||||
#define GPIO_O_CR 0x00000524 // GPIO Commit
|
||||
#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
|
||||
#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
|
||||
#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
|
||||
#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
|
||||
#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
|
||||
#define GPIO_O_DR12R 0x0000053C // GPIO 12-mA Drive Select
|
||||
#define GPIO_O_WAKEPEN 0x00000540 // GPIO Wake Pin Enable
|
||||
#define GPIO_O_WAKELVL 0x00000544 // GPIO Wake Level
|
||||
#define GPIO_O_WAKESTAT 0x00000548 // GPIO Wake Status
|
||||
#define GPIO_O_PP 0x00000FC0 // GPIO Peripheral Property
|
||||
#define GPIO_O_PC 0x00000FC4 // GPIO Peripheral Configuration
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_IM_DMAIME 0x00000100 // GPIO uDMA Done Interrupt Mask
|
||||
// Enable
|
||||
#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
|
||||
#define GPIO_IM_GPIO_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_RIS_DMARIS 0x00000100 // GPIO uDMA Done Interrupt Raw
|
||||
// Status
|
||||
#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
|
||||
#define GPIO_RIS_GPIO_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_MIS_DMAMIS 0x00000100 // GPIO uDMA Done Masked Interrupt
|
||||
// Status
|
||||
#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
|
||||
#define GPIO_MIS_GPIO_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_ICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_ICR_DMAIC 0x00000100 // GPIO uDMA Interrupt Clear
|
||||
#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
|
||||
#define GPIO_ICR_GPIO_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_LOCK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
|
||||
#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
|
||||
// and may be modified
|
||||
#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
|
||||
// and may not be modified
|
||||
#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_SI register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_DR12R register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_DR12R_DRV12_M 0x000000FF // Output Pad 12-mA Drive Enable
|
||||
#define GPIO_DR12R_DRV12_12MA 0x00000001 // The corresponding GPIO pin has
|
||||
// 12-mA drive. This encoding is
|
||||
// only valid if the GPIOPP EDE bit
|
||||
// is set and the appropriate
|
||||
// GPIOPC EDM bit field is
|
||||
// programmed to 0x3
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_WAKEPEN register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_WAKEPEN_WAKEP4 0x00000010 // P[4] Wake Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_WAKELVL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_WAKELVL_WAKELVL4 0x00000010 // P[4] Wake Level
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_WAKESTAT
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_WAKESTAT_STAT4 0x00000010 // P[4] Wake Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_PP_EDE 0x00000001 // Extended Drive Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_PC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_PC_EDM7_M 0x0000C000 // Extended Drive Mode Bit 7
|
||||
#define GPIO_PC_EDM6_M 0x00003000 // Extended Drive Mode Bit 6
|
||||
#define GPIO_PC_EDM5_M 0x00000C00 // Extended Drive Mode Bit 5
|
||||
#define GPIO_PC_EDM4_M 0x00000300 // Extended Drive Mode Bit 4
|
||||
#define GPIO_PC_EDM3_M 0x000000C0 // Extended Drive Mode Bit 3
|
||||
#define GPIO_PC_EDM2_M 0x00000030 // Extended Drive Mode Bit 2
|
||||
#define GPIO_PC_EDM1_M 0x0000000C // Extended Drive Mode Bit 1
|
||||
#define GPIO_PC_EDM0_M 0x00000003 // Extended Drive Mode Bit 0
|
||||
#define GPIO_PC_EDM0_DISABLE 0x00000000 // Drive values of 2, 4 and 8 mA
|
||||
// are maintained. GPIO n Drive
|
||||
// Select (GPIODRnR) registers
|
||||
// function as normal
|
||||
#define GPIO_PC_EDM0_6MA 0x00000001 // An additional 6 mA option is
|
||||
// provided
|
||||
#define GPIO_PC_EDM0_PLUS2MA 0x00000003 // A 2 mA driver is always enabled;
|
||||
// setting the corresponding
|
||||
// GPIODR4R register bit adds 2 mA
|
||||
// and setting the corresponding
|
||||
// GPIODR8R of GPIODR12R register
|
||||
// bit adds an additional 4 mA
|
||||
#define GPIO_PC_EDM7_S 14
|
||||
#define GPIO_PC_EDM6_S 12
|
||||
#define GPIO_PC_EDM5_S 10
|
||||
#define GPIO_PC_EDM4_S 8
|
||||
#define GPIO_PC_EDM3_S 6
|
||||
#define GPIO_PC_EDM2_S 4
|
||||
#define GPIO_PC_EDM1_S 2
|
||||
|
||||
#endif // __HW_GPIO_H__
|
||||
|
|
@ -0,0 +1,483 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_hibernate.h - Defines and Macros for the Hibernation module.
|
||||
//
|
||||
// Copyright (c) 2007-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_HIBERNATE_H__
|
||||
#define __HW_HIBERNATE_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Hibernation module register addresses.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
|
||||
#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
|
||||
#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
|
||||
#define HIB_CTL 0x400FC010 // Hibernation Control
|
||||
#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
|
||||
#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
|
||||
#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
|
||||
// Status
|
||||
#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
|
||||
#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
|
||||
#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
|
||||
#define HIB_IO 0x400FC02C // Hibernation IO Configuration
|
||||
#define HIB_DATA 0x400FC030 // Hibernation Data
|
||||
#define HIB_CALCTL 0x400FC300 // Hibernation Calendar Control
|
||||
#define HIB_CAL0 0x400FC310 // Hibernation Calendar 0
|
||||
#define HIB_CAL1 0x400FC314 // Hibernation Calendar 1
|
||||
#define HIB_CALLD0 0x400FC320 // Hibernation Calendar Load 0
|
||||
#define HIB_CALLD1 0x400FC324 // Hibernation Calendar Load
|
||||
#define HIB_CALM0 0x400FC330 // Hibernation Calendar Match 0
|
||||
#define HIB_CALM1 0x400FC334 // Hibernation Calendar Match 1
|
||||
#define HIB_LOCK 0x400FC360 // Hibernation Lock
|
||||
#define HIB_TPCTL 0x400FC400 // HIB Tamper Control
|
||||
#define HIB_TPSTAT 0x400FC404 // HIB Tamper Status
|
||||
#define HIB_TPIO 0x400FC410 // HIB Tamper I/O Control
|
||||
#define HIB_TPLOG0 0x400FC4E0 // HIB Tamper Log 0
|
||||
#define HIB_TPLOG1 0x400FC4E4 // HIB Tamper Log 1
|
||||
#define HIB_TPLOG2 0x400FC4E8 // HIB Tamper Log 2
|
||||
#define HIB_TPLOG3 0x400FC4EC // HIB Tamper Log 3
|
||||
#define HIB_TPLOG4 0x400FC4F0 // HIB Tamper Log 4
|
||||
#define HIB_TPLOG5 0x400FC4F4 // HIB Tamper Log 5
|
||||
#define HIB_TPLOG6 0x400FC4F8 // HIB Tamper Log 6
|
||||
#define HIB_TPLOG7 0x400FC4FC // HIB Tamper Log 7
|
||||
#define HIB_PP 0x400FCFC0 // Hibernation Peripheral
|
||||
// Properties
|
||||
#define HIB_CC 0x400FCFC8 // Hibernation Clock Control
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
|
||||
#define HIB_RTCC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCM0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
|
||||
#define HIB_RTCM0_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCLD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
|
||||
#define HIB_RTCLD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
|
||||
#define HIB_CTL_RETCLR 0x40000000 // GPIO Retention/Clear
|
||||
#define HIB_CTL_OSCSEL 0x00080000 // Oscillator Select
|
||||
#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
|
||||
#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
|
||||
#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
|
||||
// Comparator
|
||||
#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
|
||||
#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
|
||||
#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
|
||||
#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
|
||||
#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
|
||||
#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
|
||||
#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
|
||||
#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
|
||||
#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
|
||||
#define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable
|
||||
#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
|
||||
#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
|
||||
#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_IM_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask
|
||||
#define HIB_IM_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
|
||||
// Mask
|
||||
#define HIB_IM_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask
|
||||
#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
|
||||
// Interrupt Mask
|
||||
#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
|
||||
#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
|
||||
// Mask
|
||||
#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RIS_VDDFAIL 0x00000080 // VDD Fail Raw Interrupt Status
|
||||
#define HIB_RIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Raw
|
||||
// Interrupt Status
|
||||
#define HIB_RIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Raw Interrupt
|
||||
// Status
|
||||
#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
|
||||
// Interrupt Status
|
||||
#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
|
||||
// Status
|
||||
#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
|
||||
// Interrupt Status
|
||||
#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_MIS_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask
|
||||
#define HIB_MIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
|
||||
// Mask
|
||||
#define HIB_MIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask
|
||||
#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
|
||||
// Interrupt Status
|
||||
#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
|
||||
// Interrupt Status
|
||||
#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
|
||||
// Interrupt Status
|
||||
#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
|
||||
// Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_IC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_IC_VDDFAIL 0x00000080 // VDD Fail Interrupt Clear
|
||||
#define HIB_IC_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
|
||||
// Clear
|
||||
#define HIB_IC_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Clear
|
||||
#define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt
|
||||
// Clear
|
||||
#define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear
|
||||
#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
|
||||
// Clear
|
||||
#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
|
||||
// Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
|
||||
#define HIB_RTCT_TRIM_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCSS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
|
||||
#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
|
||||
#define HIB_RTCSS_RTCSSM_S 16
|
||||
#define HIB_RTCSS_RTCSSC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_IO register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_IO_IOWRC 0x80000000 // I/O Write Complete
|
||||
#define HIB_IO_WURSTEN 0x00000010 // Reset Wake Source Enable
|
||||
#define HIB_IO_WUUNLK 0x00000001 // I/O Wake Pad Configuration
|
||||
// Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_DATA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
|
||||
#define HIB_DATA_RTD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_CALCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_CALCTL_CAL24 0x00000004 // Calendar Mode
|
||||
#define HIB_CALCTL_CALEN 0x00000001 // RTC Calendar/Counter Mode Select
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_CAL0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_CAL0_VALID 0x80000000 // Valid Calendar Load
|
||||
#define HIB_CAL0_AMPM 0x00400000 // AM/PM Designation
|
||||
#define HIB_CAL0_HR_M 0x001F0000 // Hours
|
||||
#define HIB_CAL0_MIN_M 0x00003F00 // Minutes
|
||||
#define HIB_CAL0_SEC_M 0x0000003F // Seconds
|
||||
#define HIB_CAL0_HR_S 16
|
||||
#define HIB_CAL0_MIN_S 8
|
||||
#define HIB_CAL0_SEC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_CAL1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_CAL1_VALID 0x80000000 // Valid Calendar Load
|
||||
#define HIB_CAL1_DOW_M 0x07000000 // Day of Week
|
||||
#define HIB_CAL1_YEAR_M 0x007F0000 // Year Value
|
||||
#define HIB_CAL1_MON_M 0x00000F00 // Month
|
||||
#define HIB_CAL1_DOM_M 0x0000001F // Day of Month
|
||||
#define HIB_CAL1_DOW_S 24
|
||||
#define HIB_CAL1_YEAR_S 16
|
||||
#define HIB_CAL1_MON_S 8
|
||||
#define HIB_CAL1_DOM_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_CALLD0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_CALLD0_AMPM 0x00400000 // AM/PM Designation
|
||||
#define HIB_CALLD0_HR_M 0x001F0000 // Hours
|
||||
#define HIB_CALLD0_MIN_M 0x00003F00 // Minutes
|
||||
#define HIB_CALLD0_SEC_M 0x0000003F // Seconds
|
||||
#define HIB_CALLD0_HR_S 16
|
||||
#define HIB_CALLD0_MIN_S 8
|
||||
#define HIB_CALLD0_SEC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_CALLD1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_CALLD1_DOW_M 0x07000000 // Day of Week
|
||||
#define HIB_CALLD1_YEAR_M 0x007F0000 // Year Value
|
||||
#define HIB_CALLD1_MON_M 0x00000F00 // Month
|
||||
#define HIB_CALLD1_DOM_M 0x0000001F // Day of Month
|
||||
#define HIB_CALLD1_DOW_S 24
|
||||
#define HIB_CALLD1_YEAR_S 16
|
||||
#define HIB_CALLD1_MON_S 8
|
||||
#define HIB_CALLD1_DOM_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_CALM0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_CALM0_AMPM 0x00400000 // AM/PM Designation
|
||||
#define HIB_CALM0_HR_M 0x001F0000 // Hours
|
||||
#define HIB_CALM0_MIN_M 0x00003F00 // Minutes
|
||||
#define HIB_CALM0_SEC_M 0x0000003F // Seconds
|
||||
#define HIB_CALM0_HR_S 16
|
||||
#define HIB_CALM0_MIN_S 8
|
||||
#define HIB_CALM0_SEC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_CALM1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_CALM1_DOM_M 0x0000001F // Day of Month
|
||||
#define HIB_CALM1_DOM_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_LOCK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_LOCK_HIBLOCK_M 0xFFFFFFFF // HIbernate Lock
|
||||
#define HIB_LOCK_HIBLOCK_KEY 0xA3359554 // Hibernate Lock Key
|
||||
#define HIB_LOCK_HIBLOCK_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_TPCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_TPCTL_WAKE 0x00000800 // Wake from Hibernate on a Tamper
|
||||
// Event
|
||||
#define HIB_TPCTL_MEMCLR_M 0x00000300 // HIB Memory Clear on Tamper Event
|
||||
#define HIB_TPCTL_MEMCLR_NONE 0x00000000 // Do not Clear HIB memory on
|
||||
// tamper event
|
||||
#define HIB_TPCTL_MEMCLR_LOW32 0x00000100 // Clear Lower 32 Bytes of HIB
|
||||
// memory on tamper event
|
||||
#define HIB_TPCTL_MEMCLR_HIGH32 0x00000200 // Clear upper 32 Bytes of HIB
|
||||
// memory on tamper event
|
||||
#define HIB_TPCTL_MEMCLR_ALL 0x00000300 // Clear all HIB memory on tamper
|
||||
// event
|
||||
#define HIB_TPCTL_TPCLR 0x00000010 // Tamper Event Clear
|
||||
#define HIB_TPCTL_TPEN 0x00000001 // Tamper Module Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_TPSTAT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_TPSTAT_STATE_M 0x0000000C // Tamper Module Status
|
||||
#define HIB_TPSTAT_STATE_DISABLED \
|
||||
0x00000000 // Tamper disabled
|
||||
#define HIB_TPSTAT_STATE_CONFIGED \
|
||||
0x00000004 // Tamper configured
|
||||
#define HIB_TPSTAT_STATE_ERROR 0x00000008 // Tamper pin event occurred
|
||||
#define HIB_TPSTAT_XOSCST 0x00000002 // External Oscillator Status
|
||||
#define HIB_TPSTAT_XOSCFAIL 0x00000001 // External Oscillator Failure
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_TPIO register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_TPIO_GFLTR3 0x08000000 // TMPR3 Glitch Filtering
|
||||
#define HIB_TPIO_PUEN3 0x04000000 // TMPR3 Internal Weak Pull-up
|
||||
// Enable
|
||||
#define HIB_TPIO_LEV3 0x02000000 // TMPR3 Trigger Level
|
||||
#define HIB_TPIO_EN3 0x01000000 // TMPR3 Enable
|
||||
#define HIB_TPIO_GFLTR2 0x00080000 // TMPR2 Glitch Filtering
|
||||
#define HIB_TPIO_PUEN2 0x00040000 // TMPR2 Internal Weak Pull-up
|
||||
// Enable
|
||||
#define HIB_TPIO_LEV2 0x00020000 // TMPR2 Trigger Level
|
||||
#define HIB_TPIO_EN2 0x00010000 // TMPR2 Enable
|
||||
#define HIB_TPIO_GFLTR1 0x00000800 // TMPR1 Glitch Filtering
|
||||
#define HIB_TPIO_PUEN1 0x00000400 // TMPR1 Internal Weak Pull-up
|
||||
// Enable
|
||||
#define HIB_TPIO_LEV1 0x00000200 // TMPR1 Trigger Level
|
||||
#define HIB_TPIO_EN1 0x00000100 // TMPR1Enable
|
||||
#define HIB_TPIO_GFLTR0 0x00000008 // TMPR0 Glitch Filtering
|
||||
#define HIB_TPIO_PUEN0 0x00000004 // TMPR0 Internal Weak Pull-up
|
||||
// Enable
|
||||
#define HIB_TPIO_LEV0 0x00000002 // TMPR0 Trigger Level
|
||||
#define HIB_TPIO_EN0 0x00000001 // TMPR0 Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_TPLOG0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_TPLOG0_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
|
||||
#define HIB_TPLOG0_TIME_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_TPLOG1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_TPLOG1_XOSC 0x00010000 // Status of external 32
|
||||
#define HIB_TPLOG1_TRIG3 0x00000008 // Status of TMPR[3] Trigger
|
||||
#define HIB_TPLOG1_TRIG2 0x00000004 // Status of TMPR[2] Trigger
|
||||
#define HIB_TPLOG1_TRIG1 0x00000002 // Status of TMPR[1] Trigger
|
||||
#define HIB_TPLOG1_TRIG0 0x00000001 // Status of TMPR[0] Trigger
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_TPLOG2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_TPLOG2_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
|
||||
#define HIB_TPLOG2_TIME_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_TPLOG3 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_TPLOG3_XOSC 0x00010000 // Status of external 32
|
||||
#define HIB_TPLOG3_TRIG3 0x00000008 // Status of TMPR[3] Trigger
|
||||
#define HIB_TPLOG3_TRIG2 0x00000004 // Status of TMPR[2] Trigger
|
||||
#define HIB_TPLOG3_TRIG1 0x00000002 // Status of TMPR[1] Trigger
|
||||
#define HIB_TPLOG3_TRIG0 0x00000001 // Status of TMPR[0] Trigger
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_TPLOG4 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_TPLOG4_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
|
||||
#define HIB_TPLOG4_TIME_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_TPLOG5 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_TPLOG5_XOSC 0x00010000 // Status of external 32
|
||||
#define HIB_TPLOG5_TRIG3 0x00000008 // Status of TMPR[3] Trigger
|
||||
#define HIB_TPLOG5_TRIG2 0x00000004 // Status of TMPR[2] Trigger
|
||||
#define HIB_TPLOG5_TRIG1 0x00000002 // Status of TMPR[1] Trigger
|
||||
#define HIB_TPLOG5_TRIG0 0x00000001 // Status of TMPR[0] Trigger
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_TPLOG6 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_TPLOG6_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
|
||||
#define HIB_TPLOG6_TIME_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_TPLOG7 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_TPLOG7_XOSC 0x00010000 // Status of external 32
|
||||
#define HIB_TPLOG7_TRIG3 0x00000008 // Status of TMPR[3] Trigger
|
||||
#define HIB_TPLOG7_TRIG2 0x00000004 // Status of TMPR[2] Trigger
|
||||
#define HIB_TPLOG7_TRIG1 0x00000002 // Status of TMPR[1] Trigger
|
||||
#define HIB_TPLOG7_TRIG0 0x00000001 // Status of TMPR[0] Trigger
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_PP_TAMPER 0x00000002 // Tamper Pin Presence
|
||||
#define HIB_PP_WAKENC 0x00000001 // Wake Pin Presence
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_CC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_CC_SYSCLKEN 0x00000001 // RTCOSC to System Clock Enable
|
||||
|
||||
#endif // __HW_HIBERNATE_H__
|
||||
|
|
@ -0,0 +1,470 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_I2C_H__
|
||||
#define __HW_I2C_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the I2C register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
|
||||
#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
|
||||
#define I2C_O_MDR 0x00000008 // I2C Master Data
|
||||
#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
|
||||
#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
|
||||
#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
|
||||
#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
|
||||
// Status
|
||||
#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
|
||||
#define I2C_O_MCR 0x00000020 // I2C Master Configuration
|
||||
#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout
|
||||
// Count
|
||||
#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor
|
||||
#define I2C_O_MBLEN 0x00000030 // I2C Master Burst Length
|
||||
#define I2C_O_MBCNT 0x00000034 // I2C Master Burst Count
|
||||
#define I2C_O_MCR2 0x00000038 // I2C Master Configuration 2
|
||||
#define I2C_O_SOAR 0x00000800 // I2C Slave Own Address
|
||||
#define I2C_O_SCSR 0x00000804 // I2C Slave Control/Status
|
||||
#define I2C_O_SDR 0x00000808 // I2C Slave Data
|
||||
#define I2C_O_SIMR 0x0000080C // I2C Slave Interrupt Mask
|
||||
#define I2C_O_SRIS 0x00000810 // I2C Slave Raw Interrupt Status
|
||||
#define I2C_O_SMIS 0x00000814 // I2C Slave Masked Interrupt
|
||||
// Status
|
||||
#define I2C_O_SICR 0x00000818 // I2C Slave Interrupt Clear
|
||||
#define I2C_O_SOAR2 0x0000081C // I2C Slave Own Address 2
|
||||
#define I2C_O_SACKCTL 0x00000820 // I2C Slave ACK Control
|
||||
#define I2C_O_FIFODATA 0x00000F00 // I2C FIFO Data
|
||||
#define I2C_O_FIFOCTL 0x00000F04 // I2C FIFO Control
|
||||
#define I2C_O_FIFOSTATUS 0x00000F08 // I2C FIFO Status
|
||||
#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties
|
||||
#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MSA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
|
||||
#define I2C_MSA_RS 0x00000001 // Receive not send
|
||||
#define I2C_MSA_SA_S 1
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status
|
||||
#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status
|
||||
#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
|
||||
#define I2C_MCS_BURST 0x00000040 // Burst Enable
|
||||
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
|
||||
#define I2C_MCS_IDLE 0x00000020 // I2C Idle
|
||||
#define I2C_MCS_QCMD 0x00000020 // Quick Command
|
||||
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
|
||||
#define I2C_MCS_HS 0x00000010 // High-Speed Enable
|
||||
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
|
||||
#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
|
||||
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
|
||||
#define I2C_MCS_STOP 0x00000004 // Generate STOP
|
||||
#define I2C_MCS_ERROR 0x00000002 // Error
|
||||
#define I2C_MCS_START 0x00000002 // Generate START
|
||||
#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
|
||||
#define I2C_MCS_BUSY 0x00000001 // I2C Busy
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MDR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MDR_DATA_M 0x000000FF // This byte contains the data
|
||||
// transferred during a transaction
|
||||
#define I2C_MDR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MTPR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MTPR_PULSEL_M 0x00070000 // Glitch Suppression Pulse Width
|
||||
#define I2C_MTPR_PULSEL_BYPASS 0x00000000 // Bypass
|
||||
#define I2C_MTPR_PULSEL_1 0x00010000 // 1 clock
|
||||
#define I2C_MTPR_PULSEL_2 0x00020000 // 2 clocks
|
||||
#define I2C_MTPR_PULSEL_3 0x00030000 // 3 clocks
|
||||
#define I2C_MTPR_PULSEL_4 0x00040000 // 4 clocks
|
||||
#define I2C_MTPR_PULSEL_8 0x00050000 // 8 clocks
|
||||
#define I2C_MTPR_PULSEL_16 0x00060000 // 16 clocks
|
||||
#define I2C_MTPR_PULSEL_31 0x00070000 // 31 clocks
|
||||
#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
|
||||
#define I2C_MTPR_TPR_M 0x0000007F // Timer Period
|
||||
#define I2C_MTPR_TPR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MIMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask
|
||||
#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt
|
||||
// Mask
|
||||
#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt
|
||||
// Mask
|
||||
#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt
|
||||
// Mask
|
||||
#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask
|
||||
#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask
|
||||
#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask
|
||||
#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask
|
||||
#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask
|
||||
#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask
|
||||
#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
|
||||
#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MRIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt
|
||||
// Status
|
||||
#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw
|
||||
// Interrupt Status
|
||||
#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw
|
||||
// Interrupt Status
|
||||
#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt
|
||||
// Status
|
||||
#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt
|
||||
// Status
|
||||
#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt
|
||||
// Status
|
||||
#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt
|
||||
// Status
|
||||
#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt
|
||||
// Status
|
||||
#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt
|
||||
// Status
|
||||
#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status
|
||||
#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
|
||||
// Status
|
||||
#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MMIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask
|
||||
#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt
|
||||
// Mask
|
||||
#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt
|
||||
// Mask
|
||||
#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask
|
||||
#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask
|
||||
#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask
|
||||
#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask
|
||||
#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask
|
||||
#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status
|
||||
#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status
|
||||
#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
|
||||
// Status
|
||||
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt
|
||||
// Clear
|
||||
#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt
|
||||
// Clear
|
||||
#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt
|
||||
// Clear
|
||||
#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt
|
||||
// Clear
|
||||
#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear
|
||||
#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear
|
||||
#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear
|
||||
#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt
|
||||
// Clear
|
||||
#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear
|
||||
#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear
|
||||
#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
|
||||
#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable
|
||||
#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
|
||||
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
|
||||
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
|
||||
#define I2C_MCLKOCNT_CNTL_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MBMON register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
|
||||
#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MBLEN register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length
|
||||
#define I2C_MBLEN_CNTL_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MBCNT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count
|
||||
#define I2C_MBCNT_CNTL_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCR2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width
|
||||
#define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass
|
||||
#define I2C_MCR2_GFPW_1 0x00000010 // 1 clock
|
||||
#define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks
|
||||
#define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks
|
||||
#define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks
|
||||
#define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks
|
||||
#define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks
|
||||
#define I2C_MCR2_GFPW_31 0x00000070 // 31 clocks
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SOAR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
|
||||
#define I2C_SOAR_OAR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SCSR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status
|
||||
#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status
|
||||
#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
|
||||
#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
|
||||
#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
|
||||
#define I2C_SCSR_FBR 0x00000004 // First Byte Received
|
||||
#define I2C_SCSR_RXFIFO 0x00000004 // RX FIFO Enable
|
||||
#define I2C_SCSR_TXFIFO 0x00000002 // TX FIFO Enable
|
||||
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
|
||||
#define I2C_SCSR_DA 0x00000001 // Device Active
|
||||
#define I2C_SCSR_RREQ 0x00000001 // Receive Request
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SDR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
|
||||
#define I2C_SDR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SIMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SIMR_RXFFIM 0x00000100 // Receive FIFO Full Interrupt Mask
|
||||
#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt
|
||||
// Mask
|
||||
#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt
|
||||
// Mask
|
||||
#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt
|
||||
// Mask
|
||||
#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask
|
||||
#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask
|
||||
#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
|
||||
#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
|
||||
#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SRIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SRIS_RXFFRIS 0x00000100 // Receive FIFO Full Raw Interrupt
|
||||
// Status
|
||||
#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw
|
||||
// Interrupt Status
|
||||
#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw
|
||||
// Interrupt Status
|
||||
#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt
|
||||
// Status
|
||||
#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt
|
||||
// Status
|
||||
#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status
|
||||
#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
|
||||
// Status
|
||||
#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
|
||||
// Status
|
||||
#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SMIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask
|
||||
#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt
|
||||
// Mask
|
||||
#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt
|
||||
// Mask
|
||||
#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt
|
||||
// Mask
|
||||
#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt
|
||||
// Status
|
||||
#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt
|
||||
// Status
|
||||
#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
|
||||
// Status
|
||||
#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
|
||||
// Status
|
||||
#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask
|
||||
#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt
|
||||
// Mask
|
||||
#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask
|
||||
#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask
|
||||
#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear
|
||||
#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear
|
||||
#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
|
||||
#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
|
||||
#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SOAR2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
|
||||
#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
|
||||
#define I2C_SOAR2_OAR2_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SACKCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
|
||||
#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_FIFODATA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_FIFODATA_DATA_M 0x000000FF // I2C TX FIFO Write Data Byte
|
||||
#define I2C_FIFODATA_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_FIFOCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment
|
||||
#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush
|
||||
#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable
|
||||
#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger
|
||||
#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment
|
||||
#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush
|
||||
#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable
|
||||
#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger
|
||||
#define I2C_FIFOCTL_RXTRIG_S 16
|
||||
#define I2C_FIFOCTL_TXTRIG_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_FIFOSTATUS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_FIFOSTATUS_RXABVTRIG \
|
||||
0x00040000 // RX FIFO Above Trigger Level
|
||||
#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full
|
||||
#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty
|
||||
#define I2C_FIFOSTATUS_TXBLWTRIG \
|
||||
0x00000004 // TX FIFO Below Trigger Level
|
||||
#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full
|
||||
#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_PP_HS 0x00000001 // High-Speed Capable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_PC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_PC_HS 0x00000001 // High-Speed Capable
|
||||
|
||||
#endif // __HW_I2C_H__
|
||||
|
|
@ -0,0 +1,491 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_ints.h - Macros that define the interrupt assignment on Tiva C Series
|
||||
// MCUs.
|
||||
//
|
||||
// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_INTS_H__
|
||||
#define __HW_INTS_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the fault assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FAULT_NMI 2 // NMI fault
|
||||
#define FAULT_HARD 3 // Hard fault
|
||||
#define FAULT_MPU 4 // MPU fault
|
||||
#define FAULT_BUS 5 // Bus fault
|
||||
#define FAULT_USAGE 6 // Usage fault
|
||||
#define FAULT_SVCALL 11 // SVCall
|
||||
#define FAULT_DEBUG 12 // Debug monitor
|
||||
#define FAULT_PENDSV 14 // PendSV
|
||||
#define FAULT_SYSTICK 15 // System Tick
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// TM4C123 Class Interrupts
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_GPIOA_TM4C123 16 // GPIO Port A
|
||||
#define INT_GPIOB_TM4C123 17 // GPIO Port B
|
||||
#define INT_GPIOC_TM4C123 18 // GPIO Port C
|
||||
#define INT_GPIOD_TM4C123 19 // GPIO Port D
|
||||
#define INT_GPIOE_TM4C123 20 // GPIO Port E
|
||||
#define INT_UART0_TM4C123 21 // UART0
|
||||
#define INT_UART1_TM4C123 22 // UART1
|
||||
#define INT_SSI0_TM4C123 23 // SSI0
|
||||
#define INT_I2C0_TM4C123 24 // I2C0
|
||||
#define INT_PWM0_FAULT_TM4C123 25 // PWM0 Fault
|
||||
#define INT_PWM0_0_TM4C123 26 // PWM0 Generator 0
|
||||
#define INT_PWM0_1_TM4C123 27 // PWM0 Generator 1
|
||||
#define INT_PWM0_2_TM4C123 28 // PWM0 Generator 2
|
||||
#define INT_QEI0_TM4C123 29 // QEI0
|
||||
#define INT_ADC0SS0_TM4C123 30 // ADC0 Sequence 0
|
||||
#define INT_ADC0SS1_TM4C123 31 // ADC0 Sequence 1
|
||||
#define INT_ADC0SS2_TM4C123 32 // ADC0 Sequence 2
|
||||
#define INT_ADC0SS3_TM4C123 33 // ADC0 Sequence 3
|
||||
#define INT_WATCHDOG_TM4C123 34 // Watchdog Timers 0 and 1
|
||||
#define INT_TIMER0A_TM4C123 35 // 16/32-Bit Timer 0A
|
||||
#define INT_TIMER0B_TM4C123 36 // 16/32-Bit Timer 0B
|
||||
#define INT_TIMER1A_TM4C123 37 // 16/32-Bit Timer 1A
|
||||
#define INT_TIMER1B_TM4C123 38 // 16/32-Bit Timer 1B
|
||||
#define INT_TIMER2A_TM4C123 39 // 16/32-Bit Timer 2A
|
||||
#define INT_TIMER2B_TM4C123 40 // 16/32-Bit Timer 2B
|
||||
#define INT_COMP0_TM4C123 41 // Analog Comparator 0
|
||||
#define INT_COMP1_TM4C123 42 // Analog Comparator 1
|
||||
#define INT_COMP2_TM4C123 43 // Analog Comparator 2
|
||||
#define INT_SYSCTL_TM4C123 44 // System Control
|
||||
#define INT_FLASH_TM4C123 45 // Flash Memory Control and EEPROM
|
||||
// Control
|
||||
#define INT_GPIOF_TM4C123 46 // GPIO Port F
|
||||
#define INT_GPIOG_TM4C123 47 // GPIO Port G
|
||||
#define INT_GPIOH_TM4C123 48 // GPIO Port H
|
||||
#define INT_UART2_TM4C123 49 // UART2
|
||||
#define INT_SSI1_TM4C123 50 // SSI1
|
||||
#define INT_TIMER3A_TM4C123 51 // 16/32-Bit Timer 3A
|
||||
#define INT_TIMER3B_TM4C123 52 // Timer 3B
|
||||
#define INT_I2C1_TM4C123 53 // I2C1
|
||||
#define INT_QEI1_TM4C123 54 // QEI1
|
||||
#define INT_CAN0_TM4C123 55 // CAN0
|
||||
#define INT_CAN1_TM4C123 56 // CAN1
|
||||
#define INT_HIBERNATE_TM4C123 59 // Hibernation Module
|
||||
#define INT_USB0_TM4C123 60 // USB
|
||||
#define INT_PWM0_3_TM4C123 61 // PWM Generator 3
|
||||
#define INT_UDMA_TM4C123 62 // uDMA Software
|
||||
#define INT_UDMAERR_TM4C123 63 // uDMA Error
|
||||
#define INT_ADC1SS0_TM4C123 64 // ADC1 Sequence 0
|
||||
#define INT_ADC1SS1_TM4C123 65 // ADC1 Sequence 1
|
||||
#define INT_ADC1SS2_TM4C123 66 // ADC1 Sequence 2
|
||||
#define INT_ADC1SS3_TM4C123 67 // ADC1 Sequence 3
|
||||
#define INT_GPIOJ_TM4C123 70 // GPIO Port J
|
||||
#define INT_GPIOK_TM4C123 71 // GPIO Port K
|
||||
#define INT_GPIOL_TM4C123 72 // GPIO Port L
|
||||
#define INT_SSI2_TM4C123 73 // SSI2
|
||||
#define INT_SSI3_TM4C123 74 // SSI3
|
||||
#define INT_UART3_TM4C123 75 // UART3
|
||||
#define INT_UART4_TM4C123 76 // UART4
|
||||
#define INT_UART5_TM4C123 77 // UART5
|
||||
#define INT_UART6_TM4C123 78 // UART6
|
||||
#define INT_UART7_TM4C123 79 // UART7
|
||||
#define INT_I2C2_TM4C123 84 // I2C2
|
||||
#define INT_I2C3_TM4C123 85 // I2C3
|
||||
#define INT_TIMER4A_TM4C123 86 // 16/32-Bit Timer 4A
|
||||
#define INT_TIMER4B_TM4C123 87 // 16/32-Bit Timer 4B
|
||||
#define INT_TIMER5A_TM4C123 108 // 16/32-Bit Timer 5A
|
||||
#define INT_TIMER5B_TM4C123 109 // 16/32-Bit Timer 5B
|
||||
#define INT_WTIMER0A_TM4C123 110 // 32/64-Bit Timer 0A
|
||||
#define INT_WTIMER0B_TM4C123 111 // 32/64-Bit Timer 0B
|
||||
#define INT_WTIMER1A_TM4C123 112 // 32/64-Bit Timer 1A
|
||||
#define INT_WTIMER1B_TM4C123 113 // 32/64-Bit Timer 1B
|
||||
#define INT_WTIMER2A_TM4C123 114 // 32/64-Bit Timer 2A
|
||||
#define INT_WTIMER2B_TM4C123 115 // 32/64-Bit Timer 2B
|
||||
#define INT_WTIMER3A_TM4C123 116 // 32/64-Bit Timer 3A
|
||||
#define INT_WTIMER3B_TM4C123 117 // 32/64-Bit Timer 3B
|
||||
#define INT_WTIMER4A_TM4C123 118 // 32/64-Bit Timer 4A
|
||||
#define INT_WTIMER4B_TM4C123 119 // 32/64-Bit Timer 4B
|
||||
#define INT_WTIMER5A_TM4C123 120 // 32/64-Bit Timer 5A
|
||||
#define INT_WTIMER5B_TM4C123 121 // 32/64-Bit Timer 5B
|
||||
#define INT_SYSEXC_TM4C123 122 // System Exception (imprecise)
|
||||
#define INT_I2C4_TM4C123 125 // I2C4
|
||||
#define INT_I2C5_TM4C123 126 // I2C5
|
||||
#define INT_GPIOM_TM4C123 127 // GPIO Port M
|
||||
#define INT_GPION_TM4C123 128 // GPIO Port N
|
||||
#define INT_GPIOP0_TM4C123 132 // GPIO Port P (Summary or P0)
|
||||
#define INT_GPIOP1_TM4C123 133 // GPIO Port P1
|
||||
#define INT_GPIOP2_TM4C123 134 // GPIO Port P2
|
||||
#define INT_GPIOP3_TM4C123 135 // GPIO Port P3
|
||||
#define INT_GPIOP4_TM4C123 136 // GPIO Port P4
|
||||
#define INT_GPIOP5_TM4C123 137 // GPIO Port P5
|
||||
#define INT_GPIOP6_TM4C123 138 // GPIO Port P6
|
||||
#define INT_GPIOP7_TM4C123 139 // GPIO Port P7
|
||||
#define INT_GPIOQ0_TM4C123 140 // GPIO Port Q (Summary or Q0)
|
||||
#define INT_GPIOQ1_TM4C123 141 // GPIO Port Q1
|
||||
#define INT_GPIOQ2_TM4C123 142 // GPIO Port Q2
|
||||
#define INT_GPIOQ3_TM4C123 143 // GPIO Port Q3
|
||||
#define INT_GPIOQ4_TM4C123 144 // GPIO Port Q4
|
||||
#define INT_GPIOQ5_TM4C123 145 // GPIO Port Q5
|
||||
#define INT_GPIOQ6_TM4C123 146 // GPIO Port Q6
|
||||
#define INT_GPIOQ7_TM4C123 147 // GPIO Port Q7
|
||||
#define INT_PWM1_0_TM4C123 150 // PWM1 Generator 0
|
||||
#define INT_PWM1_1_TM4C123 151 // PWM1 Generator 1
|
||||
#define INT_PWM1_2_TM4C123 152 // PWM1 Generator 2
|
||||
#define INT_PWM1_3_TM4C123 153 // PWM1 Generator 3
|
||||
#define INT_PWM1_FAULT_TM4C123 154 // PWM1 Fault
|
||||
#define NUM_INTERRUPTS_TM4C123 155
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// TM4C129 Class Interrupts
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_GPIOA_TM4C129 16 // GPIO Port A
|
||||
#define INT_GPIOB_TM4C129 17 // GPIO Port B
|
||||
#define INT_GPIOC_TM4C129 18 // GPIO Port C
|
||||
#define INT_GPIOD_TM4C129 19 // GPIO Port D
|
||||
#define INT_GPIOE_TM4C129 20 // GPIO Port E
|
||||
#define INT_UART0_TM4C129 21 // UART0
|
||||
#define INT_UART1_TM4C129 22 // UART1
|
||||
#define INT_SSI0_TM4C129 23 // SSI0
|
||||
#define INT_I2C0_TM4C129 24 // I2C0
|
||||
#define INT_PWM0_FAULT_TM4C129 25 // PWM Fault
|
||||
#define INT_PWM0_0_TM4C129 26 // PWM Generator 0
|
||||
#define INT_PWM0_1_TM4C129 27 // PWM Generator 1
|
||||
#define INT_PWM0_2_TM4C129 28 // PWM Generator 2
|
||||
#define INT_QEI0_TM4C129 29 // QEI0
|
||||
#define INT_ADC0SS0_TM4C129 30 // ADC0 Sequence 0
|
||||
#define INT_ADC0SS1_TM4C129 31 // ADC0 Sequence 1
|
||||
#define INT_ADC0SS2_TM4C129 32 // ADC0 Sequence 2
|
||||
#define INT_ADC0SS3_TM4C129 33 // ADC0 Sequence 3
|
||||
#define INT_WATCHDOG_TM4C129 34 // Watchdog Timers 0 and 1
|
||||
#define INT_TIMER0A_TM4C129 35 // 16/32-Bit Timer 0A
|
||||
#define INT_TIMER0B_TM4C129 36 // 16/32-Bit Timer 0B
|
||||
#define INT_TIMER1A_TM4C129 37 // 16/32-Bit Timer 1A
|
||||
#define INT_TIMER1B_TM4C129 38 // 16/32-Bit Timer 1B
|
||||
#define INT_TIMER2A_TM4C129 39 // 16/32-Bit Timer 2A
|
||||
#define INT_TIMER2B_TM4C129 40 // 16/32-Bit Timer 2B
|
||||
#define INT_COMP0_TM4C129 41 // Analog Comparator 0
|
||||
#define INT_COMP1_TM4C129 42 // Analog Comparator 1
|
||||
#define INT_COMP2_TM4C129 43 // Analog Comparator 2
|
||||
#define INT_SYSCTL_TM4C129 44 // System Control
|
||||
#define INT_FLASH_TM4C129 45 // Flash Memory Control
|
||||
#define INT_GPIOF_TM4C129 46 // GPIO Port F
|
||||
#define INT_GPIOG_TM4C129 47 // GPIO Port G
|
||||
#define INT_GPIOH_TM4C129 48 // GPIO Port H
|
||||
#define INT_UART2_TM4C129 49 // UART2
|
||||
#define INT_SSI1_TM4C129 50 // SSI1
|
||||
#define INT_TIMER3A_TM4C129 51 // 16/32-Bit Timer 3A
|
||||
#define INT_TIMER3B_TM4C129 52 // 16/32-Bit Timer 3B
|
||||
#define INT_I2C1_TM4C129 53 // I2C1
|
||||
#define INT_CAN0_TM4C129 54 // CAN 0
|
||||
#define INT_CAN1_TM4C129 55 // CAN1
|
||||
#define INT_EMAC0_TM4C129 56 // Ethernet MAC
|
||||
#define INT_HIBERNATE_TM4C129 57 // HIB
|
||||
#define INT_USB0_TM4C129 58 // USB MAC
|
||||
#define INT_PWM0_3_TM4C129 59 // PWM Generator 3
|
||||
#define INT_UDMA_TM4C129 60 // uDMA 0 Software
|
||||
#define INT_UDMAERR_TM4C129 61 // uDMA 0 Error
|
||||
#define INT_ADC1SS0_TM4C129 62 // ADC1 Sequence 0
|
||||
#define INT_ADC1SS1_TM4C129 63 // ADC1 Sequence 1
|
||||
#define INT_ADC1SS2_TM4C129 64 // ADC1 Sequence 2
|
||||
#define INT_ADC1SS3_TM4C129 65 // ADC1 Sequence 3
|
||||
#define INT_EPI0_TM4C129 66 // EPI 0
|
||||
#define INT_GPIOJ_TM4C129 67 // GPIO Port J
|
||||
#define INT_GPIOK_TM4C129 68 // GPIO Port K
|
||||
#define INT_GPIOL_TM4C129 69 // GPIO Port L
|
||||
#define INT_SSI2_TM4C129 70 // SSI 2
|
||||
#define INT_SSI3_TM4C129 71 // SSI 3
|
||||
#define INT_UART3_TM4C129 72 // UART 3
|
||||
#define INT_UART4_TM4C129 73 // UART 4
|
||||
#define INT_UART5_TM4C129 74 // UART 5
|
||||
#define INT_UART6_TM4C129 75 // UART 6
|
||||
#define INT_UART7_TM4C129 76 // UART 7
|
||||
#define INT_I2C2_TM4C129 77 // I2C 2
|
||||
#define INT_I2C3_TM4C129 78 // I2C 3
|
||||
#define INT_TIMER4A_TM4C129 79 // Timer 4A
|
||||
#define INT_TIMER4B_TM4C129 80 // Timer 4B
|
||||
#define INT_TIMER5A_TM4C129 81 // Timer 5A
|
||||
#define INT_TIMER5B_TM4C129 82 // Timer 5B
|
||||
#define INT_SYSEXC_TM4C129 83 // Floating-Point Exception
|
||||
// (imprecise)
|
||||
#define INT_I2C4_TM4C129 86 // I2C 4
|
||||
#define INT_I2C5_TM4C129 87 // I2C 5
|
||||
#define INT_GPIOM_TM4C129 88 // GPIO Port M
|
||||
#define INT_GPION_TM4C129 89 // GPIO Port N
|
||||
#define INT_TAMPER0_TM4C129 91 // Tamper
|
||||
#define INT_GPIOP0_TM4C129 92 // GPIO Port P (Summary or P0)
|
||||
#define INT_GPIOP1_TM4C129 93 // GPIO Port P1
|
||||
#define INT_GPIOP2_TM4C129 94 // GPIO Port P2
|
||||
#define INT_GPIOP3_TM4C129 95 // GPIO Port P3
|
||||
#define INT_GPIOP4_TM4C129 96 // GPIO Port P4
|
||||
#define INT_GPIOP5_TM4C129 97 // GPIO Port P5
|
||||
#define INT_GPIOP6_TM4C129 98 // GPIO Port P6
|
||||
#define INT_GPIOP7_TM4C129 99 // GPIO Port P7
|
||||
#define INT_GPIOQ0_TM4C129 100 // GPIO Port Q (Summary or Q0)
|
||||
#define INT_GPIOQ1_TM4C129 101 // GPIO Port Q1
|
||||
#define INT_GPIOQ2_TM4C129 102 // GPIO Port Q2
|
||||
#define INT_GPIOQ3_TM4C129 103 // GPIO Port Q3
|
||||
#define INT_GPIOQ4_TM4C129 104 // GPIO Port Q4
|
||||
#define INT_GPIOQ5_TM4C129 105 // GPIO Port Q5
|
||||
#define INT_GPIOQ6_TM4C129 106 // GPIO Port Q6
|
||||
#define INT_GPIOQ7_TM4C129 107 // GPIO Port Q7
|
||||
#define INT_GPIOR_TM4C129 108 // GPIO Port R
|
||||
#define INT_GPIOS_TM4C129 109 // GPIO Port S
|
||||
#define INT_SHA0_TM4C129 110 // SHA/MD5
|
||||
#define INT_AES0_TM4C129 111 // AES
|
||||
#define INT_DES0_TM4C129 112 // DES
|
||||
#define INT_LCD0_TM4C129 113 // LCD
|
||||
#define INT_TIMER6A_TM4C129 114 // 16/32-Bit Timer 6A
|
||||
#define INT_TIMER6B_TM4C129 115 // 16/32-Bit Timer 6B
|
||||
#define INT_TIMER7A_TM4C129 116 // 16/32-Bit Timer 7A
|
||||
#define INT_TIMER7B_TM4C129 117 // 16/32-Bit Timer 7B
|
||||
#define INT_I2C6_TM4C129 118 // I2C 6
|
||||
#define INT_I2C7_TM4C129 119 // I2C 7
|
||||
#define INT_ONEWIRE0_TM4C129 121 // 1-Wire
|
||||
#define INT_I2C8_TM4C129 125 // I2C 8
|
||||
#define INT_I2C9_TM4C129 126 // I2C 9
|
||||
#define INT_GPIOT_TM4C129 127 // GPIO T
|
||||
#define NUM_INTERRUPTS_TM4C129 129
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// TM4C123 Interrupt Class Definition
|
||||
//
|
||||
//*****************************************************************************
|
||||
#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \
|
||||
defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \
|
||||
defined(TARGET_IS_TM4C123_RB1) || defined(PART_TM4C1230C3PM) || \
|
||||
defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \
|
||||
defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \
|
||||
defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \
|
||||
defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \
|
||||
defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \
|
||||
defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \
|
||||
defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \
|
||||
defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \
|
||||
defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \
|
||||
defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \
|
||||
defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \
|
||||
defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \
|
||||
defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \
|
||||
defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \
|
||||
defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \
|
||||
defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \
|
||||
defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \
|
||||
defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \
|
||||
defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \
|
||||
defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \
|
||||
defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \
|
||||
defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \
|
||||
defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \
|
||||
defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \
|
||||
defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH6ZXR)
|
||||
#define INT_RESOLVE(intname, class) intname##TM4C123
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// TM4C129 Interrupt Class Definition
|
||||
//
|
||||
//*****************************************************************************
|
||||
#elif defined(TARGET_IS_TM4C129_RA0) || defined(PART_TM4C1290NCPDT) || \
|
||||
defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) || \
|
||||
defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || \
|
||||
defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || \
|
||||
defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || \
|
||||
defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || \
|
||||
defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || \
|
||||
defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || \
|
||||
defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || \
|
||||
defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || \
|
||||
defined(PART_TM4C129XNCZAD)
|
||||
#define INT_RESOLVE(intname, class) intname##TM4C129
|
||||
#else
|
||||
#define INT_DEVICE_CLASS "UNKNOWN"
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_CONCAT(intname, class) INT_RESOLVE(intname, class)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the interrupt assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_ADC0SS0 INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC0SS1 INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC0SS2 INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC0SS3 INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC1SS0 INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC1SS1 INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC1SS2 INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS)
|
||||
#define INT_ADC1SS3 INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS)
|
||||
#define INT_AES0 INT_CONCAT(INT_AES0_, INT_DEVICE_CLASS)
|
||||
#define INT_CAN0 INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS)
|
||||
#define INT_CAN1 INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS)
|
||||
#define INT_COMP0 INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS)
|
||||
#define INT_COMP1 INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS)
|
||||
#define INT_COMP2 INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS)
|
||||
#define INT_DES0 INT_CONCAT(INT_DES0_, INT_DEVICE_CLASS)
|
||||
#define INT_EMAC0 INT_CONCAT(INT_EMAC0_, INT_DEVICE_CLASS)
|
||||
#define INT_EPI0 INT_CONCAT(INT_EPI0_, INT_DEVICE_CLASS)
|
||||
#define INT_FLASH INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOA INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOB INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOC INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOD INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOE INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOF INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOG INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOH INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOJ INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOK INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOL INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOM INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS)
|
||||
#define INT_GPION INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP0 INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP1 INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP2 INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP3 INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP4 INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP5 INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP6 INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOP7 INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ0 INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ1 INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ2 INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ3 INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ4 INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ5 INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ6 INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOQ7 INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOR INT_CONCAT(INT_GPIOR_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOS INT_CONCAT(INT_GPIOS_, INT_DEVICE_CLASS)
|
||||
#define INT_GPIOT INT_CONCAT(INT_GPIOT_, INT_DEVICE_CLASS)
|
||||
#define INT_HIBERNATE INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C0 INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C1 INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C2 INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C3 INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C4 INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C5 INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C6 INT_CONCAT(INT_I2C6_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C7 INT_CONCAT(INT_I2C7_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C8 INT_CONCAT(INT_I2C8_, INT_DEVICE_CLASS)
|
||||
#define INT_I2C9 INT_CONCAT(INT_I2C9_, INT_DEVICE_CLASS)
|
||||
#define INT_LCD0 INT_CONCAT(INT_LCD0_, INT_DEVICE_CLASS)
|
||||
#define INT_ONEWIRE0 INT_CONCAT(INT_ONEWIRE0_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM0_0 INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM0_1 INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM0_2 INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM0_3 INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM0_FAULT INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM1_0 INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM1_1 INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM1_2 INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM1_3 INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS)
|
||||
#define INT_PWM1_FAULT INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS)
|
||||
#define INT_QEI0 INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS)
|
||||
#define INT_QEI1 INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS)
|
||||
#define INT_SHA0 INT_CONCAT(INT_SHA0_, INT_DEVICE_CLASS)
|
||||
#define INT_SSI0 INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS)
|
||||
#define INT_SSI1 INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS)
|
||||
#define INT_SSI2 INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS)
|
||||
#define INT_SSI3 INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS)
|
||||
#define INT_SYSCTL INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS)
|
||||
#define INT_SYSEXC INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS)
|
||||
#define INT_TAMPER0 INT_CONCAT(INT_TAMPER0_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER0A INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER0B INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER1A INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER1B INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER2A INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER2B INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER3A INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER3B INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER4A INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER4B INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER5A INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER5B INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER6A INT_CONCAT(INT_TIMER6A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER6B INT_CONCAT(INT_TIMER6B_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER7A INT_CONCAT(INT_TIMER7A_, INT_DEVICE_CLASS)
|
||||
#define INT_TIMER7B INT_CONCAT(INT_TIMER7B_, INT_DEVICE_CLASS)
|
||||
#define INT_UART0 INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS)
|
||||
#define INT_UART1 INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS)
|
||||
#define INT_UART2 INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS)
|
||||
#define INT_UART3 INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS)
|
||||
#define INT_UART4 INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS)
|
||||
#define INT_UART5 INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS)
|
||||
#define INT_UART6 INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS)
|
||||
#define INT_UART7 INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS)
|
||||
#define INT_UDMA INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS)
|
||||
#define INT_UDMAERR INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS)
|
||||
#define INT_USB0 INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS)
|
||||
#define INT_WATCHDOG INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER0A INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER0B INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER1A INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER1B INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER2A INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER2B INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER3A INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER3B INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER4A INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER4B INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER5A INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS)
|
||||
#define INT_WTIMER5B INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the total number of interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NUM_INTERRUPTS INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the total number of priority levels.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NUM_PRIORITY 8
|
||||
#define NUM_PRIORITY_BITS 3
|
||||
|
||||
#endif // __HW_INTS_H__
|
||||
|
|
@ -0,0 +1,575 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_lcd.h - Defines and macros used when accessing the LCD controller.
|
||||
//
|
||||
// Copyright (c) 2011-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_LCD_H__
|
||||
#define __HW_LCD_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the LCD register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_O_PID 0x00000000 // LCD PID Register Format
|
||||
#define LCD_O_CTL 0x00000004 // LCD Control
|
||||
#define LCD_O_LIDDCTL 0x0000000C // LCD LIDD Control
|
||||
#define LCD_O_LIDDCS0CFG 0x00000010 // LCD LIDD CS0 Configuration
|
||||
#define LCD_O_LIDDCS0ADDR 0x00000014 // LIDD CS0 Read/Write Address
|
||||
#define LCD_O_LIDDCS0DATA 0x00000018 // LIDD CS0 Data Read/Write
|
||||
// Initiation
|
||||
#define LCD_O_LIDDCS1CFG 0x0000001C // LIDD CS1 Configuration
|
||||
#define LCD_O_LIDDCS1ADDR 0x00000020 // LIDD CS1 Address Read/Write
|
||||
// Initiation
|
||||
#define LCD_O_LIDDCS1DATA 0x00000024 // LIDD CS1 Data Read/Write
|
||||
// Initiation
|
||||
#define LCD_O_RASTRCTL 0x00000028 // LCD Raster Control
|
||||
#define LCD_O_RASTRTIM0 0x0000002C // LCD Raster Timing 0
|
||||
#define LCD_O_RASTRTIM1 0x00000030 // LCD Raster Timing 1
|
||||
#define LCD_O_RASTRTIM2 0x00000034 // LCD Raster Timing 2
|
||||
#define LCD_O_RASTRSUBP1 0x00000038 // LCD Raster Subpanel Display 1
|
||||
#define LCD_O_RASTRSUBP2 0x0000003C // LCD Raster Subpanel Display 2
|
||||
#define LCD_O_DMACTL 0x00000040 // LCD DMA Control
|
||||
#define LCD_O_DMABAFB0 0x00000044 // LCD DMA Frame Buffer 0 Base
|
||||
// Address
|
||||
#define LCD_O_DMACAFB0 0x00000048 // LCD DMA Frame Buffer 0 Ceiling
|
||||
// Address
|
||||
#define LCD_O_DMABAFB1 0x0000004C // LCD DMA Frame Buffer 1 Base
|
||||
// Address
|
||||
#define LCD_O_DMACAFB1 0x00000050 // LCD DMA Frame Buffer 1 Ceiling
|
||||
// Address
|
||||
#define LCD_O_SYSCFG 0x00000054 // LCD System Configuration
|
||||
// Register
|
||||
#define LCD_O_RISSET 0x00000058 // LCD Interrupt Raw Status and Set
|
||||
// Register
|
||||
#define LCD_O_MISCLR 0x0000005C // LCD Interrupt Status and Clear
|
||||
#define LCD_O_IM 0x00000060 // LCD Interrupt Mask
|
||||
#define LCD_O_IENC 0x00000064 // LCD Interrupt Enable Clear
|
||||
#define LCD_O_CLKEN 0x0000006C // LCD Clock Enable
|
||||
#define LCD_O_CLKRESET 0x00000070 // LCD Clock Resets
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_PID register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_PID_MAJOR_M 0x00000700 // Major Release Number
|
||||
#define LCD_PID_MINOR_M 0x0000003F // Minor Release Number
|
||||
#define LCD_PID_MAJOR_S 8
|
||||
#define LCD_PID_MINOR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_CTL_CLKDIV_M 0x0000FF00 // Clock Divisor
|
||||
#define LCD_CTL_UFLOWRST 0x00000002 // Underflow Restart
|
||||
#define LCD_CTL_LCDMODE 0x00000001 // LCD Mode Select
|
||||
#define LCD_CTL_CLKDIV_S 8
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_LIDDCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_LIDDCTL_DMACS 0x00000200 // CS0/CS1 Select for LIDD DMA
|
||||
// Writes
|
||||
#define LCD_LIDDCTL_DMAEN 0x00000100 // LIDD DMA Enable
|
||||
#define LCD_LIDDCTL_CS1E1 0x00000080 // Chip Select 1 (CS1)/Enable 1(E1)
|
||||
// Polarity Control
|
||||
#define LCD_LIDDCTL_CS0E0 0x00000040 // Chip Select 0 (CS0)/Enable 0
|
||||
// (E0) Polarity Control
|
||||
#define LCD_LIDDCTL_WRDIRINV 0x00000020 // Write Strobe (WR) /Direction
|
||||
// (DIR) Polarity Control
|
||||
#define LCD_LIDDCTL_RDEN 0x00000010 // Read Strobe (RD) /Direct Enable
|
||||
// (EN) Polarity Control
|
||||
#define LCD_LIDDCTL_ALE 0x00000008 // Address Latch Enable (ALE)
|
||||
// Polarity Control
|
||||
#define LCD_LIDDCTL_MODE_M 0x00000007 // LIDD Mode Select
|
||||
#define LCD_LIDDCTL_MODE_SYNCM68 \
|
||||
0x00000000 // Synchronous Motorola 6800 Mode
|
||||
#define LCD_LIDDCTL_MODE_ASYNCM68 \
|
||||
0x00000001 // Asynchronous Motorola 6800 Mode
|
||||
#define LCD_LIDDCTL_MODE_SYNCM80 \
|
||||
0x00000002 // Synchronous Intel 8080 mode
|
||||
#define LCD_LIDDCTL_MODE_ASYNCM80 \
|
||||
0x00000003 // Asynchronous Intel 8080 mode
|
||||
#define LCD_LIDDCTL_MODE_ASYNCHIT \
|
||||
0x00000004 // Asynchronous Hitachi mode
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_LIDDCS0CFG
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_LIDDCS0CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles
|
||||
#define LCD_LIDDCS0CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration
|
||||
// Cycles
|
||||
#define LCD_LIDDCS0CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles
|
||||
#define LCD_LIDDCS0CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles
|
||||
#define LCD_LIDDCS0CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles
|
||||
#define LCD_LIDDCS0CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles
|
||||
#define LCD_LIDDCS0CFG_GAP_M 0x00000003 // Field value defines the number
|
||||
// of LCDMCLK cycles (GAP +1)
|
||||
// between the end of one CS0
|
||||
// (LCDAC) device access and the
|
||||
// start of another CS0 (LCDAC)
|
||||
// device access unless the two
|
||||
// accesses are both reads
|
||||
#define LCD_LIDDCS0CFG_WRSU_S 27
|
||||
#define LCD_LIDDCS0CFG_WRDUR_S 21
|
||||
#define LCD_LIDDCS0CFG_WRHOLD_S 17
|
||||
#define LCD_LIDDCS0CFG_RDSU_S 12
|
||||
#define LCD_LIDDCS0CFG_RDDUR_S 6
|
||||
#define LCD_LIDDCS0CFG_RDHOLD_S 2
|
||||
#define LCD_LIDDCS0CFG_GAP_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_LIDDCS0ADDR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_LIDDCS0ADDR_CS0ADDR_M \
|
||||
0x0000FFFF // LCD Address
|
||||
#define LCD_LIDDCS0ADDR_CS0ADDR_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_LIDDCS0DATA
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_LIDDCS0DATA_CS0DATA_M \
|
||||
0x0000FFFF // LCD Data Read/Write
|
||||
#define LCD_LIDDCS0DATA_CS0DATA_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_LIDDCS1CFG
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_LIDDCS1CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles
|
||||
#define LCD_LIDDCS1CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration
|
||||
// Cycles
|
||||
#define LCD_LIDDCS1CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles
|
||||
#define LCD_LIDDCS1CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles
|
||||
#define LCD_LIDDCS1CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles
|
||||
#define LCD_LIDDCS1CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles
|
||||
#define LCD_LIDDCS1CFG_GAP_M 0x00000003 // Field value defines the number
|
||||
// of LCDMCLK cycles (GAP + 1)
|
||||
// between the end of one CS1
|
||||
// (LCDAC) device access and the
|
||||
// start of another CS0 (LCDAC)
|
||||
// device access unless the two
|
||||
// accesses are both reads
|
||||
#define LCD_LIDDCS1CFG_WRSU_S 27
|
||||
#define LCD_LIDDCS1CFG_WRDUR_S 21
|
||||
#define LCD_LIDDCS1CFG_WRHOLD_S 17
|
||||
#define LCD_LIDDCS1CFG_RDSU_S 12
|
||||
#define LCD_LIDDCS1CFG_RDDUR_S 6
|
||||
#define LCD_LIDDCS1CFG_RDHOLD_S 2
|
||||
#define LCD_LIDDCS1CFG_GAP_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_LIDDCS1ADDR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_LIDDCS1ADDR_CS1ADDR_M \
|
||||
0x0000FFFF // LCD Address Bus
|
||||
#define LCD_LIDDCS1ADDR_CS1ADDR_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_LIDDCS1DATA
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_LIDDCS1DATA_CS0DATA_M \
|
||||
0x0000FFFF // LCD Data Read/Write Initiation
|
||||
#define LCD_LIDDCS1DATA_CS0DATA_S \
|
||||
0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_RASTRCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_RASTRCTL_TFT24UPCK 0x04000000 // 24-bit TFT Mode Packing
|
||||
#define LCD_RASTRCTL_TFT24 0x02000000 // 24-Bit TFT Mode
|
||||
#define LCD_RASTRCTL_FRMBUFSZ 0x01000000 // Frame Buffer Select
|
||||
#define LCD_RASTRCTL_TFTMAP 0x00800000 // TFT Mode Alternate Signal
|
||||
// Mapping for Palettized
|
||||
// Framebuffer
|
||||
#define LCD_RASTRCTL_NIBMODE 0x00400000 // Nibble Mode
|
||||
#define LCD_RASTRCTL_PALMODE_M 0x00300000 // Pallette Loading Mode
|
||||
#define LCD_RASTRCTL_PALMODE_PALDAT \
|
||||
0x00000000 // Palette and data loading, reset
|
||||
// value
|
||||
#define LCD_RASTRCTL_PALMODE_PAL \
|
||||
0x00100000 // Palette loading only
|
||||
#define LCD_RASTRCTL_PALMODE_DAT \
|
||||
0x00200000 // Data loading only
|
||||
#define LCD_RASTRCTL_REQDLY_M 0x000FF000 // Palette Loading Delay
|
||||
#define LCD_RASTRCTL_MONO8B 0x00000200 // Mono 8-Bit
|
||||
#define LCD_RASTRCTL_RDORDER 0x00000100 // Raster Data Order Select
|
||||
#define LCD_RASTRCTL_LCDTFT 0x00000080 // LCD TFT
|
||||
#define LCD_RASTRCTL_LCDBW 0x00000002 // LCD Monochrome
|
||||
#define LCD_RASTRCTL_LCDEN 0x00000001 // LCD Controller Enable for Raster
|
||||
// Operations
|
||||
#define LCD_RASTRCTL_REQDLY_S 12
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_RASTRTIM0
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_RASTRTIM0_HBP_M 0xFF000000 // Horizontal Back Porch Lowbits
|
||||
#define LCD_RASTRTIM0_HFP_M 0x00FF0000 // Horizontal Front Porch Lowbits
|
||||
#define LCD_RASTRTIM0_HSW_M 0x0000FC00 // Horizontal Sync Pulse Width
|
||||
// Lowbits
|
||||
#define LCD_RASTRTIM0_PPL_M 0x000003F0 // Pixels-per-line LSB[9:4]
|
||||
#define LCD_RASTRTIM0_MSBPPL 0x00000008 // Pixels-per-line MSB[10]
|
||||
#define LCD_RASTRTIM0_HBP_S 24
|
||||
#define LCD_RASTRTIM0_HFP_S 16
|
||||
#define LCD_RASTRTIM0_HSW_S 10
|
||||
#define LCD_RASTRTIM0_PPL_S 4
|
||||
#define LCD_RASTRTIM0_MSBPPL_S 3
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_RASTRTIM1
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_RASTRTIM1_VBP_M 0xFF000000 // Vertical Back Porch
|
||||
#define LCD_RASTRTIM1_VFP_M 0x00FF0000 // Vertical Front Porch
|
||||
#define LCD_RASTRTIM1_VSW_M 0x0000FC00 // Vertical Sync Width Pulse
|
||||
#define LCD_RASTRTIM1_LPP_M 0x000003FF // Lines Per Panel
|
||||
#define LCD_RASTRTIM1_VBP_S 24
|
||||
#define LCD_RASTRTIM1_VFP_S 16
|
||||
#define LCD_RASTRTIM1_VSW_S 10
|
||||
#define LCD_RASTRTIM1_LPP_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_RASTRTIM2
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_RASTRTIM2_HSW_M 0x78000000 // Bits 9:6 of the horizontal sync
|
||||
// width field
|
||||
#define LCD_RASTRTIM2_MSBLPP 0x04000000 // MSB of Lines Per Panel
|
||||
#define LCD_RASTRTIM2_PXLCLKCTL 0x02000000 // Hsync/Vsync Pixel Clock Control
|
||||
// On/Off
|
||||
#define LCD_RASTRTIM2_PSYNCRF 0x01000000 // Program HSYNC/VSYNC Rise or Fall
|
||||
#define LCD_RASTRTIM2_INVOE 0x00800000 // Invert Output Enable
|
||||
#define LCD_RASTRTIM2_INVPXLCLK 0x00400000 // Invert Pixel Clock
|
||||
#define LCD_RASTRTIM2_IHS 0x00200000 // Invert Hysync
|
||||
#define LCD_RASTRTIM2_IVS 0x00100000 // Invert Vsync
|
||||
#define LCD_RASTRTIM2_ACBI_M 0x000F0000 // AC Bias Pins Transitions per
|
||||
// Interrupt
|
||||
#define LCD_RASTRTIM2_ACBF_M 0x0000FF00 // AC Bias Pin Frequency
|
||||
#define LCD_RASTRTIM2_MSBHBP_M 0x00000030 // Bits 9:8 of the horizontal back
|
||||
// porch field
|
||||
#define LCD_RASTRTIM2_MSBHFP_M 0x00000003 // Bits 9:8 of the horizontal front
|
||||
// porch field
|
||||
#define LCD_RASTRTIM2_HSW_S 27
|
||||
#define LCD_RASTRTIM2_MSBLPP_S 26
|
||||
#define LCD_RASTRTIM2_ACBI_S 16
|
||||
#define LCD_RASTRTIM2_ACBF_S 8
|
||||
#define LCD_RASTRTIM2_MSBHBP_S 4
|
||||
#define LCD_RASTRTIM2_MSBHFP_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_RASTRSUBP1
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_RASTRSUBP1_SPEN 0x80000000 // Sub Panel Enable
|
||||
#define LCD_RASTRSUBP1_HOLS 0x20000000 // High or Low Signal
|
||||
#define LCD_RASTRSUBP1_LPPT_M 0x03FF0000 // Line Per Panel Threshold
|
||||
#define LCD_RASTRSUBP1_DPDLSB_M 0x0000FFFF // Default Pixel Data LSB[15:0]
|
||||
#define LCD_RASTRSUBP1_LPPT_S 16
|
||||
#define LCD_RASTRSUBP1_DPDLSB_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_RASTRSUBP2
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_RASTRSUBP2_LPPTMSB 0x00000100 // Lines Per Panel Threshold Bit 10
|
||||
#define LCD_RASTRSUBP2_DPDMSB_M 0x000000FF // Default Pixel Data MSB [23:16]
|
||||
#define LCD_RASTRSUBP2_DPDMSB_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_DMACTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_DMACTL_FIFORDY_M 0x00000700 // DMA FIFO threshold
|
||||
#define LCD_DMACTL_FIFORDY_8 0x00000000 // 8 words
|
||||
#define LCD_DMACTL_FIFORDY_16 0x00000100 // 16 words
|
||||
#define LCD_DMACTL_FIFORDY_32 0x00000200 // 32 words
|
||||
#define LCD_DMACTL_FIFORDY_64 0x00000300 // 64 words
|
||||
#define LCD_DMACTL_FIFORDY_128 0x00000400 // 128 words
|
||||
#define LCD_DMACTL_FIFORDY_256 0x00000500 // 256 words
|
||||
#define LCD_DMACTL_FIFORDY_512 0x00000600 // 512 words
|
||||
#define LCD_DMACTL_BURSTSZ_M 0x00000070 // Burst Size setting for DMA
|
||||
// transfers (all DMA transfers are
|
||||
// 32 bits wide):
|
||||
#define LCD_DMACTL_BURSTSZ_4 0x00000020 // burst size of 4
|
||||
#define LCD_DMACTL_BURSTSZ_8 0x00000030 // burst size of 8
|
||||
#define LCD_DMACTL_BURSTSZ_16 0x00000040 // burst size of 16
|
||||
#define LCD_DMACTL_BYTESWAP 0x00000008 // This bit controls the bytelane
|
||||
// ordering of the data on the
|
||||
// output of the DMA module
|
||||
#define LCD_DMACTL_BIGDEND 0x00000002 // Big Endian Enable
|
||||
#define LCD_DMACTL_FMODE 0x00000001 // Frame Mode
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_DMABAFB0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_DMABAFB0_FB0BA_M 0xFFFFFFFC // Frame Buffer 0 Base Address
|
||||
// pointer
|
||||
#define LCD_DMABAFB0_FB0BA_S 2
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_DMACAFB0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_DMACAFB0_FB0CA_M 0xFFFFFFFC // Frame Buffer 0 Ceiling Address
|
||||
// pointer
|
||||
#define LCD_DMACAFB0_FB0CA_S 2
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_DMABAFB1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_DMABAFB1_FB1BA_M 0xFFFFFFFC // Frame Buffer 1 Base Address
|
||||
// pointer
|
||||
#define LCD_DMABAFB1_FB1BA_S 2
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_DMACAFB1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_DMACAFB1_FB1CA_M 0xFFFFFFFC // Frame Buffer 1 Ceiling Address
|
||||
// pointer
|
||||
#define LCD_DMACAFB1_FB1CA_S 2
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_SYSCFG register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_SYSCFG_STDBY_M 0x00000030 // Standby Mode
|
||||
#define LCD_SYSCFG_STDBY_FORCE 0x00000000 // Force-standby mode: local
|
||||
// initiator is unconditionally
|
||||
// placed in standby state. Backup
|
||||
// mode, for debug only
|
||||
#define LCD_SYSCFG_STDBY_NONE 0x00000010 // No-standby mode: local initiator
|
||||
// is unconditionally placed out of
|
||||
// standby state. Backup mode, for
|
||||
// debug only
|
||||
#define LCD_SYSCFG_STDBY_SMART 0x00000020 // Smart-standby mode: local
|
||||
// initiator standby status depends
|
||||
// on local conditions, that is,
|
||||
// the module's functional
|
||||
// requirement from the initiator.
|
||||
// IP module shall not generate
|
||||
// (initiator-related) wakeup
|
||||
// events
|
||||
#define LCD_SYSCFG_IDLEMODE_M 0x0000000C // Idle Mode
|
||||
#define LCD_SYSCFG_IDLEMODE_FORCE \
|
||||
0x00000000 // Force-idle mode: local target's
|
||||
// idle state follows
|
||||
// (acknowledges) the system's idle
|
||||
// requests unconditionally, that
|
||||
// is, regardless of the IP
|
||||
// module's internal requirements.
|
||||
// Backup mode, for debug only
|
||||
#define LCD_SYSCFG_IDLEMODE_NONE \
|
||||
0x00000004 // No-idle mode: local target never
|
||||
// enters idle state. Backup mode,
|
||||
// for debug only
|
||||
#define LCD_SYSCFG_IDLEMODE_SMART \
|
||||
0x00000008 // Smart-idle mode: local target's
|
||||
// idle state eventually follows
|
||||
// (acknowledges) the system's idle
|
||||
// requests, depending on the IP
|
||||
// module's internal requirements.
|
||||
// IP module shall not generate
|
||||
// (IRQ- or DMA-requestrelated)
|
||||
// wakeup events
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_RISSET register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_RISSET_EOF1 0x00000200 // DMA End-of-Frame 1 Raw Interrupt
|
||||
// Status and Set
|
||||
#define LCD_RISSET_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt
|
||||
// Status and Set
|
||||
#define LCD_RISSET_PALLOAD 0x00000040 // DMA Palette Loaded Raw Interrupt
|
||||
// Status and Set
|
||||
#define LCD_RISSET_FIFOU 0x00000020 // DMA FIFO Underflow Raw Interrupt
|
||||
// Status and Set
|
||||
#define LCD_RISSET_ACBS 0x00000008 // AC Bias Count Raw Interrupt
|
||||
// Status and Set
|
||||
#define LCD_RISSET_SYNCS 0x00000004 // Frame Synchronization Lost Raw
|
||||
// Interrupt Status and Set
|
||||
#define LCD_RISSET_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt
|
||||
#define LCD_RISSET_DONE 0x00000001 // Raster or LIDD Frame Done
|
||||
// (shared, depends on whether
|
||||
// Raster or LIDD mode enabled) Raw
|
||||
// Interrupt Status and Set
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_MISCLR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_MISCLR_EOF1 0x00000200 // DMA End-of-Frame 1 Enabled
|
||||
// Interrupt and Clear
|
||||
#define LCD_MISCLR_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt
|
||||
// and Clear
|
||||
#define LCD_MISCLR_PALLOAD 0x00000040 // DMA Palette Loaded Enabled
|
||||
// Interrupt and Clear
|
||||
#define LCD_MISCLR_FIFOU 0x00000020 // DMA FIFO Underflow Enabled
|
||||
// Interrupt and Clear
|
||||
#define LCD_MISCLR_ACBS 0x00000008 // AC Bias Count Enabled Interrupt
|
||||
// and Clear
|
||||
#define LCD_MISCLR_SYNCS 0x00000004 // Frame Synchronization Lost
|
||||
// Enabled Interrupt and Clear
|
||||
#define LCD_MISCLR_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt
|
||||
#define LCD_MISCLR_DONE 0x00000001 // Raster or LIDD Frame Done
|
||||
// (shared, depends on whether
|
||||
// Raster or LIDD mode enabled)
|
||||
// Enabled Interrupt and Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_IM_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt
|
||||
// Enable Set
|
||||
#define LCD_IM_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt
|
||||
// Enable Set
|
||||
#define LCD_IM_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt
|
||||
// Enable Set
|
||||
#define LCD_IM_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt
|
||||
// Enable Set
|
||||
#define LCD_IM_ACBS 0x00000008 // AC Bias Count Interrupt Enable
|
||||
// Set
|
||||
#define LCD_IM_SYNCS 0x00000004 // Frame Synchronization Lost
|
||||
// Interrupt Enable Set
|
||||
#define LCD_IM_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt
|
||||
// Enable Set
|
||||
#define LCD_IM_DONE 0x00000001 // Raster or LIDD Frame Done
|
||||
// (shared, depends on whether
|
||||
// Raster or LIDD mode enabled)
|
||||
// Interrupt Enable Set
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_IENC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_IENC_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt
|
||||
// Enable Clear
|
||||
#define LCD_IENC_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt
|
||||
// Enable Clear
|
||||
#define LCD_IENC_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt
|
||||
// Enable Clear
|
||||
#define LCD_IENC_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt
|
||||
// Enable Clear
|
||||
#define LCD_IENC_ACBS 0x00000008 // AC Bias Count Interrupt Enable
|
||||
// Clear
|
||||
#define LCD_IENC_SYNCS 0x00000004 // Frame Synchronization Lost
|
||||
// Interrupt Enable Clear
|
||||
#define LCD_IENC_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt
|
||||
// Enable Clear
|
||||
#define LCD_IENC_DONE 0x00000001 // Raster or LIDD Frame Done
|
||||
// (shared, depends on whether
|
||||
// Raster or LIDD mode enabled)
|
||||
// Interrupt Enable Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_CLKEN register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_CLKEN_DMA 0x00000004 // DMA Clock Enable
|
||||
#define LCD_CLKEN_LIDD 0x00000002 // LIDD Submodule Clock Enable
|
||||
#define LCD_CLKEN_CORE 0x00000001 // LCD Core Clock Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the LCD_O_CLKRESET register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define LCD_CLKRESET_MAIN 0x00000008 // Software Reset for the entire
|
||||
// LCD module
|
||||
#define LCD_CLKRESET_DMA 0x00000004 // Software Reset for the DMA
|
||||
// submodule
|
||||
#define LCD_CLKRESET_LIDD 0x00000002 // Software Reset for the LIDD
|
||||
// submodule (character displays)
|
||||
#define LCD_CLKRESET_CORE 0x00000001 // Software Reset for the Core,
|
||||
// which encompasses the Raster
|
||||
// Active Matrix and Passive Matrix
|
||||
// logic
|
||||
|
||||
#endif // __HW_LCD_H__
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
//*****************************************************************************
|
||||
//
|
||||
// hw_memmap.h - Macros defining the memory map of the device.
|
||||
//
|
||||
// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_MEMMAP_H__
|
||||
#define __HW_MEMMAP_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the base address of the memories and
|
||||
// peripherals.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_BASE 0x00000000 // FLASH memory
|
||||
#define SRAM_BASE 0x20000000 // SRAM memory
|
||||
#define WATCHDOG0_BASE 0x40000000 // Watchdog0
|
||||
#define WATCHDOG1_BASE 0x40001000 // Watchdog1
|
||||
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
|
||||
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
|
||||
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
|
||||
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
|
||||
#define SSI0_BASE 0x40008000 // SSI0
|
||||
#define SSI1_BASE 0x40009000 // SSI1
|
||||
#define SSI2_BASE 0x4000A000 // SSI2
|
||||
#define SSI3_BASE 0x4000B000 // SSI3
|
||||
#define UART0_BASE 0x4000C000 // UART0
|
||||
#define UART1_BASE 0x4000D000 // UART1
|
||||
#define UART2_BASE 0x4000E000 // UART2
|
||||
#define UART3_BASE 0x4000F000 // UART3
|
||||
#define UART4_BASE 0x40010000 // UART4
|
||||
#define UART5_BASE 0x40011000 // UART5
|
||||
#define UART6_BASE 0x40012000 // UART6
|
||||
#define UART7_BASE 0x40013000 // UART7
|
||||
#define I2C0_BASE 0x40020000 // I2C0
|
||||
#define I2C1_BASE 0x40021000 // I2C1
|
||||
#define I2C2_BASE 0x40022000 // I2C2
|
||||
#define I2C3_BASE 0x40023000 // I2C3
|
||||
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
|
||||
#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
|
||||
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
|
||||
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
|
||||
#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
|
||||
#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
|
||||
#define QEI0_BASE 0x4002C000 // QEI0
|
||||
#define QEI1_BASE 0x4002D000 // QEI1
|
||||
#define TIMER0_BASE 0x40030000 // Timer0
|
||||
#define TIMER1_BASE 0x40031000 // Timer1
|
||||
#define TIMER2_BASE 0x40032000 // Timer2
|
||||
#define TIMER3_BASE 0x40033000 // Timer3
|
||||
#define TIMER4_BASE 0x40034000 // Timer4
|
||||
#define TIMER5_BASE 0x40035000 // Timer5
|
||||
#define WTIMER0_BASE 0x40036000 // Wide Timer0
|
||||
#define WTIMER1_BASE 0x40037000 // Wide Timer1
|
||||
#define ADC0_BASE 0x40038000 // ADC0
|
||||
#define ADC1_BASE 0x40039000 // ADC1
|
||||
#define COMP_BASE 0x4003C000 // Analog comparators
|
||||
#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
|
||||
#define CAN0_BASE 0x40040000 // CAN0
|
||||
#define CAN1_BASE 0x40041000 // CAN1
|
||||
#define WTIMER2_BASE 0x4004C000 // Wide Timer2
|
||||
#define WTIMER3_BASE 0x4004D000 // Wide Timer3
|
||||
#define WTIMER4_BASE 0x4004E000 // Wide Timer4
|
||||
#define WTIMER5_BASE 0x4004F000 // Wide Timer5
|
||||
#define USB0_BASE 0x40050000 // USB 0 Controller
|
||||
#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
|
||||
#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
|
||||
#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
|
||||
#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
|
||||
#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
|
||||
#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
|
||||
#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
|
||||
#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
|
||||
#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
|
||||
#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
|
||||
#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
|
||||
#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
|
||||
#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
|
||||
#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
|
||||
#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
|
||||
#define GPIO_PORTR_BASE 0x40067000 // General-Purpose Input/Outputs
|
||||
// (GPIOs)
|
||||
#define GPIO_PORTS_BASE 0x40068000 // General-Purpose Input/Outputs
|
||||
// (GPIOs)
|
||||
#define GPIO_PORTT_BASE 0x40069000 // General-Purpose Input/Outputs
|
||||
// (GPIOs)
|
||||
#define EEPROM_BASE 0x400AF000 // EEPROM memory
|
||||
#define ONEWIRE0_BASE 0x400B6000 // 1-Wire Master Module
|
||||
#define I2C8_BASE 0x400B8000 // I2C8
|
||||
#define I2C9_BASE 0x400B9000 // I2C9
|
||||
#define I2C4_BASE 0x400C0000 // I2C4
|
||||
#define I2C5_BASE 0x400C1000 // I2C5
|
||||
#define I2C6_BASE 0x400C2000 // I2C6
|
||||
#define I2C7_BASE 0x400C3000 // I2C7
|
||||
#define EPI0_BASE 0x400D0000 // EPI0
|
||||
#define TIMER6_BASE 0x400E0000 // General-Purpose Timers
|
||||
#define TIMER7_BASE 0x400E1000 // General-Purpose Timers
|
||||
#define EMAC0_BASE 0x400EC000 // Ethernet Controller
|
||||
#define SYSEXC_BASE 0x400F9000 // System Exception Module
|
||||
#define HIB_BASE 0x400FC000 // Hibernation Module
|
||||
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
|
||||
#define SYSCTL_BASE 0x400FE000 // System Control
|
||||
#define UDMA_BASE 0x400FF000 // uDMA Controller
|
||||
#define CCM0_BASE 0x44030000 // Cyclical Redundancy Check (CRC)
|
||||
#define SHAMD5_BASE 0x44034000 // SHA/MD5 Accelerator
|
||||
#define AES_BASE 0x44036000 // Advance Encryption
|
||||
// Hardware-Accelerated Module
|
||||
#define DES_BASE 0x44038000 // Data Encryption Standard
|
||||
// Accelerator (DES)
|
||||
#define LCD0_BASE 0x44050000 // LCD Controller
|
||||
// #define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
|
||||
// #define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
|
||||
// #define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
|
||||
// #define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
|
||||
// #define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
|
||||
|
||||
#endif // __HW_MEMMAP_H__
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue