From 6faa8b96a93f56f1d40512135e4909f44bbff19c Mon Sep 17 00:00:00 2001 From: Alex Lewontin Date: Fri, 11 Dec 2020 12:39:59 -0500 Subject: [PATCH] Style clean up --- os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c | 11 +- os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.h | 495 +++++++++--------- os/hal/ports/NUMICRO/NUC123/hal_lld.c | 48 +- os/hal/ports/NUMICRO/NUC123/nuc123_isr.h | 4 +- os/hal/ports/NUMICRO/NUC123/nuc123_registry.h | 10 +- .../Blinky/cfg/osalconf.h | 134 ++--- .../NUTINY-SDK-NUC123-V2.0/Blinky/readme.txt | 5 +- 7 files changed, 345 insertions(+), 362 deletions(-) diff --git a/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c b/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c index e76efedd..c6f221aa 100644 --- a/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c +++ b/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c @@ -51,7 +51,6 @@ OSAL_IRQ_HANDLER(NUC123_GPIOAB_HANDLER){ OSAL_IRQ_PROLOGUE(); - GPIO_TOGGLE(PB4); GPIO_TOGGLE(PB5); GPIO_TOGGLE(PB6); @@ -88,7 +87,7 @@ OSAL_IRQ_HANDLER(NUC123_GPIOCDF_HANDLER){ */ void _pal_lld_init(const PALConfig *config) { - //(void)config; + /* (void)config; */ /* Turn on GPIO subsystem * Set all GPIO to Input/HZ * Clear all GPIO Interrupts @@ -148,7 +147,7 @@ void _pal_lld_init(const PALConfig *config) { /* Enable External Crystal Oscillator pins */ SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN; -// SYS->GPD_MFP |= SYS_GPD_MFP_PD10_CLKO; +/* SYS->GPD_MFP |= SYS_GPD_MFP_PD10_CLKO; */ /* Enable UART1 data pins */ SYS->GPB_MFP |= SYS_GPB_MFP_PB1_UART0_TXD | SYS_GPB_MFP_PB0_UART0_RXD; @@ -181,10 +180,10 @@ void _pal_lld_setgroupmode(ioportid_t port, else nucMode = GPIO_PMD_QUASI; - // GPIO_SetMode(port, mask, nucMode); + /* GPIO_SetMode(port, mask, nucMode); */ for (uint32_t i = 0; i < PAL_IOPORTS_WIDTH; i++) { - // for(uint32_t i = 0; i < GPIO_PINSPERPORT_MAX; i++) { - if(mask & (1 << i)) { + /* for (uint32_t i = 0; i < GPIO_PINSPERPORT_MAX; i++) { */ + if (mask & (1 << i)) { port->PMD = (port->PMD & ~(0x03ul << (i << 1))) | (nucMode << (i << 1)); } } diff --git a/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.h b/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.h index 10091cfb..3776e1b5 100644 --- a/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.h +++ b/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.h @@ -66,19 +66,17 @@ #define PAL_MODE_NUC123_ALTERNATE_QUASI GPIO_PMD_QUASI /** @} */ - /** * @brief Alternate GPIO pin defines - * + * * @description SYS defines for alternative GPIO pin usage (instead of general I/O) * These are all for two sets of registers - GPx_MFP and ALT_MFP/ALT_MFP1 - * + * */ - /** * GPIO Port A Alternative Pin Modes - * + * */ /* Pin 10 */ @@ -88,22 +86,22 @@ #define SYS_ALT_MFP1_PA10_GPIO NULL /* I2C1 SDA */ -#define SYS_GPA_MFP_PA10_I2C1_SDA (0x01ul<DOUT = bits) - /** * @brief Sets a bits mask on a I/O port. * @note The @ref PAL provides a default software implementation of this @@ -1268,7 +1260,6 @@ typedef GPIO_T * ioportid_t; */ #define pal_lld_setport(port, bits) (port->DOUT |= bits) - /** * @brief Clears a bits mask on a I/O port. * @note The @ref PAL provides a default software implementation of this @@ -1282,7 +1273,6 @@ typedef GPIO_T * ioportid_t; */ #define pal_lld_clearport(port, bits) (port->DOUT &= ~bits) - /** * @brief Toggles a bits mask on a I/O port. * @note The @ref PAL provides a default software implementation of this @@ -1309,7 +1299,7 @@ typedef GPIO_T * ioportid_t; * * @notapi */ -//#define pal_lld_readgroup(port, mask, offset) 0U +/* #define pal_lld_readgroup(port, mask, offset) 0U */ /** * @brief Writes a group of bits. @@ -1377,7 +1367,7 @@ typedef GPIO_T * ioportid_t; * * @notapi */ -/*#define pal_lld_readpad(port, pad) PAL_LOW*/ +/* #define pal_lld_readpad(port, pad) PAL_LOW */ #define pal_lld_readpad(port, pad) ((port->PIN & PAL_PORT_BIT(pad)) >> pad) /** @@ -1417,7 +1407,6 @@ typedef GPIO_T * ioportid_t; #define pal_lld_setpad(port, pad) \ (port->DOUT |= PAL_PORT_BIT(pad)) - /** * @brief Clears a pad logical state to @p PAL_LOW. * @note The @ref PAL provides a default software implementation of this @@ -1432,7 +1421,6 @@ typedef GPIO_T * ioportid_t; #define pal_lld_clearpad(port, pad) \ (port->DOUT &= ~(0xFFFF0000U | PAL_PORT_BIT(pad))) - /** * @brief Toggles a pad logical state. * @note The @ref PAL provides a default software implementation of this @@ -1447,7 +1435,6 @@ typedef GPIO_T * ioportid_t; #define pal_lld_togglepad(port, pad) \ (port->DOUT ^= PAL_PORT_BIT(pad)) - /** * @brief Pad mode setup. * @details This function programs a pad with the specified mode. @@ -1464,7 +1451,7 @@ typedef GPIO_T * ioportid_t; */ #define pal_lld_setpadmode(port, pad, mode) \ _pal_lld_setgroupmode(port, PAL_PORT_BIT(pad), mode) - //GPIO_SetMode(port, PAL_PORT_BIT(pad), mode) + /* GPIO_SetMode(port, PAL_PORT_BIT(pad), mode) */ #if !defined(__DOXYGEN__) extern const PALConfig pal_default_config; diff --git a/os/hal/ports/NUMICRO/NUC123/hal_lld.c b/os/hal/ports/NUMICRO/NUC123/hal_lld.c index 0fe71550..2d13d697 100644 --- a/os/hal/ports/NUMICRO/NUC123/hal_lld.c +++ b/os/hal/ports/NUMICRO/NUC123/hal_lld.c @@ -60,7 +60,7 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */ register settings. This function can be used to retrieve the system core clock frequeny after user changed register sittings. */ - // SystemCoreClock = SYSTEM_CLOCK; + /* SystemCoreClock = SYSTEM_CLOCK; */ uint32_t clkFreq; uint32_t PllReg; @@ -68,7 +68,7 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */ uint32_t pllFIN, pllNF, pllNR, pllNO; /* Update PLL Clock */ - // PllClock = clks_lld_get_pll_clock_freq(); + /* PllClock = clks_lld_get_pll_clock_freq(); */ PllReg = CLK->PLLCON; if (PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) { @@ -106,19 +106,19 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */ /* Pick Clock Source */ switch (CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk) { - case 0: // External HF Xtal + case 0: /* External HF Xtal */ clkFreq = __HXT; break; - case 1: // PLL clock / 2 + case 1: /* PLL clock / 2 */ clkFreq = PllClock >> 1; break; - case 3: // Internal 10kHz + case 3: /* Internal 10kHz */ clkFreq = __LIRC; break; - case 2: // PLL clock + case 2: /* PLL clock */ clkFreq = PllClock; break; - case 7: // Internal 22.184MHz + case 7: /* Internal 22.184MHz */ clkFreq = __HIRC; break; default: @@ -157,13 +157,13 @@ static inline uint32_t get_pll_clock_freq(void) PllClock = pllFIN; } else { switch (((PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)) { - case 0: // OUT_DIV == 00 : NO = 1 + case 0: /* OUT_DIV == 00 : NO = 1 */ pllNO = 1; break; - case 3: // OUT_DIV == 11 : NO = 4 + case 3: /* OUT_DIV == 11 : NO = 4 */ pllNO = 4; break; - default: // OUT_DIV == 01 or 10 : NO = 2 + default: /* OUT_DIV == 01 or 10 : NO = 2 */ pllNO = 2; break; } @@ -171,7 +171,7 @@ static inline uint32_t get_pll_clock_freq(void) pllNF = ((PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2; pllNR = ((PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2; - /* shift to avoid overflow condition */ + /* Shift to avoid overflow condition */ PllClock = (((pllFIN >> 2) * pllNF) / (pllNR * pllNO) << 2); } } @@ -181,9 +181,9 @@ static inline uint32_t get_pll_clock_freq(void) /** * @brief Wait for stable clock - * + * * @description Always wait around 300ms for clock to be stable - * + * */ static uint32_t wait_for_clock_ready(uint32_t clkMask) { @@ -199,13 +199,13 @@ static uint32_t wait_for_clock_ready(uint32_t clkMask) } /** @brief Set system HCLK - * + * * @description Setup HCLK source and divider - * + * * Always switch to a known stable clock source before changing a * system clock, to avoid issues related to the original clock's * speed/settings. - * + * */ static void set_HCLK(uint32_t clkSource, uint32_t clkDivider) { @@ -265,13 +265,13 @@ static uint32_t enable_pll(uint32_t pllSrc, uint32_t pllFreq) /** * Calculate best PLL variables from requested frequency - * + * * See NUC123 Technical Reference Manual 5.4.8 PLL Control Register Description, page 124 - * + * * NF 1 * FOUT = FIN x -- x -- * NR NO - * + * */ uint32_t NO = 0; @@ -328,9 +328,9 @@ static uint32_t enable_pll(uint32_t pllSrc, uint32_t pllFreq) /** * Loop to calculate best/lowest NR (between 0 or 2 and 31) and best/lowest NF (between 0 and 511) - * + * * Best results are off-by-2 until final equation calculation (to allow use in PLLCON) - * + * */ uint32_t bestNR = 0; uint32_t bestNF = 0; @@ -383,13 +383,13 @@ static uint32_t enable_pll(uint32_t pllSrc, uint32_t pllFreq) } /** @brief Set Core Clock - * + * * @description Set the core system clock some reference speed (Hz). - * This should be between 25MHz and 72MHz. + * This should be between 25MHz and 72MHz for the NUC123SD4AN0. * * Use either the HXT (exact) or HIRC (nearest using 22.1184MHz) * as the clock source. - * + * */ static uint32_t set_core_clock(uint32_t clkCore) { diff --git a/os/hal/ports/NUMICRO/NUC123/nuc123_isr.h b/os/hal/ports/NUMICRO/NUC123/nuc123_isr.h index f8356a52..a6ed35d0 100644 --- a/os/hal/ports/NUMICRO/NUC123/nuc123_isr.h +++ b/os/hal/ports/NUMICRO/NUC123/nuc123_isr.h @@ -34,16 +34,14 @@ * @{ */ -/* +/* * GPIO units. */ -#if defined(NUC123SD4AN0) #define NUC123_GPIOAB_HANDLER Vector50 #define NUC123_GPIOCDF_HANDLER Vector54 #define NUC123_GPIOAB_NUMBER GPAB_IRQn #define NUC123_GPIOCDF_NUMBER GPCDF_IRQn -#endif /* * Special ST unit diff --git a/os/hal/ports/NUMICRO/NUC123/nuc123_registry.h b/os/hal/ports/NUMICRO/NUC123/nuc123_registry.h index bf503b62..a1ae53bd 100644 --- a/os/hal/ports/NUMICRO/NUC123/nuc123_registry.h +++ b/os/hal/ports/NUMICRO/NUC123/nuc123_registry.h @@ -95,8 +95,8 @@ #define NUC123_HAS_ETH FALSE /* EXTI attributes.*/ -//#define NUC123_EXTI_NUM_LINES 20 -//#define NUC123_EXTI_IMR_MASK 0xFFF50000U +/* #define NUC123_EXTI_NUM_LINES 20 */ +/* #define NUC123_EXTI_IMR_MASK 0xFFF50000U */ /* GPIO attributes.*/ #define NUC123_HAS_GPIOA TRUE @@ -199,7 +199,7 @@ #define NUC123_HAS_TIM22 FALSE /* USART attributes.*/ -/*#define NUC123_HAS_USART1 TRUE +/* #define NUC123_HAS_USART1 TRUE #define NUC123_USART1_RX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 1) |\ NUC123_DMA_STREAM_ID_MSK(1, 3) |\ NUC123_DMA_STREAM_ID_MSK(1, 5)) @@ -215,8 +215,8 @@ #define NUC123_USART2_RX_DMA_CHN 0x00090909 #define NUC123_USART2_TX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 2) |\ NUC123_DMA_STREAM_ID_MSK(1, 4)) -#define NUC123_USART2_TX_DMA_CHN 0x00009090 -*/ +#define NUC123_USART2_TX_DMA_CHN 0x00009090 */ + #define NUC123_HAS_USART1 FALSE #define NUC123_HAS_USART2 FALSE #define NUC123_HAS_USART3 FALSE diff --git a/testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/cfg/osalconf.h b/testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/cfg/osalconf.h index 666d0c37..af565601 100644 --- a/testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/cfg/osalconf.h +++ b/testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/cfg/osalconf.h @@ -1,67 +1,67 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file templates/halconf.h - * @brief Bare-metal OSAL configuration header. - * - * @addtogroup OSAL_CONF - * @{ - */ - -#ifndef OSALCONF_H -#define OSALCONF_H - -/** - * @brief Frequency in Hertz of the system tick. - */ -#if !defined(OSAL_ST_FREQUENCY) || defined(__DOXYGEN__) -#define OSAL_ST_FREQUENCY 10000 -#endif - -/** - * @brief Enables OSAL assertions. - */ -#if !defined(OSAL_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define OSAL_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Enables OSAL functions parameters checks. - */ -#if !defined(OSAL_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define OSAL_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief OSAL initialization hook. - */ -#if !defined(OSAL_INIT_HOOK) || defined(__DOXYGEN__) -#define OSAL_INIT_HOOK() { \ -} -#endif - -/** - * @brief Idle loop hook macro. - */ -#if !defined(OSAL_IDLE_HOOK) || defined(__DOXYGEN__) -#define OSAL_IDLE_HOOK() { \ -} -#endif - -#endif /* OSALCONF_H */ - -/** @} */ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief Bare-metal OSAL configuration header. + * + * @addtogroup OSAL_CONF + * @{ + */ + +#ifndef OSALCONF_H +#define OSALCONF_H + +/** + * @brief Frequency in Hertz of the system tick. + */ +#if !defined(OSAL_ST_FREQUENCY) || defined(__DOXYGEN__) +#define OSAL_ST_FREQUENCY 10000 +#endif + +/** + * @brief Enables OSAL assertions. + */ +#if !defined(OSAL_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define OSAL_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Enables OSAL functions parameters checks. + */ +#if !defined(OSAL_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define OSAL_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief OSAL initialization hook. + */ +#if !defined(OSAL_INIT_HOOK) || defined(__DOXYGEN__) +#define OSAL_INIT_HOOK() { \ +} +#endif + +/** + * @brief Idle loop hook macro. + */ +#if !defined(OSAL_IDLE_HOOK) || defined(__DOXYGEN__) +#define OSAL_IDLE_HOOK() { \ +} +#endif + +#endif /* OSALCONF_H */ + +/** @} */ diff --git a/testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/readme.txt b/testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/readme.txt index c82b0bc0..ddaf0f12 100644 --- a/testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/readme.txt +++ b/testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/readme.txt @@ -1,5 +1,5 @@ ***************************************************************************** -** ChibiOS/HAL - USB driver demo for NUC123. ** +** ChibiOS/HAL - Blinky demo for NUC123. ** ***************************************************************************** ** TARGET ** @@ -12,7 +12,6 @@ The application demonstrates the use of the NUC123 platform driver, and a little bit of the PAL. A successful run of the test involves the on-board LED blinking at .5 Hz (on for 1 second, then off for one second). - ** Board Setup ** - None @@ -20,4 +19,4 @@ bit of the PAL. A successful run of the test involves the on-board LED blinking ** Build Procedure ** The demo has been tested using gcc version 9.3.1 (GNU Arm Embedded Toolchain 9-2020-q2-update). -Just modify the TRGT line in the makefile in order to use different GCC ports. \ No newline at end of file +Just modify the TRGT line in the makefile in order to use different GCC ports.