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Rename RCU APB1RSTR register and remove unused peripherals

This commit is contained in:
Stefan Kerkmann 2021-04-05 18:52:41 +02:00
parent f6d7eda01b
commit 7262f2ed74
2 changed files with 83 additions and 151 deletions
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104
os/hal/ports/GD/GD32VF103/gd32_rcu.h
View File

@ -226,7 +226,7 @@
*
* @api
*/
#define rcuResetDAC() rcuResetAPB1(RCU_APB1RSTR_DACRST)
#define rcuResetDAC() rcuResetAPB1(RCU_APB1RST_DACRST)
/** @} */
/**
@ -291,7 +291,7 @@
*
* @api
*/
#define rcuResetPMUInterface() rcuResetAPB1(RCU_APB1RSTR_PMURST)
#define rcuResetPMUInterface() rcuResetAPB1(RCU_APB1RST_PMURST)
/** @} */
/**
@ -320,7 +320,7 @@
*
* @api
*/
#define rcuResetCAN0() rcuResetAPB1(RCU_APB1RSTR_CAN0RST)
#define rcuResetCAN0() rcuResetAPB1(RCU_APB1RST_CAN0RST)
/**
* @brief Enables the CAN1 peripheral clock.
@ -343,7 +343,7 @@
*
* @api
*/
#define rcuResetCAN1() rcuResetAPB1(RCU_APB1RSTR_CAN1RST)
#define rcuResetCAN1() rcuResetAPB1(RCU_APB1RST_CAN1RST)
/** @} */
/**
@ -401,42 +401,6 @@
#define rcuResetDMA1()
/** @} */
/**
* @name ETH peripheral specific RCU operations
* @{
*/
/**
* @brief Enables the ETH peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rcuEnableETH(lp) rcuEnableAHB(RCU_AHBENR_ETHMACEN | \
RCU_AHBENR_ETHMACTXEN | \
RCU_AHBENR_ETHMACRXEN, lp)
/**
* @brief Disables the ETH peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rcuDisableETH() rcuDisableAHB(RCU_AHBENR_ETHMACEN | \
RCU_AHBENR_ETHMACTXEN | \
RCU_AHBENR_ETHMACRXEN)
/**
* @brief Resets the ETH peripheral.
*
* @api
*/
#define rcuResetETH() rcuResetAHB(RCU_AHBRSTR_ETHMACRST)
/** @} */
/**
* @name I2C peripherals specific RCU operations
* @{
@ -463,7 +427,7 @@
*
* @api
*/
#define rcuResetI2C0() rcuResetAPB1(RCU_APB1RSTR_I2C0RST)
#define rcuResetI2C0() rcuResetAPB1(RCU_APB1RST_I2C0RST)
/**
* @brief Enables the I2C1 peripheral clock.
@ -487,7 +451,7 @@
*
* @api
*/
#define rcuResetI2C1() rcuResetAPB1(RCU_APB1RSTR_I2C1RST)
#define rcuResetI2C1() rcuResetAPB1(RCU_APB1RST_I2C1RST)
/** @} */
/**
@ -518,36 +482,6 @@
#define rcuResetUSBFS() rcuResetAHB(RCU_AHBRSTR_OTGFSRST)
/** @} */
/**
* @name SDIO peripheral specific RCU operations
* @{
*/
/**
* @brief Enables the SDIO peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rcuEnableSDIO(lp) rcuEnableAHB(RCU_AHBENR_SDIOEN, lp)
/**
* @brief Disables the SDIO peripheral clock.
*
* @api
*/
#define rcuDisableSDIO() rcuDisableAHB(RCU_AHBENR_SDIOEN)
/**
* @brief Resets the SDIO peripheral.
* @note Not supported in this family, does nothing.
*
* @api
*/
#define rcuResetSDIO()
/** @} */
/**
* @name SPI peripherals specific RCU operations
* @{
@ -598,7 +532,7 @@
*
* @api
*/
#define rcuResetSPI1() rcuResetAPB1(RCU_APB1RSTR_SPI1RST)
#define rcuResetSPI1() rcuResetAPB1(RCU_APB1RST_SPI1RST)
/**
* @brief Enables the SPI2 peripheral clock.
@ -622,7 +556,7 @@
*
* @api
*/
#define rcuResetSPI2() rcuResetAPB1(RCU_APB1RSTR_SPI2RST)
#define rcuResetSPI2() rcuResetAPB1(RCU_APB1RST_SPI2RST)
/** @} */
/**
@ -675,7 +609,7 @@
*
* @api
*/
#define rcuResetTIM1() rcuResetAPB1(RCU_APB1RSTR_TIM1RST)
#define rcuResetTIM1() rcuResetAPB1(RCU_APB1RST_TIMER1RST)
/**
* @brief Enables the TIM2 peripheral clock.
@ -699,7 +633,7 @@
*
* @api
*/
#define rcuResetTIM2() rcuResetAPB1(RCU_APB1RSTR_TIM2RST)
#define rcuResetTIM2() rcuResetAPB1(RCU_APB1RST_TIMER2RST)
/**
* @brief Enables the TIM3 peripheral clock.
@ -723,7 +657,7 @@
*
* @api
*/
#define rcuResetTIM3() rcuResetAPB1(RCU_APB1RSTR_TIM3RST)
#define rcuResetTIM3() rcuResetAPB1(RCU_APB1RST_TIMER3RST)
/**
* @brief Enables the TIM4 peripheral clock.
@ -747,7 +681,7 @@
*
* @api
*/
#define rcuResetTIM4() rcuResetAPB1(RCU_APB1RSTR_TIM4RST)
#define rcuResetTIM4() rcuResetAPB1(RCU_APB1RST_TIMER4RST)
/**
* @brief Enables the TIM5 peripheral clock.
@ -770,7 +704,7 @@
*
* @api
*/
#define rcuResetTIM5() rcuResetAPB1(RCU_APB1RSTR_TIM5RST)
#define rcuResetTIM5() rcuResetAPB1(RCU_APB1RST_TIMER5RST)
/**
* @brief Enables the TIM6 peripheral clock.
@ -793,7 +727,7 @@
*
* @api
*/
#define rcuResetTIM6() rcuResetAPB1(RCU_APB1RSTR_TIM6RST)
#define rcuResetTIM6() rcuResetAPB1(RCU_APB1RST_TIMER6RST)
/** @} */
@ -848,7 +782,7 @@
*
* @api
*/
#define rcuResetUSART1() rcuResetAPB1(RCU_APB1RSTR_USART1RST)
#define rcuResetUSART1() rcuResetAPB1(RCU_APB1RST_USART1RST)
/**
* @brief Enables the USART2 peripheral clock.
@ -872,7 +806,7 @@
*
* @api
*/
#define rcuResetUSART2() rcuResetAPB1(RCU_APB1RSTR_USART2RST)
#define rcuResetUSART2() rcuResetAPB1(RCU_APB1RST_USART2RST)
/**
* @brief Enables the UART3 peripheral clock.
@ -896,7 +830,7 @@
*
* @api
*/
#define rcuResetUART3() rcuResetAPB1(RCU_APB1RSTR_UART3RST)
#define rcuResetUART3() rcuResetAPB1(RCU_APB1RST_UART3RST)
/**
* @brief Enables the UART4 peripheral clock.
@ -920,7 +854,7 @@
*
* @api
*/
#define rcuResetUART4() rcuResetAPB1(RCU_APB1RSTR_UART4RST)
#define rcuResetUART4() rcuResetAPB1(RCU_APB1RST_UART4RST)
/** @} */
/**
@ -949,7 +883,7 @@
*
* @api
*/
#define rcuResetUSB() rcuResetAPB1(RCU_APB1RSTR_USBRST)
#define rcuResetUSB() rcuResetAPB1(RCU_APB1RST_USBRST)
/** @} */
/**

130
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -1347,78 +1347,76 @@ typedef struct
#define RCU_APB2RST_PERST RCU_APB2RST_PERST_Msk /*!< I/O port E reset */
/***************** Bit definition for RCU_APB1RST register *****************/
#define RCU_APB1RST_TIMER1RST_Pos (0U)
#define RCU_APB1RST_TIMER1RST_Msk (0x1U << RCU_APB1RST_TIMER1RST_Pos) /*!< 0x00000001 */
#define RCU_APB1RST_TIMER1RST RCU_APB1RST_TIMER1RST_Msk /*!< Timer 2 reset */
#define RCU_APB1RST_TIMER2RST_Pos (1U)
#define RCU_APB1RST_TIMER2RST_Msk (0x1U << RCU_APB1RST_TIMER2RST_Pos) /*!< 0x00000002 */
#define RCU_APB1RST_TIMER2RST RCU_APB1RST_TIMER2RST_Msk /*!< Timer 3 reset */
#define RCU_APB1RST_WWDGTRST_Pos (11U)
#define RCU_APB1RST_WWDGTRST_Msk (0x1U << RCU_APB1RST_WWDGTRST_Pos) /*!< 0x00000800 */
#define RCU_APB1RST_WWDGTRST RCU_APB1RST_WWDGTRST_Msk /*!< Window Watchdog reset */
#define RCU_APB1RST_USART1RST_Pos (17U)
#define RCU_APB1RST_USART1RST_Msk (0x1U << RCU_APB1RST_USART1RST_Pos) /*!< 0x00020000 */
#define RCU_APB1RST_USART1RST RCU_APB1RST_USART1RST_Msk /*!< USART 2 reset */
#define RCU_APB1RST_I2C0RST_Pos (21U)
#define RCU_APB1RST_I2C0RST_Msk (0x1U << RCU_APB1RST_I2C0RST_Pos) /*!< 0x00200000 */
#define RCU_APB1RST_I2C0RST RCU_APB1RST_I2C0RST_Msk /*!< I2C 1 reset */
#define RCU_APB1RST_CAN0RST_Pos (25U)
#define RCU_APB1RST_CAN0RST_Msk (0x1U << RCU_APB1RST_CAN0RST_Pos) /*!< 0x02000000 */
#define RCU_APB1RST_CAN0RST RCU_APB1RST_CAN0RST_Msk /*!< CAN0 reset */
#define RCU_APB1RST_BKPIRST_Pos (27U)
#define RCU_APB1RST_BKPIRST_Msk (0x1U << RCU_APB1RST_BKPIRST_Pos) /*!< 0x08000000 */
#define RCU_APB1RST_BKPIRST RCU_APB1RST_BKPIRST_Msk /*!< Backup interface reset */
#define RCU_APB1RST_PMURST_Pos (28U)
#define RCU_APB1RST_PMURST_Msk (0x1U << RCU_APB1RST_PMURST_Pos) /*!< 0x10000000 */
#define RCU_APB1RST_PMURST RCU_APB1RST_PMURST_Msk /*!< Power interface reset */
#define RCU_APB1RST_TIMER3RST_Pos (2U)
#define RCU_APB1RST_TIMER3RST_Msk (0x1U << RCU_APB1RST_TIMER3RST_Pos) /*!< 0x00000004 */
#define RCU_APB1RST_TIMER3RST RCU_APB1RST_TIMER3RST_Msk /*!< Timer 4 reset */
#define RCU_APB1RST_SPI1RST_Pos (14U)
#define RCU_APB1RST_SPI1RST_Msk (0x1U << RCU_APB1RST_SPI1RST_Pos) /*!< 0x00004000 */
#define RCU_APB1RST_SPI1RST RCU_APB1RST_SPI1RST_Msk /*!< SPI 2 reset */
#define RCU_APB1RST_USART2RST_Pos (18U)
#define RCU_APB1RST_USART2RST_Msk (0x1U << RCU_APB1RST_USART2RST_Pos) /*!< 0x00040000 */
#define RCU_APB1RST_USART2RST RCU_APB1RST_USART2RST_Msk /*!< USART 3 reset */
#define RCU_APB1RST_I2C1RST_Pos (22U)
#define RCU_APB1RST_I2C1RST_Msk (0x1U << RCU_APB1RST_I2C1RST_Pos) /*!< 0x00400000 */
#define RCU_APB1RST_I2C1RST RCU_APB1RST_I2C1RST_Msk /*!< I2C 2 reset */
/***************** Bit definition for RCU_APB1RSTR register *****************/
#define RCU_APB1RSTR_TIM1RST_Pos (0U)
#define RCU_APB1RSTR_TIM1RST_Msk (0x1U << RCU_APB1RSTR_TIM1RST_Pos) /*!< 0x00000001 */
#define RCU_APB1RSTR_TIM1RST RCU_APB1RSTR_TIM1RST_Msk /*!< Timer 2 reset */
#define RCU_APB1RSTR_TIM2RST_Pos (1U)
#define RCU_APB1RSTR_TIM2RST_Msk (0x1U << RCU_APB1RSTR_TIM2RST_Pos) /*!< 0x00000002 */
#define RCU_APB1RSTR_TIM2RST RCU_APB1RSTR_TIM2RST_Msk /*!< Timer 3 reset */
#define RCU_APB1RSTR_WWDGRST_Pos (11U)
#define RCU_APB1RSTR_WWDGRST_Msk (0x1U << RCU_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
#define RCU_APB1RSTR_WWDGRST RCU_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
#define RCU_APB1RSTR_USART1RST_Pos (17U)
#define RCU_APB1RSTR_USART1RST_Msk (0x1U << RCU_APB1RSTR_USART1RST_Pos) /*!< 0x00020000 */
#define RCU_APB1RSTR_USART1RST RCU_APB1RSTR_USART1RST_Msk /*!< USART 2 reset */
#define RCU_APB1RSTR_I2C0RST_Pos (21U)
#define RCU_APB1RSTR_I2C0RST_Msk (0x1U << RCU_APB1RSTR_I2C0RST_Pos) /*!< 0x00200000 */
#define RCU_APB1RSTR_I2C0RST RCU_APB1RSTR_I2C0RST_Msk /*!< I2C 1 reset */
#define RCU_APB1RSTR_CAN0RST_Pos (25U)
#define RCU_APB1RSTR_CAN0RST_Msk (0x1U << RCU_APB1RSTR_CAN0RST_Pos) /*!< 0x02000000 */
#define RCU_APB1RSTR_CAN0RST RCU_APB1RSTR_CAN0RST_Msk /*!< CAN0 reset */
#define RCU_APB1RSTR_BKPRST_Pos (27U)
#define RCU_APB1RSTR_BKPRST_Msk (0x1U << RCU_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
#define RCU_APB1RSTR_BKPRST RCU_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
#define RCU_APB1RSTR_PMURST_Pos (28U)
#define RCU_APB1RSTR_PMURST_Msk (0x1U << RCU_APB1RSTR_PMURST_Pos) /*!< 0x10000000 */
#define RCU_APB1RSTR_PMURST RCU_APB1RSTR_PMURST_Msk /*!< Power interface reset */
#define RCU_APB1RSTR_TIM3RST_Pos (2U)
#define RCU_APB1RSTR_TIM3RST_Msk (0x1U << RCU_APB1RSTR_TIM3RST_Pos) /*!< 0x00000004 */
#define RCU_APB1RSTR_TIM3RST RCU_APB1RSTR_TIM3RST_Msk /*!< Timer 4 reset */
#define RCU_APB1RSTR_SPI1RST_Pos (14U)
#define RCU_APB1RSTR_SPI1RST_Msk (0x1U << RCU_APB1RSTR_SPI1RST_Pos) /*!< 0x00004000 */
#define RCU_APB1RSTR_SPI1RST RCU_APB1RSTR_SPI1RST_Msk /*!< SPI 2 reset */
#define RCU_APB1RSTR_USART2RST_Pos (18U)
#define RCU_APB1RSTR_USART2RST_Msk (0x1U << RCU_APB1RSTR_USART2RST_Pos) /*!< 0x00040000 */
#define RCU_APB1RSTR_USART2RST RCU_APB1RSTR_USART2RST_Msk /*!< USART 3 reset */
#define RCU_APB1RSTR_I2C1RST_Pos (22U)
#define RCU_APB1RSTR_I2C1RST_Msk (0x1U << RCU_APB1RSTR_I2C1RST_Pos) /*!< 0x00400000 */
#define RCU_APB1RSTR_I2C1RST RCU_APB1RSTR_I2C1RST_Msk /*!< I2C 2 reset */
#define RCU_APB1RSTR_TIM4RST_Pos (3U)
#define RCU_APB1RSTR_TIM4RST_Msk (0x1U << RCU_APB1RSTR_TIM4RST_Pos) /*!< 0x00000008 */
#define RCU_APB1RSTR_TIM4RST RCU_APB1RSTR_TIM4RST_Msk /*!< Timer 5 reset */
#define RCU_APB1RSTR_TIM5RST_Pos (4U)
#define RCU_APB1RSTR_TIM5RST_Msk (0x1U << RCU_APB1RSTR_TIM5RST_Pos) /*!< 0x00000010 */
#define RCU_APB1RSTR_TIM5RST RCU_APB1RSTR_TIM5RST_Msk /*!< Timer 6 reset */
#define RCU_APB1RSTR_TIM6RST_Pos (5U)
#define RCU_APB1RSTR_TIM6RST_Msk (0x1U << RCU_APB1RSTR_TIM6RST_Pos) /*!< 0x00000020 */
#define RCU_APB1RSTR_TIM6RST RCU_APB1RSTR_TIM6RST_Msk /*!< Timer 7 reset */
#define RCU_APB1RSTR_SPI2RST_Pos (15U)
#define RCU_APB1RSTR_SPI2RST_Msk (0x1U << RCU_APB1RSTR_SPI2RST_Pos) /*!< 0x00008000 */
#define RCU_APB1RSTR_SPI2RST RCU_APB1RSTR_SPI2RST_Msk /*!< SPI 3 reset */
#define RCU_APB1RSTR_UART3RST_Pos (19U)
#define RCU_APB1RSTR_UART3RST_Msk (0x1U << RCU_APB1RSTR_UART3RST_Pos) /*!< 0x00080000 */
#define RCU_APB1RSTR_UART3RST RCU_APB1RSTR_UART3RST_Msk /*!< UART 4 reset */
#define RCU_APB1RSTR_UART4RST_Pos (20U)
#define RCU_APB1RSTR_UART4RST_Msk (0x1U << RCU_APB1RSTR_UART4RST_Pos) /*!< 0x00100000 */
#define RCU_APB1RSTR_UART4RST RCU_APB1RSTR_UART4RST_Msk /*!< UART 5 reset */
#define RCU_APB1RST_TIMER4RST_Pos (3U)
#define RCU_APB1RST_TIMER4RST_Msk (0x1U << RCU_APB1RST_TIMER4RST_Pos) /*!< 0x00000008 */
#define RCU_APB1RST_TIMER4RST RCU_APB1RST_TIMER4RST_Msk /*!< Timer 5 reset */
#define RCU_APB1RST_TIMER5RST_Pos (4U)
#define RCU_APB1RST_TIMER5RST_Msk (0x1U << RCU_APB1RST_TIMER5RST_Pos) /*!< 0x00000010 */
#define RCU_APB1RST_TIMER5RST RCU_APB1RST_TIMER5RST_Msk /*!< Timer 6 reset */
#define RCU_APB1RST_TIMER6RST_Pos (5U)
#define RCU_APB1RST_TIMER6RST_Msk (0x1U << RCU_APB1RST_TIMER6RST_Pos) /*!< 0x00000020 */
#define RCU_APB1RST_TIMER6RST RCU_APB1RST_TIMER6RST_Msk /*!< Timer 7 reset */
#define RCU_APB1RST_SPI2RST_Pos (15U)
#define RCU_APB1RST_SPI2RST_Msk (0x1U << RCU_APB1RST_SPI2RST_Pos) /*!< 0x00008000 */
#define RCU_APB1RST_SPI2RST RCU_APB1RST_SPI2RST_Msk /*!< SPI 3 reset */
#define RCU_APB1RST_UART3RST_Pos (19U)
#define RCU_APB1RST_UART3RST_Msk (0x1U << RCU_APB1RST_UART3RST_Pos) /*!< 0x00080000 */
#define RCU_APB1RST_UART3RST RCU_APB1RST_UART3RST_Msk /*!< UART 4 reset */
#define RCU_APB1RST_UART4RST_Pos (20U)
#define RCU_APB1RST_UART4RST_Msk (0x1U << RCU_APB1RST_UART4RST_Pos) /*!< 0x00100000 */
#define RCU_APB1RST_UART4RST RCU_APB1RST_UART4RST_Msk /*!< UART 5 reset */
#define RCU_APB1RSTR_CAN1RST_Pos (26U)
#define RCU_APB1RSTR_CAN1RST_Msk (0x1U << RCU_APB1RSTR_CAN1RST_Pos) /*!< 0x04000000 */
#define RCU_APB1RSTR_CAN1RST RCU_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
#define RCU_APB1RST_CAN1RST_Pos (26U)
#define RCU_APB1RST_CAN1RST_Msk (0x1U << RCU_APB1RST_CAN1RST_Pos) /*!< 0x04000000 */
#define RCU_APB1RST_CAN1RST RCU_APB1RST_CAN1RST_Msk /*!< CAN1 reset */
#define RCU_APB1RSTR_DACRST_Pos (29U)
#define RCU_APB1RSTR_DACRST_Msk (0x1U << RCU_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
#define RCU_APB1RSTR_DACRST RCU_APB1RSTR_DACRST_Msk /*!< DAC interface reset */
#define RCU_APB1RST_DACRST_Pos (29U)
#define RCU_APB1RST_DACRST_Msk (0x1U << RCU_APB1RST_DACRST_Pos) /*!< 0x20000000 */
#define RCU_APB1RST_DACRST RCU_APB1RST_DACRST_Msk /*!< DAC interface reset */
/****************** Bit definition for RCU_AHBENR register ******************/
#define RCU_AHBENR_DMA0EN_Pos (0U)