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Rename STM32 clocks to GD32 names 

HSE -> HXTAL
LSE -> LXTAL
HSI -> IRC8M
LSI -> IRC40K
This commit is contained in:
Stefan Kerkmann 2021-03-31 15:17:51 +02:00
parent b8f128c86c
commit 7636389126
6 changed files with 670 additions and 682 deletions
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100
os/hal/ports/GD/GD32VF103/hal_lld.c
View File

@ -64,18 +64,18 @@ static void hal_lld_backup_domain_init(void) {
RCU->BDCTL = 0;
}
/* If enabled then the LSE is started.*/
#if GD32_LSE_ENABLED
#if defined(GD32_LSE_BYPASS)
/* LSE Bypass.*/
RCU->BDCTL |= RCU_BDCR_LSEON | RCU_BDCR_LSEBYP;
/* If enabled then the LXTAL is started.*/
#if GD32_LXTAL_ENABLED
#if defined(GD32_LXTAL_BYPASS)
/* LXTAL Bypass.*/
RCU->BDCTL |= RCU_BDCR_LXTALON | RCU_BDCR_LXTALBYP;
#else
/* No LSE Bypass.*/
RCU->BDCTL |= RCU_BDCR_LSEON;
/* No LXTAL Bypass.*/
RCU->BDCTL |= RCU_BDCR_LXTALON;
#endif
while ((RCU->BDCTL & RCU_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
#endif /* GD32_LSE_ENABLED */
while ((RCU->BDCTL & RCU_BDCR_LXTALRDY) == 0)
; /* Waits until LXTAL is stable. */
#endif /* GD32_LXTAL_ENABLED */
#if GD32_RTCSEL != GD32_RTCSEL_NOCLOCK
/* If the backup domain hasn't been initialized yet then proceed with
@ -171,39 +171,39 @@ void hal_lld_init(void) {
void gd32_clock_init(void) {
#if !GD32_NO_INIT
/* HSI setup, it enforces the reset situation in order to handle possible
/* IRC8M setup, it enforces the reset situation in order to handle possible
problems with JTAG probes and re-initializations.*/
RCU->CTL |= RCU_CR_HSION; /* Make sure HSI is ON. */
while (!(RCU->CTL & RCU_CR_HSIRDY))
; /* Wait until HSI is stable. */
RCU->CTL |= RCU_CTL_IRC8MEN; /* Make sure IRC8M is ON. */
while (!(RCU->CTL & RCU_CTL_IRC8MSTB))
; /* Wait until IRC8M is stable. */
/* HSI is selected as new source without touching the other fields in
CFGR. Clearing the register has to be postponed after HSI is the
/* IRC8M is selected as new source without touching the other fields in
CFGR. Clearing the register has to be postponed after IRC8M is the
new source.*/
RCU->CFG0 &= ~RCU_CFGR_SW; /* Reset SW, selecting HSI. */
while ((RCU->CFG0 & RCU_CFGR_SWS) != RCU_CFGR_SWS_HSI)
; /* Wait until HSI is selected. */
RCU->CFG0 &= ~RCU_CFG0_SCS; /* Reset SW, selecting IRC8M. */
while ((RCU->CFG0 & RCU_CFG0_SCSS) != RCU_CFG0_SCSS_IRC8M)
; /* Wait until IRC8M is selected. */
/* Registers finally cleared to reset values.*/
RCU->CTL &= RCU_CR_HSITRIM | RCU_CR_HSION; /* CR Reset value. */
RCU->CTL &= RCU_CTL_IRC8MADJ | RCU_CTL_IRC8MEN; /* CR Reset value. */
RCU->CFG0 = 0; /* CFGR reset value. */
#if GD32_HSE_ENABLED
#if defined(GD32_HSE_BYPASS)
/* HSE Bypass.*/
RCU->CTL |= RCU_CR_HSEBYP;
#if GD32_HXTAL_ENABLED
#if defined(GD32_HXTAL_BYPASS)
/* HXTAL Bypass.*/
RCU->CTL |= RCU_CTL_HXTALBPS;
#endif
/* HSE activation.*/
RCU->CTL |= RCU_CR_HSEON;
while (!(RCU->CTL & RCU_CR_HSERDY))
; /* Waits until HSE is stable. */
/* HXTAL activation.*/
RCU->CTL |= RCU_CTL_HXTALEN;
while (!(RCU->CTL & RCU_CTL_HXTALSTB))
; /* Waits until HXTAL is stable. */
#endif
#if GD32_LSI_ENABLED
/* LSI activation.*/
RCU->RSTSCK |= RCU_CSR_LSION;
while ((RCU->RSTSCK & RCU_CSR_LSIRDY) == 0)
; /* Waits until LSI is stable. */
#if GD32_IRC40K_ENABLED
/* IRC40K activation.*/
RCU->RSTSCK |= RCU_CSR_IRC40KON;
while ((RCU->RSTSCK & RCU_CSR_IRC40KRDY) == 0)
; /* Waits until IRC40K is stable. */
#endif
/* Settings of various dividers and multipliers in CFGR2.*/
@ -212,34 +212,34 @@ void gd32_clock_init(void) {
/* PLL2 setup, if activated.*/
#if GD32_ACTIVATE_PLL2
RCU->CTL |= RCU_CR_PLL2ON;
while (!(RCU->CTL & RCU_CR_PLL2RDY))
RCU->CTL |= RCU_CTL_PLL1EN;
while (!(RCU->CTL & RCU_CTL_PLL1STB))
; /* Waits until PLL2 is stable. */
#endif
/* PLL3 setup, if activated.*/
#if GD32_ACTIVATE_PLL3
RCU->CTL |= RCU_CR_PLL3ON;
while (!(RCU->CTL & RCU_CR_PLL3RDY))
RCU->CTL |= RCU_CTL_PLL2EN;
while (!(RCU->CTL & RCU_CTL_PLL2STB))
; /* Waits until PLL3 is stable. */
#endif
/* PLL1 setup, if activated.*/
//#if GD32_ACTIVATE_PLL1
#if GD32_ACTIVATE_PLL
RCU->CFG0 |= GD32_PLLMUL | GD32_PLLSRC;
RCU->CTL |= RCU_CR_PLLON;
while (!(RCU->CTL & RCU_CR_PLLRDY))
RCU->CFG0 |= GD32_PLLMF | GD32_PLLSEL;
RCU->CTL |= RCU_CTL_PLLEN;
while (!(RCU->CTL & RCU_CTL_PLLSTB))
; /* Waits until PLL1 is stable. */
#endif
/* Clock settings.*/
#if GD32_HAS_USBFS
RCU->CFG0 = GD32_MCOSEL | GD32_USBPRE | GD32_PLLMUL | GD32_PLLSRC |
GD32_ADCPRE | GD32_PPRE2 | GD32_PPRE1 | GD32_HPRE;
RCU->CFG0 = GD32_CKOUT0SEL | GD32_USBFSPSC | GD32_PLLMF | GD32_PLLSEL |
GD32_ADCPSC | GD32_APB2PSC | GD32_APB1PSC | GD32_AHBPSC;
#else
RCU->CFG0 = GD32_MCO | GD32_PLLMUL | GD32_PLLSRC |
GD32_ADCPRE | GD32_PPRE2 | GD32_PPRE1 | GD32_HPRE;
RCU->CFG0 = GD32_MCO | GD32_PLLMF | GD32_PLLSEL |
GD32_ADCPSC | GD32_APB2PSC | GD32_APB1PSC | GD32_AHBPSC;
#endif
/* Flash setup and final clock selection. */
@ -248,15 +248,15 @@ void gd32_clock_init(void) {
(GD32_FLASHBITS & FLASH_WS_WSCNT_Msk)) {
}
/* Switching to the configured clock source if it is different from HSI.*/
#if (GD32_SW != GD32_SW_HSI)
RCU->CFG0 |= GD32_SW; /* Switches on the selected clock source. */
while ((RCU->CFG0 & RCU_CFGR_SWS) != (GD32_SW << 2))
/* Switching to the configured clock source if it is different from IRC8M.*/
#if (GD32_SCS != GD32_SCS_IRC8M)
RCU->CFG0 |= GD32_SCS; /* Switches on the selected clock source. */
while ((RCU->CFG0 & RCU_CFG0_SCSS) != (GD32_SCS << 2))
;
#endif
#if !GD32_HSI_ENABLED
RCU->CTL &= ~RCU_CR_HSION;
#if !GD32_IRC8M_ENABLED
RCU->CTL &= ~RCU_CTL_IRC8MEN;
#endif
#endif /* !GD32_NO_INIT */
}

36
os/hal/ports/GD/GD32VF103/hal_lld.h
View File

@ -20,10 +20,10 @@
* @brief GD32VF103 HAL subsystem low level driver header.
* @pre This module requires the following macros to be defined in the
* @p board.h file:
* - GD32_LSECLK.
* - GD32_LSE_BYPASS (optionally).
* - GD32_HSECLK.
* - GD32_HSE_BYPASS (optionally).
* - GD32_LXTALCLK.
* - GD32_LXTAL_BYPASS (optionally).
* - GD32_HXTALCLK.
* - GD32_HXTAL_BYPASS (optionally).
*
* @addtogroup HAL
* @{
@ -63,8 +63,8 @@
* @name Internal clock sources
* @{
*/
#define GD32_HSICLK 8000000 /**< High speed internal clock. */
#define GD32_LSICLK 40000 /**< Low speed internal clock. */
#define GD32_IRC8MCLK 8000000 /**< High speed internal clock. */
#define GD32_IRC40KCLK 40000 /**< Low speed internal clock. */
/** @} */
/**
@ -116,31 +116,31 @@
#endif
/**
* @brief Enables or disables the HSI clock source.
* @brief Enables or disables the IRC8M clock source.
*/
#if !defined(GD32_HSI_ENABLED) || defined(__DOXYGEN__)
#define GD32_HSI_ENABLED TRUE
#if !defined(GD32_IRC8M_ENABLED) || defined(__DOXYGEN__)
#define GD32_IRC8M_ENABLED TRUE
#endif
/**
* @brief Enables or disables the LSI clock source.
* @brief Enables or disables the IRC40K clock source.
*/
#if !defined(GD32_LSI_ENABLED) || defined(__DOXYGEN__)
#define GD32_LSI_ENABLED FALSE
#if !defined(GD32_IRC40K_ENABLED) || defined(__DOXYGEN__)
#define GD32_IRC40K_ENABLED FALSE
#endif
/**
* @brief Enables or disables the HSE clock source.
* @brief Enables or disables the HXTAL clock source.
*/
#if !defined(GD32_HSE_ENABLED) || defined(__DOXYGEN__)
#define GD32_HSE_ENABLED TRUE
#if !defined(GD32_HXTAL_ENABLED) || defined(__DOXYGEN__)
#define GD32_HXTAL_ENABLED TRUE
#endif
/**
* @brief Enables or disables the LSE clock source.
* @brief Enables or disables the LXTAL clock source.
*/
#if !defined(GD32_LSE_ENABLED) || defined(__DOXYGEN__)
#define GD32_LSE_ENABLED FALSE
#if !defined(GD32_LXTAL_ENABLED) || defined(__DOXYGEN__)
#define GD32_LXTAL_ENABLED FALSE
#endif
/** @} */

380
os/hal/ports/GD/GD32VF103/hal_lld_f103.h
View File

@ -50,24 +50,24 @@
#endif
/**
* @brief Maximum HSE clock frequency.
* @brief Maximum HXTAL clock frequency.
*/
#define GD32_HSECLK_MAX 25000000
#define GD32_HXTALCLK_MAX 25000000
/**
* @brief Minimum HSE clock frequency.
* @brief Minimum HXTAL clock frequency.
*/
#define GD32_HSECLK_MIN 1000000
#define GD32_HXTALCLK_MIN 1000000
/**
* @brief Maximum LSE clock frequency.
* @brief Maximum LXTAL clock frequency.
*/
#define GD32_LSECLK_MAX 1000000
#define GD32_LXTALCLK_MAX 1000000
/**
* @brief Minimum LSE clock frequency.
* @brief Minimum LXTAL clock frequency.
*/
#define GD32_LSECLK_MIN 32768
#define GD32_LXTALCLK_MIN 32768
/**
* @brief Maximum PLLs input clock frequency.
@ -121,55 +121,55 @@
* @name RCU_CFG0 register bits definitions
* @{
*/
#define GD32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
#define GD32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
#define GD32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
#define GD32_SCS_IRC8M (0 << 0) /**< SYSCLK source is IRC8M. */
#define GD32_SCS_HXTAL (1 << 0) /**< SYSCLK source is HXTAL. */
#define GD32_SCS_PLL (2 << 0) /**< SYSCLK source is PLL. */
#define GD32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
#define GD32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
#define GD32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
#define GD32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
#define GD32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
#define GD32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
#define GD32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
#define GD32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
#define GD32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
#define GD32_AHBPSC_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
#define GD32_AHBPSC_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
#define GD32_AHBPSC_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
#define GD32_AHBPSC_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
#define GD32_AHBPSC_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
#define GD32_AHBPSC_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
#define GD32_AHBPSC_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
#define GD32_AHBPSC_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
#define GD32_AHBPSC_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
#define GD32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
#define GD32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
#define GD32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
#define GD32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
#define GD32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
#define GD32_APB1PSC_DIV1 (0 << 8) /**< HCLK divided by 1. */
#define GD32_APB1PSC_DIV2 (4 << 8) /**< HCLK divided by 2. */
#define GD32_APB1PSC_DIV4 (5 << 8) /**< HCLK divided by 4. */
#define GD32_APB1PSC_DIV8 (6 << 8) /**< HCLK divided by 8. */
#define GD32_APB1PSC_DIV16 (7 << 8) /**< HCLK divided by 16. */
#define GD32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
#define GD32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
#define GD32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
#define GD32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
#define GD32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
#define GD32_APB2PSC_DIV1 (0 << 11) /**< HCLK divided by 1. */
#define GD32_APB2PSC_DIV2 (4 << 11) /**< HCLK divided by 2. */
#define GD32_APB2PSC_DIV4 (5 << 11) /**< HCLK divided by 4. */
#define GD32_APB2PSC_DIV8 (6 << 11) /**< HCLK divided by 8. */
#define GD32_APB2PSC_DIV16 (7 << 11) /**< HCLK divided by 16. */
#define GD32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
#define GD32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
#define GD32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
#define GD32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
#define GD32_ADCPRE_DIV12 ((1 << 28) | (1 << 14)) /**< PPRE2 divided by 8. */
#define GD32_ADCPRE_DIV16 ((1 << 28) | (3 << 14)) /**< PPRE2 divided by 8. */
#define GD32_ADCPSC_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
#define GD32_ADCPSC_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
#define GD32_ADCPSC_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
#define GD32_ADCPSC_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
#define GD32_ADCPSC_DIV12 ((1 << 28) | (1 << 14)) /**< PPRE2 divided by 8. */
#define GD32_ADCPSC_DIV16 ((1 << 28) | (3 << 14)) /**< PPRE2 divided by 8. */
#define GD32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
#define GD32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
#define GD32_PLLSEL_IRC8M (0 << 16) /**< PLL clock source is IRC8M. */
#define GD32_PLLSEL_HXTAL (1 << 16) /**< PLL clock source is HXTAL. */
#define GD32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
#define GD32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
#define GD32_PREDV0_DIV1 (0 << 17) /**< HXTAL divided by 1. */
#define GD32_PREDV0_DIV2 (1 << 17) /**< HXTAL divided by 2. */
#define GD32_USBPRE_DIV1P5 (0 << 22) /**< PLLOUT divided by 1.5. */
#define GD32_USBPRE_DIV1 (1 << 22) /**< PLLOUT divided by 1. */
#define GD32_USBPRE_DIV2P5 (2 << 22) /**< PLLOUT divided by 2.5. */
#define GD32_USBPRE_DIV2 (3 << 22) /**< PLLOUT divided by 2. */
#define GD32_USBFSPSC_DIV1P5 (0 << 22) /**< PLLOUT divided by 1.5. */
#define GD32_USBFSPSC_DIV1 (1 << 22) /**< PLLOUT divided by 1. */
#define GD32_USBFSPSC_DIV2P5 (2 << 22) /**< PLLOUT divided by 2.5. */
#define GD32_USBFSPSC_DIV2 (3 << 22) /**< PLLOUT divided by 2. */
#define GD32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define GD32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
#define GD32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
#define GD32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define GD32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
#define GD32_CKOUT0SEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define GD32_CKOUT0SEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
#define GD32_CKOUT0SEL_IRC8M (5 << 24) /**< IRC8M clock on MCO pin. */
#define GD32_CKOUT0SEL_HXTAL (6 << 24) /**< HXTAL clock on MCO pin. */
#define GD32_CKOUT0SEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
/** @} */
/**
@ -178,9 +178,9 @@
*/
#define GD32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
#define GD32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define GD32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
#define GD32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
#define GD32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
#define GD32_RTCSEL_LXTAL (1 << 8) /**< LXTAL used as RTC clock. */
#define GD32_RTCSEL_IRC40K (2 << 8) /**< IRC40K used as RTC clock. */
#define GD32_RTCSEL_HXTALDIV (3 << 8) /**< HXTAL divided by 128 used as
RTC clock. */
/** @} */
@ -199,8 +199,8 @@
* @note The default value is calculated for a 72MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(GD32_SW) || defined(__DOXYGEN__)
#define GD32_SW GD32_SW_PLL
#if !defined(GD32_SCS) || defined(__DOXYGEN__)
#define GD32_SCS GD32_SCS_PLL
#endif
/**
@ -210,8 +210,8 @@
* @note The default value is calculated for a 72MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(GD32_PLLSRC) || defined(__DOXYGEN__)
#define GD32_PLLSRC GD32_PLLSRC_HSE
#if !defined(GD32_PLLSEL) || defined(__DOXYGEN__)
#define GD32_PLLSEL GD32_PLLSEL_HXTAL
#endif
/**
@ -221,18 +221,18 @@
* @note The default value is calculated for a 72MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(GD32_PLLXTPRE) || defined(__DOXYGEN__)
#define GD32_PLLXTPRE GD32_PLLXTPRE_DIV1
#if !defined(GD32_PREDV0) || defined(__DOXYGEN__)
#define GD32_PREDV0 GD32_PREDV0_DIV1
#endif
/**
* @brief PLL multiplier value.
* @note The allowed range is 2...16.
* @note The allowed range is 2...32
* @note The default value is calculated for a 72MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(GD32_PLLMUL_VALUE) || defined(__DOXYGEN__)
#define GD32_PLLMUL_VALUE 9
#if !defined(GD32_PLLMF_VALUE) || defined(__DOXYGEN__)
#define GD32_PLLMF_VALUE 9
#endif
/**
@ -240,29 +240,29 @@
* @note The default value is calculated for a 72MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(GD32_HPRE) || defined(__DOXYGEN__)
#define GD32_HPRE GD32_HPRE_DIV1
#if !defined(GD32_AHBPSC) || defined(__DOXYGEN__)
#define GD32_AHBPSC GD32_AHBPSC_DIV1
#endif
/**
* @brief APB1 prescaler value.
*/
#if !defined(GD32_PPRE1) || defined(__DOXYGEN__)
#define GD32_PPRE1 GD32_PPRE1_DIV2
#if !defined(GD32_APB1PSC) || defined(__DOXYGEN__)
#define GD32_APB1PSC GD32_APB1PSC_DIV2
#endif
/**
* @brief APB2 prescaler value.
*/
#if !defined(GD32_PPRE2) || defined(__DOXYGEN__)
#define GD32_PPRE2 GD32_PPRE2_DIV2
#if !defined(GD32_APB2PSC) || defined(__DOXYGEN__)
#define GD32_APB2PSC GD32_APB2PSC_DIV2
#endif
/**
* @brief ADC prescaler value.
*/
#if !defined(GD32_ADCPRE) || defined(__DOXYGEN__)
#define GD32_ADCPRE GD32_ADCPRE_DIV4
#if !defined(GD32_ADCPSC) || defined(__DOXYGEN__)
#define GD32_ADCPSC GD32_ADCPSC_DIV4
#endif
/**
@ -275,22 +275,22 @@
/**
* @brief USB prescaler initialization.
*/
#if !defined(GD32_USBPRE) || defined(__DOXYGEN__)
#define GD32_USBPRE GD32_USBPRE_DIV1P5
#if !defined(GD32_USBFSPSC) || defined(__DOXYGEN__)
#define GD32_USBFSPSC GD32_USBFSPSC_DIV1P5
#endif
/**
* @brief MCO pin setting.
*/
#if !defined(GD32_MCOSEL) || defined(__DOXYGEN__)
#define GD32_MCOSEL GD32_MCOSEL_NOCLOCK
#if !defined(GD32_CKOUT0SEL) || defined(__DOXYGEN__)
#define GD32_CKOUT0SEL GD32_CKOUT0SEL_NOCLOCK
#endif
/**
* @brief RTC clock source.
*/
#if !defined(GD32_RTCSEL) || defined(__DOXYGEN__)
#define GD32_RTCSEL GD32_RTCSEL_LSI
#define GD32_RTCSEL GD32_RTCSEL_IRC40K
#endif
/** @} */
@ -306,97 +306,97 @@
#endif
/*
* HSI related checks.
* IRC8M related checks.
*/
#if GD32_HSI_ENABLED
#else /* !GD32_HSI_ENABLED */
#if GD32_IRC8M_ENABLED
#else /* !GD32_IRC8M_ENABLED */
#if GD32_SW == GD32_SW_HSI
#error "HSI not enabled, required by GD32_SW"
#if GD32_SCS == GD32_SCS_IRC8M
#error "IRC8M not enabled, required by GD32_SCS"
#endif
#if (GD32_SW == GD32_SW_PLL) && (GD32_PLLSRC == GD32_PLLSRC_HSI)
#error "HSI not enabled, required by GD32_SW and GD32_PLLSRC"
#if (GD32_SCS == GD32_SCS_PLL) && (GD32_PLLSEL == GD32_PLLSEL_IRC8M)
#error "IRC8M not enabled, required by GD32_SCS and GD32_PLLSEL"
#endif
#if (GD32_MCOSEL == GD32_MCOSEL_HSI) || \
((GD32_MCOSEL == GD32_MCOSEL_PLLDIV2) && \
(GD32_PLLSRC == GD32_PLLSRC_HSI))
#error "HSI not enabled, required by GD32_MCOSEL"
#if (GD32_CKOUT0SEL == GD32_CKOUT0SEL_IRC8M) || \
((GD32_CKOUT0SEL == GD32_CKOUT0SEL_PLLDIV2) && \
(GD32_PLLSEL == GD32_PLLSEL_IRC8M))
#error "IRC8M not enabled, required by GD32_CKOUT0SEL"
#endif
#endif /* !GD32_HSI_ENABLED */
#endif /* !GD32_IRC8M_ENABLED */
/*
* HSE related checks.
* HXTAL related checks.
*/
#if GD32_HSE_ENABLED
#if GD32_HXTAL_ENABLED
#if GD32_HSECLK == 0
#error "HSE frequency not defined"
#elif (GD32_HSECLK < GD32_HSECLK_MIN) || (GD32_HSECLK > GD32_HSECLK_MAX)
#error "GD32_HSECLK outside acceptable range (GD32_HSECLK_MIN...GD32_HSECLK_MAX)"
#if GD32_HXTALCLK == 0
#error "HXTAL frequency not defined"
#elif (GD32_HXTALCLK < GD32_HXTALCLK_MIN) || (GD32_HXTALCLK > GD32_HXTALCLK_MAX)
#error "GD32_HXTALCLK outside acceptable range (GD32_HXTALCLK_MIN...GD32_HXTALCLK_MAX)"
#endif
#else /* !GD32_HSE_ENABLED */
#else /* !GD32_HXTAL_ENABLED */
#if GD32_SW == GD32_SW_HSE
#error "HSE not enabled, required by GD32_SW"
#if GD32_SCS == GD32_SCS_HXTAL
#error "HXTAL not enabled, required by GD32_SCS"
#endif
#if (GD32_SW == GD32_SW_PLL) && (GD32_PLLSRC == GD32_PLLSRC_HSE)
#error "HSE not enabled, required by GD32_SW and GD32_PLLSRC"
#if (GD32_SCS == GD32_SCS_PLL) && (GD32_PLLSEL == GD32_PLLSEL_HXTAL)
#error "HXTAL not enabled, required by GD32_SCS and GD32_PLLSEL"
#endif
#if (GD32_MCOSEL == GD32_MCOSEL_HSE) || \
((GD32_MCOSEL == GD32_MCOSEL_PLLDIV2) && \
(GD32_PLLSRC == GD32_PLLSRC_HSE))
#error "HSE not enabled, required by GD32_MCOSEL"
#if (GD32_CKOUT0SEL == GD32_CKOUT0SEL_HXTAL) || \
((GD32_CKOUT0SEL == GD32_CKOUT0SEL_PLLDIV2) && \
(GD32_PLLSEL == GD32_PLLSEL_HXTAL))
#error "HXTAL not enabled, required by GD32_CKOUT0SEL"
#endif
#if GD32_RTCSEL == GD32_RTCSEL_HSEDIV
#error "HSE not enabled, required by GD32_RTCSEL"
#if GD32_RTCSEL == GD32_RTCSEL_HXTALDIV
#error "HXTAL not enabled, required by GD32_RTCSEL"
#endif
#endif /* !GD32_HSE_ENABLED */
#endif /* !GD32_HXTAL_ENABLED */
/*
* LSI related checks.
* IRC40K related checks.
*/
#if GD32_LSI_ENABLED
#else /* !GD32_LSI_ENABLED */
#if GD32_IRC40K_ENABLED
#else /* !GD32_IRC40K_ENABLED */
#if GD32_RTCSEL == GD32_RTCSEL_LSI
#error "LSI not enabled, required by GD32_RTCSEL"
#if GD32_RTCSEL == GD32_RTCSEL_IRC40K
#error "IRC40K not enabled, required by GD32_RTCSEL"
#endif
#endif /* !GD32_LSI_ENABLED */
#endif /* !GD32_IRC40K_ENABLED */
/*
* LSE related checks.
* LXTAL related checks.
*/
#if GD32_LSE_ENABLED
#if GD32_LXTAL_ENABLED
#if (GD32_LSECLK == 0)
#error "LSE frequency not defined"
#if (GD32_LXTALCLK == 0)
#error "LXTAL frequency not defined"
#endif
#if (GD32_LSECLK < GD32_LSECLK_MIN) || (GD32_LSECLK > GD32_LSECLK_MAX)
#error "GD32_LSECLK outside acceptable range (GD32_LSECLK_MIN...GD32_LSECLK_MAX)"
#if (GD32_LXTALCLK < GD32_LXTALCLK_MIN) || (GD32_LXTALCLK > GD32_LXTALCLK_MAX)
#error "GD32_LXTALCLK outside acceptable range (GD32_LXTALCLK_MIN...GD32_LXTALCLK_MAX)"
#endif
#else /* !GD32_LSE_ENABLED */
#else /* !GD32_LXTAL_ENABLED */
#if GD32_RTCSEL == GD32_RTCSEL_LSE
#error "LSE not enabled, required by GD32_RTCSEL"
#if GD32_RTCSEL == GD32_RTCSEL_LXTAL
#error "LXTAL not enabled, required by GD32_RTCSEL"
#endif
#endif /* !GD32_LSE_ENABLED */
#endif /* !GD32_LXTAL_ENABLED */
/* PLL activation conditions.*/
#if GD32_USB_CLOCK_REQUIRED || \
(GD32_SW == GD32_SW_PLL) || \
(GD32_MCOSEL == GD32_MCOSEL_PLLDIV2) || \
(GD32_SCS == GD32_SCS_PLL) || \
(GD32_CKOUT0SEL == GD32_CKOUT0SEL_PLLDIV2) || \
defined(__DOXYGEN__)
/**
* @brief PLL activation flag.
@ -406,41 +406,41 @@
#define GD32_ACTIVATE_PLL FALSE
#endif
/* HSE prescaler setting check.*/
#if (GD32_PLLXTPRE != GD32_PLLXTPRE_DIV1) && \
(GD32_PLLXTPRE != GD32_PLLXTPRE_DIV2)
#error "invalid GD32_PLLXTPRE value specified"
/* HXTAL prescaler setting check.*/
#if (GD32_PREDV0 != GD32_PREDV0_DIV1) && \
(GD32_PREDV0 != GD32_PREDV0_DIV2)
#error "invalid GD32_PREDV0 value specified"
#endif
/**
* @brief PLLMUL field.
*/
/*#if GD32_PLLMUL_VALUE == 6.5
#define GD32_PLLMUL 13 << 18*/
#if ((GD32_PLLMUL_VALUE >= 2) && (GD32_PLLMUL_VALUE <= 16)) || \
/*#if GD32_PLLMF_VALUE == 6.5
#define GD32_PLLMF 13 << 18*/
#if ((GD32_PLLMF_VALUE >= 2) && (GD32_PLLMF_VALUE <= 16)) || \
defined(__DOXYGEN__)
#define GD32_PLLMUL ((GD32_PLLMUL_VALUE - 2) << 18)
#elif ((GD32_PLLMUL_VALUE >= 17) && (GD32_PLLMUL_VALUE <= 32))
#define GD32_PLLMUL ((1 << 29) | ((GD32_PLLMUL_VALUE - 17) << 18))
#define GD32_PLLMF ((GD32_PLLMF_VALUE - 2) << 18)
#elif ((GD32_PLLMF_VALUE >= 17) && (GD32_PLLMF_VALUE <= 32))
#define GD32_PLLMF ((1 << 29) | ((GD32_PLLMF_VALUE - 17) << 18))
#else
#error "invalid GD32_PLLMUL_VALUE value specified"
#error "invalid GD32_PLLMF_VALUE value specified"
#endif
//#pragma message(STRING(GD32_PLLMUL))
//#pragma message(STRING(GD32_PLLMF))
/**
* @brief PLL input clock frequency.
*/
#if (GD32_PLLSRC == GD32_PLLSRC_HSE) || defined(__DOXYGEN__)
#if GD32_PLLXTPRE == GD32_PLLXTPRE_DIV1
#define GD32_PLLCLKIN (GD32_HSECLK / 1)
#if (GD32_PLLSEL == GD32_PLLSEL_HXTAL) || defined(__DOXYGEN__)
#if GD32_PREDV0 == GD32_PREDV0_DIV1
#define GD32_PLLCLKIN (GD32_HXTALCLK / 1)
#else
#define GD32_PLLCLKIN (GD32_HSECLK / 2)
#define GD32_PLLCLKIN (GD32_HXTALCLK / 2)
#endif
#elif GD32_PLLSRC == GD32_PLLSRC_HSI
#define GD32_PLLCLKIN (GD32_HSICLK / 2)
#elif GD32_PLLSEL == GD32_PLLSEL_IRC8M
#define GD32_PLLCLKIN (GD32_IRC8MCLK / 2)
#else
#error "invalid GD32_PLLSRC value specified"
#error "invalid GD32_PLLSEL value specified"
#endif
/* PLL input frequency range check.*/
@ -451,7 +451,7 @@
/**
* @brief PLL output clock frequency.
*/
#define GD32_PLLCLKOUT (GD32_PLLCLKIN * GD32_PLLMUL_VALUE)
#define GD32_PLLCLKOUT (GD32_PLLCLKIN * GD32_PLLMF_VALUE)
/* PLL output frequency range check.*/
#if (GD32_PLLCLKOUT < GD32_PLLOUT_MIN) || (GD32_PLLCLKOUT > GD32_PLLOUT_MAX)
@ -461,14 +461,14 @@
/**
* @brief System clock source.
*/
#if (GD32_SW == GD32_SW_PLL) || defined(__DOXYGEN__)
#if (GD32_SCS == GD32_SCS_PLL) || defined(__DOXYGEN__)
#define GD32_SYSCLK GD32_PLLCLKOUT
#elif (GD32_SW == GD32_SW_HSI)
#define GD32_SYSCLK GD32_HSICLK
#elif (GD32_SW == GD32_SW_HSE)
#define GD32_SYSCLK GD32_HSECLK
#elif (GD32_SCS == GD32_SCS_IRC8M)
#define GD32_SYSCLK GD32_IRC8MCLK
#elif (GD32_SCS == GD32_SCS_HXTAL)
#define GD32_SYSCLK GD32_HXTALCLK
#else
#error "invalid GD32_SW value specified"
#error "invalid GD32_SCS value specified"
#endif
/* Check on the system clock.*/
@ -479,26 +479,26 @@
/**
* @brief AHB frequency.
*/
#if (GD32_HPRE == GD32_HPRE_DIV1) || defined(__DOXYGEN__)
#if (GD32_AHBPSC == GD32_AHBPSC_DIV1) || defined(__DOXYGEN__)
#define GD32_HCLK (GD32_SYSCLK / 1)
#elif GD32_HPRE == GD32_HPRE_DIV2
#elif GD32_AHBPSC == GD32_AHBPSC_DIV2
#define GD32_HCLK (GD32_SYSCLK / 2)
#elif GD32_HPRE == GD32_HPRE_DIV4
#elif GD32_AHBPSC == GD32_AHBPSC_DIV4
#define GD32_HCLK (GD32_SYSCLK / 4)
#elif GD32_HPRE == GD32_HPRE_DIV8
#elif GD32_AHBPSC == GD32_AHBPSC_DIV8
#define GD32_HCLK (GD32_SYSCLK / 8)
#elif GD32_HPRE == GD32_HPRE_DIV16
#elif GD32_AHBPSC == GD32_AHBPSC_DIV16
#define GD32_HCLK (GD32_SYSCLK / 16)
#elif GD32_HPRE == GD32_HPRE_DIV64
#elif GD32_AHBPSC == GD32_AHBPSC_DIV64
#define GD32_HCLK (GD32_SYSCLK / 64)
#elif GD32_HPRE == GD32_HPRE_DIV128
#elif GD32_AHBPSC == GD32_AHBPSC_DIV128
#define GD32_HCLK (GD32_SYSCLK / 128)
#elif GD32_HPRE == GD32_HPRE_DIV256
#elif GD32_AHBPSC == GD32_AHBPSC_DIV256
#define GD32_HCLK (GD32_SYSCLK / 256)
#elif GD32_HPRE == GD32_HPRE_DIV512
#elif GD32_AHBPSC == GD32_AHBPSC_DIV512
#define GD32_HCLK (GD32_SYSCLK / 512)
#else
#error "invalid GD32_HPRE value specified"
#error "invalid GD32_AHBPSC value specified"
#endif
/* AHB frequency check.*/
@ -509,18 +509,18 @@
/**
* @brief APB1 frequency.
*/
#if (GD32_PPRE1 == GD32_PPRE1_DIV1) || defined(__DOXYGEN__)
#if (GD32_APB1PSC == GD32_APB1PSC_DIV1) || defined(__DOXYGEN__)
#define GD32_PCLK1 (GD32_HCLK / 1)
#elif GD32_PPRE1 == GD32_PPRE1_DIV2
#elif GD32_APB1PSC == GD32_APB1PSC_DIV2
#define GD32_PCLK1 (GD32_HCLK / 2)
#elif GD32_PPRE1 == GD32_PPRE1_DIV4
#elif GD32_APB1PSC == GD32_APB1PSC_DIV4
#define GD32_PCLK1 (GD32_HCLK / 4)
#elif GD32_PPRE1 == GD32_PPRE1_DIV8
#elif GD32_APB1PSC == GD32_APB1PSC_DIV8
#define GD32_PCLK1 (GD32_HCLK / 8)
#elif GD32_PPRE1 == GD32_PPRE1_DIV16
#elif GD32_APB1PSC == GD32_APB1PSC_DIV16
#define GD32_PCLK1 (GD32_HCLK / 16)
#else
#error "invalid GD32_PPRE1 value specified"
#error "invalid GD32_APB1PSC value specified"
#endif
/* APB1 frequency check.*/
@ -531,18 +531,18 @@
/**
* @brief APB2 frequency.
*/
#if (GD32_PPRE2 == GD32_PPRE2_DIV1) || defined(__DOXYGEN__)
#if (GD32_APB2PSC == GD32_APB2PSC_DIV1) || defined(__DOXYGEN__)
#define GD32_PCLK2 (GD32_HCLK / 1)
#elif GD32_PPRE2 == GD32_PPRE2_DIV2
#elif GD32_APB2PSC == GD32_APB2PSC_DIV2
#define GD32_PCLK2 (GD32_HCLK / 2)
#elif GD32_PPRE2 == GD32_PPRE2_DIV4
#elif GD32_APB2PSC == GD32_APB2PSC_DIV4
#define GD32_PCLK2 (GD32_HCLK / 4)
#elif GD32_PPRE2 == GD32_PPRE2_DIV8
#elif GD32_APB2PSC == GD32_APB2PSC_DIV8
#define GD32_PCLK2 (GD32_HCLK / 8)
#elif GD32_PPRE2 == GD32_PPRE2_DIV16
#elif GD32_APB2PSC == GD32_APB2PSC_DIV16
#define GD32_PCLK2 (GD32_HCLK / 16)
#else
#error "invalid GD32_PPRE2 value specified"
#error "invalid GD32_APB2PSC value specified"
#endif
/* APB2 frequency check.*/
@ -553,12 +553,12 @@
/**
* @brief RTC clock.
*/
#if (GD32_RTCSEL == GD32_RTCSEL_LSE) || defined(__DOXYGEN__)
#define GD32_RTCCLK GD32_LSECLK
#elif GD32_RTCSEL == GD32_RTCSEL_LSI
#define GD32_RTCCLK GD32_LSICLK
#elif GD32_RTCSEL == GD32_RTCSEL_HSEDIV
#define GD32_RTCCLK (GD32_HSECLK / 128)
#if (GD32_RTCSEL == GD32_RTCSEL_LXTAL) || defined(__DOXYGEN__)
#define GD32_RTCCLK GD32_LXTALCLK
#elif GD32_RTCSEL == GD32_RTCSEL_IRC40K
#define GD32_RTCCLK GD32_IRC40KCLK
#elif GD32_RTCSEL == GD32_RTCSEL_HXTALDIV
#define GD32_RTCCLK (GD32_HXTALCLK / 128)
#elif GD32_RTCSEL == GD32_RTCSEL_NOCLOCK
#define GD32_RTCCLK 0
#else
@ -568,20 +568,20 @@
/**
* @brief ADC frequency.
*/
#if (GD32_ADCPRE == GD32_ADCPRE_DIV2) || defined(__DOXYGEN__)
#if (GD32_ADCPSC == GD32_ADCPSC_DIV2) || defined(__DOXYGEN__)
#define GD32_ADCCLK (GD32_PCLK2 / 2)
#elif GD32_ADCPRE == GD32_ADCPRE_DIV4
#elif GD32_ADCPSC == GD32_ADCPSC_DIV4
#define GD32_ADCCLK (GD32_PCLK2 / 4)
#elif GD32_ADCPRE == GD32_ADCPRE_DIV6
#elif GD32_ADCPSC == GD32_ADCPSC_DIV6
#define GD32_ADCCLK (GD32_PCLK2 / 6)
#elif GD32_ADCPRE == GD32_ADCPRE_DIV8
#elif GD32_ADCPSC == GD32_ADCPSC_DIV8
#define GD32_ADCCLK (GD32_PCLK2 / 8)
#elif GD32_ADCPRE == GD32_ADCPRE_DIV12
#elif GD32_ADCPSC == GD32_ADCPSC_DIV12
#define GD32_ADCCLK (GD32_PCLK2 / 12)
#elif GD32_ADCPRE == GD32_ADCPRE_DIV16
#elif GD32_ADCPSC == GD32_ADCPSC_DIV16
#define GD32_ADCCLK (GD32_PCLK2 / 16)
#else
#error "invalid GD32_ADCPRE value specified"
#error "invalid GD32_ADCPSC value specified"
#endif
/* ADC frequency check.*/
@ -592,22 +592,22 @@
/**
* @brief USB frequency.
*/
#if (GD32_USBPRE == GD32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
#if (GD32_USBFSPSC == GD32_USBFSPSC_DIV1P5) || defined(__DOXYGEN__)
#define GD32_USBFSCLK ((GD32_PLLCLKOUT * 2) / 3)
#elif (GD32_USBPRE == GD32_USBPRE_DIV1)
#elif (GD32_USBFSPSC == GD32_USBFSPSC_DIV1)
#define GD32_USBFSCLK GD32_PLLCLKOUT
#elif (GD32_USBPRE == GD32_USBPRE_DIV2)
#elif (GD32_USBFSPSC == GD32_USBFSPSC_DIV2)
#define GD32_USBFSCLK GD32_PLLCLKOUT / 2
#elif (GD32_USBPRE == GD32_USBPRE_DIV2P5)
#elif (GD32_USBFSPSC == GD32_USBFSPSC_DIV2P5)
#define GD32_USBFSCLK ((GD32_PLLCLKOUT * 2) / 5)
#else
#error "invalid GD32_USBPRE value specified"
#error "invalid GD32_USBFSPSC value specified"
#endif
/**
* @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
*/
#if (GD32_PPRE1 == GD32_PPRE1_DIV1) || defined(__DOXYGEN__)
#if (GD32_APB1PSC == GD32_APB1PSC_DIV1) || defined(__DOXYGEN__)
#define GD32_TIMCLK1 (GD32_PCLK1 * 1)
#else
#define GD32_TIMCLK1 (GD32_PCLK1 * 2)
@ -616,7 +616,7 @@
/**
* @brief Timers 1, 8, 9, 10, 11 clock.
*/
#if (GD32_PPRE2 == GD32_PPRE2_DIV1) || defined(__DOXYGEN__)
#if (GD32_APB2PSC == GD32_APB2PSC_DIV1) || defined(__DOXYGEN__)
#define GD32_TIMCLK2 (GD32_PCLK2 * 1)
#else
#define GD32_TIMCLK2 (GD32_PCLK2 * 2)

354
os/hal/ports/GD/GD32VF103/hal_lld_f105_f107.h
View File

@ -46,24 +46,24 @@
#define GD32_SYSCLK_MAX 72000000
/**
* @brief Maximum HSE clock frequency.
* @brief Maximum HXTAL clock frequency.
*/
#define GD32_HSECLK_MAX 50000000
#define GD32_HXTALCLK_MAX 50000000
/**
* @brief Minimum HSE clock frequency.
* @brief Minimum HXTAL clock frequency.
*/
#define GD32_HSECLK_MIN 1000000
#define GD32_HXTALCLK_MIN 1000000
/**
* @brief Maximum LSE clock frequency.
* @brief Maximum LXTAL clock frequency.
*/
#define GD32_LSECLK_MAX 1000000
#define GD32_LXTALCLK_MAX 1000000
/**
* @brief Minimum LSE clock frequency.
* @brief Minimum LXTAL clock frequency.
*/
#define GD32_LSECLK_MIN 32768
#define GD32_LXTALCLK_MIN 32768
/**
* @brief Maximum PLLs input clock frequency.
@ -127,56 +127,56 @@
/** @} */
/**
* @name RCU_CFGR register bits definitions
* @name RCU_CFG0 register bits definitions
* @{
*/
#define GD32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
#define GD32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
#define GD32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
#define GD32_SCS_IRC8M (0 << 0) /**< SYSCLK source is IRC8M. */
#define GD32_SCS_HXTAL (1 << 0) /**< SYSCLK source is HXTAL. */
#define GD32_SCS_PLL (2 << 0) /**< SYSCLK source is PLL. */
#define GD32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
#define GD32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
#define GD32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
#define GD32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
#define GD32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
#define GD32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
#define GD32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
#define GD32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
#define GD32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
#define GD32_AHBPSC_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
#define GD32_AHBPSC_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
#define GD32_AHBPSC_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
#define GD32_AHBPSC_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
#define GD32_AHBPSC_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
#define GD32_AHBPSC_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
#define GD32_AHBPSC_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
#define GD32_AHBPSC_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
#define GD32_AHBPSC_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
#define GD32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
#define GD32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
#define GD32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
#define GD32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
#define GD32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
#define GD32_APB1PSC_DIV1 (0 << 8) /**< HCLK divided by 1. */
#define GD32_APB1PSC_DIV2 (4 << 8) /**< HCLK divided by 2. */
#define GD32_APB1PSC_DIV4 (5 << 8) /**< HCLK divided by 4. */
#define GD32_APB1PSC_DIV8 (6 << 8) /**< HCLK divided by 8. */
#define GD32_APB1PSC_DIV16 (7 << 8) /**< HCLK divided by 16. */
#define GD32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
#define GD32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
#define GD32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
#define GD32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
#define GD32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
#define GD32_APB2PSC_DIV1 (0 << 11) /**< HCLK divided by 1. */
#define GD32_APB2PSC_DIV2 (4 << 11) /**< HCLK divided by 2. */
#define GD32_APB2PSC_DIV4 (5 << 11) /**< HCLK divided by 4. */
#define GD32_APB2PSC_DIV8 (6 << 11) /**< HCLK divided by 8. */
#define GD32_APB2PSC_DIV16 (7 << 11) /**< HCLK divided by 16. */
#define GD32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
#define GD32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
#define GD32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
#define GD32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
#define GD32_ADCPSC_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
#define GD32_ADCPSC_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
#define GD32_ADCPSC_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
#define GD32_ADCPSC_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
#define GD32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
#define GD32_PLLSRC_PREDIV1 (1 << 16) /**< PLL clock source is
#define GD32_PLLSEL_IRC8M (0 << 16) /**< PLL clock source is IRC8M. */
#define GD32_PLLSEL_PREDIV1 (1 << 16) /**< PLL clock source is
PREDIV1. */
#define GD32_USBFSPRE_DIV2 (1 << 22) /**< HCLK*2 divided by 2. */
#define GD32_USBFSPRE_DIV3 (0 << 22) /**< HCLK*2 divided by 3. */
#define GD32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define GD32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
#define GD32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
#define GD32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define GD32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
#define GD32_MCOSEL_PLL2 (8 << 24) /**< PLL2 clock on MCO pin. */
#define GD32_MCOSEL_PLL3DIV2 (9 << 24) /**< PLL3/2 clock on MCO pin. */
#define GD32_MCOSEL_XT1 (10 << 24) /**< XT1 clock on MCO pin. */
#define GD32_MCOSEL_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */
#define GD32_CKOUT0SEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define GD32_CKOUT0SEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
#define GD32_CKOUT0SEL_IRC8M (5 << 24) /**< IRC8M clock on MCO pin. */
#define GD32_CKOUT0SEL_HXTAL (6 << 24) /**< HXTAL clock on MCO pin. */
#define GD32_CKOUT0SEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
#define GD32_CKOUT0SEL_PLL2 (8 << 24) /**< PLL2 clock on MCO pin. */
#define GD32_CKOUT0SEL_PLL3DIV2 (9 << 24) /**< PLL3/2 clock on MCO pin. */
#define GD32_CKOUT0SEL_XT1 (10 << 24) /**< XT1 clock on MCO pin. */
#define GD32_CKOUT0SEL_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */
/** @} */
/**
@ -185,17 +185,17 @@
*/
#define GD32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
#define GD32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define GD32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
#define GD32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
#define GD32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
#define GD32_RTCSEL_LXTAL (1 << 8) /**< LXTAL used as RTC clock. */
#define GD32_RTCSEL_IRC40K (2 << 8) /**< IRC40K used as RTC clock. */
#define GD32_RTCSEL_HXTALDIV (3 << 8) /**< HXTAL divided by 128 used as
RTC clock. */
/** @} */
/**
* @name RCU_CFGR2 register bits definitions
* @name RCU_CFG02 register bits definitions
* @{
*/
#define GD32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */
#define GD32_PREDIV1SRC_HXTAL (0 << 16) /**< PREDIV1 source is HXTAL. */
#define GD32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */
/** @} */
@ -212,8 +212,8 @@
* @note The default value is calculated for a 72MHz system clock from
* a 25MHz crystal using both PLL and PLL2.
*/
#if !defined(GD32_SW) || defined(__DOXYGEN__)
#define GD32_SW GD32_SW_PLL
#if !defined(GD32_SCS) || defined(__DOXYGEN__)
#define GD32_SCS GD32_SCS_PLL
#endif
/**
@ -221,8 +221,8 @@
* @note The default value is calculated for a 72MHz system clock from
* a 25MHz crystal using both PLL and PLL2.
*/
#if !defined(GD32_PLLSRC) || defined(__DOXYGEN__)
#define GD32_PLLSRC GD32_PLLSRC_PREDIV1
#if !defined(GD32_PLLSEL) || defined(__DOXYGEN__)
#define GD32_PLLSEL GD32_PLLSEL_PREDIV1
#endif
/**
@ -231,7 +231,7 @@
* a 25MHz crystal using both PLL and PLL2.
*/
#if !defined(GD32_PREDIV1SRC) || defined(__DOXYGEN__)
#define GD32_PREDIV1SRC GD32_PREDIV1SRC_HSE
#define GD32_PREDIV1SRC GD32_PREDIV1SRC_HXTAL
#endif
/**
@ -250,8 +250,8 @@
* @note The default value is calculated for a 72MHz system clock from
* a 25MHz crystal using both PLL and PLL2.
*/
#if !defined(GD32_PLLMUL_VALUE) || defined(__DOXYGEN__)
#define GD32_PLLMUL_VALUE 9
#if !defined(GD32_PLLMF_VALUE) || defined(__DOXYGEN__)
#define GD32_PLLMF_VALUE 9
#endif
/**
@ -287,29 +287,29 @@
* @note The default value is calculated for a 72MHz system clock from
* a 25MHz crystal using both PLL and PLL2.
*/
#if !defined(GD32_HPRE) || defined(__DOXYGEN__)
#define GD32_HPRE GD32_HPRE_DIV1
#if !defined(GD32_AHBPSC) || defined(__DOXYGEN__)
#define GD32_AHBPSC GD32_AHBPSC_DIV1
#endif
/**
* @brief APB1 prescaler value.
*/
#if !defined(GD32_PPRE1) || defined(__DOXYGEN__)
#define GD32_PPRE1 GD32_PPRE1_DIV2
#if !defined(GD32_APB1PSC) || defined(__DOXYGEN__)
#define GD32_APB1PSC GD32_APB1PSC_DIV2
#endif
/**
* @brief APB2 prescaler value.
*/
#if !defined(GD32_PPRE2) || defined(__DOXYGEN__)
#define GD32_PPRE2 GD32_PPRE2_DIV2
#if !defined(GD32_APB2PSC) || defined(__DOXYGEN__)
#define GD32_APB2PSC GD32_APB2PSC_DIV2
#endif
/**
* @brief ADC prescaler value.
*/
#if !defined(GD32_ADCPRE) || defined(__DOXYGEN__)
#define GD32_ADCPRE GD32_ADCPRE_DIV4
#if !defined(GD32_ADCPSC) || defined(__DOXYGEN__)
#define GD32_ADCPSC GD32_ADCPSC_DIV4
#endif
/**
@ -336,15 +336,15 @@
/**
* @brief MCO pin setting.
*/
#if !defined(GD32_MCOSEL) || defined(__DOXYGEN__)
#define GD32_MCOSEL GD32_MCOSEL_NOCLOCK
#if !defined(GD32_CKOUT0SEL) || defined(__DOXYGEN__)
#define GD32_CKOUT0SEL GD32_CKOUT0SEL_NOCLOCK
#endif
/**
* @brief RTC clock source.
*/
#if !defined(GD32_RTCSEL) || defined(__DOXYGEN__)
#define GD32_RTCSEL GD32_RTCSEL_HSEDIV
#define GD32_RTCSEL GD32_RTCSEL_HXTALDIV
#endif
/** @} */
@ -360,101 +360,101 @@
#endif*/
/*
* HSI related checks.
* IRC8M related checks.
*/
#if GD32_HSI_ENABLED
#else /* !GD32_HSI_ENABLED */
#if GD32_IRC8M_ENABLED
#else /* !GD32_IRC8M_ENABLED */
#if GD32_SW == GD32_SW_HSI
#error "HSI not enabled, required by GD32_SW"
#if GD32_SCS == GD32_SCS_IRC8M
#error "IRC8M not enabled, required by GD32_SCS"
#endif
#if (GD32_SW == GD32_SW_PLL) && (GD32_PLLSRC == GD32_PLLSRC_HSI)
#error "HSI not enabled, required by GD32_SW and GD32_PLLSRC"
#if (GD32_SCS == GD32_SCS_PLL) && (GD32_PLLSEL == GD32_PLLSEL_IRC8M)
#error "IRC8M not enabled, required by GD32_SCS and GD32_PLLSEL"
#endif
#if (GD32_MCOSEL == GD32_MCOSEL_HSI) || \
((GD32_MCOSEL == GD32_MCOSEL_PLLDIV2) && \
(GD32_PLLSRC == GD32_PLLSRC_HSI))
#error "HSI not enabled, required by GD32_MCOSEL"
#if (GD32_CKOUT0SEL == GD32_CKOUT0SEL_IRC8M) || \
((GD32_CKOUT0SEL == GD32_CKOUT0SEL_PLLDIV2) && \
(GD32_PLLSEL == GD32_PLLSEL_IRC8M))
#error "IRC8M not enabled, required by GD32_CKOUT0SEL"
#endif
#endif /* !GD32_HSI_ENABLED */
#endif /* !GD32_IRC8M_ENABLED */
/*
* HSE related checks.
* HXTAL related checks.
*/
#if GD32_HSE_ENABLED
#if GD32_HXTAL_ENABLED
#if GD32_HSECLK == 0
#error "HSE frequency not defined"
#elif (GD32_HSECLK < GD32_HSECLK_MIN) || (GD32_HSECLK > GD32_HSECLK_MAX)
#error "GD32_HSECLK outside acceptable range (GD32_HSECLK_MIN...GD32_HSECLK_MAX)"
#if GD32_HXTALCLK == 0
#error "HXTAL frequency not defined"
#elif (GD32_HXTALCLK < GD32_HXTALCLK_MIN) || (GD32_HXTALCLK > GD32_HXTALCLK_MAX)
#error "GD32_HXTALCLK outside acceptable range (GD32_HXTALCLK_MIN...GD32_HXTALCLK_MAX)"
#endif
#else /* !GD32_HSE_ENABLED */
#else /* !GD32_HXTAL_ENABLED */
#if GD32_SW == GD32_SW_HSE
#error "HSE not enabled, required by GD32_SW"
#if GD32_SCS == GD32_SCS_HXTAL
#error "HXTAL not enabled, required by GD32_SCS"
#endif
#if (GD32_SW == GD32_SW_PLL) && (GD32_PLLSRC == GD32_PLLSRC_PREDIV1)
#error "HSE not enabled, required by GD32_SW and GD32_PLLSRC"
#if (GD32_SCS == GD32_SCS_PLL) && (GD32_PLLSEL == GD32_PLLSEL_PREDIV1)
#error "HXTAL not enabled, required by GD32_SCS and GD32_PLLSEL"
#endif
#if (GD32_MCOSEL == GD32_MCOSEL_HSE) || \
(((GD32_MCOSEL == GD32_MCOSEL_PLLDIV2) || \
(GD32_MCOSEL == GD32_MCOSEL_PLL2) || \
(GD32_MCOSEL == GD32_MCOSEL_PLL3) || \
(GD32_MCOSEL == GD32_MCOSEL_PLL3DIV2)) && \
(GD32_PLLSRC == GD32_PLLSRC_HSE)) || \
(GD32_MCOSEL == GD32_MCOSEL_XT1)
#error "HSE not enabled, required by GD32_MCOSEL"
#if (GD32_CKOUT0SEL == GD32_CKOUT0SEL_HXTAL) || \
(((GD32_CKOUT0SEL == GD32_CKOUT0SEL_PLLDIV2) || \
(GD32_CKOUT0SEL == GD32_CKOUT0SEL_PLL2) || \
(GD32_CKOUT0SEL == GD32_CKOUT0SEL_PLL3) || \
(GD32_CKOUT0SEL == GD32_CKOUT0SEL_PLL3DIV2)) && \
(GD32_PLLSEL == GD32_PLLSEL_HXTAL)) || \
(GD32_CKOUT0SEL == GD32_CKOUT0SEL_XT1)
#error "HXTAL not enabled, required by GD32_CKOUT0SEL"
#endif
#if GD32_RTCSEL == GD32_RTCSEL_HSEDIV
#error "HSE not enabled, required by GD32_RTCSEL"
#if GD32_RTCSEL == GD32_RTCSEL_HXTALDIV
#error "HXTAL not enabled, required by GD32_RTCSEL"
#endif
#endif /* !GD32_HSE_ENABLED */
#endif /* !GD32_HXTAL_ENABLED */
/*
* LSI related checks.
* IRC40K related checks.
*/
#if GD32_LSI_ENABLED
#else /* !GD32_LSI_ENABLED */
#if GD32_IRC40K_ENABLED
#else /* !GD32_IRC40K_ENABLED */
#if GD32_RTCSEL == GD32_RTCSEL_LSI
#error "LSI not enabled, required by GD32_RTCSEL"
#if GD32_RTCSEL == GD32_RTCSEL_IRC40K
#error "IRC40K not enabled, required by GD32_RTCSEL"
#endif
#endif /* !GD32_LSI_ENABLED */
#endif /* !GD32_IRC40K_ENABLED */
/*
* LSE related checks.
* LXTAL related checks.
*/
#if GD32_LSE_ENABLED
#if GD32_LXTAL_ENABLED
#if (GD32_LSECLK == 0)
#error "LSE frequency not defined"
#if (GD32_LXTALCLK == 0)
#error "LXTAL frequency not defined"
#endif
#if (GD32_LSECLK < GD32_LSECLK_MIN) || (GD32_LSECLK > GD32_LSECLK_MAX)
#error "GD32_LSECLK outside acceptable range (GD32_LSECLK_MIN...GD32_LSECLK_MAX)"
#if (GD32_LXTALCLK < GD32_LXTALCLK_MIN) || (GD32_LXTALCLK > GD32_LXTALCLK_MAX)
#error "GD32_LXTALCLK outside acceptable range (GD32_LXTALCLK_MIN...GD32_LXTALCLK_MAX)"
#endif
#else /* !GD32_LSE_ENABLED */
#else /* !GD32_LXTAL_ENABLED */
#if GD32_RTCSEL == GD32_RTCSEL_LSE
#error "LSE not enabled, required by GD32_RTCSEL"
#if GD32_RTCSEL == GD32_RTCSEL_LXTAL
#error "LXTAL not enabled, required by GD32_RTCSEL"
#endif
#endif /* !GD32_LSE_ENABLED */
#endif /* !GD32_LXTAL_ENABLED */
/* PLL1 activation conditions.*/
#if GD32_USBFS_CLOCK_REQUIRED || \
(GD32_SW == GD32_SW_PLL) || \
(GD32_MCOSEL == GD32_MCOSEL_PLLDIV2) || \
(GD32_SCS == GD32_SCS_PLL) || \
(GD32_CKOUT0SEL == GD32_CKOUT0SEL_PLLDIV2) || \
defined(__DOXYGEN__)
/**
* @brief PLL1 activation flag.
@ -466,7 +466,7 @@
/* PLL2 activation conditions.*/
#if ((GD32_PREDIV1SRC == GD32_PREDIV1SRC_PLL2) && GD32_ACTIVATE_PLL1) || \
(GD32_MCOSEL == GD32_MCOSEL_PLL2) || defined(__DOXYGEN__)
(GD32_CKOUT0SEL == GD32_CKOUT0SEL_PLL2) || defined(__DOXYGEN__)
/**
* @brief PLL2 activation flag.
*/
@ -477,8 +477,8 @@
/* PLL3 activation conditions.*/
#if GD32_I2S_CLOCK_REQUIRED || \
(GD32_MCOSEL == GD32_MCOSEL_PLL3DIV2) || \
(GD32_MCOSEL == GD32_MCOSEL_PLL3) || \
(GD32_CKOUT0SEL == GD32_CKOUT0SEL_PLL3DIV2) || \
(GD32_CKOUT0SEL == GD32_CKOUT0SEL_PLL3) || \
defined(__DOXYGEN__)
/**
* @brief PLL3 activation flag.
@ -511,11 +511,11 @@
/**
* @brief PLLMUL field.
*/
/*#if ((GD32_PLLMUL_VALUE >= 4) && (GD32_PLLMUL_VALUE <= 9)) || \
/*#if ((GD32_PLLMF_VALUE >= 4) && (GD32_PLLMF_VALUE <= 9)) || \
defined(__DOXYGEN__)
#define GD32_PLLMUL ((GD32_PLLMUL_VALUE - 2) << 18)
#define GD32_PLLMF ((GD32_PLLMF_VALUE - 2) << 18)
#else
#error "invalid GD32_PLLMUL_VALUE value specified"
#error "invalid GD32_PLLMF_VALUE value specified"
#endif*/
/**
@ -549,7 +549,7 @@
/**
* @brief PLL2 input frequency.
*/
#define GD32_PLL2CLKIN (GD32_HSECLK / GD32_PREDIV2_VALUE)
#define GD32_PLL2CLKIN (GD32_HXTALCLK / GD32_PREDIV2_VALUE)
/* PLL2 input frequency range check.*/
#if (GD32_PLL2CLKIN < GD32_PLL23IN_MIN) || \
@ -576,7 +576,7 @@
/**
* @brief PLL3 input frequency.
*/
#define GD32_PLL3CLKIN (GD32_HSECLK / GD32_PREDIV2_VALUE)
#define GD32_PLL3CLKIN (GD32_HXTALCLK / GD32_PREDIV2_VALUE)
/* PLL3 input frequency range check.*/
#if (GD32_PLL3CLKIN < GD32_PLL23IN_MIN) || \
@ -603,8 +603,8 @@
/**
* @brief PREDIV1 input frequency.
*/
#if (GD32_PREDIV1SRC == GD32_PREDIV1SRC_HSE) || defined(__DOXYGEN__)
#define GD32_PREDIV1CLK GD32_HSECLK
#if (GD32_PREDIV1SRC == GD32_PREDIV1SRC_HXTAL) || defined(__DOXYGEN__)
#define GD32_PREDIV1CLK GD32_HXTALCLK
#elif GD32_PREDIV1SRC == GD32_PREDIV1SRC_PLL2
#define GD32_PREDIV1CLK GD32_PLL2CLKOUT
#else
@ -614,12 +614,12 @@
/**
* @brief PLL input clock frequency.
*/
#if (GD32_PLLSRC == GD32_PLLSRC_PREDIV1) || defined(__DOXYGEN__)
#if (GD32_PLLSEL == GD32_PLLSEL_PREDIV1) || defined(__DOXYGEN__)
#define GD32_PLLCLKIN (GD32_PREDIV1CLK / GD32_PREDIV1_VALUE)
#elif GD32_PLLSRC == GD32_PLLSRC_HSI
#define GD32_PLLCLKIN (GD32_HSICLK / 2)
#elif GD32_PLLSEL == GD32_PLLSEL_IRC8M
#define GD32_PLLCLKIN (GD32_IRC8MCLK / 2)
#else
#error "invalid GD32_PLLSRC value specified"
#error "invalid GD32_PLLSEL value specified"
#endif
/* PLL input frequency range check.*/
@ -630,7 +630,7 @@
/**
* @brief PLL output clock frequency.
*/
#define GD32_PLLCLKOUT (GD32_PLLCLKIN * GD32_PLLMUL_VALUE)
#define GD32_PLLCLKOUT (GD32_PLLCLKIN * GD32_PLLMF_VALUE)
/**
* @brief PLL VCO clock frequency.
@ -645,14 +645,14 @@
/**
* @brief System clock source.
*/
#if (GD32_SW == GD32_SW_PLL) || defined(__DOXYGEN__)
#if (GD32_SCS == GD32_SCS_PLL) || defined(__DOXYGEN__)
#define GD32_SYSCLK GD32_PLLCLKOUT
#elif (GD32_SW == GD32_SW_HSI)
#define GD32_SYSCLK GD32_HSICLK
#elif (GD32_SW == GD32_SW_HSE)
#define GD32_SYSCLK GD32_HSECLK
#elif (GD32_SCS == GD32_SCS_IRC8M)
#define GD32_SYSCLK GD32_IRC8MCLK
#elif (GD32_SCS == GD32_SCS_HXTAL)
#define GD32_SYSCLK GD32_HXTALCLK
#else
#error "invalid GD32_SW value specified"
#error "invalid GD32_SCS value specified"
#endif
/* Check on the system clock.*/
@ -663,26 +663,26 @@
/**
* @brief AHB frequency.
*/
#if (GD32_HPRE == GD32_HPRE_DIV1) || defined(__DOXYGEN__)
#if (GD32_AHBPSC == GD32_AHBPSC_DIV1) || defined(__DOXYGEN__)
#define GD32_HCLK (GD32_SYSCLK / 1)
#elif GD32_HPRE == GD32_HPRE_DIV2
#elif GD32_AHBPSC == GD32_AHBPSC_DIV2
#define GD32_HCLK (GD32_SYSCLK / 2)
#elif GD32_HPRE == GD32_HPRE_DIV4
#elif GD32_AHBPSC == GD32_AHBPSC_DIV4
#define GD32_HCLK (GD32_SYSCLK / 4)
#elif GD32_HPRE == GD32_HPRE_DIV8
#elif GD32_AHBPSC == GD32_AHBPSC_DIV8
#define GD32_HCLK (GD32_SYSCLK / 8)
#elif GD32_HPRE == GD32_HPRE_DIV16
#elif GD32_AHBPSC == GD32_AHBPSC_DIV16
#define GD32_HCLK (GD32_SYSCLK / 16)
#elif GD32_HPRE == GD32_HPRE_DIV64
#elif GD32_AHBPSC == GD32_AHBPSC_DIV64
#define GD32_HCLK (GD32_SYSCLK / 64)
#elif GD32_HPRE == GD32_HPRE_DIV128
#elif GD32_AHBPSC == GD32_AHBPSC_DIV128
#define GD32_HCLK (GD32_SYSCLK / 128)
#elif GD32_HPRE == GD32_HPRE_DIV256
#elif GD32_AHBPSC == GD32_AHBPSC_DIV256
#define GD32_HCLK (GD32_SYSCLK / 256)
#elif GD32_HPRE == GD32_HPRE_DIV512
#elif GD32_AHBPSC == GD32_AHBPSC_DIV512
#define GD32_HCLK (GD32_SYSCLK / 512)
#else
#error "invalid GD32_HPRE value specified"
#error "invalid GD32_AHBPSC value specified"
#endif
/* AHB frequency check.*/
@ -693,18 +693,18 @@
/**
* @brief APB1 frequency.
*/
#if (GD32_PPRE1 == GD32_PPRE1_DIV1) || defined(__DOXYGEN__)
#if (GD32_APB1PSC == GD32_APB1PSC_DIV1) || defined(__DOXYGEN__)
#define GD32_PCLK1 (GD32_HCLK / 1)
#elif GD32_PPRE1 == GD32_PPRE1_DIV2
#elif GD32_APB1PSC == GD32_APB1PSC_DIV2
#define GD32_PCLK1 (GD32_HCLK / 2)
#elif GD32_PPRE1 == GD32_PPRE1_DIV4
#elif GD32_APB1PSC == GD32_APB1PSC_DIV4
#define GD32_PCLK1 (GD32_HCLK / 4)
#elif GD32_PPRE1 == GD32_PPRE1_DIV8
#elif GD32_APB1PSC == GD32_APB1PSC_DIV8
#define GD32_PCLK1 (GD32_HCLK / 8)
#elif GD32_PPRE1 == GD32_PPRE1_DIV16
#elif GD32_APB1PSC == GD32_APB1PSC_DIV16
#define GD32_PCLK1 (GD32_HCLK / 16)
#else
#error "invalid GD32_PPRE1 value specified"
#error "invalid GD32_APB1PSC value specified"
#endif
/* APB1 frequency check.*/
@ -715,18 +715,18 @@
/**
* @brief APB2 frequency.
*/
#if (GD32_PPRE2 == GD32_PPRE2_DIV1) || defined(__DOXYGEN__)
#if (GD32_APB2PSC == GD32_APB2PSC_DIV1) || defined(__DOXYGEN__)
#define GD32_PCLK2 (GD32_HCLK / 1)
#elif GD32_PPRE2 == GD32_PPRE2_DIV2
#elif GD32_APB2PSC == GD32_APB2PSC_DIV2
#define GD32_PCLK2 (GD32_HCLK / 2)
#elif GD32_PPRE2 == GD32_PPRE2_DIV4
#elif GD32_APB2PSC == GD32_APB2PSC_DIV4
#define GD32_PCLK2 (GD32_HCLK / 4)
#elif GD32_PPRE2 == GD32_PPRE2_DIV8
#elif GD32_APB2PSC == GD32_APB2PSC_DIV8
#define GD32_PCLK2 (GD32_HCLK / 8)
#elif GD32_PPRE2 == GD32_PPRE2_DIV16
#elif GD32_APB2PSC == GD32_APB2PSC_DIV16
#define GD32_PCLK2 (GD32_HCLK / 16)
#else
#error "invalid GD32_PPRE2 value specified"
#error "invalid GD32_APB2PSC value specified"
#endif
/* APB2 frequency check.*/
@ -737,12 +737,12 @@
/**
* @brief RTC clock.
*/
#if (GD32_RTCSEL == GD32_RTCSEL_LSE) || defined(__DOXYGEN__)
#define GD32_RTCCLK GD32_LSECLK
#elif GD32_RTCSEL == GD32_RTCSEL_LSI
#define GD32_RTCCLK GD32_LSICLK
#elif GD32_RTCSEL == GD32_RTCSEL_HSEDIV
#define GD32_RTCCLK (GD32_HSECLK / 128)
#if (GD32_RTCSEL == GD32_RTCSEL_LXTAL) || defined(__DOXYGEN__)
#define GD32_RTCCLK GD32_LXTALCLK
#elif GD32_RTCSEL == GD32_RTCSEL_IRC40K
#define GD32_RTCCLK GD32_IRC40KCLK
#elif GD32_RTCSEL == GD32_RTCSEL_HXTALDIV
#define GD32_RTCCLK (GD32_HXTALCLK / 128)
#elif GD32_RTCSEL == GD32_RTCSEL_NOCLOCK
#define GD32_RTCCLK 0
#else
@ -752,16 +752,16 @@
/**
* @brief ADC frequency.
*/
#if (GD32_ADCPRE == GD32_ADCPRE_DIV2) || defined(__DOXYGEN__)
#if (GD32_ADCPSC == GD32_ADCPSC_DIV2) || defined(__DOXYGEN__)
#define GD32_ADCCLK (GD32_PCLK2 / 2)
#elif GD32_ADCPRE == GD32_ADCPRE_DIV4
#elif GD32_ADCPSC == GD32_ADCPSC_DIV4
#define GD32_ADCCLK (GD32_PCLK2 / 4)
#elif GD32_ADCPRE == GD32_ADCPRE_DIV6
#elif GD32_ADCPSC == GD32_ADCPSC_DIV6
#define GD32_ADCCLK (GD32_PCLK2 / 6)
#elif GD32_ADCPRE == GD32_ADCPRE_DIV8
#elif GD32_ADCPSC == GD32_ADCPSC_DIV8
#define GD32_ADCCLK (GD32_PCLK2 / 8)
#else
#error "invalid GD32_ADCPRE value specified"
#error "invalid GD32_ADCPSC value specified"
#endif
/* ADC frequency check.*/
@ -783,7 +783,7 @@
/**
* @brief Timers 2, 3, 4, 5, 6, 7 clock.
*/
#if (GD32_PPRE1 == GD32_PPRE1_DIV1) || defined(__DOXYGEN__)
#if (GD32_APB1PSC == GD32_APB1PSC_DIV1) || defined(__DOXYGEN__)
#define GD32_TIMCLK1 (GD32_PCLK1 * 1)
#else
#define GD32_TIMCLK1 (GD32_PCLK1 * 2)
@ -792,7 +792,7 @@
/**
* @brief Timers 1, 8 clock.
*/
#if (GD32_PPRE2 == GD32_PPRE2_DIV1) || defined(__DOXYGEN__)
#if (GD32_APB2PSC == GD32_APB2PSC_DIV1) || defined(__DOXYGEN__)
#define GD32_TIMCLK2 (GD32_PCLK2 * 1)
#else
#define GD32_TIMCLK2 (GD32_PCLK2 * 2)

474
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -1163,269 +1163,257 @@ typedef struct
/* */
/******************************************************************************/
/******************** Bit definition for RCU_CR register ********************/
#define RCU_CR_HSION_Pos (0U)
#define RCU_CR_HSION_Msk (0x1U << RCU_CR_HSION_Pos) /*!< 0x00000001 */
#define RCU_CR_HSION RCU_CR_HSION_Msk /*!< Internal High Speed clock enable */
#define RCU_CR_HSIRDY_Pos (1U)
#define RCU_CR_HSIRDY_Msk (0x1U << RCU_CR_HSIRDY_Pos) /*!< 0x00000002 */
#define RCU_CR_HSIRDY RCU_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
#define RCU_CR_HSITRIM_Pos (3U)
#define RCU_CR_HSITRIM_Msk (0x1FU << RCU_CR_HSITRIM_Pos) /*!< 0x000000F8 */
#define RCU_CR_HSITRIM RCU_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
#define RCU_CR_HSICAL_Pos (8U)
#define RCU_CR_HSICAL_Msk (0xFFU << RCU_CR_HSICAL_Pos) /*!< 0x0000FF00 */
#define RCU_CR_HSICAL RCU_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
#define RCU_CR_HSEON_Pos (16U)
#define RCU_CR_HSEON_Msk (0x1U << RCU_CR_HSEON_Pos) /*!< 0x00010000 */
#define RCU_CR_HSEON RCU_CR_HSEON_Msk /*!< External High Speed clock enable */
#define RCU_CR_HSERDY_Pos (17U)
#define RCU_CR_HSERDY_Msk (0x1U << RCU_CR_HSERDY_Pos) /*!< 0x00020000 */
#define RCU_CR_HSERDY RCU_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
#define RCU_CR_HSEBYP_Pos (18U)
#define RCU_CR_HSEBYP_Msk (0x1U << RCU_CR_HSEBYP_Pos) /*!< 0x00040000 */
#define RCU_CR_HSEBYP RCU_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
#define RCU_CR_CSSON_Pos (19U)
#define RCU_CR_CSSON_Msk (0x1U << RCU_CR_CSSON_Pos) /*!< 0x00080000 */
#define RCU_CR_CSSON RCU_CR_CSSON_Msk /*!< Clock Security System enable */
#define RCU_CR_PLLON_Pos (24U)
#define RCU_CR_PLLON_Msk (0x1U << RCU_CR_PLLON_Pos) /*!< 0x01000000 */
#define RCU_CR_PLLON RCU_CR_PLLON_Msk /*!< PLL enable */
#define RCU_CR_PLLRDY_Pos (25U)
#define RCU_CR_PLLRDY_Msk (0x1U << RCU_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCU_CR_PLLRDY RCU_CR_PLLRDY_Msk /*!< PLL clock ready flag */
/******************** Bit definition for RCU_CTL register ********************/
#define RCU_CTL_IRC8MEN_Pos (0U)
#define RCU_CTL_IRC8MEN_Msk (0x1U << RCU_CTL_IRC8MEN_Pos) /*!< 0x00000001 */
#define RCU_CTL_IRC8MEN RCU_CTL_IRC8MEN_Msk /*!< Internal High Speed clock enable */
#define RCU_CTL_IRC8MSTB_Pos (1U)
#define RCU_CTL_IRC8MSTB_Msk (0x1U << RCU_CTL_IRC8MSTB_Pos) /*!< 0x00000002 */
#define RCU_CTL_IRC8MSTB RCU_CTL_IRC8MSTB_Msk /*!< Internal High Speed clock ready flag */
#define RCU_CTL_IRC8MADJ_Pos (3U)
#define RCU_CTL_IRC8MADJ_Msk (0x1FU << RCU_CTL_IRC8MADJ_Pos) /*!< 0x000000F8 */
#define RCU_CTL_IRC8MADJ RCU_CTL_IRC8MADJ_Msk /*!< Internal High Speed clock trimming */
#define RCU_CTL_IRC8CALIB_Pos (8U)
#define RCU_CTL_IRC8CALIB_Msk (0xFFU << RCU_CTL_IRC8CALIB_Pos) /*!< 0x0000FF00 */
#define RCU_CTL_IRC8CALIB RCU_CTL_IRC8CALIB_Msk /*!< Internal High Speed clock Calibration */
#define RCU_CTL_HXTALEN_Pos (16U)
#define RCU_CTL_HXTALEN_Msk (0x1U << RCU_CTL_HXTALEN_Pos) /*!< 0x00010000 */
#define RCU_CTL_HXTALEN RCU_CTL_HXTALEN_Msk /*!< External High Speed clock enable */
#define RCU_CTL_HXTALSTB_Pos (17U)
#define RCU_CTL_HXTALSTB_Msk (0x1U << RCU_CTL_HXTALSTB_Pos) /*!< 0x00020000 */
#define RCU_CTL_HXTALSTB RCU_CTL_HXTALSTB_Msk /*!< External High Speed clock ready flag */
#define RCU_CTL_HXTALBPS_Pos (18U)
#define RCU_CTL_HXTALBPS_Msk (0x1U << RCU_CTL_HXTALBPS_Pos) /*!< 0x00040000 */
#define RCU_CTL_HXTALBPS RCU_CTL_HXTALBPS_Msk /*!< External High Speed clock Bypass */
#define RCU_CTL_CKMEN_Pos (19U)
#define RCU_CTL_CKMEN_Msk (0x1U << RCU_CTL_CKMEN_Pos) /*!< 0x00080000 */
#define RCU_CTL_CKMEN RCU_CTL_CKMEN_Msk /*!< Clock Security System enable */
#define RCU_CTL_PLLEN_Pos (24U)
#define RCU_CTL_PLLEN_Msk (0x1U << RCU_CTL_PLLEN_Pos) /*!< 0x01000000 */
#define RCU_CTL_PLLEN RCU_CTL_PLLEN_Msk /*!< PLL enable */
#define RCU_CTL_PLLSTB_Pos (25U)
#define RCU_CTL_PLLSTB_Msk (0x1U << RCU_CTL_PLLSTB_Pos) /*!< 0x02000000 */
#define RCU_CTL_PLLSTB RCU_CTL_PLLSTB_Msk /*!< PLL clock ready flag */
#define RCU_CTL_PLL1EN_Pos (26U)
#define RCU_CTL_PLL1EN_Msk (0x1U << RCU_CTL_PLL1EN_Pos) /*!< 0x04000000 */
#define RCU_CTL_PLL1EN RCU_CTL_PLL1EN_Msk /*!< PLL2 enable */
#define RCU_CTL_PLL1STB_Pos (27U)
#define RCU_CTL_PLL1STB_Msk (0x1U << RCU_CTL_PLL1STB_Pos) /*!< 0x08000000 */
#define RCU_CTL_PLL1STB RCU_CTL_PLL1STB_Msk /*!< PLL2 clock ready flag */
#define RCU_CTL_PLL2EN_Pos (28U)
#define RCU_CTL_PLL2EN_Msk (0x1U << RCU_CTL_PLL2EN_Pos) /*!< 0x10000000 */
#define RCU_CTL_PLL2EN RCU_CTL_PLL2EN_Msk /*!< PLL3 enable */
#define RCU_CTL_PLL2STB_Pos (29U)
#define RCU_CTL_PLL2STB_Msk (0x1U << RCU_CTL_PLL2STB_Pos) /*!< 0x20000000 */
#define RCU_CTL_PLL2STB RCU_CTL_PLL2STB_Msk /*!< PLL3 clock ready flag */
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
*/
#define RCU_PLL2_SUPPORT /*!< Support PLL2 */
#define RCU_CR_PLL2ON_Pos (26U)
#define RCU_CR_PLL2ON_Msk (0x1U << RCU_CR_PLL2ON_Pos) /*!< 0x04000000 */
#define RCU_CR_PLL2ON RCU_CR_PLL2ON_Msk /*!< PLL2 enable */
#define RCU_CR_PLL2RDY_Pos (27U)
#define RCU_CR_PLL2RDY_Msk (0x1U << RCU_CR_PLL2RDY_Pos) /*!< 0x08000000 */
#define RCU_CR_PLL2RDY RCU_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
*/
#define RCU_PLLI2S_SUPPORT /*!< Support PLL3 (PLLI2S)*/
#define RCU_CR_PLL3ON_Pos (28U)
#define RCU_CR_PLL3ON_Msk (0x1U << RCU_CR_PLL3ON_Pos) /*!< 0x10000000 */
#define RCU_CR_PLL3ON RCU_CR_PLL3ON_Msk /*!< PLL3 enable */
#define RCU_CR_PLL3RDY_Pos (29U)
#define RCU_CR_PLL3RDY_Msk (0x1U << RCU_CR_PLL3RDY_Pos) /*!< 0x20000000 */
#define RCU_CR_PLL3RDY RCU_CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */
/******************* Bit definition for RCU_CFGR register *******************/
/******************* Bit definition for RCU_CFG0 register *******************/
/*!< SW configuration */
#define RCU_CFGR_SW_Pos (0U)
#define RCU_CFGR_SW_Msk (0x3U << RCU_CFGR_SW_Pos) /*!< 0x00000003 */
#define RCU_CFGR_SW RCU_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
#define RCU_CFGR_SW_0 (0x1U << RCU_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCU_CFGR_SW_1 (0x2U << RCU_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCU_CFG0_SCS_Pos (0U)
#define RCU_CFG0_SCS_Msk (0x3U << RCU_CFG0_SCS_Pos) /*!< 0x00000003 */
#define RCU_CFG0_SCS RCU_CFG0_SCS_Msk /*!< SW[1:0] bits (System clock Switch) */
#define RCU_CFG0_SCS_0 (0x1U << RCU_CFG0_SCS_Pos) /*!< 0x00000001 */
#define RCU_CFG0_SCS_1 (0x2U << RCU_CFG0_SCS_Pos) /*!< 0x00000002 */
#define RCU_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
#define RCU_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
#define RCU_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
#define RCU_CFG0_SCS_IRC8M 0x00000000U /*!< IRC8M selected as system clock */
#define RCU_CFG0_SCS_HXTAL 0x00000001U /*!< HXTAL selected as system clock */
#define RCU_CFG0_SCS_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCU_CFGR_SWS_Pos (2U)
#define RCU_CFGR_SWS_Msk (0x3U << RCU_CFGR_SWS_Pos) /*!< 0x0000000C */
#define RCU_CFGR_SWS RCU_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCU_CFGR_SWS_0 (0x1U << RCU_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCU_CFGR_SWS_1 (0x2U << RCU_CFGR_SWS_Pos) /*!< 0x00000008 */
#define RCU_CFG0_SCSS_Pos (2U)
#define RCU_CFG0_SCSS_Msk (0x3U << RCU_CFG0_SCSS_Pos) /*!< 0x0000000C */
#define RCU_CFG0_SCSS RCU_CFG0_SCSS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCU_CFG0_SCSS_0 (0x1U << RCU_CFG0_SCSS_Pos) /*!< 0x00000004 */
#define RCU_CFG0_SCSS_1 (0x2U << RCU_CFG0_SCSS_Pos) /*!< 0x00000008 */
#define RCU_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
#define RCU_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
#define RCU_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
#define RCU_CFG0_SCSS_IRC8M 0x00000000U /*!< IRC8M oscillator used as system clock */
#define RCU_CFG0_SCSS_HXTAL 0x00000004U /*!< HXTAL oscillator used as system clock */
#define RCU_CFG0_SCSS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCU_CFGR_HPRE_Pos (4U)
#define RCU_CFGR_HPRE_Msk (0xFU << RCU_CFGR_HPRE_Pos) /*!< 0x000000F0 */
#define RCU_CFGR_HPRE RCU_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCU_CFGR_HPRE_0 (0x1U << RCU_CFGR_HPRE_Pos) /*!< 0x00000010 */
#define RCU_CFGR_HPRE_1 (0x2U << RCU_CFGR_HPRE_Pos) /*!< 0x00000020 */
#define RCU_CFGR_HPRE_2 (0x4U << RCU_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCU_CFGR_HPRE_3 (0x8U << RCU_CFGR_HPRE_Pos) /*!< 0x00000080 */
#define RCU_CFG0_AHBPSC_Pos (4U)
#define RCU_CFG0_AHBPSC_Msk (0xFU << RCU_CFG0_AHBPSC_Pos) /*!< 0x000000F0 */
#define RCU_CFG0_AHBPSC RCU_CFG0_AHBPSC_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCU_CFG0_AHBPSC_0 (0x1U << RCU_CFG0_AHBPSC_Pos) /*!< 0x00000010 */
#define RCU_CFG0_AHBPSC_1 (0x2U << RCU_CFG0_AHBPSC_Pos) /*!< 0x00000020 */
#define RCU_CFG0_AHBPSC_2 (0x4U << RCU_CFG0_AHBPSC_Pos) /*!< 0x00000040 */
#define RCU_CFG0_AHBPSC_3 (0x8U << RCU_CFG0_AHBPSC_Pos) /*!< 0x00000080 */
#define RCU_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
#define RCU_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
#define RCU_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
#define RCU_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
#define RCU_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
#define RCU_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
#define RCU_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
#define RCU_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
#define RCU_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
#define RCU_CFG0_AHBPSC_DIV1 0x00000000U /*!< SYSCLK not divided */
#define RCU_CFG0_AHBPSC_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
#define RCU_CFG0_AHBPSC_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
#define RCU_CFG0_AHBPSC_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
#define RCU_CFG0_AHBPSC_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
#define RCU_CFG0_AHBPSC_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
#define RCU_CFG0_AHBPSC_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
#define RCU_CFG0_AHBPSC_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
#define RCU_CFG0_AHBPSC_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCU_CFGR_PPRE1_Pos (8U)
#define RCU_CFGR_PPRE1_Msk (0x7U << RCU_CFGR_PPRE1_Pos) /*!< 0x00000700 */
#define RCU_CFGR_PPRE1 RCU_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
#define RCU_CFGR_PPRE1_0 (0x1U << RCU_CFGR_PPRE1_Pos) /*!< 0x00000100 */
#define RCU_CFGR_PPRE1_1 (0x2U << RCU_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCU_CFGR_PPRE1_2 (0x4U << RCU_CFGR_PPRE1_Pos) /*!< 0x00000400 */
#define RCU_CFG0_APB1PSC_Pos (8U)
#define RCU_CFG0_APB1PSC_Msk (0x7U << RCU_CFG0_APB1PSC_Pos) /*!< 0x00000700 */
#define RCU_CFG0_APB1PSC RCU_CFG0_APB1PSC_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
#define RCU_CFG0_APB1PSC_0 (0x1U << RCU_CFG0_APB1PSC_Pos) /*!< 0x00000100 */
#define RCU_CFG0_APB1PSC_1 (0x2U << RCU_CFG0_APB1PSC_Pos) /*!< 0x00000200 */
#define RCU_CFG0_APB1PSC_2 (0x4U << RCU_CFG0_APB1PSC_Pos) /*!< 0x00000400 */
#define RCU_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
#define RCU_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
#define RCU_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
#define RCU_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
#define RCU_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
#define RCU_CFG0_APB1PSC_DIV1 0x00000000U /*!< HCLK not divided */
#define RCU_CFG0_APB1PSC_DIV2 0x00000400U /*!< HCLK divided by 2 */
#define RCU_CFG0_APB1PSC_DIV4 0x00000500U /*!< HCLK divided by 4 */
#define RCU_CFG0_APB1PSC_DIV8 0x00000600U /*!< HCLK divided by 8 */
#define RCU_CFG0_APB1PSC_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCU_CFGR_PPRE2_Pos (11U)
#define RCU_CFGR_PPRE2_Msk (0x7U << RCU_CFGR_PPRE2_Pos) /*!< 0x00003800 */
#define RCU_CFGR_PPRE2 RCU_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCU_CFGR_PPRE2_0 (0x1U << RCU_CFGR_PPRE2_Pos) /*!< 0x00000800 */
#define RCU_CFGR_PPRE2_1 (0x2U << RCU_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCU_CFGR_PPRE2_2 (0x4U << RCU_CFGR_PPRE2_Pos) /*!< 0x00002000 */
#define RCU_CFG0_APB2PSC_Pos (11U)
#define RCU_CFG0_APB2PSC_Msk (0x7U << RCU_CFG0_APB2PSC_Pos) /*!< 0x00003800 */
#define RCU_CFG0_APB2PSC RCU_CFG0_APB2PSC_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCU_CFG0_APB2PSC_0 (0x1U << RCU_CFG0_APB2PSC_Pos) /*!< 0x00000800 */
#define RCU_CFG0_APB2PSC_1 (0x2U << RCU_CFG0_APB2PSC_Pos) /*!< 0x00001000 */
#define RCU_CFG0_APB2PSC_2 (0x4U << RCU_CFG0_APB2PSC_Pos) /*!< 0x00002000 */
#define RCU_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
#define RCU_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
#define RCU_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
#define RCU_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
#define RCU_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
#define RCU_CFG0_APB2PSC_DIV1 0x00000000U /*!< HCLK not divided */
#define RCU_CFG0_APB2PSC_DIV2 0x00002000U /*!< HCLK divided by 2 */
#define RCU_CFG0_APB2PSC_DIV4 0x00002800U /*!< HCLK divided by 4 */
#define RCU_CFG0_APB2PSC_DIV8 0x00003000U /*!< HCLK divided by 8 */
#define RCU_CFG0_APB2PSC_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCU_CFGR_ADCPRE_Pos (14U)
#define RCU_CFGR_ADCPRE_Msk (0x3U << RCU_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
#define RCU_CFGR_ADCPRE RCU_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
#define RCU_CFGR_ADCPRE_0 (0x1U << RCU_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCU_CFGR_ADCPRE_1 (0x2U << RCU_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
#define RCU_CFG0_ADCPSC_Pos (14U)
#define RCU_CFG0_ADCPSC_Msk (0x3U << RCU_CFG0_ADCPSC_Pos) /*!< 0x0000C000 */
#define RCU_CFG0_ADCPSC RCU_CFG0_ADCPSC_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
#define RCU_CFG0_ADCPSC_0 (0x1U << RCU_CFG0_ADCPSC_Pos) /*!< 0x00004000 */
#define RCU_CFG0_ADCPSC_1 (0x2U << RCU_CFG0_ADCPSC_Pos) /*!< 0x00008000 */
#define RCU_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
#define RCU_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
#define RCU_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
#define RCU_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCU_CFG0_ADCPSC_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
#define RCU_CFG0_ADCPSC_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
#define RCU_CFG0_ADCPSC_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
#define RCU_CFG0_ADCPSC_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCU_CFGR_PLLSRC_Pos (16U)
#define RCU_CFGR_PLLSRC_Msk (0x1U << RCU_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
#define RCU_CFGR_PLLSRC RCU_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
#define RCU_CFG0_PLLSEL_Pos (16U)
#define RCU_CFG0_PLLSEL_Msk (0x1U << RCU_CFG0_PLLSEL_Pos) /*!< 0x00010000 */
#define RCU_CFG0_PLLSEL RCU_CFG0_PLLSEL_Msk /*!< PLL entry clock source */
#define RCU_CFGR_PLLXTPRE_Pos (17U)
#define RCU_CFGR_PLLXTPRE_Msk (0x1U << RCU_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
#define RCU_CFGR_PLLXTPRE RCU_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
#define RCU_CFG0_PREDV0_LSB_Pos (17U)
#define RCU_CFG0_PREDV0_LSB_Msk (0x1U << RCU_CFG0_PREDV0_LSB_Pos) /*!< 0x00020000 */
#define RCU_CFG0_PREDV0_LSB RCU_CFG0_PREDV0_LSB_Msk /*!< HXTAL divider for PLL entry */
/*!< PLLMUL configuration */
#define RCU_CFGR_PLLMULL_Pos (18U)
#define RCU_CFGR_PLLMULL_Msk (0xFU << RCU_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
#define RCU_CFGR_PLLMULL RCU_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
#define RCU_CFGR_PLLMULL_0 (0x1U << RCU_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
#define RCU_CFGR_PLLMULL_1 (0x2U << RCU_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
#define RCU_CFGR_PLLMULL_2 (0x4U << RCU_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCU_CFGR_PLLMULL_3 (0x8U << RCU_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
#define RCU_CFG0_PLLMF_Pos (18U)
#define RCU_CFG0_PLLMF_Msk (0xFU << RCU_CFG0_PLLMF_Pos) /*!< 0x003C0000 */
#define RCU_CFG0_PLLMF RCU_CFG0_PLLMF_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
#define RCU_CFG0_PLLMF_0 (0x1U << RCU_CFG0_PLLMF_Pos) /*!< 0x00040000 */
#define RCU_CFG0_PLLMF_1 (0x2U << RCU_CFG0_PLLMF_Pos) /*!< 0x00080000 */
#define RCU_CFG0_PLLMF_2 (0x4U << RCU_CFG0_PLLMF_Pos) /*!< 0x00100000 */
#define RCU_CFG0_PLLMF_3 (0x8U << RCU_CFG0_PLLMF_Pos) /*!< 0x00200000 */
#define RCU_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */
#define RCU_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */
#define RCU_CFG0_PREDV0_LSB_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */
#define RCU_CFG0_PREDV0_LSB_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */
#define RCU_CFGR_PLLMULL4_Pos (19U)
#define RCU_CFGR_PLLMULL4_Msk (0x1U << RCU_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
#define RCU_CFGR_PLLMULL4 RCU_CFGR_PLLMULL4_Msk /*!< PLL input clock * 4 */
#define RCU_CFGR_PLLMULL5_Pos (18U)
#define RCU_CFGR_PLLMULL5_Msk (0x3U << RCU_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
#define RCU_CFGR_PLLMULL5 RCU_CFGR_PLLMULL5_Msk /*!< PLL input clock * 5 */
#define RCU_CFGR_PLLMULL6_Pos (20U)
#define RCU_CFGR_PLLMULL6_Msk (0x1U << RCU_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
#define RCU_CFGR_PLLMULL6 RCU_CFGR_PLLMULL6_Msk /*!< PLL input clock * 6 */
#define RCU_CFGR_PLLMULL7_Pos (18U)
#define RCU_CFGR_PLLMULL7_Msk (0x5U << RCU_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
#define RCU_CFGR_PLLMULL7 RCU_CFGR_PLLMULL7_Msk /*!< PLL input clock * 7 */
#define RCU_CFGR_PLLMULL8_Pos (19U)
#define RCU_CFGR_PLLMULL8_Msk (0x3U << RCU_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
#define RCU_CFGR_PLLMULL8 RCU_CFGR_PLLMULL8_Msk /*!< PLL input clock * 8 */
#define RCU_CFGR_PLLMULL9_Pos (18U)
#define RCU_CFGR_PLLMULL9_Msk (0x7U << RCU_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
#define RCU_CFGR_PLLMULL9 RCU_CFGR_PLLMULL9_Msk /*!< PLL input clock * 9 */
#define RCU_CFGR_PLLMULL6_5 0x00340000U /*!< PLL input clock * 6.5 */
#define RCU_CFG0_PLLMF4_Pos (19U)
#define RCU_CFG0_PLLMF4_Msk (0x1U << RCU_CFG0_PLLMF4_Pos) /*!< 0x00080000 */
#define RCU_CFG0_PLLMF4 RCU_CFG0_PLLMF4_Msk /*!< PLL input clock * 4 */
#define RCU_CFG0_PLLMF5_Pos (18U)
#define RCU_CFG0_PLLMF5_Msk (0x3U << RCU_CFG0_PLLMF5_Pos) /*!< 0x000C0000 */
#define RCU_CFG0_PLLMF5 RCU_CFG0_PLLMF5_Msk /*!< PLL input clock * 5 */
#define RCU_CFG0_PLLMF6_Pos (20U)
#define RCU_CFG0_PLLMF6_Msk (0x1U << RCU_CFG0_PLLMF6_Pos) /*!< 0x00100000 */
#define RCU_CFG0_PLLMF6 RCU_CFG0_PLLMF6_Msk /*!< PLL input clock * 6 */
#define RCU_CFG0_PLLMF7_Pos (18U)
#define RCU_CFG0_PLLMF7_Msk (0x5U << RCU_CFG0_PLLMF7_Pos) /*!< 0x00140000 */
#define RCU_CFG0_PLLMF7 RCU_CFG0_PLLMF7_Msk /*!< PLL input clock * 7 */
#define RCU_CFG0_PLLMF8_Pos (19U)
#define RCU_CFG0_PLLMF8_Msk (0x3U << RCU_CFG0_PLLMF8_Pos) /*!< 0x00180000 */
#define RCU_CFG0_PLLMF8 RCU_CFG0_PLLMF8_Msk /*!< PLL input clock * 8 */
#define RCU_CFG0_PLLMF9_Pos (18U)
#define RCU_CFG0_PLLMF9_Msk (0x7U << RCU_CFG0_PLLMF9_Pos) /*!< 0x001C0000 */
#define RCU_CFG0_PLLMF9 RCU_CFG0_PLLMF9_Msk /*!< PLL input clock * 9 */
#define RCU_CFG0_PLLMF6_5 0x00340000U /*!< PLL input clock * 6.5 */
#define RCU_CFGR_OTGFSPRE_Pos (22U)
#define RCU_CFGR_OTGFSPRE_Msk (0x1U << RCU_CFGR_OTGFSPRE_Pos) /*!< 0x00400000 */
#define RCU_CFGR_OTGFSPRE RCU_CFGR_OTGFSPRE_Msk /*!< USB OTG FS prescaler */
#define RCU_CFG0_USBFSPSC_Pos (22U)
#define RCU_CFG0_USBFSPSC_Msk (0x1U << RCU_CFG0_USBFSPSC_Pos) /*!< 0x00400000 */
#define RCU_CFG0_USBFSPSC RCU_CFG0_USBFSPSC_Msk /*!< USB OTG FS prescaler */
/*!< MCO configuration */
#define RCU_CFGR_MCO_Pos (24U)
#define RCU_CFGR_MCO_Msk (0xFU << RCU_CFGR_MCO_Pos) /*!< 0x0F000000 */
#define RCU_CFGR_MCO RCU_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
#define RCU_CFGR_MCO_0 (0x1U << RCU_CFGR_MCO_Pos) /*!< 0x01000000 */
#define RCU_CFGR_MCO_1 (0x2U << RCU_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCU_CFGR_MCO_2 (0x4U << RCU_CFGR_MCO_Pos) /*!< 0x04000000 */
#define RCU_CFGR_MCO_3 (0x8U << RCU_CFGR_MCO_Pos) /*!< 0x08000000 */
#define RCU_CFG0_CKOUT0SEL_Pos (24U)
#define RCU_CFG0_CKOUT0SEL_Msk (0xFU << RCU_CFG0_CKOUT0SEL_Pos) /*!< 0x0F000000 */
#define RCU_CFG0_CKOUT0SEL RCU_CFG0_CKOUT0SEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
#define RCU_CFG0_CKOUT0SEL_0 (0x1U << RCU_CFG0_CKOUT0SEL_Pos) /*!< 0x01000000 */
#define RCU_CFG0_CKOUT0SEL_1 (0x2U << RCU_CFG0_CKOUT0SEL_Pos) /*!< 0x02000000 */
#define RCU_CFG0_CKOUT0SEL_2 (0x4U << RCU_CFG0_CKOUT0SEL_Pos) /*!< 0x04000000 */
#define RCU_CFG0_CKOUT0SEL_3 (0x8U << RCU_CFG0_CKOUT0SEL_Pos) /*!< 0x08000000 */
#define RCU_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
#define RCU_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
#define RCU_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
#define RCU_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
#define RCU_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
#define RCU_CFGR_MCO_PLL2CLK 0x08000000U /*!< PLL2 clock selected as MCO source*/
#define RCU_CFGR_MCO_PLL3CLK_DIV2 0x09000000U /*!< PLL3 clock divided by 2 selected as MCO source*/
#define RCU_CFGR_MCO_EXT_HSE 0x0A000000U /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
#define RCU_CFGR_MCO_PLL3CLK 0x0B000000U /*!< PLL3 clock selected as MCO source */
#define RCU_CFG0_CKOUT0SEL_NOCLOCK 0x00000000U /*!< No clock */
#define RCU_CFG0_CKOUT0SEL_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
#define RCU_CFG0_CKOUT0SEL_IRC8M 0x05000000U /*!< IRC8M clock selected as MCO source */
#define RCU_CFG0_CKOUT0SEL_HXTAL 0x06000000U /*!< HXTAL clock selected as MCO source */
#define RCU_CFG0_CKOUT0SEL_CK_PLL_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
#define RCU_CFG0_CKOUT0SEL_CK_PLL1 0x08000000U /*!< PLL2 clock selected as MCO source*/
#define RCU_CFG0_CKOUT0SEL_CK_PLL2_DIV2 0x09000000U /*!< PLL3 clock divided by 2 selected as MCO source*/
#define RCU_CFG0_CKOUT0SEL_EXT_HXTAL 0x0A000000U /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
#define RCU_CFG0_CKOUT0SEL_CK_PLL2 0x0B000000U /*!< PLL3 clock selected as MCO source */
/* Reference defines */
#define RCU_CFGR_MCOSEL RCU_CFGR_MCO
#define RCU_CFGR_MCOSEL_0 RCU_CFGR_MCO_0
#define RCU_CFGR_MCOSEL_1 RCU_CFGR_MCO_1
#define RCU_CFGR_MCOSEL_2 RCU_CFGR_MCO_2
#define RCU_CFGR_MCOSEL_3 RCU_CFGR_MCO_3
#define RCU_CFGR_MCOSEL_NOCLOCK RCU_CFGR_MCO_NOCLOCK
#define RCU_CFGR_MCOSEL_SYSCLK RCU_CFGR_MCO_SYSCLK
#define RCU_CFGR_MCOSEL_HSI RCU_CFGR_MCO_HSI
#define RCU_CFGR_MCOSEL_HSE RCU_CFGR_MCO_HSE
#define RCU_CFGR_MCOSEL_PLL_DIV2 RCU_CFGR_MCO_PLLCLK_DIV2
#define RCU_CFGR_MCOSEL_PLL2 RCU_CFGR_MCO_PLL2CLK
#define RCU_CFGR_MCOSEL_PLL3_DIV2 RCU_CFGR_MCO_PLL3CLK_DIV2
#define RCU_CFGR_MCOSEL_EXT_HSE RCU_CFGR_MCO_EXT_HSE
#define RCU_CFGR_MCOSEL_PLL3CLK RCU_CFGR_MCO_PLL3CLK
/*define RCU_CFG0_CKOUT0SELSEL RCU_CFG0_CKOUT0SEL
#define RCU_CFG0_CKOUT0SELSEL_0 RCU_CFG0_CKOUT0SEL_0
#define RCU_CFG0_CKOUT0SELSEL_1 RCU_CFG0_CKOUT0SEL_1
#define RCU_CFG0_CKOUT0SELSEL_2 RCU_CFG0_CKOUT0SEL_2
#define RCU_CFG0_CKOUT0SELSEL_3 RCU_CFG0_CKOUT0SEL_3
#define RCU_CFG0_CKOUT0SELSEL_NOCLOCK RCU_CFG0_CKOUT0SEL_NOCLOCK
#define RCU_CFG0_CKOUT0SELSEL_SYSCLK RCU_CFG0_CKOUT0SEL_SYSCLK
#define RCU_CFG0_CKOUT0SELSEL_IRC8M RCU_CFG0_CKOUT0SEL_IRC8M
#define RCU_CFG0_CKOUT0SELSEL_HXTAL RCU_CFG0_CKOUT0SEL_HXTAL
#define RCU_CFG0_CKOUT0SELSEL_PLL_DIV2 RCU_CFG0_CKOUT0SEL_CK_PLL_DIV2
#define RCU_CFG0_CKOUT0SELSEL_PLL2 RCU_CFG0_CKOUT0SEL_CK_PLL1
#define RCU_CFG0_CKOUT0SELSEL_PLL3_DIV2 RCU_CFG0_CKOUT0SEL_CK_PLL2_DIV2
#define RCU_CFG0_CKOUT0SELSEL_EXT_HXTAL RCU_CFG0_CKOUT0SEL_EXT_HXTAL
#define RCU_CFG0_CKOUT0SELSEL_PLL3CLK RCU_CFG0_CKOUT0SEL_CK_PLL2*/
/*!<****************** Bit definition for RCU_CIR register ********************/
#define RCU_CIR_LSIRDYF_Pos (0U)
#define RCU_CIR_LSIRDYF_Msk (0x1U << RCU_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
#define RCU_CIR_LSIRDYF RCU_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
#define RCU_CIR_LSERDYF_Pos (1U)
#define RCU_CIR_LSERDYF_Msk (0x1U << RCU_CIR_LSERDYF_Pos) /*!< 0x00000002 */
#define RCU_CIR_LSERDYF RCU_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
#define RCU_CIR_HSIRDYF_Pos (2U)
#define RCU_CIR_HSIRDYF_Msk (0x1U << RCU_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
#define RCU_CIR_HSIRDYF RCU_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
#define RCU_CIR_HSERDYF_Pos (3U)
#define RCU_CIR_HSERDYF_Msk (0x1U << RCU_CIR_HSERDYF_Pos) /*!< 0x00000008 */
#define RCU_CIR_HSERDYF RCU_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
#define RCU_CIR_IRC40KRDYF_Pos (0U)
#define RCU_CIR_IRC40KRDYF_Msk (0x1U << RCU_CIR_IRC40KRDYF_Pos) /*!< 0x00000001 */
#define RCU_CIR_IRC40KRDYF RCU_CIR_IRC40KRDYF_Msk /*!< IRC40K Ready Interrupt flag */
#define RCU_CIR_LXTALRDYF_Pos (1U)
#define RCU_CIR_LXTALRDYF_Msk (0x1U << RCU_CIR_LXTALRDYF_Pos) /*!< 0x00000002 */
#define RCU_CIR_LXTALRDYF RCU_CIR_LXTALRDYF_Msk /*!< LXTAL Ready Interrupt flag */
#define RCU_CIR_IRC8MRDYF_Pos (2U)
#define RCU_CIR_IRC8MRDYF_Msk (0x1U << RCU_CIR_IRC8MRDYF_Pos) /*!< 0x00000004 */
#define RCU_CIR_IRC8MRDYF RCU_CIR_IRC8MRDYF_Msk /*!< IRC8M Ready Interrupt flag */
#define RCU_CIR_HXTALRDYF_Pos (3U)
#define RCU_CIR_HXTALRDYF_Msk (0x1U << RCU_CIR_HXTALRDYF_Pos) /*!< 0x00000008 */
#define RCU_CIR_HXTALRDYF RCU_CIR_HXTALRDYF_Msk /*!< HXTAL Ready Interrupt flag */
#define RCU_CIR_PLLRDYF_Pos (4U)
#define RCU_CIR_PLLRDYF_Msk (0x1U << RCU_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
#define RCU_CIR_PLLRDYF RCU_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
#define RCU_CIR_CSSF_Pos (7U)
#define RCU_CIR_CSSF_Msk (0x1U << RCU_CIR_CSSF_Pos) /*!< 0x00000080 */
#define RCU_CIR_CSSF RCU_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
#define RCU_CIR_LSIRDYIE_Pos (8U)
#define RCU_CIR_LSIRDYIE_Msk (0x1U << RCU_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
#define RCU_CIR_LSIRDYIE RCU_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
#define RCU_CIR_LSERDYIE_Pos (9U)
#define RCU_CIR_LSERDYIE_Msk (0x1U << RCU_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
#define RCU_CIR_LSERDYIE RCU_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
#define RCU_CIR_HSIRDYIE_Pos (10U)
#define RCU_CIR_HSIRDYIE_Msk (0x1U << RCU_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
#define RCU_CIR_HSIRDYIE RCU_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
#define RCU_CIR_HSERDYIE_Pos (11U)
#define RCU_CIR_HSERDYIE_Msk (0x1U << RCU_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
#define RCU_CIR_HSERDYIE RCU_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
#define RCU_CIR_IRC40KRDYIE_Pos (8U)
#define RCU_CIR_IRC40KRDYIE_Msk (0x1U << RCU_CIR_IRC40KRDYIE_Pos) /*!< 0x00000100 */
#define RCU_CIR_IRC40KRDYIE RCU_CIR_IRC40KRDYIE_Msk /*!< IRC40K Ready Interrupt Enable */
#define RCU_CIR_LXTALRDYIE_Pos (9U)
#define RCU_CIR_LXTALRDYIE_Msk (0x1U << RCU_CIR_LXTALRDYIE_Pos) /*!< 0x00000200 */
#define RCU_CIR_LXTALRDYIE RCU_CIR_LXTALRDYIE_Msk /*!< LXTAL Ready Interrupt Enable */
#define RCU_CIR_IRC8MRDYIE_Pos (10U)
#define RCU_CIR_IRC8MRDYIE_Msk (0x1U << RCU_CIR_IRC8MRDYIE_Pos) /*!< 0x00000400 */
#define RCU_CIR_IRC8MRDYIE RCU_CIR_IRC8MRDYIE_Msk /*!< IRC8M Ready Interrupt Enable */
#define RCU_CIR_HXTALRDYIE_Pos (11U)
#define RCU_CIR_HXTALRDYIE_Msk (0x1U << RCU_CIR_HXTALRDYIE_Pos) /*!< 0x00000800 */
#define RCU_CIR_HXTALRDYIE RCU_CIR_HXTALRDYIE_Msk /*!< HXTAL Ready Interrupt Enable */
#define RCU_CIR_PLLRDYIE_Pos (12U)
#define RCU_CIR_PLLRDYIE_Msk (0x1U << RCU_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
#define RCU_CIR_PLLRDYIE RCU_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
#define RCU_CIR_LSIRDYC_Pos (16U)
#define RCU_CIR_LSIRDYC_Msk (0x1U << RCU_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
#define RCU_CIR_LSIRDYC RCU_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
#define RCU_CIR_LSERDYC_Pos (17U)
#define RCU_CIR_LSERDYC_Msk (0x1U << RCU_CIR_LSERDYC_Pos) /*!< 0x00020000 */
#define RCU_CIR_LSERDYC RCU_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
#define RCU_CIR_HSIRDYC_Pos (18U)
#define RCU_CIR_HSIRDYC_Msk (0x1U << RCU_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
#define RCU_CIR_HSIRDYC RCU_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
#define RCU_CIR_HSERDYC_Pos (19U)
#define RCU_CIR_HSERDYC_Msk (0x1U << RCU_CIR_HSERDYC_Pos) /*!< 0x00080000 */
#define RCU_CIR_HSERDYC RCU_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
#define RCU_CIR_IRC40KRDYC_Pos (16U)
#define RCU_CIR_IRC40KRDYC_Msk (0x1U << RCU_CIR_IRC40KRDYC_Pos) /*!< 0x00010000 */
#define RCU_CIR_IRC40KRDYC RCU_CIR_IRC40KRDYC_Msk /*!< IRC40K Ready Interrupt Clear */
#define RCU_CIR_LXTALRDYC_Pos (17U)
#define RCU_CIR_LXTALRDYC_Msk (0x1U << RCU_CIR_LXTALRDYC_Pos) /*!< 0x00020000 */
#define RCU_CIR_LXTALRDYC RCU_CIR_LXTALRDYC_Msk /*!< LXTAL Ready Interrupt Clear */
#define RCU_CIR_IRC8MRDYC_Pos (18U)
#define RCU_CIR_IRC8MRDYC_Msk (0x1U << RCU_CIR_IRC8MRDYC_Pos) /*!< 0x00040000 */
#define RCU_CIR_IRC8MRDYC RCU_CIR_IRC8MRDYC_Msk /*!< IRC8M Ready Interrupt Clear */
#define RCU_CIR_HXTALRDYC_Pos (19U)
#define RCU_CIR_HXTALRDYC_Msk (0x1U << RCU_CIR_HXTALRDYC_Pos) /*!< 0x00080000 */
#define RCU_CIR_HXTALRDYC RCU_CIR_HXTALRDYC_Msk /*!< HXTAL Ready Interrupt Clear */
#define RCU_CIR_PLLRDYC_Pos (20U)
#define RCU_CIR_PLLRDYC_Msk (0x1U << RCU_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
#define RCU_CIR_PLLRDYC RCU_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
@ -1702,15 +1690,15 @@ typedef struct
#define RCU_APB1ENR_DACEN RCU_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
/******************* Bit definition for RCU_BDCR register *******************/
#define RCU_BDCR_LSEON_Pos (0U)
#define RCU_BDCR_LSEON_Msk (0x1U << RCU_BDCR_LSEON_Pos) /*!< 0x00000001 */
#define RCU_BDCR_LSEON RCU_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
#define RCU_BDCR_LSERDY_Pos (1U)
#define RCU_BDCR_LSERDY_Msk (0x1U << RCU_BDCR_LSERDY_Pos) /*!< 0x00000002 */
#define RCU_BDCR_LSERDY RCU_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
#define RCU_BDCR_LSEBYP_Pos (2U)
#define RCU_BDCR_LSEBYP_Msk (0x1U << RCU_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
#define RCU_BDCR_LSEBYP RCU_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
#define RCU_BDCR_LXTALON_Pos (0U)
#define RCU_BDCR_LXTALON_Msk (0x1U << RCU_BDCR_LXTALON_Pos) /*!< 0x00000001 */
#define RCU_BDCR_LXTALON RCU_BDCR_LXTALON_Msk /*!< External Low Speed oscillator enable */
#define RCU_BDCR_LXTALRDY_Pos (1U)
#define RCU_BDCR_LXTALRDY_Msk (0x1U << RCU_BDCR_LXTALRDY_Pos) /*!< 0x00000002 */
#define RCU_BDCR_LXTALRDY RCU_BDCR_LXTALRDY_Msk /*!< External Low Speed oscillator Ready */
#define RCU_BDCR_LXTALBYP_Pos (2U)
#define RCU_BDCR_LXTALBYP_Msk (0x1U << RCU_BDCR_LXTALBYP_Pos) /*!< 0x00000004 */
#define RCU_BDCR_LXTALBYP RCU_BDCR_LXTALBYP_Msk /*!< External Low Speed oscillator Bypass */
#define RCU_BDCR_RTCSEL_Pos (8U)
#define RCU_BDCR_RTCSEL_Msk (0x3U << RCU_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
@ -1720,9 +1708,9 @@ typedef struct
/*!< RTC congiguration */
#define RCU_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
#define RCU_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
#define RCU_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
#define RCU_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCU_BDCR_RTCSEL_LXTAL 0x00000100U /*!< LXTAL oscillator clock used as RTC clock */
#define RCU_BDCR_RTCSEL_IRC40K 0x00000200U /*!< IRC40K oscillator clock used as RTC clock */
#define RCU_BDCR_RTCSEL_HXTAL 0x00000300U /*!< HXTAL oscillator clock divided by 128 used as RTC clock */
#define RCU_BDCR_RTCEN_Pos (15U)
#define RCU_BDCR_RTCEN_Msk (0x1U << RCU_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@ -1732,12 +1720,12 @@ typedef struct
#define RCU_BDCR_BDRST RCU_BDCR_BDRST_Msk /*!< Backup domain software reset */
/******************* Bit definition for RCU_CSR register ********************/
#define RCU_CSR_LSION_Pos (0U)
#define RCU_CSR_LSION_Msk (0x1U << RCU_CSR_LSION_Pos) /*!< 0x00000001 */
#define RCU_CSR_LSION RCU_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
#define RCU_CSR_LSIRDY_Pos (1U)
#define RCU_CSR_LSIRDY_Msk (0x1U << RCU_CSR_LSIRDY_Pos) /*!< 0x00000002 */
#define RCU_CSR_LSIRDY RCU_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
#define RCU_CSR_IRC40KON_Pos (0U)
#define RCU_CSR_IRC40KON_Msk (0x1U << RCU_CSR_IRC40KON_Pos) /*!< 0x00000001 */
#define RCU_CSR_IRC40KON RCU_CSR_IRC40KON_Msk /*!< Internal Low Speed oscillator enable */
#define RCU_CSR_IRC40KRDY_Pos (1U)
#define RCU_CSR_IRC40KRDY_Msk (0x1U << RCU_CSR_IRC40KRDY_Pos) /*!< 0x00000002 */
#define RCU_CSR_IRC40KRDY RCU_CSR_IRC40KRDY_Msk /*!< Internal Low Speed oscillator Ready */
#define RCU_CSR_RMVF_Pos (24U)
#define RCU_CSR_RMVF_Msk (0x1U << RCU_CSR_RMVF_Pos) /*!< 0x01000000 */
#define RCU_CSR_RMVF RCU_CSR_RMVF_Msk /*!< Remove reset flag */
@ -1958,7 +1946,7 @@ typedef struct
#define RCU_CFGR2_PREDIV1SRC_PLL2_Pos (16U)
#define RCU_CFGR2_PREDIV1SRC_PLL2_Msk (0x1U << RCU_CFGR2_PREDIV1SRC_PLL2_Pos) /*!< 0x00010000 */
#define RCU_CFGR2_PREDIV1SRC_PLL2 RCU_CFGR2_PREDIV1SRC_PLL2_Msk /*!< PLL2 selected as PREDIV1 entry clock source */
#define RCU_CFGR2_PREDIV1SRC_HSE 0x00000000U /*!< HSE selected as PREDIV1 entry clock source */
#define RCU_CFGR2_PREDIV1SRC_HXTAL 0x00000000U /*!< HXTAL selected as PREDIV1 entry clock source */
#define RCU_CFGR2_I2S2SRC_Pos (17U)
#define RCU_CFGR2_I2S2SRC_Msk (0x1U << RCU_CFGR2_I2S2SRC_Pos) /*!< 0x00020000 */
#define RCU_CFGR2_I2S2SRC RCU_CFGR2_I2S2SRC_Msk /*!< I2S2 entry clock source */
@ -12846,8 +12834,8 @@ typedef struct
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_USBFS)
#define RCU_HSE_MIN 3000000U
#define RCU_HSE_MAX 25000000U
#define RCU_HXTAL_MIN 3000000U
#define RCU_HXTAL_MAX 25000000U
#define RCU_MAX_FREQUENCY 72000000U

8
os/hal/ports/GD/GD32VF103/xWDG/hal_wdg_lld.h
View File

@ -83,12 +83,12 @@
#error "WDG driver activated but no xWDG peripheral assigned"
#endif
#if !defined(GD32_LSI_ENABLED)
#error "GD32_LSI_ENABLED not defined"
#if !defined(GD32_IRC40K_ENABLED)
#error "GD32_IRC40K_ENABLED not defined"
#endif
#if (GD32_WDG_USE_FWDGT == TRUE) && (GD32_LSI_ENABLED == FALSE)
#error "FWDGT requires LSI clock"
#if (GD32_WDG_USE_FWDGT == TRUE) && (GD32_IRC40K_ENABLED == FALSE)
#error "FWDGT requires IRC40K clock"
#endif
/*===========================================================================*/