sn32: cleanup CT
24xB doesn't have CT32 Remove CMSIS leftover SysTick code
This commit is contained in:
Dimitris Mantzouranis
parent
d596a79ae4
commit
777f1fcbb1
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@ -1,71 +0,0 @@
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/******************** (C) COPYRIGHT 2013 SONiX *******************************
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* COMPANY: SONiX
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* DATE: 2013/12
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* AUTHOR: SA1
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* IC: SN32F240/230/220
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* DESCRIPTION: SysTick related functions.
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*____________________________________________________________________________
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* REVISION Date User Description
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* 1.0 2013/12/17 SA1 First release
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*
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*____________________________________________________________________________
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* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
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* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
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* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
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* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
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* IN CONNECTION WITH THEIR PRODUCTS.
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*****************************************************************************/
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/*_____ I N C L U D E S ____________________________________________________*/
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#include "SysTick.h"
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/*_____ D E C L A R A T I O N S ____________________________________________*/
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/*_____ D E F I N I T I O N S ______________________________________________*/
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/*_____ M A C R O S ________________________________________________________*/
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/*_____ F U N C T I O N S __________________________________________________*/
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/*****************************************************************************
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* Function : SysTick_Init
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* Description : Initialization of SysTick timer
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* Input : None
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* Output : None
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* Return : None
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* Note : None
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*****************************************************************************/
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void SysTick_Init (void)
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{
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SystemCoreClockUpdate();
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__SYSTICK_SET_TIMER_PERIOD(10); //RELOAD = (system tick clock frequency ¡Ñ 10 ms)/1000 -1
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__SYSTICK_CLEAR_COUNTER_AND_FLAG;
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#if SYSTICK_IRQ == INTERRUPT_METHOD
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SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
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#else
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SysTick->CTRL = 0x5; //Enable SysTick timer ONLY
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#endif
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}
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/*****************************************************************************
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* Function : SysTick_Handler
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* Description : ISR of SysTick interrupt
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* Input : None
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* Output : None
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* Return : None
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* Note : None
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*****************************************************************************/
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__irq void SysTick_Handler(void)
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{
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__SYSTICK_CLEAR_COUNTER_AND_FLAG;
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}
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@ -1,23 +0,0 @@
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#ifndef __SN32F240_SYSTICK_H
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#define __SN32F240_SYSTICK_H
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/*_____ I N C L U D E S ____________________________________________________*/
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#include <SN32F240.h>
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#include <SN32F200_Def.h>
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/*_____ D E F I N I T I O N S ______________________________________________*/
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#define SYSTICK_IRQ POLLING_METHOD //INTERRUPT_METHOD: Enable SysTick timer and interrupt
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//POLLING_METHOD: Enable SysTick timer ONLY
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/*_____ M A C R O S ________________________________________________________*/
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#define __SYSTICK_SET_TIMER_PERIOD(ms) SysTick->LOAD = SystemCoreClock * ms /1000 - 1
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#define __SYSTICK_CLEAR_COUNTER_AND_FLAG SysTick->VAL = 0xFF
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/*_____ D E C L A R A T I O N S ____________________________________________*/
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void SysTick_Init(void);
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#endif /*__SN32F240_SYSTICK_H*/
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@ -1,347 +0,0 @@
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/******************** (C) COPYRIGHT 2013 SONiX *******************************
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* COMPANY: SONiX
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* DATE: 2013/12
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* AUTHOR: SA1
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* IC: SN32F240/230/220
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* DESCRIPTION: CT16B2 related functions.
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*____________________________________________________________________________
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* REVISION Date User Description
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* 1.0 2013/12/17 SA1 First release
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*
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*____________________________________________________________________________
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* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
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* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
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* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
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* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
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* IN CONNECTION WITH THEIR PRODUCTS.
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*****************************************************************************/
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/*_____ I N C L U D E S ____________________________________________________*/
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#include <SN32F240B.h>
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#include "CT16.h"
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#include "CT16B2.h"
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/*_____ D E C L A R A T I O N S ____________________________________________*/
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volatile uint32_t iwCT16B2_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS
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void CT16B2_Init (void);
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void CT16B2_NvicEnable (void);
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void CT16B2_NvicDisable (void);
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/*_____ D E F I N I T I O N S ______________________________________________*/
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/*_____ M A C R O S ________________________________________________________*/
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/*_____ F U N C T I O N S __________________________________________________*/
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/*****************************************************************************
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* Function : CT16B2_Init
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* Description : Initialization of CT16B2 timer
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* Input : None
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* Output : None
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* Return : None
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* Note : None
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*****************************************************************************/
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void CT16B2_Init (void)
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{
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//Enable P_CLOCK for CT16B2.
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__CT16B2_ENABLE;
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//CT16B2 PCLK prescalar setting
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SN_SYS1->APBCP1_b.CT16B2PRE = 0x00; //PCLK = HCLK/1
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//SN_SYS1->APBCP1_b.CT16B2PRE = 0x01; //PCLK = HCLK/2
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//SN_SYS1->APBCP1_b.CT16B2PRE = 0x02; //PCLK = HCLK/4
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//SN_SYS1->APBCP1_b.CT16B2PRE = 0x03; //PCLK = HCLK/8
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//SN_SYS1->APBCP1_b.CT16B2PRE = 0x04; //PCLK = HCLK/16
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}
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/*****************************************************************************
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* Function : CT16B2_NvicEnable
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* Description : Enable CT16B2 timer interrupt
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* Input : None
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* Output : None
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* Return : None
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* Note : None
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*****************************************************************************/
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void CT16B2_NvicEnable (void)
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{
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NVIC_ClearPendingIRQ(CT16B2_IRQn);
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NVIC_EnableIRQ(CT16B2_IRQn);
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NVIC_SetPriority(CT16B2_IRQn,0); // Set interrupt priority (default)
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}
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/*****************************************************************************
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* Function : CT16B2_NvicDisable
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* Description : Disable CT16B2 timer interrupt
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* Input : None
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* Output : None
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* Return : None
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* Note : None
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*****************************************************************************/
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void CT16B2_NvicDisable (void)
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{
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NVIC_DisableIRQ(CT16B2_IRQn);
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}
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/*****************************************************************************
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* Function : CT16B2_IRQHandler
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* Description : ISR of CT16B2 interrupt
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* Input : None
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* Output : None
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* Return : None
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* Note : None
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*****************************************************************************/
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void CT16B2_IRQHandler(void)
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{
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uint32_t iwRisStatus;
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iwRisStatus = SN_CT16B2->RIS; // Save the interrupt status.
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//Before checking the status, always re-check the interrupt enable register first.
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//In practice, user might use only one or two timer interrupt source.
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//Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary.
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//User can add the directive pair of "#if 0" and "#endif" pair
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//to COMMENT the un-used parts to reduce ISR overheads and ROM usage.
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//Check the status in oder.
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//MR0
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if (SN_CT16B2->MCTRL_b.MR0IE) //Check if MR0 IE enables?
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{
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if(iwRisStatus & mskCT16_MR0IF)
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{
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iwCT16B2_IrqEvent |= mskCT16_MR0IF;
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SN_CT16B2->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status
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}
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}
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//MR1
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if (SN_CT16B2->MCTRL_b.MR1IE) //Check if MR1 IE enables?
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{
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if(iwRisStatus & mskCT16_MR1IF)
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{
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iwCT16B2_IrqEvent |= mskCT16_MR1IF;
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SN_CT16B2->IC = mskCT16_MR1IC; //Clear MR1 match interrupt status
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}
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}
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//MR2
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if (SN_CT16B2->MCTRL_b.MR2IE) //Check if MR2 IE enables?
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{
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if(iwRisStatus & mskCT16_MR2IF)
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{
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iwCT16B2_IrqEvent |= mskCT16_MR2IF;
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SN_CT16B2->IC = mskCT16_MR2IC; //Clear MR2 match interrupt status
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}
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}
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//MR3
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if (SN_CT16B2->MCTRL_b.MR3IE) //Check if MR3 IE enables?
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{
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if(iwRisStatus & mskCT16_MR3IF)
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{
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iwCT16B2_IrqEvent |= mskCT16_MR3IF;
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SN_CT16B2->IC = mskCT16_MR3IC; //Clear MR3 match interrupt status
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}
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}
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//MR4
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if (SN_CT16B1->MCTRL_b.MR4IE) //Check if MR4 IE enables?
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{
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if(iwRisStatus & mskCT16_MR4IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR4IF;
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SN_CT16B1->IC = mskCT16_MR4IC; //Clear MR4 match interrupt status
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}
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}
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//MR5
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if (SN_CT16B1->MCTRL_b.MR5IE) //Check if MR5 IE enables?
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{
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if(iwRisStatus & mskCT16_MR5IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR5IF;
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SN_CT16B1->IC = mskCT16_MR5IC; //Clear MR5 match interrupt status
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}
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}
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//MR6
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if (SN_CT16B1->MCTRL_b.MR6IE) //Check if MR6 IE enables?
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{
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if(iwRisStatus & mskCT16_MR6IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR6IF;
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SN_CT16B1->IC = mskCT16_MR6IC; //Clear MR6 match interrupt status
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}
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}
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//MR7
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if (SN_CT16B1->MCTRL_b.MR7IE) //Check if MR7 IE enables?
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{
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if(iwRisStatus & mskCT16_MR7IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR7IF;
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SN_CT16B1->IC = mskCT16_MR7IC; //Clear MR7 match interrupt status
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}
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}
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//MR8
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if (SN_CT16B1->MCTRL_b.MR8IE) //Check if MR8 IE enables?
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{
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if(iwRisStatus & mskCT16_MR8IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR8IF;
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SN_CT16B1->IC = mskCT16_MR8IC; //Clear MR8 match interrupt status
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}
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}
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//MR9
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if (SN_CT16B1->MCTRL_b.MR9IE) //Check if MR9 IE enables?
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{
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if(iwRisStatus & mskCT16_MR9IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR9IF;
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SN_CT16B1->IC = mskCT16_MR9IC; //Clear MR9 match interrupt status
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}
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}
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//MR10
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if (SN_CT16B1->MCTRL_b.MR10IE) //Check if MR10 IE enables?
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{
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if(iwRisStatus & mskCT16_MR10IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR10IF;
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SN_CT16B1->IC = mskCT16_MR10IC; //Clear MR10 match interrupt status
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}
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}
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//MR11
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if (SN_CT16B1->MCTRL_b.MR11IE) //Check if MR11 IE enables?
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{
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if(iwRisStatus & mskCT16_MR11IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR11IF;
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SN_CT16B1->IC = mskCT16_MR11IC; //Clear MR11 match interrupt status
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}
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}
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//MR12
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if (SN_CT16B1->MCTRL_b.MR12IE) //Check if MR12 IE enables?
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{
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if(iwRisStatus & mskCT16_MR12IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR12IF;
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SN_CT16B1->IC = mskCT16_MR12IC; //Clear MR12 match interrupt status
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}
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}
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//MR13
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if (SN_CT16B1->MCTRL_b.MR13IE) //Check if MR13 IE enables?
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{
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if(iwRisStatus & mskCT16_MR13IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR13IF;
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SN_CT16B1->IC = mskCT16_MR13IC; //Clear MR13 match interrupt status
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}
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}
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//MR14
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if (SN_CT16B1->MCTRL_b.MR14IE) //Check if MR14 IE enables?
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{
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if(iwRisStatus & mskCT16_MR14IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR14IF;
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SN_CT16B1->IC = mskCT16_MR14IC; //Clear MR14 match interrupt status
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}
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}
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//MR15
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if (SN_CT16B1->MCTRL_b.MR15IE) //Check if MR15 IE enables?
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{
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if(iwRisStatus & mskCT16_MR15IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR15IF;
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SN_CT16B1->IC = mskCT16_MR15IC; //Clear MR15 match interrupt status
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}
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}
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//MR16
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if (SN_CT16B1->MCTRL_b.MR16IE) //Check if MR16 IE enables?
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{
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if(iwRisStatus & mskCT16_MR16IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR16IF;
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SN_CT16B1->IC = mskCT16_MR16IC; //Clear MR16 match interrupt status
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}
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}
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//MR17
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if (SN_CT16B1->MCTRL_b.MR17IE) //Check if MR17 IE enables?
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{
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if(iwRisStatus & mskCT16_MR17IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR17IF;
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SN_CT16B1->IC = mskCT16_MR17IC; //Clear MR17 match interrupt status
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}
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}
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//MR18
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if (SN_CT16B1->MCTRL_b.MR18IE) //Check if MR18 IE enables?
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{
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if(iwRisStatus & mskCT16_MR18IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR18IF;
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SN_CT16B1->IC = mskCT16_MR18IC; //Clear MR18 match interrupt status
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}
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}
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//MR19
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if (SN_CT16B1->MCTRL_b.MR19IE) //Check if MR19 IE enables?
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{
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if(iwRisStatus & mskCT16_MR19IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR19IF;
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SN_CT16B1->IC = mskCT16_MR19IC; //Clear MR19 match interrupt status
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}
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}
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//MR20
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if (SN_CT16B1->MCTRL_b.MR20IE) //Check if MR20 IE enables?
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{
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if(iwRisStatus & mskCT16_MR20IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR20IF;
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SN_CT16B1->IC = mskCT16_MR20IC; //Clear MR20 match interrupt status
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}
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}
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//MR21
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if (SN_CT16B1->MCTRL_b.MR21IE) //Check if MR21 IE enables?
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{
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if(iwRisStatus & mskCT16_MR21IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR21IF;
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SN_CT16B1->IC = mskCT16_MR21IC; //Clear MR21 match interrupt status
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}
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}
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//MR22
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if (SN_CT16B1->MCTRL_b.MR22IE) //Check if MR22 IE enables?
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{
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if(iwRisStatus & mskCT16_MR22IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR22IF;
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SN_CT16B1->IC = mskCT16_MR22IC; //Clear MR22 match interrupt status
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}
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}
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//MR23
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if (SN_CT16B1->MCTRL_b.MR23IE) //Check if MR23 IE enables?
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{
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if(iwRisStatus & mskCT16_MR23IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR23IF;
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SN_CT16B1->IC = mskCT16_MR23IC; //Clear MR23 match interrupt status
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}
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}
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//MR24
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if (SN_CT16B1->MCTRL_b.MR24IE) //Check if MR24 IE enables?
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{
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if(iwRisStatus & mskCT16_MR24IF)
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{
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iwCT16B1_IrqEvent |= mskCT16_MR24IF;
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SN_CT16B1->IC = mskCT16_MR24IC; //Clear MR24 match interrupt status
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}
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}
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//CAP0
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if (SN_CT16B2->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables?
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{
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if(iwRisStatus & mskCT16_CAP0IF) //CAP0
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{
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iwCT16B2_IrqEvent |= mskCT16_CAP0IF;
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SN_CT16B2->IC = mskCT16_CAP0IC; //Clear CAP0 interrupt status
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}
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}
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}
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@ -1,25 +0,0 @@
|
|||
#ifndef __SN32F240_CT16B2_H
|
||||
#define __SN32F240_CT16B2_H
|
||||
|
||||
/*_____ I N C L U D E S ____________________________________________________*/
|
||||
#include <stdint.h>
|
||||
#include <SN32F200_Def.h>
|
||||
|
||||
|
||||
/*_____ D E F I N I T I O N S ______________________________________________*/
|
||||
#define CT16B2_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B2 timer and interrupt
|
||||
//POLLING_METHOD: Enable CT16B2 timer ONLY
|
||||
|
||||
/*_____ M A C R O S ________________________________________________________*/
|
||||
// Enable CT16B2 PCLK
|
||||
#define __CT16B2_ENABLE SN_SYS1->AHBCLKEN_b.CT16B2CLKEN = ENABLE
|
||||
// Disable CT16B1 PCLK
|
||||
#define __CT16B2_DISABLE SN_SYS1->AHBCLKEN_b.CT16B2CLKEN = DISABLE
|
||||
|
||||
/*_____ D E C L A R A T I O N S ____________________________________________*/
|
||||
extern volatile uint32_t iwCT16B2_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS
|
||||
|
||||
extern void CT16B2_Init(void);
|
||||
extern void CT16B2_NvicEnable(void);
|
||||
extern void CT16B2_NvicDisable(void);
|
||||
#endif /*__SN32F240_CT16B2_H*/
|
||||
|
|
@ -1,279 +0,0 @@
|
|||
#ifndef __SN32F240_CT32_H
|
||||
#define __SN32F240_CT32_H
|
||||
|
||||
|
||||
/*_____ I N C L U D E S ____________________________________________________*/
|
||||
|
||||
/*_____ D E F I N I T I O N S ______________________________________________*/
|
||||
/*
|
||||
Base Address: 0x4000 6000 (CT32B0)
|
||||
0x4000 8000 (CT32B1)
|
||||
0x4000 A000 (CT32B2)
|
||||
*/
|
||||
|
||||
/* CT32Bn Timer Control register <CT32Bn_TMRCTRL> (0x00) */
|
||||
#define CT32_CEN_DIS 0 //[0:0] CT32Bn enable bit
|
||||
#define CT32_CEN_EN 1
|
||||
#define mskCT32_CEN_DIS (CT32_CEN_DIS<<0)
|
||||
#define mskCT32_CEN_EN (CT32_CEN_EN<<0)
|
||||
|
||||
#define CT32_CRST 1 //[1:1] CT32Bn counter reset bit
|
||||
#define mskCT32_CRST (CT32_CRST<<1)
|
||||
|
||||
//[6:4] CT32Bn counting mode selection
|
||||
#define CT32_CM_EDGE_UP 0 //Edge-aligned Up-counting mode
|
||||
#define CT32_CM_EDGE_DOWN 1 //Edge-aligned Down-counting mode
|
||||
#define CT32_CM_CENTER_UP 2 //Center-aligned mode 1. Match interrupt is set during up-counting period
|
||||
#define CT32_CM_CENTER_DOWN 4 //Center-aligned mode 2. Match interrupt is set during down-counting period
|
||||
#define CT32_CM_CENTER_BOTH 6 //Center-aligned mode 3. Match interrupt is set during both up and down period.
|
||||
#define mskCT32_CM_EDGE_UP (CT32_CM_EDGE_UP<<4)
|
||||
#define mskCT32_CM_EDGE_DOWN (CT32_CM_EDGE_DOWN<<4)
|
||||
#define mskCT32_CM_CENTER_UP (CT32_CM_CENTER_UP<<4)
|
||||
#define mskCT32_CM_CENTER_DOWN (CT32_CM_CENTER_DOWN<<4)
|
||||
#define mskCT32_CM_CENTER_BOTH (CT32_CM_CENTER_BOTH<<4)
|
||||
|
||||
/* CT32Bn Count Control register <CT32Bn_CNTCTRL> (0x10) */
|
||||
//[1:0] Count/Timer Mode selection.
|
||||
#define CT32_CTM_TIMER 0 //Timer mode: Every rising PCLK edge.
|
||||
#define CT32_CTM_CNTER_RISING 1 //Counter mode: TC increments on rising edge of CAP input.
|
||||
#define CT32_CTM_CNTER_FALLING 2 //Counter mode: TC increments on falling edge of CAP input.
|
||||
#define CT32_CTM_CNTER_BOTH 3 //Counter mode: TC increments on both edge of CAP input.
|
||||
#define mskCT32_CTM_TIMER (CT32_CTM_TIMER<<0)
|
||||
#define mskCT32_CTM_CNTER_RISING (CT32_CTM_CNTER_RISING<<0)
|
||||
#define mskCT32_CTM_CNTER_FALLING (CT32_CTM_CNTER_FALLING<<0)
|
||||
#define mskCT32_CTM_CNTER_BOTH (CT32_CTM_CNTER_BOTH<<0)
|
||||
|
||||
#define CT32_CIS 0 //[3:2] Count Input Select
|
||||
#define mskCT32_CIS (CT32_CIS<<2)
|
||||
|
||||
/* CT32Bn Match Control register <CT32Bn_MCTRL> (0x14) */
|
||||
#define CT32_MR0IE_EN 1 //[0:0] Enable MR0 match interrupt
|
||||
#define CT32_MR0IE_DIS 0
|
||||
#define mskCT32_MR0IE_EN (CT32_MR0IE_EN<<0)
|
||||
#define mskCT32_MR0IE_DIS (CT32_MR0IE_DIS<<0)
|
||||
|
||||
#define CT32_MR0RST_EN 1 //[1:1] Enable reset TC when MR0 matches TC.
|
||||
#define CT32_MR0RST_DIS 0
|
||||
#define mskCT32_MR0RST_EN (CT32_MR0RST_EN<<1)
|
||||
#define mskCT32_MR0RST_DIS (CT32_MR0RST_DIS<<1)
|
||||
|
||||
#define CT32_MR0STOP_EN 1 //[2:2] Enable stop TC and clear CEN when MR0 matches TC.
|
||||
#define CT32_MR0STOP_DIS 0
|
||||
#define mskCT32_MR0STOP_EN (CT32_MR0STOP_EN<<2)
|
||||
#define mskCT32_MR0STOP_DIS (CT32_MR0STOP_DIS<<2)
|
||||
|
||||
#define CT32_MR1IE_EN 1 //[3:3] Enable MR1 match interrupt
|
||||
#define CT32_MR1IE_DIS 0
|
||||
#define mskCT32_MR1IE_EN (CT32_MR1IE_EN<<3)
|
||||
#define mskCT32_MR1IE_DIS (CT32_MR1IE_DIS<<3)
|
||||
|
||||
#define CT32_MR1RST_EN 1 //[4:4] Enable reset TC when MR1 matches TC.
|
||||
#define CT32_MR1RST_DIS 0
|
||||
#define mskCT32_MR1RST_EN (CT32_MR1RST_EN<<4)
|
||||
#define mskCT32_MR1RST_DIS (CT32_MR1RST_DIS<<4)
|
||||
|
||||
#define CT32_MR1STOP_EN 1 //[5:5] Enable stop TC and clear CEN when MR1 matches TC.
|
||||
#define CT32_MR1STOP_DIS 0
|
||||
#define mskCT32_MR1STOP_EN (CT32_MR1STOP_EN<<5)
|
||||
#define mskCT32_MR1STOP_DIS (CT32_MR1STOP_DIS<<5)
|
||||
|
||||
#define CT32_MR2IE_EN 1 //[6:6] Enable MR2 match interrupt
|
||||
#define CT32_MR2IE_DIS 0
|
||||
#define mskCT32_MR2IE_EN (CT32_MR2IE_EN<<6)
|
||||
#define mskCT32_MR2IE_DIS (CT32_MR2IE_DIS<<6)
|
||||
|
||||
#define CT32_MR2RST_EN 1 //[7:7] Enable reset TC when MR2 matches TC.
|
||||
#define CT32_MR2RST_DIS 0
|
||||
#define mskCT32_MR2RST_EN (CT32_MR2RST_EN<<7)
|
||||
#define mskCT32_MR2RST_DIS (CT32_MR2RST_DIS<<7)
|
||||
|
||||
#define CT32_MR2STOP_EN 1 //[8:8] Enable stop TC and clear CEN when MR2 matches TC.
|
||||
#define CT32_MR2STOP_DIS 0
|
||||
#define mskCT32_MR2STOP_EN (CT32_MR2STOP_EN<<8)
|
||||
#define mskCT32_MR2STOP_DIS (CT32_MR2STOP_DIS<<8)
|
||||
|
||||
#define CT32_MR3IE_EN 1 //[9:9] Enable MR3 match interrupt
|
||||
#define CT32_MR3IE_DIS 0
|
||||
#define mskCT32_MR3IE_EN (CT32_MR3IE_EN<<9)
|
||||
#define mskCT32_MR3IE_DIS (CT32_MR3IE_DIS<<9)
|
||||
|
||||
#define CT32_MR3RST_EN 1 //[10:10] Enable reset TC when MR3 matches TC.
|
||||
#define CT32_MR3RST_DIS 0
|
||||
#define mskCT32_MR3RST_EN (CT32_MR3RST_EN<<10)
|
||||
#define mskCT32_MR3RST_DIS (CT32_MR3RST_DIS<<10)
|
||||
|
||||
#define CT32_MR3STOP_EN 1 //[11:11] Enable stop TC and clear CEN when MR3 matches TC.
|
||||
#define CT32_MR3STOP_DIS 0
|
||||
#define mskCT32_MR3STOP_EN (CT32_MR3STOP_EN<<11)
|
||||
#define mskCT32_MR3STOP_DIS (CT32_MR3STOP_DIS<<11)
|
||||
|
||||
/* CT32Bn Capture Control register <CT32Bn_CAPCTRL> (0x28) */
|
||||
#define CT32_CAP0RE_EN 1 //[0:0] Enable CAP0 capture on rising edge.
|
||||
#define CT32_CAP0RE_DIS 0
|
||||
#define mskCT32_CAP0RE_EN (CT32_CAP0RE_EN<<0)
|
||||
#define mskCT32_CAP0RE_DIS (CT32_CAP0RE_DIS<<0)
|
||||
|
||||
#define CT32_CAP0FE_EN 1 //[1:1] Enable CAP0 capture on fallng edge.
|
||||
#define CT32_CAP0FE_DIS 0
|
||||
#define mskCT32_CAP0FE_EN (CT32_CAP0FE_EN<<1)
|
||||
#define mskCT32_CAP0FE_DIS (CT32_CAP0FE_DIS<<1)
|
||||
|
||||
#define CT32_CAP0IE_EN 1 //[2:2] Enable CAP0 interrupt.
|
||||
#define CT32_CAP0IE_DIS 0
|
||||
#define mskCT32_CAP0IE_EN (CT32_CAP0IE_EN<<2)
|
||||
#define mskCT32_CAP0IE_DIS (CT32_CAP0IE_DIS<<2)
|
||||
|
||||
#define CT32_CAP0EN_EN 1 //[3:3] Enable CAP0 function.
|
||||
#define CT32_CAP0EN_DIS 0
|
||||
#define mskCT32_CAP0EN_EN (CT32_CAP0EN_EN<<3)
|
||||
#define mskCT32_CAP0EN_DIS (CT32_CAP0EN_DIS<<3)
|
||||
|
||||
/* CT32Bn External Match register <CT32Bn_EM> (0x30) */
|
||||
#define CT32_EM0 1 //[0:0] CT32Bn PWM0 drive state
|
||||
#define mskCT32_EM0 (CT32_EM0<<0)
|
||||
#define CT32_EM1 1 //[1:1] CT32Bn PWM1 drive state
|
||||
#define mskCT32_EM1 (CT32_EM1<<1)
|
||||
#define CT32_EM2 1 //[2:2] CT32Bn PWM2 drive state
|
||||
#define mskCT32_EM2 (CT32_EM2<<2)
|
||||
#define CT32_EM3 1 //[3:3] CT32Bn PWM3 drive state
|
||||
#define mskCT32_EM3 (CT32_EM3<<3)
|
||||
|
||||
//[5:4] CT32Bn PWM0 functionality
|
||||
#define CT32_EMC0_DO_NOTHING 0 //Do nothing.
|
||||
#define CT32_EMC0_LOW 1 //CT32Bn PWM0 pin is low.
|
||||
#define CT32_EMC0_HIGH 2 //CT32Bn PWM0 pin is high.
|
||||
#define CT32_EMC0_TOGGLE 3 //Toggle CT32Bn PWM0 pin.
|
||||
#define mskCT32_EMC0_DO_NOTHING (CT32_EMC0_LOW<<4)
|
||||
#define mskCT32_EMC0_LOW (CT32_EMC0_LOW<<4)
|
||||
#define mskCT32_EMC0_HIGH (CT32_EMC0_HIGH<<4)
|
||||
#define mskCT32_EMC0_TOGGLE (CT32_EMC0_TOGGLE<<4)
|
||||
|
||||
//[7:6] CT32Bn PWM1 functionality
|
||||
#define CT32_EMC1_DO_NOTHING 0 //Do nothing.
|
||||
#define CT32_EMC1_LOW 1 //CT32Bn PWM1 pin is low.
|
||||
#define CT32_EMC1_HIGH 2 //CT32Bn PWM1 pin is high.
|
||||
#define CT32_EMC1_TOGGLE 3 //Toggle CT32Bn PWM1 pin.
|
||||
#define mskCT32_EMC1_DO_NOTHING (CT32_EMC1_LOW<<6)
|
||||
#define mskCT32_EMC1_LOW (CT32_EMC1_LOW<<6)
|
||||
#define mskCT32_EMC1_HIGH (CT32_EMC1_HIGH<<6)
|
||||
#define mskCT32_EMC1_TOGGLE (CT32_EMC1_TOGGLE<<6)
|
||||
|
||||
//[9:8] CT32Bn PWM2 functionality
|
||||
#define CT32_EMC2_DO_NOTHING 0 //Do nothing.
|
||||
#define CT32_EMC2_LOW 1 //CT32Bn PWM2 pin is low.
|
||||
#define CT32_EMC2_HIGH 2 //CT32Bn PWM2 pin is high.
|
||||
#define CT32_EMC2_TOGGLE 3 //Toggle CT32Bn PWM2 pin.
|
||||
#define mskCT32_EMC2_DO_NOTHING (CT32_EMC2_LOW<<8)
|
||||
#define mskCT32_EMC2_LOW (CT32_EMC2_LOW<<8)
|
||||
#define mskCT32_EMC2_HIGH (CT32_EMC2_HIGH<<8)
|
||||
#define mskCT32_EMC2_TOGGLE (CT32_EMC2_TOGGLE<<8)
|
||||
|
||||
//[11:10] CT32Bn PWM3 functionality
|
||||
#define CT32_EMC3_DO_NOTHING 0 //Do nothing.
|
||||
#define CT32_EMC3_LOW 1 //CT32Bn PWM3 pin is low.
|
||||
#define CT32_EMC3_HIGH 2 //CT32Bn PWM3 pin is high.
|
||||
#define CT32_EMC3_TOGGLE 3 //Toggle CT32Bn PWM3 pin.
|
||||
#define mskCT32_EMC3_DO_NOTHING (CT32_EMC2_LOW<<10)
|
||||
#define mskCT32_EMC3_LOW (CT32_EMC2_LOW<<10)
|
||||
#define mskCT32_EMC3_HIGH (CT32_EMC2_HIGH<<10)
|
||||
#define mskCT32_EMC3_TOGGLE (CT32_EMC2_TOGGLE<<10)
|
||||
|
||||
/* CT32Bn PWM Control register <CT32Bn_PWMCTRL> (0x34) */
|
||||
//[0:0] CT32Bn PWM0 enable.
|
||||
#define CT32_PWM0EN_EN 1 // CT32Bn PWM0 is enabled for PWM mode.
|
||||
#define CT32_PWM0EN_EM0 0 // CT32Bn PWM0 is controlled by EM0.
|
||||
#define mskCT32_PWM0EN_EN (CT32_PWM0EN_EN<<0)
|
||||
#define mskCT32_PWM0EN_EM0 (CT32_PWM0EN_EM0<<0)
|
||||
|
||||
//[1:1] CT32Bn PWM1 enable.
|
||||
#define CT32_PWM1EN_EN 1 // CT32Bn PWM1 is enabled for PWM mode.
|
||||
#define CT32_PWM1EN_EM1 0 // CT32Bn PWM1 is controlled by EM1.
|
||||
#define mskCT32_PWM1EN_EN (CT32_PWM1EN_EN<<1)
|
||||
#define mskCT32_PWM1EN_EM1 (CT32_PWM1EN_EM1<<1)
|
||||
|
||||
//[2:2] CT32Bn PWM2 enable.
|
||||
#define CT32_PWM2EN_EN 1 // CT32Bn PWM2 is enabled for PWM mode.
|
||||
#define CT32_PWM2EN_EM2 0 // CT32Bn PWM2 is controlled by EM2.
|
||||
#define mskCT32_PWM2EN_EN (CT32_PWM2EN_EN<<2)
|
||||
#define mskCT32_PWM2EN_EM2 (CT32_PWM2EN_EM2<<2)
|
||||
|
||||
//[3:3] CT32Bn PWM3 enable.
|
||||
#define CT32_PWM3EN_EN 1 // CT32Bn PWM3 is enabled for PWM mode.
|
||||
#define CT32_PWM3EN_EM3 0 // CT32Bn PWM3 is controlled by EM3.
|
||||
#define mskCT32_PWM3EN_EN (CT32_PWM3EN_EN<<3)
|
||||
#define mskCT32_PWM3EN_EM3 (CT32_PWM3EN_EM3<<3)
|
||||
|
||||
//[5:4] CT32Bn PWM0 output mode.
|
||||
#define CT32_PWM0MODE_1 0 // PWM mode 1.
|
||||
#define CT32_PWM0MODE_2 1 // PWM mode 2.
|
||||
#define CT32_PWM0MODE_FORCE_0 2 // Force 0.
|
||||
#define CT32_PWM0MODE_FORCE_1 3 // Force 1.
|
||||
#define mskCT32_PWM0MODE_1 (CT32_PWM0MODE_1<<4)
|
||||
#define mskCT32_PWM0MODE_2 (CT32_PWM0MODE_2<<4)
|
||||
#define mskCT32_PWM0MODE_FORCE_0 (CT32_PWM0MODE_FORCE_0<<4)
|
||||
#define mskCT32_PWM0MODE_FORCE_1 (CT32_PWM0MODE_FORCE_1<<4)
|
||||
|
||||
//[7:6] CT32Bn PWM1 output mode.
|
||||
#define CT32_PWM1MODE_1 0 // PWM mode 1.
|
||||
#define CT32_PWM1MODE_2 1 // PWM mode 2.
|
||||
#define CT32_PWM1MODE_FORCE_0 2 // Force 0.
|
||||
#define CT32_PWM1MODE_FORCE_1 3 // Force 1.
|
||||
#define mskCT32_PWM1MODE_1 (CT32_PWM1MODE_1<<6)
|
||||
#define mskCT32_PWM1MODE_2 (CT32_PWM1MODE_2<<6)
|
||||
#define mskCT32_PWM1MODE_FORCE_0 (CT32_PWM1MODE_FORCE_0<<6)
|
||||
#define mskCT32_PWM1MODE_FORCE_1 (CT32_PWM1MODE_FORCE_1<<6)
|
||||
|
||||
//[9:8] CT32Bn PWM2 output mode.
|
||||
#define CT32_PWM2MODE_1 0 // PWM mode 1.
|
||||
#define CT32_PWM2MODE_2 1 // PWM mode 2.
|
||||
#define CT32_PWM2MODE_FORCE_0 2 // Force 0.
|
||||
#define CT32_PWM2MODE_FORCE_1 3 // Force 1.
|
||||
#define mskCT32_PWM2MODE_1 (CT32_PWM2MODE_1<<8)
|
||||
#define mskCT32_PWM2MODE_2 (CT32_PWM2MODE_2<<8)
|
||||
#define mskCT32_PWM2MODE_FORCE_0 (CT32_PWM2MODE_FORCE_0<<8)
|
||||
#define mskCT32_PWM2MODE_FORCE_1 (CT32_PWM2MODE_FORCE_1<<8)
|
||||
|
||||
//[20:20] CT32Bn PWM0 IO selection.
|
||||
#define CT32_PWM0IOEN_EN 1 // PWM 0 pin acts as match output.
|
||||
#define CT32_PWM0IOEN_DIS 0 // PWM 0 pin acts as GPIO.
|
||||
#define mskCT32_PWM0IOEN_EN (CT32_PWM0IOEN_EN<<20)
|
||||
#define mskCT32_PWM0IOEN_DIS (CT32_PWM0IOEN_DIS<<20)
|
||||
|
||||
//[21:21] CT32Bn PWM1 IO selection.
|
||||
#define CT32_PWM1IOEN_EN 1 // PWM 1 pin acts as match output.
|
||||
#define CT32_PWM1IOEN_DIS 0 // PWM 1 pin acts as GPIO.
|
||||
#define mskCT32_PWM1IOEN_EN (CT32_PWM1IOEN_EN<<21)
|
||||
#define mskCT32_PWM1IOEN_DIS (CT32_PWM1IOEN_DIS<<21)
|
||||
|
||||
//[22:22] CT32Bn PWM2 IO selection.
|
||||
#define CT32_PWM2IOEN_EN 1 // PWM 2 pin acts as match output.
|
||||
#define CT32_PWM2IOEN_DIS 0 // PWM 2 pin acts as GPIO.
|
||||
#define mskCT32_PWM2IOEN_EN (CT32_PWM2IOEN_EN<<22)
|
||||
#define mskCT32_PWM2IOEN_DIS (CT32_PWM2IOEN_DIS<<22)
|
||||
|
||||
//[23:23] CT32Bn PWM3 IO selection.
|
||||
#define CT32_PWM3IOEN_EN 0 // PWM 3 pin acts as match output.
|
||||
#define CT32_PWM3IOEN_DIS 0 // PWM 3 pin acts as GPIO.
|
||||
#define mskCT32_PWM3IOEN_EN (CT32_PWM3IOEN_EN<<23)
|
||||
#define mskCT32_PWM3IOEN_DIS (CT32_PWM3IOEN_DIS<<23)
|
||||
|
||||
/* CT32Bn Timer Raw Interrupt Status register <CT32Bn_RIS> (0x38) */
|
||||
/* CT32Bn Timer Interrupt Clear register <CT32Bn_IC> (0x3C) */
|
||||
/* The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS*/
|
||||
#define mskCT32_MR0IF (0x1<<0) //[0:0] Interrupt flag for match channel 0
|
||||
#define mskCT32_MR0IC mskCT32_MR0IF
|
||||
#define mskCT32_MR1IF (0x1<<1) //[1:1] Interrupt flag for match channel 1
|
||||
#define mskCT32_MR1IC mskCT32_MR1IF
|
||||
#define mskCT32_MR2IF (0x1<<2) //[2:2] Interrupt flag for match channel 2
|
||||
#define mskCT32_MR2IC mskCT32_MR2IF
|
||||
#define mskCT32_MR3IF (0x1<<3) //[3:3] Interrupt flag for match channel 3
|
||||
#define mskCT32_MR3IC mskCT32_MR3IF
|
||||
#define mskCT32_CAP0IF (0x1<<4) //[4:4] Interrupt flag for capture channel 0
|
||||
#define mskCT32_CAP0IC mskCT32_CAP0IF
|
||||
|
||||
/*_____ M A C R O S ________________________________________________________*/
|
||||
|
||||
|
||||
/*_____ D E C L A R A T I O N S ____________________________________________*/
|
||||
#endif /*__SN32F240_CT32_H*/
|
||||
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
/******************** (C) COPYRIGHT 2013 SONiX *******************************
|
||||
* COMPANY: SONiX
|
||||
* DATE: 2013/12
|
||||
* AUTHOR: SA1
|
||||
* IC: SN32F240/230/220
|
||||
* DESCRIPTION: CT32B0 related functions.
|
||||
*____________________________________________________________________________
|
||||
* REVISION Date User Description
|
||||
* 1.0 2013/12/17 SA1 First release
|
||||
*
|
||||
*____________________________________________________________________________
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
|
||||
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
|
||||
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
|
||||
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
|
||||
* IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*****************************************************************************/
|
||||
|
||||
/*_____ I N C L U D E S ____________________________________________________*/
|
||||
#include <SN32F240B.h>
|
||||
#include "CT32.h"
|
||||
#include "CT32B0.h"
|
||||
|
||||
|
||||
/*_____ D E C L A R A T I O N S ____________________________________________*/
|
||||
volatile uint32_t iwCT32B0_IrqEvent = 0x00; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS
|
||||
|
||||
void CT32B0_Init (void);
|
||||
void CT32B0_NvicEnable (void);
|
||||
void CT32B0_NvicDisable (void);
|
||||
|
||||
/*_____ D E F I N I T I O N S ______________________________________________*/
|
||||
|
||||
|
||||
/*_____ M A C R O S ________________________________________________________*/
|
||||
|
||||
|
||||
/*_____ F U N C T I O N S __________________________________________________*/
|
||||
|
||||
/*****************************************************************************
|
||||
* Function : CT32B0_Init
|
||||
* Description : Initialization of CT32B0 timer
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
void CT32B0_Init (void)
|
||||
{
|
||||
//Enable P_CLOCK for CT32B0.
|
||||
__CT32B0_ENABLE;
|
||||
|
||||
//CT32B0 PCLK prescalar setting
|
||||
SN_SYS1->APBCP0_b.CT32B0PRE = 0x00; //PCLK = HCLK/1
|
||||
//SN_SYS1->APBCP0_b.CT32B0PRE = 0x01; //PCLK = HCLK/2
|
||||
//SN_SYS1->APBCP0_b.CT32B0PRE = 0x02; //PCLK = HCLK/4
|
||||
//SN_SYS1->APBCP0_b.CT32B0PRE = 0x03; //PCLK = HCLK/8
|
||||
//SN_SYS1->APBCP0_b.CT32B0PRE = 0x04; //PCLK = HCLK/16
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Function : CT32B0_NvicEnable
|
||||
* Description : Enable CT32B0 timer interrupt
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
void CT32B0_NvicEnable (void)
|
||||
{
|
||||
NVIC_ClearPendingIRQ(CT32B0_IRQn);
|
||||
NVIC_EnableIRQ(CT32B0_IRQn);
|
||||
//NVIC_SetPriority(CT32B0_IRQn,0); //Set interrupt priority (default)
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Function : CT32B0_NvicDisable
|
||||
* Description : Disable CT32B0 timer interrupt
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
void CT32B0_NvicDisable (void)
|
||||
{
|
||||
NVIC_DisableIRQ(CT32B0_IRQn);
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Function : TIMER32_0_IRQHandler
|
||||
* Description : ISR of CT32B0 interrupt
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
__irq void CT32B0_IRQHandler(void)
|
||||
{
|
||||
uint32_t iwRisStatus;
|
||||
|
||||
iwRisStatus = SN_CT32B0->RIS; // Save the interrupt status.
|
||||
|
||||
//Before checking the status, always re-check the interrupt enable register first.
|
||||
//In practice, user might use only one or two timer interrupt source.
|
||||
//Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary.
|
||||
//User can add the directive pair of "#if 0" and "#endif" pair
|
||||
//to COMMENT the un-used parts to reduce ISR overheads and ROM usage.
|
||||
|
||||
//Check the status in oder.
|
||||
//MR0
|
||||
if (SN_CT32B0->MCTRL_b.MR0IE) //Check if MR0 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_MR0IF)
|
||||
{
|
||||
iwCT32B0_IrqEvent |= mskCT32_MR0IF;
|
||||
SN_CT32B0->IC = mskCT32_MR0IC; //Clear MR0 match interrupt status
|
||||
}
|
||||
}
|
||||
//MR1
|
||||
if (SN_CT32B0->MCTRL_b.MR1IE) //Check if MR1 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_MR1IF)
|
||||
{
|
||||
iwCT32B0_IrqEvent |= mskCT32_MR1IF;
|
||||
SN_CT32B0->IC = mskCT32_MR1IC; //Clear MR1 match interrupt status
|
||||
}
|
||||
}
|
||||
//MR2
|
||||
if (SN_CT32B0->MCTRL_b.MR2IE) //Check if MR2 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_MR2IF)
|
||||
{
|
||||
iwCT32B0_IrqEvent |= mskCT32_MR2IF;
|
||||
SN_CT32B0->IC = mskCT32_MR2IC; //Clear MR2 match interrupt status
|
||||
}
|
||||
}
|
||||
//MR3
|
||||
if (SN_CT32B0->MCTRL_b.MR3IE) //Check if MR3 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_MR3IF)
|
||||
{
|
||||
iwCT32B0_IrqEvent |= mskCT32_MR3IF;
|
||||
SN_CT32B0->IC = mskCT32_MR3IC; //Clear MR3 match interrupt status
|
||||
}
|
||||
}
|
||||
//CAP0
|
||||
if (SN_CT32B0->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_CAP0IF) //CAP0
|
||||
{
|
||||
iwCT32B0_IrqEvent |= mskCT32_CAP0IF;
|
||||
SN_CT32B0->IC = mskCT32_CAP0IC; //Clear CAP0 interrupt status
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
#ifndef __SN32F240_CT32B0_H
|
||||
#define __SN32F240_CT32B0_H
|
||||
|
||||
|
||||
/*_____ I N C L U D E S ____________________________________________________*/
|
||||
#include <stdint.h>
|
||||
#include <SN32F200_Def.h>
|
||||
|
||||
|
||||
/*_____ D E F I N I T I O N S ______________________________________________*/
|
||||
#define CT32B0_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT32B0 timer and interrupt
|
||||
//POLLING_METHOD: Enable CT32B0 timer ONLY
|
||||
|
||||
/*_____ M A C R O S ________________________________________________________*/
|
||||
// Enable CT32B0 PCLK
|
||||
#define __CT32B0_ENABLE SN_SYS1->AHBCLKEN_b.CT32B0CLKEN = ENABLE
|
||||
// Disable CT32B0 PCLK
|
||||
#define __CT32B0_DISABLE SN_SYS1->AHBCLKEN_b.CT32B0CLKEN = DISABLE
|
||||
|
||||
/*_____ D E C L A R A T I O N S ____________________________________________*/
|
||||
extern volatile uint32_t iwCT32B0_IrqEvent; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS
|
||||
|
||||
extern void CT32B0_Init(void);
|
||||
extern void CT32B0_NvicEnable(void);
|
||||
extern void CT32B0_NvicDisable(void);
|
||||
#endif /*__SN32F240_CT32B0_H*/
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
/******************** (C) COPYRIGHT 2013 SONiX *******************************
|
||||
* COMPANY: SONiX
|
||||
* DATE: 2013/12
|
||||
* AUTHOR: SA1
|
||||
* IC: SN32F240/230/220
|
||||
* DESCRIPTION: CT32B1 related functions.
|
||||
*____________________________________________________________________________
|
||||
* REVISION Date User Description
|
||||
* 1.0 2013/12/17 SA1 First release
|
||||
*
|
||||
*____________________________________________________________________________
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
|
||||
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
|
||||
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
|
||||
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
|
||||
* IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*****************************************************************************/
|
||||
|
||||
/*_____ I N C L U D E S ____________________________________________________*/
|
||||
#include <SN32F240B.h>
|
||||
#include "CT32.h"
|
||||
#include "CT32B1.h"
|
||||
|
||||
|
||||
/*_____ D E C L A R A T I O N S ____________________________________________*/
|
||||
volatile uint32_t iwCT32B1_IrqEvent = 0x00; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS
|
||||
|
||||
void CT32B1_Init (void);
|
||||
void CT32B1_NvicEnable (void);
|
||||
void CT32B1_NvicDisable (void);
|
||||
|
||||
/*_____ D E F I N I T I O N S ______________________________________________*/
|
||||
|
||||
|
||||
/*_____ M A C R O S ________________________________________________________*/
|
||||
|
||||
|
||||
/*_____ F U N C T I O N S __________________________________________________*/
|
||||
|
||||
/*****************************************************************************
|
||||
* Function : CT32B1_Init
|
||||
* Description : Initialization of CT32B1 timer
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
void CT32B1_Init (void)
|
||||
{
|
||||
//Enable P_CLOCK for CT32B1.
|
||||
__CT32B1_ENABLE;
|
||||
|
||||
//CT32B1 PCLK prescalar setting
|
||||
SN_SYS1->APBCP0_b.CT32B1PRE = 0x00; //PCLK = HCLK/1
|
||||
//SN_SYS1->APBCP0_b.CT32B1PRE = 0x01; //PCLK = HCLK/2
|
||||
//SN_SYS1->APBCP0_b.CT32B1PRE = 0x02; //PCLK = HCLK/4
|
||||
//SN_SYS1->APBCP0_b.CT32B1PRE = 0x03; //PCLK = HCLK/8
|
||||
//SN_SYS1->APBCP0_b.CT32B1PRE = 0x04; //PCLK = HCLK/16
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Function : CT32B1_NvicEnable
|
||||
* Description : Enable CT32B1 timer interrupt
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
void CT32B1_NvicEnable (void)
|
||||
{
|
||||
NVIC_ClearPendingIRQ(CT32B1_IRQn);
|
||||
NVIC_EnableIRQ(CT32B1_IRQn);
|
||||
//NVIC_SetPriority(CT32B1_IRQn,0); //Set interrupt priority (default)
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Function : CT32B1_NvicDisable
|
||||
* Description : Disable CT32B1 timer interrupt
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
void CT32B1_NvicDisable (void)
|
||||
{
|
||||
NVIC_DisableIRQ(CT32B1_IRQn);
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Function : TIMER32_0_IRQHandler
|
||||
* Description : ISR of CT32B1 interrupt
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
__irq void CT32B1_IRQHandler(void)
|
||||
{
|
||||
uint32_t iwRisStatus;
|
||||
|
||||
iwRisStatus = SN_CT32B1->RIS; // Save the interrupt status.
|
||||
|
||||
//Before checking the status, always re-check the interrupt enable register first.
|
||||
//In practice, user might use only one or two timer interrupt source.
|
||||
//Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary.
|
||||
//User can add the directive pair of "#if 0" and "#endif" pair
|
||||
//to COMMENT the un-used parts to reduce ISR overheads and ROM usage.
|
||||
|
||||
//Check the status in oder.
|
||||
//MR0
|
||||
if (SN_CT32B1->MCTRL_b.MR0IE) //Check if MR0 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_MR0IF)
|
||||
{
|
||||
iwCT32B1_IrqEvent |= mskCT32_MR0IF;
|
||||
SN_CT32B1->IC = mskCT32_MR0IC; //Clear MR0 match interrupt status
|
||||
}
|
||||
}
|
||||
//MR1
|
||||
if (SN_CT32B1->MCTRL_b.MR1IE) //Check if MR1 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_MR1IF)
|
||||
{
|
||||
iwCT32B1_IrqEvent |= mskCT32_MR1IF;
|
||||
SN_CT32B1->IC = mskCT32_MR1IC; //Clear MR1 match interrupt status
|
||||
}
|
||||
}
|
||||
//MR2
|
||||
if (SN_CT32B1->MCTRL_b.MR2IE) //Check if MR2 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_MR2IF)
|
||||
{
|
||||
iwCT32B1_IrqEvent |= mskCT32_MR2IF;
|
||||
SN_CT32B1->IC = mskCT32_MR2IC; //Clear MR2 match interrupt status
|
||||
}
|
||||
}
|
||||
//MR3
|
||||
if (SN_CT32B1->MCTRL_b.MR3IE) //Check if MR3 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_MR3IF)
|
||||
{
|
||||
iwCT32B1_IrqEvent |= mskCT32_MR3IF;
|
||||
SN_CT32B1->IC = mskCT32_MR3IC; //Clear MR3 match interrupt status
|
||||
}
|
||||
}
|
||||
//CAP0
|
||||
if (SN_CT32B1->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_CAP0IF) //CAP0
|
||||
{
|
||||
iwCT32B1_IrqEvent |= mskCT32_CAP0IF;
|
||||
SN_CT32B1->IC = mskCT32_CAP0IC; //Clear CAP0 interrupt status
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
#ifndef __SN32F240_CT32B1_H
|
||||
#define __SN32F240_CT32B1_H
|
||||
|
||||
|
||||
/*_____ I N C L U D E S ____________________________________________________*/
|
||||
#include <stdint.h>
|
||||
#include <SN32F200_Def.h>
|
||||
|
||||
|
||||
/*_____ D E F I N I T I O N S ______________________________________________*/
|
||||
#define CT32B1_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT32B1 timer and interrupt
|
||||
//POLLING_METHOD: Enable CT32B1 timer ONLY
|
||||
|
||||
/*_____ M A C R O S ________________________________________________________*/
|
||||
// Enable CT32B1 PCLK
|
||||
#define __CT32B1_ENABLE SN_SYS1->AHBCLKEN_b.CT32B1CLKEN = ENABLE
|
||||
// Disable CT32B1 PCLK
|
||||
#define __CT32B1_DISABLE SN_SYS1->AHBCLKEN_b.CT32B1CLKEN = DISABLE
|
||||
|
||||
/*_____ D E C L A R A T I O N S ____________________________________________*/
|
||||
extern volatile uint32_t iwCT32B1_IrqEvent; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS
|
||||
|
||||
extern void CT32B1_Init(void);
|
||||
extern void CT32B1_NvicEnable(void);
|
||||
extern void CT32B1_NvicDisable(void);
|
||||
#endif /*__SN32F240_CT32B1_H*/
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
/******************** (C) COPYRIGHT 2013 SONiX *******************************
|
||||
* COMPANY: SONiX
|
||||
* DATE: 2013/12
|
||||
* AUTHOR: SA1
|
||||
* IC: SN32F240/230/220
|
||||
* DESCRIPTION: CT32B2 related functions.
|
||||
*____________________________________________________________________________
|
||||
* REVISION Date User Description
|
||||
* 1.0 2013/12/17 SA1 First release
|
||||
*
|
||||
*____________________________________________________________________________
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
|
||||
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
|
||||
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
|
||||
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
|
||||
* IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*****************************************************************************/
|
||||
|
||||
/*_____ I N C L U D E S ____________________________________________________*/
|
||||
#include <SN32F240B.h>
|
||||
#include "CT32.h"
|
||||
#include "CT32B2.h"
|
||||
|
||||
|
||||
/*_____ D E C L A R A T I O N S ____________________________________________*/
|
||||
volatile uint32_t iwCT32B2_IrqEvent = 0x00; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS
|
||||
|
||||
void CT32B2_Init (void);
|
||||
void CT32B2_NvicEnable (void);
|
||||
void CT32B2_NvicDisable (void);
|
||||
|
||||
/*_____ D E F I N I T I O N S ______________________________________________*/
|
||||
|
||||
|
||||
/*_____ M A C R O S ________________________________________________________*/
|
||||
|
||||
|
||||
/*_____ F U N C T I O N S __________________________________________________*/
|
||||
|
||||
/*****************************************************************************
|
||||
* Function : CT32B2_Init
|
||||
* Description : Initialization of CT32B2 timer
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
void CT32B2_Init (void)
|
||||
{
|
||||
//Enable P_CLOCK for CT32B2.
|
||||
__CT32B2_ENABLE;
|
||||
|
||||
//CT32B2 PCLK prescalar setting
|
||||
SN_SYS1->APBCP0_b.CT32B2PRE = 0x00; //PCLK = HCLK/1
|
||||
//SN_SYS1->APBCP0_b.CT32B2PRE = 0x01; //PCLK = HCLK/2
|
||||
//SN_SYS1->APBCP0_b.CT32B2PRE = 0x02; //PCLK = HCLK/4
|
||||
//SN_SYS1->APBCP0_b.CT32B2PRE = 0x03; //PCLK = HCLK/8
|
||||
//SN_SYS1->APBCP0_b.CT32B2PRE = 0x04; //PCLK = HCLK/16
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Function : CT32B2_NvicEnable
|
||||
* Description : Enable CT32B2 timer interrupt
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
void CT32B2_NvicEnable (void)
|
||||
{
|
||||
NVIC_ClearPendingIRQ(CT32B2_IRQn);
|
||||
NVIC_EnableIRQ(CT32B2_IRQn);
|
||||
//NVIC_SetPriority(CT32B2_IRQn,0); //Set interrupt priority (default)
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Function : CT32B2_NvicDisable
|
||||
* Description : Disable CT32B2 timer interrupt
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
void CT32B2_NvicDisable (void)
|
||||
{
|
||||
NVIC_DisableIRQ(CT32B2_IRQn);
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Function : TIMER32_0_IRQHandler
|
||||
* Description : ISR of CT32B2 interrupt
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
__irq void CT32B2_IRQHandler(void)
|
||||
{
|
||||
uint32_t iwRisStatus;
|
||||
|
||||
iwRisStatus = SN_CT32B2->RIS; // Save the interrupt status.
|
||||
|
||||
//Before checking the status, always re-check the interrupt enable register first.
|
||||
//In practice, user might use only one or two timer interrupt source.
|
||||
//Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary.
|
||||
//User can add the directive pair of "#if 0" and "#endif" pair
|
||||
//to COMMENT the un-used parts to reduce ISR overheads and ROM usage.
|
||||
|
||||
//Check the status in oder.
|
||||
//MR0
|
||||
if (SN_CT32B2->MCTRL_b.MR0IE) //Check if MR0 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_MR0IF)
|
||||
{
|
||||
iwCT32B2_IrqEvent |= mskCT32_MR0IF;
|
||||
SN_CT32B2->IC = mskCT32_MR0IC; //Clear MR0 match interrupt status
|
||||
}
|
||||
}
|
||||
//MR1
|
||||
if (SN_CT32B2->MCTRL_b.MR1IE) //Check if MR1 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_MR1IF)
|
||||
{
|
||||
iwCT32B2_IrqEvent |= mskCT32_MR1IF;
|
||||
SN_CT32B2->IC = mskCT32_MR1IC; //Clear MR1 match interrupt status
|
||||
}
|
||||
}
|
||||
//MR2
|
||||
if (SN_CT32B2->MCTRL_b.MR2IE) //Check if MR2 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_MR2IF)
|
||||
{
|
||||
iwCT32B2_IrqEvent |= mskCT32_MR2IF;
|
||||
SN_CT32B2->IC = mskCT32_MR2IC; //Clear MR2 match interrupt status
|
||||
}
|
||||
}
|
||||
//MR3
|
||||
if (SN_CT32B2->MCTRL_b.MR3IE) //Check if MR3 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_MR3IF)
|
||||
{
|
||||
iwCT32B2_IrqEvent |= mskCT32_MR3IF;
|
||||
SN_CT32B2->IC = mskCT32_MR3IC; //Clear MR3 match interrupt status
|
||||
}
|
||||
}
|
||||
//CAP0
|
||||
if (SN_CT32B2->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables?
|
||||
{
|
||||
if(iwRisStatus & mskCT32_CAP0IF) //CAP0
|
||||
{
|
||||
iwCT32B2_IrqEvent |= mskCT32_CAP0IF;
|
||||
SN_CT32B2->IC = mskCT32_CAP0IC; //Clear CAP0 interrupt status
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
#ifndef __SN32F240_CT32B2_H
|
||||
#define __SN32F240_CT32B2_H
|
||||
|
||||
|
||||
/*_____ I N C L U D E S ____________________________________________________*/
|
||||
#include <stdint.h>
|
||||
#include <SN32F200_Def.h>
|
||||
|
||||
|
||||
/*_____ D E F I N I T I O N S ______________________________________________*/
|
||||
#define CT32B2_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT32B2 timer and interrupt
|
||||
//POLLING_METHOD: Enable CT32B2 timer ONLY
|
||||
|
||||
/*_____ M A C R O S ________________________________________________________*/
|
||||
// Enable CT32B2 PCLK
|
||||
#define __CT32B2_ENABLE SN_SYS1->AHBCLKEN_b.CT32B2CLKEN = ENABLE
|
||||
// Disable CT32B2 PCLK
|
||||
#define __CT32B2_DISABLE SN_SYS1->AHBCLKEN_b.CT32B2CLKEN = DISABLE
|
||||
|
||||
/*_____ D E C L A R A T I O N S ____________________________________________*/
|
||||
extern volatile uint32_t iwCT32B2_IrqEvent; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS
|
||||
|
||||
extern void CT32B2_Init(void);
|
||||
extern void CT32B2_NvicEnable(void);
|
||||
extern void CT32B2_NvicDisable(void);
|
||||
#endif /*__SN32F240_CT32B2_H*/
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
/******************** (C) COPYRIGHT 2013 SONiX *******************************
|
||||
* COMPANY: SONiX
|
||||
* DATE: 2013/12
|
||||
* AUTHOR: SA1
|
||||
* IC: SN32F240/230/220
|
||||
* DESCRIPTION: SysTick related functions.
|
||||
*____________________________________________________________________________
|
||||
* REVISION Date User Description
|
||||
* 1.0 2013/12/17 SA1 First release
|
||||
*
|
||||
*____________________________________________________________________________
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
|
||||
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
|
||||
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
|
||||
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
|
||||
* IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*****************************************************************************/
|
||||
|
||||
/*_____ I N C L U D E S ____________________________________________________*/
|
||||
#include "SysTick.h"
|
||||
|
||||
|
||||
/*_____ D E C L A R A T I O N S ____________________________________________*/
|
||||
|
||||
|
||||
/*_____ D E F I N I T I O N S ______________________________________________*/
|
||||
|
||||
|
||||
/*_____ M A C R O S ________________________________________________________*/
|
||||
|
||||
|
||||
/*_____ F U N C T I O N S __________________________________________________*/
|
||||
/*****************************************************************************
|
||||
* Function : SysTick_Init
|
||||
* Description : Initialization of SysTick timer
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
void SysTick_Init (void)
|
||||
{
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
__SYSTICK_SET_TIMER_PERIOD(10); //RELOAD = (system tick clock frequency <20><> 10 ms)/1000 -1
|
||||
|
||||
__SYSTICK_CLEAR_COUNTER_AND_FLAG;
|
||||
|
||||
#if SYSTICK_IRQ == INTERRUPT_METHOD
|
||||
SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
|
||||
#else
|
||||
SysTick->CTRL = 0x5; //Enable SysTick timer ONLY
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Function : SysTick_Handler
|
||||
* Description : ISR of SysTick interrupt
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
* Note : None
|
||||
*****************************************************************************/
|
||||
// void SysTick_Handler(void)
|
||||
// {
|
||||
// __SYSTICK_CLEAR_COUNTER_AND_FLAG;
|
||||
// }
|
||||
|
||||
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
#ifndef __SN32F240_SYSTICK_H
|
||||
#define __SN32F240_SYSTICK_H
|
||||
|
||||
|
||||
/*_____ I N C L U D E S ____________________________________________________*/
|
||||
#include <SN32F240B.h>
|
||||
#include <SN32F200_Def.h>
|
||||
|
||||
|
||||
/*_____ D E F I N I T I O N S ______________________________________________*/
|
||||
#define SYSTICK_IRQ POLLING_METHOD //INTERRUPT_METHOD: Enable SysTick timer and interrupt
|
||||
//POLLING_METHOD: Enable SysTick timer ONLY
|
||||
|
||||
/*_____ M A C R O S ________________________________________________________*/
|
||||
#define __SYSTICK_SET_TIMER_PERIOD(ms) SysTick->LOAD = SystemCoreClock * ms /1000 - 1
|
||||
#define __SYSTICK_CLEAR_COUNTER_AND_FLAG SysTick->VAL = 0xFF
|
||||
|
||||
|
||||
|
||||
/*_____ D E C L A R A T I O N S ____________________________________________*/
|
||||
void SysTick_Init(void);
|
||||
|
||||
#endif /*__SN32F240_SYSTICK_H*/
|
||||
Loading…
Reference in New Issue