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USBH test corrections

This commit is contained in:
Diego Ismirlian 2018-09-02 11:59:32 -03:00
parent 2366ead14e
commit 8139109715
3 changed files with 11 additions and 9 deletions
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8
testhal/STM32/STM32F4xx/USB_HOST/chconf.h
View File

@ -49,7 +49,7 @@
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#define CH_CFG_ST_FREQUENCY 10000
#define CH_CFG_ST_FREQUENCY 1000
/**
* @brief Time intervals data size.
@ -71,7 +71,7 @@
* The value one is not valid, timeouts are rounded up to
* this value.
*/
#define CH_CFG_ST_TIMEDELTA 2
#define CH_CFG_ST_TIMEDELTA 0
/** @} */
@ -427,7 +427,7 @@
*
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
*/
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
/**
* @brief Trace buffer entries.
@ -586,6 +586,8 @@
*/
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
/* System halt code here.*/ \
void usbDbgSystemHalted(void); \
usbDbgSystemHalted(); \
}
/**

6
testhal/STM32/STM32F4xx/USB_HOST/halconf.h
View File

@ -41,7 +41,7 @@
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC TRUE
#define HAL_USE_ADC FALSE
#endif
/**
@ -323,7 +323,7 @@
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#define SERIAL_DEFAULT_BITRATE 115200
#endif
/**
@ -334,7 +334,7 @@
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#define SERIAL_BUFFERS_SIZE 64
#endif
/*===========================================================================*/

6
testhal/STM32/STM32F4xx/USB_HOST/mcuconf.h
View File

@ -86,9 +86,9 @@
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_ADC2 TRUE
#define STM32_ADC_USE_ADC3 TRUE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)