From 1021a7771fce7d85f444dd8b00d44c6a19e15434 Mon Sep 17 00:00:00 2001 From: Stefan Kerkmann Date: Sat, 3 Jul 2021 13:45:27 +0200 Subject: [PATCH 1/2] Rename missed AFIO register names --- os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c | 4 ++-- os/hal/ports/GD/GD32VF103/gd32vf103.h | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c b/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c index 1c18bf9c..3d0768d6 100644 --- a/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c +++ b/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c @@ -215,7 +215,7 @@ void _pal_lld_enablepadevent(ioportid_t port, portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU; /* Port selection in SYSCFG.*/ - AFIO->EXTICR[cridx] = (AFIO->EXTICR[cridx] & crmask) | (portidx << croff); + AFIO->EXTISS[cridx] = (AFIO->EXTISS[cridx] & crmask) | (portidx << croff); /* Programming edge registers.*/ if (mode & PAL_EVENT_MODE_RISING_EDGE) @@ -262,7 +262,7 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { 0x400 intervals in memory space. So far this is true for all devices.*/ portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU; - crport = (AFIO->EXTICR[cridx] >> croff) & 0xFU; + crport = (AFIO->EXTISS[cridx] >> croff) & 0xFU; osalDbgAssert(crport == portidx, "channel mapped on different port"); diff --git a/os/hal/ports/GD/GD32VF103/gd32vf103.h b/os/hal/ports/GD/GD32VF103/gd32vf103.h index 78de527a..1e2f895a 100644 --- a/os/hal/ports/GD/GD32VF103/gd32vf103.h +++ b/os/hal/ports/GD/GD32VF103/gd32vf103.h @@ -327,11 +327,11 @@ typedef struct typedef struct { - __IO uint32_t EVCR; - __IO uint32_t MAPR; - __IO uint32_t EXTICR[4]; + __IO uint32_t EC; + __IO uint32_t PCF0; + __IO uint32_t EXTISS[4]; uint32_t RESERVED0; - __IO uint32_t MAPR2; + __IO uint32_t PCF1; } AFIO_TypeDef; /** * @brief Inter Integrated Circuit Interface From 24ec55baa79ce6b76f65ef2dab8eee85e0dc703e Mon Sep 17 00:00:00 2001 From: Stefan Kerkmann Date: Sat, 3 Jul 2021 13:50:03 +0200 Subject: [PATCH 2/2] Free B4 pin on Longan Nano Board By default B4 has the JTAG NJRST signal with a pull up enabled. On the longan Nano this PIN is broken out as a regular pin. So we just disable NJRST by default and make it available as a regular GPIO. --- os/hal/boards/SIPEED_LONGAN_NANO/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/os/hal/boards/SIPEED_LONGAN_NANO/board.c b/os/hal/boards/SIPEED_LONGAN_NANO/board.c index 6bf05ce0..36a27cb5 100644 --- a/os/hal/boards/SIPEED_LONGAN_NANO/board.c +++ b/os/hal/boards/SIPEED_LONGAN_NANO/board.c @@ -44,4 +44,6 @@ void __early_init(void) { * Board-specific initialization code. */ void boardInit(void) { + /* Free B4 pin by disabling JTAG NJTRST. */ + AFIO->PCF0 |= AFIO_PCF0_SWJ_CFG_NOJNTRST; }