[KINETIS] Move I2C and ADC demo to proper subdir.
This commit is contained in:
flabbergast
parent
9f5d7fd40b
commit
82ada2bb21
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@ -70,6 +70,11 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
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USE_EXCEPTIONS_STACKSIZE = 0x400
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endif
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# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
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ifeq ($(USE_FPU),)
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USE_FPU = no
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endif
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#
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# Architecture or project specific options
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##############################################################################
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@ -82,14 +87,19 @@ endif
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PROJECT = ch
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# Imported source files and paths
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CHIBIOS = ../../..
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include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk
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CHIBIOS = ../../../../../ChibiOS-RT
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CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
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# Startup files.
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include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x5.mk
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# HAL-OSAL files (optional).
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include $(CHIBIOS)/os/hal/hal.mk
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include $(CHIBIOS)/os/hal/ports/KINETIS/K20x/platform.mk
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include $(CHIBIOS)/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk
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include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/K20x/platform.mk
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include $(CHIBIOS_CONTRIB)/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk
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include $(CHIBIOS)/os/hal/osal/rt/osal.mk
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# RTOS files (optional).
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include $(CHIBIOS)/os/rt/rt.mk
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include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
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# Other files (optional).
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# Define linker script file here
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LDSCRIPT= $(STARTUPLD)/MK20DX128.ld
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@ -27,6 +27,8 @@
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#ifndef _CHCONF_H_
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#define _CHCONF_H_
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#define _CHIBIOS_RT_CONF_
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/*===========================================================================*/
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/**
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@ -262,14 +264,6 @@
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*/
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#define CH_CFG_USE_MAILBOXES TRUE
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/**
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* @brief I/O Queues APIs.
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* @details If enabled then the I/O queues APIs are included in the kernel.
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*
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* @note The default is @p TRUE.
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*/
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#define CH_CFG_USE_QUEUES TRUE
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/**
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* @brief Core Memory Manager APIs.
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* @details If enabled then the core memory manager APIs are included
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@ -443,6 +437,20 @@
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#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
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/* Context switch code here.*/ \
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}
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/**
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* @brief ISR enter hook.
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*/
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#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
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/* IRQ prologue code here.*/ \
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}
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/**
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* @brief ISR exit hook.
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*/
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#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
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/* IRQ epilogue code here.*/ \
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}
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/**
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* @brief Idle thread enter hook.
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@ -487,6 +495,15 @@
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#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
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/* System halt code here.*/ \
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}
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/**
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* @brief Trace hook.
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* @details This hook is invoked each time a new record is written in the
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* trace buffer.
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*/
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#define CH_CFG_TRACE_HOOK(tep) { \
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/* Trace code here.*/ \
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}
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/** @} */
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@ -17,21 +17,7 @@
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#ifndef _MCUCONF_H_
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#define _MCUCONF_H_
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/*
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* STM32F0xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 3...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define KL2x_MCUCONF
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#define K20x_MCUCONF
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/*
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* HAL driver system settings.
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@ -39,32 +25,51 @@
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/* Select the MCU clocking mode below by enabling the appropriate block. */
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/* FEI mode */
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/* Enable clock initialization by HAL */
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#define KINETIS_NO_INIT FALSE
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/* PEE mode - external (8 MHz) crystal with PLL for 48 MHz core/system clock. */
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#if 1
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
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#define KINETIS_PLLCLK_FREQUENCY 96000000UL
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#define KINETIS_SYSCLK_FREQUENCY 48000000UL
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#endif
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/* FEI mode - 48 MHz with internal 32.768 kHz oscillator */
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#if 0
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
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#define KINETIS_SYSCLK_FREQUENCY 21000000UL
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#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
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#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
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#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
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#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide MCGCLKOUT (~48MHz) by 1 to SYSCLK */
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#define KINETIS_CLKDIV1_OUTDIV2 1 /* Divide by 1 for (~48MHz) peripheral clock */
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#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide by 2 for (~24MHz) flash clock */
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#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY
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#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2
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#endif /* 0 */
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/* FEE mode - 24 MHz with external 32.768 kHz crystal */
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/* not implemented */
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#if 0
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
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#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
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#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
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#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
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#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
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#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
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#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
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#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
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#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
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#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
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#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
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#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
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#endif /* 0 */
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/* FEE mode - 48 MHz */
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/* not implemented */
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#if 0
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
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#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
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#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
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#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
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#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
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#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
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#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
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#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
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#endif /* 0 */
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@ -72,10 +77,7 @@
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* SERIAL driver system settings.
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*/
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#define KINETIS_SERIAL_USE_UART0 FALSE
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/*
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* ADC driver system settings.
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*/
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#define KINETIS_ADC_USE_ADC0 TRUE
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#define KINETIS_I2C_USE_I2C0 TRUE
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#define KINETIS_I2C_I2C0_PRIORITY 8
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#endif /* _MCUCONF_H_ */
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@ -81,17 +81,19 @@ endif
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PROJECT = ch
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# Imported source files and paths
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CHIBIOS = ../../..
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include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
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CHIBIOS = ../../../../../ChibiOS-RT
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CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
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include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
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include $(CHIBIOS)/os/hal/hal.mk
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include $(CHIBIOS)/os/hal/ports/KINETIS/KL2x/platform.mk
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include $(CHIBIOS)/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk
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include $(CHIBIOS_CONTRIB)/os/hal/ports/KINETIS/KL2x/platform.mk
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include $(CHIBIOS_CONTRIB)/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk
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include $(CHIBIOS)/os/hal/osal/rt/osal.mk
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include $(CHIBIOS)/os/rt/rt.mk
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include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
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# Define linker script file here
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LDSCRIPT= $(STARTUPLD)/KL25Z128.ld
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LDSCRIPT= $(STARTUPLD)/MKL2xZ128.ld
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# C sources that can be compiled in ARM or THUMB mode depending on the global
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# setting.
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@ -27,6 +27,8 @@
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#ifndef _CHCONF_H_
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#define _CHCONF_H_
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#define _CHIBIOS_RT_CONF_
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/*===========================================================================*/
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/**
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@ -262,14 +264,6 @@
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*/
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#define CH_CFG_USE_MAILBOXES TRUE
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/**
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* @brief I/O Queues APIs.
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* @details If enabled then the I/O queues APIs are included in the kernel.
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*
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* @note The default is @p TRUE.
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*/
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#define CH_CFG_USE_QUEUES TRUE
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/**
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* @brief Core Memory Manager APIs.
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* @details If enabled then the core memory manager APIs are included
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@ -443,6 +437,20 @@
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#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
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/* Context switch code here.*/ \
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}
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/**
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* @brief ISR enter hook.
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*/
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#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
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/* IRQ prologue code here.*/ \
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}
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/**
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* @brief ISR exit hook.
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*/
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#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
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/* IRQ epilogue code here.*/ \
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}
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/**
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* @brief Idle thread enter hook.
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@ -487,6 +495,15 @@
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#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
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/* System halt code here.*/ \
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}
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/**
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* @brief Trace hook.
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* @details This hook is invoked each time a new record is written in the
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* trace buffer.
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*/
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#define CH_CFG_TRACE_HOOK(tep) { \
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/* Trace code here.*/ \
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}
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/** @} */
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@ -17,30 +17,29 @@
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#ifndef _MCUCONF_H_
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#define _MCUCONF_H_
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#define K20x_MCUCONF
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#define KL2x_MCUCONF
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/*
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* HAL driver system settings.
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*/
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/* Select the MCU clocking mode below by enabling the appropriate block. */
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/* The defaults are MCG_MODE_PEE, SYSCLK 48MHz, PLLCLK 96MHz, BUSCLK 24MHz */
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/* Enable clock initialization by HAL */
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#define KINETIS_NO_INIT FALSE
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/* PEE mode - external 8 MHz crystal with PLL for 48 MHz core/system clock. */
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/* PEE mode - 48MHz system clock driven by external crystal. */
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#if 1
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
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#define KINETIS_XTAL_FREQUENCY 8000000UL
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#define KINETIS_PLLCLK_FREQUENCY 96000000UL
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#define KINETIS_SYSCLK_FREQUENCY 48000000UL
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#endif
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/* FEI mode - 48 MHz with internal 32.768 kHz oscillator */
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/* crystal-less FEI mode - 48 MHz with internal 32.768 kHz crystal */
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#if 0
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
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#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
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#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
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#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
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#define KINETIS_CLKDIV1_OUTDIV1 1 /* do not divide system clock */
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#endif /* 0 */
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/* FEE mode - 24 MHz with external 32.768 kHz crystal */
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@ -48,12 +47,12 @@
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
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#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
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#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
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#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
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#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
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#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
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#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
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#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
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#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
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#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
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#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
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#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
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#endif /* 0 */
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/* FEE mode - 48 MHz */
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@ -61,8 +60,8 @@
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
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#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
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#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
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#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
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#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
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#define KINETIS_CLKDIV1_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
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#define KINETIS_CLKDIV1_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
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#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
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#endif /* 0 */
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@ -70,7 +69,10 @@
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* SERIAL driver system settings.
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*/
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#define KINETIS_SERIAL_USE_UART0 FALSE
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#define KINETIS_I2C_USE_I2C0 TRUE
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#define KINETIS_I2C_I2C0_PRIORITY 8
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/*
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* ADC driver system settings.
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*/
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#define KINETIS_ADC_USE_ADC0 TRUE
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#endif /* _MCUCONF_H_ */
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