Fabio Utzig
GitHub
commit
8306aabdfc
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@ -92,7 +92,7 @@ CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
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include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk
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# HAL-OSAL files (optional).
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include $(CHIBIOS)/os/hal/hal.mk
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include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF51/NRF51822/platform.mk
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include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF5/NRF51822/platform.mk
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include $(CHIBIOS_CONTRIB)/os/hal/boards/OSHCHIP_V1.0/board.mk
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include $(CHIBIOS)/os/hal/osal/rt/osal.mk
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# RTOS files (optional).
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@ -92,7 +92,7 @@ CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
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include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk
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# HAL-OSAL files (optional).
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include $(CHIBIOS)/os/hal/hal.mk
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include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF51/NRF51822/platform.mk
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include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF5/NRF51822/platform.mk
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include $(CHIBIOS_CONTRIB)/os/hal/boards/WVSHARE_BLE400/board.mk
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include $(CHIBIOS)/os/hal/osal/rt/osal.mk
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# RTOS files (optional).
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@ -8,4 +8,4 @@ BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF51-DK
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JLINK_DEVICE = nrf51422
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JLINK_PRE_FLASH = w4 4001e504 1
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JLINK_ERASE_ALL = w4 4001e504 2\nw4 4001e50c 1\nsleep 100
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JLINK_PIN_RESET = w4 40000544 1
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@ -6,10 +6,10 @@
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* nrf51 from Nordic Semiconductor.
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*
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* @version V522
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* @date 26. January 2015
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* @date 23. February 2016
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*
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* @note Generated with SVDConv V2.81d
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* from CMSIS SVD File 'nrf51.xml' Version 522,
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* from CMSIS SVD File 'nrf51.svd' Version 522,
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*
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* @par Copyright (c) 2013, Nordic Semiconductor ASA
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* All rights reserved.
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@ -293,27 +293,6 @@ typedef struct { /*!< MPU Structure
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} NRF_MPU_Type;
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/* ================================================================================ */
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/* ================ PU ================ */
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/* ================================================================================ */
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/**
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* @brief Patch unit. (PU)
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*/
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typedef struct { /*!< PU Structure */
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__I uint32_t RESERVED0[448];
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__IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
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__I uint32_t RESERVED1[24];
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__IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
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__I uint32_t RESERVED2[24];
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__IO uint32_t PATCHEN; /*!< Patch enable register. */
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__IO uint32_t PATCHENSET; /*!< Patch enable register. */
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__IO uint32_t PATCHENCLR; /*!< Patch disable register. */
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} NRF_PU_Type;
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/* ================================================================================ */
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/* ================ AMLI ================ */
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/* ================================================================================ */
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@ -367,11 +346,11 @@ typedef struct { /*!< RADIO Structure
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__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
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__I uint32_t RESERVED4[61];
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__I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
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__I uint32_t CD; /*!< Carrier detect. */
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__I uint32_t RESERVED5;
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__I uint32_t RXMATCH; /*!< Received address. */
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__I uint32_t RXCRC; /*!< Received CRC. */
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__I uint32_t DAI; /*!< Device address match index. */
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__I uint32_t RESERVED5[60];
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__I uint32_t RESERVED6[60];
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__IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
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__IO uint32_t FREQUENCY; /*!< Frequency. */
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__IO uint32_t TXPOWER; /*!< Output power. */
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@ -390,22 +369,22 @@ typedef struct { /*!< RADIO Structure
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__IO uint32_t TEST; /*!< Test features enable register. */
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__IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
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__I uint32_t RSSISAMPLE; /*!< RSSI sample. */
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__I uint32_t RESERVED6;
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__I uint32_t RESERVED7;
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__I uint32_t STATE; /*!< Current radio state. */
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__IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
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__I uint32_t RESERVED7[2];
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__I uint32_t RESERVED8[2];
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__IO uint32_t BCC; /*!< Bit counter compare. */
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__I uint32_t RESERVED8[39];
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__I uint32_t RESERVED9[39];
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__IO uint32_t DAB[8]; /*!< Device address base segment. */
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__IO uint32_t DAP[8]; /*!< Device address prefix. */
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__IO uint32_t DACNF; /*!< Device address match configuration. */
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__I uint32_t RESERVED9[56];
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__I uint32_t RESERVED10[56];
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__IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
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__IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
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__IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
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__IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
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__IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
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__I uint32_t RESERVED10[561];
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__I uint32_t RESERVED11[561];
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__IO uint32_t POWER; /*!< Peripheral power control. */
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} NRF_RADIO_Type;
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@ -564,39 +543,41 @@ typedef struct { /*!< SPIS Structure
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__O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
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__I uint32_t RESERVED1[54];
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__IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
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__I uint32_t RESERVED2[8];
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__I uint32_t RESERVED2[2];
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__IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
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__I uint32_t RESERVED3[5];
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__IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
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__I uint32_t RESERVED3[53];
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__I uint32_t RESERVED4[53];
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__IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
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__I uint32_t RESERVED4[64];
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__I uint32_t RESERVED5[64];
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__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
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__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
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__I uint32_t RESERVED5[61];
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__I uint32_t RESERVED6[61];
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__I uint32_t SEMSTAT; /*!< Semaphore status. */
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__I uint32_t RESERVED6[15];
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__I uint32_t RESERVED7[15];
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__IO uint32_t STATUS; /*!< Status from last transaction. */
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__I uint32_t RESERVED7[47];
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__I uint32_t RESERVED8[47];
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__IO uint32_t ENABLE; /*!< Enable SPIS. */
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__I uint32_t RESERVED8;
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__I uint32_t RESERVED9;
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__IO uint32_t PSELSCK; /*!< Pin select for SCK. */
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__IO uint32_t PSELMISO; /*!< Pin select for MISO. */
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__IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
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__IO uint32_t PSELCSN; /*!< Pin select for CSN. */
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__I uint32_t RESERVED9[7];
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__I uint32_t RESERVED10[7];
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__IO uint32_t RXDPTR; /*!< RX data pointer. */
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__IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
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__I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
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__I uint32_t RESERVED10;
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__I uint32_t RESERVED11;
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__IO uint32_t TXDPTR; /*!< TX data pointer. */
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__IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
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__I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
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__I uint32_t RESERVED11;
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__IO uint32_t CONFIG; /*!< Configuration register. */
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__I uint32_t RESERVED12;
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__IO uint32_t CONFIG; /*!< Configuration register. */
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__I uint32_t RESERVED13;
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__IO uint32_t DEF; /*!< Default character. */
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__I uint32_t RESERVED13[24];
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__I uint32_t RESERVED14[24];
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__IO uint32_t ORC; /*!< Over-read character. */
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__I uint32_t RESERVED14[654];
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__I uint32_t RESERVED15[654];
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__IO uint32_t POWER; /*!< Peripheral power control. */
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} NRF_SPIS_Type;
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@ -621,32 +602,28 @@ typedef struct { /*!< SPIM Structure
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__IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
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__I uint32_t RESERVED3[2];
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__IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
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__I uint32_t RESERVED4;
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__IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
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__I uint32_t RESERVED5;
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__I uint32_t RESERVED4[3];
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__IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
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__I uint32_t RESERVED6[10];
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__I uint32_t RESERVED5[10];
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__IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
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__I uint32_t RESERVED7[44];
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__IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
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__I uint32_t RESERVED8[64];
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__I uint32_t RESERVED6[109];
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__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
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__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
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__I uint32_t RESERVED9[125];
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__I uint32_t RESERVED7[125];
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__IO uint32_t ENABLE; /*!< Enable SPIM. */
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__I uint32_t RESERVED10;
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__I uint32_t RESERVED8;
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SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
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__I uint32_t RESERVED11[4];
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__I uint32_t RESERVED9[4];
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__IO uint32_t FREQUENCY; /*!< SPI frequency. */
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__I uint32_t RESERVED12[3];
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__I uint32_t RESERVED10[3];
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SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
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__I uint32_t RESERVED13;
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__I uint32_t RESERVED11;
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SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
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__I uint32_t RESERVED14;
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__I uint32_t RESERVED12;
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__IO uint32_t CONFIG; /*!< Configuration register. */
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__I uint32_t RESERVED15[26];
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__I uint32_t RESERVED13[26];
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__IO uint32_t ORC; /*!< Over-read character. */
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__I uint32_t RESERVED16[654];
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__I uint32_t RESERVED14[654];
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__IO uint32_t POWER; /*!< Peripheral power control. */
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} NRF_SPIM_Type;
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@ -889,8 +866,8 @@ typedef struct { /*!< AAR Structure
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__IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
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__I uint32_t RESERVED5;
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__IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
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__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
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during resolution. A minimum of 3 bytes must be reserved. */
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__IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
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resolution. A minimum of 3 bytes must be reserved. */
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__I uint32_t RESERVED6[697];
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__IO uint32_t POWER; /*!< Peripheral power control. */
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} NRF_AAR_Type;
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@ -928,8 +905,8 @@ typedef struct { /*!< CCM Structure
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__IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
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__IO uint32_t INPTR; /*!< Pointer to the input packet. */
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__IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
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__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
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during resolution. A minimum of 43 bytes must be reserved. */
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__IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
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resolution. A minimum of 43 bytes must be reserved. */
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__I uint32_t RESERVED5[697];
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__IO uint32_t POWER; /*!< Peripheral power control. */
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} NRF_CCM_Type;
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@ -1083,11 +1060,7 @@ typedef struct { /*!< NVMC Structure
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__IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
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};
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__IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
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union {
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__IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
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__IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
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};
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__IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
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} NRF_NVMC_Type;
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@ -1229,7 +1202,6 @@ typedef struct { /*!< GPIO Structure
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#define NRF_POWER_BASE 0x40000000UL
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#define NRF_CLOCK_BASE 0x40000000UL
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#define NRF_MPU_BASE 0x40000000UL
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#define NRF_PU_BASE 0x40000000UL
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#define NRF_AMLI_BASE 0x40000000UL
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#define NRF_RADIO_BASE 0x40001000UL
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#define NRF_UART0_BASE 0x40002000UL
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@ -1269,7 +1241,6 @@ typedef struct { /*!< GPIO Structure
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#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
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#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
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#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
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#define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
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#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
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#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
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#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
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@ -4596,186 +4596,6 @@
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#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
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/* Peripheral: PU */
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/* Description: Patch unit. */
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/* Register: PU_PATCHADDR */
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/* Description: Relative address of patch instructions. */
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/* Bits 24..0 : Relative address of patch instructions. */
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#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
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#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
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/* Register: PU_PATCHEN */
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/* Description: Patch enable register. */
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/* Bit 7 : Patch 7 enabled. */
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#define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
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#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
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#define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
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#define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
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/* Bit 6 : Patch 6 enabled. */
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#define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
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#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
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#define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
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#define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
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/* Bit 5 : Patch 5 enabled. */
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#define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
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#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
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#define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
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#define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
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/* Bit 4 : Patch 4 enabled. */
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#define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
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#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
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#define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
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#define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
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/* Bit 3 : Patch 3 enabled. */
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#define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
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#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
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#define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
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#define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
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/* Bit 2 : Patch 2 enabled. */
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#define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
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#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
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#define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
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#define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
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/* Bit 1 : Patch 1 enabled. */
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#define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
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#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
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#define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
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#define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
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/* Bit 0 : Patch 0 enabled. */
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#define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
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#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
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#define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
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#define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
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/* Register: PU_PATCHENSET */
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/* Description: Patch enable register. */
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/* Bit 7 : Patch 7 enabled. */
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#define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
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#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
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#define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
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#define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
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#define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
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/* Bit 6 : Patch 6 enabled. */
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#define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
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#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
|
||||
#define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
|
||||
|
||||
/* Bit 5 : Patch 5 enabled. */
|
||||
#define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
|
||||
#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
|
||||
#define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
|
||||
|
||||
/* Bit 4 : Patch 4 enabled. */
|
||||
#define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
|
||||
#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
|
||||
#define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
|
||||
|
||||
/* Bit 3 : Patch 3 enabled. */
|
||||
#define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
|
||||
#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
|
||||
#define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
|
||||
|
||||
/* Bit 2 : Patch 2 enabled. */
|
||||
#define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
|
||||
#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
|
||||
#define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
|
||||
|
||||
/* Bit 1 : Patch 1 enabled. */
|
||||
#define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
|
||||
#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
|
||||
#define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
|
||||
|
||||
/* Bit 0 : Patch 0 enabled. */
|
||||
#define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
|
||||
#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
|
||||
#define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
|
||||
|
||||
/* Register: PU_PATCHENCLR */
|
||||
/* Description: Patch disable register. */
|
||||
|
||||
/* Bit 7 : Patch 7 enabled. */
|
||||
#define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
|
||||
#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
|
||||
#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
|
||||
|
||||
/* Bit 6 : Patch 6 enabled. */
|
||||
#define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
|
||||
#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
|
||||
#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
|
||||
|
||||
/* Bit 5 : Patch 5 enabled. */
|
||||
#define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
|
||||
#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
|
||||
#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
|
||||
|
||||
/* Bit 4 : Patch 4 enabled. */
|
||||
#define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
|
||||
#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
|
||||
#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
|
||||
|
||||
/* Bit 3 : Patch 3 enabled. */
|
||||
#define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
|
||||
#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
|
||||
#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
|
||||
|
||||
/* Bit 2 : Patch 2 enabled. */
|
||||
#define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
|
||||
#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
|
||||
#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
|
||||
|
||||
/* Bit 1 : Patch 1 enabled. */
|
||||
#define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
|
||||
#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
|
||||
#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
|
||||
|
||||
/* Bit 0 : Patch 0 enabled. */
|
||||
#define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
|
||||
#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
|
||||
#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
|
||||
#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
|
||||
#define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
|
||||
|
||||
|
||||
/* Peripheral: QDEC */
|
||||
/* Description: Rotary decoder. */
|
||||
|
||||
|
|
@ -5132,13 +4952,6 @@
|
|||
#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
|
||||
#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
|
||||
|
||||
/* Register: RADIO_CD */
|
||||
/* Description: Carrier detect. */
|
||||
|
||||
/* Bit 0 : Carrier detect. */
|
||||
#define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */
|
||||
#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */
|
||||
|
||||
/* Register: RADIO_RXMATCH */
|
||||
/* Description: Received address. */
|
||||
|
||||
|
|
@ -5960,15 +5773,6 @@
|
|||
/* Peripheral: SPIM */
|
||||
/* Description: SPI master with easyDMA 1. */
|
||||
|
||||
/* Register: SPIM_SHORTS */
|
||||
/* Description: Shortcuts for SPIM. */
|
||||
|
||||
/* Bit 17 : Shortcut between END event and START task. */
|
||||
#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
|
||||
#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
|
||||
#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
|
||||
#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
|
||||
|
||||
/* Register: SPIM_INTENSET */
|
||||
/* Description: Interrupt enable set register. */
|
||||
|
||||
|
|
@ -5986,13 +5790,6 @@
|
|||
#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
|
||||
#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */
|
||||
|
||||
/* Bit 6 : Enable interrupt on END event. */
|
||||
#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
|
||||
#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
|
||||
#define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
|
||||
#define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
|
||||
#define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
|
||||
|
||||
/* Bit 4 : Enable interrupt on ENDRX event. */
|
||||
#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
|
||||
#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
|
||||
|
|
@ -6024,13 +5821,6 @@
|
|||
#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
|
||||
#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */
|
||||
|
||||
/* Bit 6 : Disable interrupt on END event. */
|
||||
#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
|
||||
#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
|
||||
#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
|
||||
#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
|
||||
#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
|
||||
|
||||
/* Bit 4 : Disable interrupt on ENDRX event. */
|
||||
#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
|
||||
#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
|
||||
|
|
@ -6170,6 +5960,13 @@
|
|||
#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
|
||||
#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
|
||||
|
||||
/* Bit 4 : enable interrupt on ENDRX event. */
|
||||
#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
|
||||
#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
|
||||
#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
|
||||
#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
|
||||
#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
|
||||
|
||||
/* Bit 1 : Enable interrupt on END event. */
|
||||
#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
|
||||
#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
|
||||
|
|
@ -6187,6 +5984,13 @@
|
|||
#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
|
||||
#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
|
||||
|
||||
/* Bit 4 : Disable interrupt on ENDRX event. */
|
||||
#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
|
||||
#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
|
||||
#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
|
||||
#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
|
||||
#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
|
||||
|
||||
/* Bit 1 : Disable interrupt on END event. */
|
||||
#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
|
||||
#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
|
||||
|
|
@ -6678,13 +6482,13 @@
|
|||
/* Register: UART_SHORTS */
|
||||
/* Description: Shortcuts for UART. */
|
||||
|
||||
/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
|
||||
/* Bit 4 : Shortcut between NCTS event and STOPRX task. */
|
||||
#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
|
||||
#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
|
||||
#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
|
||||
#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
|
||||
|
||||
/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
|
||||
/* Bit 3 : Shortcut between CTS event and STARTRX task. */
|
||||
#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
|
||||
#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
|
||||
#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
ifeq ($(USE_SMART_BUILD),yes)
|
||||
HALCONF := $(strip $(shell cat halconf.h halconf_community.h 2>/dev/null | egrep -e "define"))
|
||||
|
||||
# List of all the NRF51x platform files.
|
||||
PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_st_lld.c
|
||||
|
||||
ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_pal_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_serial_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_spi_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_i2c_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_gpt_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_wdg_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_rng_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_qei_lld.c
|
||||
endif
|
||||
else
|
||||
PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_pal_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_serial_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_st_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_spi_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld_isr.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_ext_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_i2c_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_adc_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_gpt_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_wdg_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_rng_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_pwm_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822/hal_qei_lld.c
|
||||
endif
|
||||
|
||||
# Required include directories
|
||||
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF5/NRF51822
|
||||
|
||||
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
ifeq ($(USE_SMART_BUILD),yes)
|
||||
HALCONF := $(strip $(shell cat halconf.h halconf_community.h 2>/dev/null | egrep -e "define"))
|
||||
|
||||
# List of all the NRF51x platform files.
|
||||
PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_st_lld.c
|
||||
|
||||
ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_pal_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_serial_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_spi_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_ext_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_adc_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_RNG TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_rng_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c
|
||||
endif
|
||||
ifneq ($(findstring HAL_USE_QEI TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_qei_lld.c
|
||||
endif
|
||||
else
|
||||
PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_pal_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_serial_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_st_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_spi_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_ext_lld_isr.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_ext_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_i2c_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_adc_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_gpt_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_wdg_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_rng_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_pwm_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822/hal_qei_lld.c
|
||||
endif
|
||||
|
||||
# Required include directories
|
||||
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/NRF51/NRF51822
|
||||
|
||||
|
||||
Loading…
Reference in New Issue