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Finished memtest code

This commit is contained in:
barthess 2015-02-24 17:43:53 +03:00
parent 33f1b2541e
commit 900963482d
4 changed files with 61 additions and 41 deletions
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4
os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
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@ -591,7 +591,7 @@
PIN_PUPDR_FLOATING(GPIOD_MEM_OE) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_WE) | \
NAND_RB_NWAIT_PUPDR(GPIOD_NAND_RB_NWAIT) | \
PIN_PUPDR_FLOATING(GPIOD_NAND_CE1) | \
PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_D13) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_D14) | \
PIN_PUPDR_FLOATING(GPIOD_MEM_D15) | \
@ -899,7 +899,7 @@
NAND_RB1_PUPDR(GPIOG_NAND_RB1) | \
PIN_PUPDR_FLOATING(GPIOG_NAND_RB2) | \
PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
PIN_PUPDR_FLOATING(GPIOG_NAND_CE2) | \
PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \
PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
PIN_PUPDR_FLOATING(GPIOG_SRAM_CS1) | \

26
testhal/STM32/STM32F4xx/FSMC_SRAM/main.c
View File

@ -26,8 +26,8 @@
* DEFINES
******************************************************************************
*/
#define SRAM_START ((void *)FSMC_Bank1_4_MAP)
#define SRAM_SIZE (512 * 1024)
#define SRAM_START ((void *)FSMC_Bank1_4_MAP)
/*
******************************************************************************
@ -49,11 +49,18 @@ static void mem_error_cb(memtest_t *memp, testtype_t e, size_t address);
******************************************************************************
*/
static size_t errors = 0;
/*
*
*/
static uint8_t int_buf[64*1024];
/*
* SRAM driver configuration structure.
*/
static const SRAMConfig sram_cfg = {
2 << 8
(0 << 16) | (2 << 8) | (1 << 0)
};
/*
@ -75,11 +82,6 @@ static membench_t membench_ext = {
SRAM_SIZE,
};
/*
*
*/
static uint8_t int_buf[64*1024];
/*
*
*/
@ -108,13 +110,15 @@ static inline void green_led_on(void) {palSetPad(GPIOI, GPIOI_LED_G);}
static inline void green_led_off(void) {palClearPad(GPIOI, GPIOI_LED_G);}
static inline void green_led_toggle(void) {palTogglePad(GPIOI, GPIOI_LED_G);}
static void mem_error_cb(memtest_t *memp, testtype_t e, size_t address) {
void mem_error_cb(memtest_t *memp, testtype_t e, size_t address) {
(void)memp;
(void)e;
(void)address;
green_led_off();
red_led_on();
osalThreadSleepMilliseconds(10);
errors++;
osalSysHalt("Memory broken");
}
@ -126,14 +130,8 @@ static void memtest(void) {
red_led_off();
while (true) {
memtest_struct.width = MEMTEST_WIDTH_16;
memtest_struct.rand_seed = chSysGetRealtimeCounterX();
memtest_run(&memtest_struct, MEMTEST_RUN_ALL);
memtest_struct.width = MEMTEST_WIDTH_8;
memtest_struct.rand_seed = chSysGetRealtimeCounterX();
memtest_run(&memtest_struct, MEMTEST_RUN_ALL);
green_led_toggle();
}

64
testhal/STM32/STM32F4xx/FSMC_SRAM/memtest.cpp
View File

@ -82,18 +82,21 @@ template <typename T>
class GeneratorMovingInvRand : public Generator<T> {
public:
GeneratorMovingInvRand(void) : step(0), prev(0){;}
void init(size_t seed) {
void init(T seed) {
srand(seed);
step = 0;
prev = 0;
}
T get(void) {
T ret;
T mask = -1;
if ((step & 1) == 0) {
ret = rand();
ret = rand() & mask;
prev = ret;
}
else {
ret = ~prev;
ret = ~prev & mask;
}
step++;
@ -116,9 +119,8 @@ static void memtest_sequential(memtest_t *memp, Generator<T> &generator, T seed)
/* fill ram */
generator.init(seed);
for (i=0; i<steps; i++) {
for (i=0; i<steps; i++)
mem[i] = generator.get();
}
/* read back and compare */
generator.init(seed);
@ -149,15 +151,26 @@ static void own_address(memtest_t *memp) {
}
template <typename T>
static void moving_inversion(memtest_t *memp) {
static void moving_inversion_zero(memtest_t *memp) {
GeneratorMovingInv<T> generator;
T mask = -1;
memtest_sequential<T>(memp, generator, 0);
memtest_sequential<T>(memp, generator, 0xFFFFFFFF & mask);
}
template <typename T>
static void moving_inversion_55aa(memtest_t *memp) {
GeneratorMovingInv<T> generator;
T mask = -1;
memtest_sequential<T>(memp, generator, 0x55555555 & mask);
memtest_sequential<T>(memp, generator, 0xAAAAAAAA & mask);
}
template <typename T>
static void moving_inversion_rand(memtest_t *memp) {
GeneratorMovingInvRand<T> generator;
memtest_sequential<T>(memp, generator, memp->rand_seed);
T mask = -1;
memtest_sequential<T>(memp, generator, memp->rand_seed & mask);
}
/*
@ -169,13 +182,13 @@ static void memtest_wrapper(memtest_t *memp,
void (*p_u32)(memtest_t *memp)) {
switch(memp->width){
case MEMTEST_WIDTH_32:
p_u32(memp);
p_u16(memp);
p_u8(memp);
p_u16(memp);
p_u32(memp);
break;
case MEMTEST_WIDTH_16:
p_u16(memp);
p_u8(memp);
p_u16(memp);
break;
case MEMTEST_WIDTH_8:
p_u8(memp);
@ -190,37 +203,44 @@ void memtest_run(memtest_t *memp, uint32_t testmask) {
if ((testmask & MEMTEST_WALKING_ONE) == MEMTEST_WALKING_ONE) {
memtest_wrapper(memp,
walking_one<uint32_t>,
walking_one<uint8_t>,
walking_one<uint16_t>,
walking_one<uint8_t>);
walking_one<uint32_t>);
}
if ((testmask & MEMTEST_WALKING_ZERO) == MEMTEST_WALKING_ZERO) {
memtest_wrapper(memp,
walking_zero<uint32_t>,
walking_zero<uint8_t>,
walking_zero<uint16_t>,
walking_zero<uint8_t>);
walking_zero<uint32_t>);
}
if ((testmask & MEMTEST_OWN_ADDRESS) == MEMTEST_OWN_ADDRESS) {
memtest_wrapper(memp,
own_address<uint32_t>,
own_address<uint8_t>,
own_address<uint16_t>,
own_address<uint8_t>);
own_address<uint32_t>);
}
if ((testmask & MEMTEST_MOVING_INVERSION) == MEMTEST_MOVING_INVERSION) {
if ((testmask & MEMTEST_MOVING_INVERSION_ZERO) == MEMTEST_MOVING_INVERSION_ZERO) {
memtest_wrapper(memp,
moving_inversion<uint32_t>,
moving_inversion<uint16_t>,
moving_inversion<uint8_t>);
moving_inversion_zero<uint8_t>,
moving_inversion_zero<uint16_t>,
moving_inversion_zero<uint32_t>);
}
if ((testmask & MEMTEST_MOVING_INVERSION_55AA) == MEMTEST_MOVING_INVERSION_55AA) {
memtest_wrapper(memp,
moving_inversion_55aa<uint8_t>,
moving_inversion_55aa<uint16_t>,
moving_inversion_55aa<uint32_t>);
}
if ((testmask & MEMTEST_MOVING_INVERSION_RAND) == MEMTEST_MOVING_INVERSION_RAND) {
memtest_wrapper(memp,
moving_inversion_rand<uint32_t>,
moving_inversion_rand<uint8_t>,
moving_inversion_rand<uint16_t>,
moving_inversion_rand<uint8_t>);
moving_inversion_rand<uint32_t>);
}
}

8
testhal/STM32/STM32F4xx/FSMC_SRAM/memtest.hpp
View File

@ -4,13 +4,15 @@
#define MEMTEST_WALKING_ONE (1 << 0)
#define MEMTEST_WALKING_ZERO (1 << 1)
#define MEMTEST_OWN_ADDRESS (1 << 2)
#define MEMTEST_MOVING_INVERSION (1 << 3)
#define MEMTEST_MOVING_INVERSION_RAND (1 << 4)
#define MEMTEST_MOVING_INVERSION_ZERO (1 << 3)
#define MEMTEST_MOVING_INVERSION_55AA (1 << 4)
#define MEMTEST_MOVING_INVERSION_RAND (1 << 5)
#define MEMTEST_RUN_ALL (MEMTEST_WALKING_ONE | \
MEMTEST_WALKING_ZERO | \
MEMTEST_OWN_ADDRESS | \
MEMTEST_MOVING_INVERSION | \
MEMTEST_MOVING_INVERSION_ZERO | \
MEMTEST_MOVING_INVERSION_55AA | \
MEMTEST_MOVING_INVERSION_RAND)
typedef struct memtest_t memtest_t;