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Rename DMA2 -> DMA1 and channels to start at zero

This commit is contained in:
Stefan Kerkmann 2021-03-20 23:47:28 +01:00
parent 161449d7c3
commit 92646d6824
7 changed files with 163 additions and 165 deletions
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118
os/hal/ports/GD/GD32VF103/DMA/gd32_dma.c
View File

@ -45,9 +45,9 @@
#define GD32_DMA0_STREAMS_MASK ((1U << GD32_DMA0_NUM_CHANNELS) - 1U) #define GD32_DMA0_STREAMS_MASK ((1U << GD32_DMA0_NUM_CHANNELS) - 1U)
/** /**
* @brief Mask of the DMA2 streams in @p dma_streams_mask. * @brief Mask of the DMA1 streams in @p dma_streams_mask.
*/ */
#define GD32_DMA2_STREAMS_MASK (((1U << GD32_DMA2_NUM_CHANNELS) - \ #define GD32_DMA1_STREAMS_MASK (((1U << GD32_DMA1_NUM_CHANNELS) - \
1U) << GD32_DMA0_NUM_CHANNELS) 1U) << GD32_DMA0_NUM_CHANNELS)
#define DMA0_CH0_VARIANT 0 #define DMA0_CH0_VARIANT 0
@ -57,13 +57,11 @@
#define DMA0_CH4_VARIANT 0 #define DMA0_CH4_VARIANT 0
#define DMA0_CH5_VARIANT 0 #define DMA0_CH5_VARIANT 0
#define DMA0_CH6_VARIANT 0 #define DMA0_CH6_VARIANT 0
#define DMA2_CH1_VARIANT 0 #define DMA1_CH0_VARIANT 0
#define DMA2_CH2_VARIANT 0 #define DMA1_CH1_VARIANT 0
#define DMA2_CH3_VARIANT 0 #define DMA1_CH2_VARIANT 0
#define DMA2_CH4_VARIANT 0 #define DMA1_CH3_VARIANT 0
#define DMA2_CH5_VARIANT 0 #define DMA1_CH4_VARIANT 0
#define DMA2_CH6_VARIANT 0
#define DMA2_CH7_VARIANT 0
/* /*
* Default ISR collision masks. * Default ISR collision masks.
@ -96,24 +94,24 @@
#define GD32_DMA0_CH6_CMASK (1U << 6U) #define GD32_DMA0_CH6_CMASK (1U << 6U)
#endif #endif
#if !defined(GD32_DMA2_CH1_CMASK) #if !defined(GD32_DMA1_CH0_CMASK)
#define GD32_DMA2_CH1_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 0U)) #define GD32_DMA1_CH0_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 0U))
#endif #endif
#if !defined(GD32_DMA2_CH2_CMASK) #if !defined(GD32_DMA1_CH1_CMASK)
#define GD32_DMA2_CH2_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 1U)) #define GD32_DMA1_CH1_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 1U))
#endif #endif
#if !defined(GD32_DMA2_CH3_CMASK) #if !defined(GD32_DMA1_CH2_CMASK)
#define GD32_DMA2_CH3_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 2U)) #define GD32_DMA1_CH2_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 2U))
#endif #endif
#if !defined(GD32_DMA2_CH4_CMASK) #if !defined(GD32_DMA1_CH3_CMASK)
#define GD32_DMA2_CH4_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 3U)) #define GD32_DMA1_CH3_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 3U))
#endif #endif
#if !defined(GD32_DMA2_CH5_CMASK) #if !defined(GD32_DMA1_CH4_CMASK)
#define GD32_DMA2_CH5_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 4U)) #define GD32_DMA1_CH4_CMASK (1U << (GD32_DMA0_NUM_CHANNELS + 4U))
#endif #endif
/*===========================================================================*/ /*===========================================================================*/
@ -135,11 +133,11 @@ const gd32_dma_stream_t _gd32_dma_streams[GD32_DMA_STREAMS] = {
{DMA0, DMA0_Channel5, GD32_DMA0_CH4_CMASK, DMA0_CH4_VARIANT, 16, 4, GD32_DMA0_CH4_NUMBER}, {DMA0, DMA0_Channel5, GD32_DMA0_CH4_CMASK, DMA0_CH4_VARIANT, 16, 4, GD32_DMA0_CH4_NUMBER},
{DMA0, DMA0_Channel6, GD32_DMA0_CH5_CMASK, DMA0_CH5_VARIANT, 20, 5, GD32_DMA0_CH5_NUMBER}, {DMA0, DMA0_Channel6, GD32_DMA0_CH5_CMASK, DMA0_CH5_VARIANT, 20, 5, GD32_DMA0_CH5_NUMBER},
{DMA0, DMA0_Channel7, GD32_DMA0_CH6_CMASK, DMA0_CH6_VARIANT, 24, 6, GD32_DMA0_CH6_NUMBER}, {DMA0, DMA0_Channel7, GD32_DMA0_CH6_CMASK, DMA0_CH6_VARIANT, 24, 6, GD32_DMA0_CH6_NUMBER},
{DMA2, DMA2_Channel1, GD32_DMA2_CH1_CMASK, DMA2_CH1_VARIANT, 0, 0 + GD32_DMA0_NUM_CHANNELS, GD32_DMA2_CH1_NUMBER}, {DMA1, DMA1_Channel1, GD32_DMA1_CH0_CMASK, DMA1_CH0_VARIANT, 0, 0 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH0_NUMBER},
{DMA2, DMA2_Channel2, GD32_DMA2_CH2_CMASK, DMA2_CH2_VARIANT, 4, 1 + GD32_DMA0_NUM_CHANNELS, GD32_DMA2_CH2_NUMBER}, {DMA1, DMA1_Channel2, GD32_DMA1_CH1_CMASK, DMA1_CH1_VARIANT, 4, 1 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH1_NUMBER},
{DMA2, DMA2_Channel3, GD32_DMA2_CH3_CMASK, DMA2_CH3_VARIANT, 8, 2 + GD32_DMA0_NUM_CHANNELS, GD32_DMA2_CH3_NUMBER}, {DMA1, DMA1_Channel3, GD32_DMA1_CH2_CMASK, DMA1_CH2_VARIANT, 8, 2 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH2_NUMBER},
{DMA2, DMA2_Channel4, GD32_DMA2_CH4_CMASK, DMA2_CH4_VARIANT, 12, 3 + GD32_DMA0_NUM_CHANNELS, GD32_DMA2_CH4_NUMBER}, {DMA1, DMA1_Channel4, GD32_DMA1_CH3_CMASK, DMA1_CH3_VARIANT, 12, 3 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH3_NUMBER},
{DMA2, DMA2_Channel5, GD32_DMA2_CH5_CMASK, DMA2_CH5_VARIANT, 16, 4 + GD32_DMA0_NUM_CHANNELS, GD32_DMA2_CH5_NUMBER}, {DMA1, DMA1_Channel5, GD32_DMA1_CH4_CMASK, DMA1_CH4_VARIANT, 16, 4 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH4_NUMBER},
}; };
/*===========================================================================*/ /*===========================================================================*/
@ -183,7 +181,7 @@ static struct {
#if defined(GD32_DMA0_CH0_HANDLER) || defined(__DOXYGEN__) #if defined(GD32_DMA0_CH0_HANDLER) || defined(__DOXYGEN__)
/** /**
* @brief DMA0 stream 1 shared ISR. * @brief DMA0 stream 0 shared ISR.
* *
* @isr * @isr
*/ */
@ -199,7 +197,7 @@ OSAL_IRQ_HANDLER(GD32_DMA0_CH0_HANDLER) {
#if defined(GD32_DMA0_CH1_HANDLER) || defined(__DOXYGEN__) #if defined(GD32_DMA0_CH1_HANDLER) || defined(__DOXYGEN__)
/** /**
* @brief DMA0 stream 2 shared ISR. * @brief DMA0 stream 1 shared ISR.
* *
* @isr * @isr
*/ */
@ -215,7 +213,7 @@ OSAL_IRQ_HANDLER(GD32_DMA0_CH1_HANDLER) {
#if defined(GD32_DMA0_CH2_HANDLER) || defined(__DOXYGEN__) #if defined(GD32_DMA0_CH2_HANDLER) || defined(__DOXYGEN__)
/** /**
* @brief DMA0 stream 3 shared ISR. * @brief DMA0 stream 2 shared ISR.
* *
* @isr * @isr
*/ */
@ -231,7 +229,7 @@ OSAL_IRQ_HANDLER(GD32_DMA0_CH2_HANDLER) {
#if defined(GD32_DMA0_CH3_HANDLER) || defined(__DOXYGEN__) #if defined(GD32_DMA0_CH3_HANDLER) || defined(__DOXYGEN__)
/** /**
* @brief DMA0 stream 4 shared ISR. * @brief DMA0 stream 3 shared ISR.
* *
* @isr * @isr
*/ */
@ -247,7 +245,7 @@ OSAL_IRQ_HANDLER(GD32_DMA0_CH3_HANDLER) {
#if defined(GD32_DMA0_CH4_HANDLER) || defined(__DOXYGEN__) #if defined(GD32_DMA0_CH4_HANDLER) || defined(__DOXYGEN__)
/** /**
* @brief DMA0 stream 5 shared ISR. * @brief DMA0 stream 4 shared ISR.
* *
* @isr * @isr
*/ */
@ -263,7 +261,7 @@ OSAL_IRQ_HANDLER(GD32_DMA0_CH4_HANDLER) {
#if defined(GD32_DMA0_CH5_HANDLER) || defined(__DOXYGEN__) #if defined(GD32_DMA0_CH5_HANDLER) || defined(__DOXYGEN__)
/** /**
* @brief DMA0 stream 6 shared ISR. * @brief DMA0 stream 5 shared ISR.
* *
* @isr * @isr
*/ */
@ -279,7 +277,7 @@ OSAL_IRQ_HANDLER(GD32_DMA0_CH5_HANDLER) {
#if defined(GD32_DMA0_CH6_HANDLER) || defined(__DOXYGEN__) #if defined(GD32_DMA0_CH6_HANDLER) || defined(__DOXYGEN__)
/** /**
* @brief DMA0 stream 7 shared ISR. * @brief DMA0 stream 6 shared ISR.
* *
* @isr * @isr
*/ */
@ -293,81 +291,81 @@ OSAL_IRQ_HANDLER(GD32_DMA0_CH6_HANDLER) {
} }
#endif #endif
#if defined(GD32_DMA2_CH1_HANDLER) || defined(__DOXYGEN__) #if defined(GD32_DMA1_CH0_HANDLER) || defined(__DOXYGEN__)
/** /**
* @brief DMA2 stream 1 shared ISR. * @brief DMA1 stream 0 shared ISR.
* *
* @isr * @isr
*/ */
OSAL_IRQ_HANDLER(GD32_DMA2_CH1_HANDLER) { OSAL_IRQ_HANDLER(GD32_DMA1_CH0_HANDLER) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(GD32_DMA2_STREAM1); dmaServeInterrupt(GD32_DMA1_STREAM0);
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
#endif #endif
#if defined(GD32_DMA2_CH2_HANDLER) || defined(__DOXYGEN__) #if defined(GD32_DMA1_CH1_HANDLER) || defined(__DOXYGEN__)
/** /**
* @brief DMA2 stream 2 shared ISR. * @brief DMA1 stream 1 shared ISR.
* *
* @isr * @isr
*/ */
OSAL_IRQ_HANDLER(GD32_DMA2_CH2_HANDLER) { OSAL_IRQ_HANDLER(GD32_DMA1_CH1_HANDLER) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(GD32_DMA2_STREAM2); dmaServeInterrupt(GD32_DMA1_STREAM1);
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
#endif #endif
#if defined(GD32_DMA2_CH3_HANDLER) || defined(__DOXYGEN__) #if defined(GD32_DMA1_CH2_HANDLER) || defined(__DOXYGEN__)
/** /**
* @brief DMA2 stream 3 shared ISR. * @brief DMA1 stream 2 shared ISR.
* *
* @isr * @isr
*/ */
OSAL_IRQ_HANDLER(GD32_DMA2_CH3_HANDLER) { OSAL_IRQ_HANDLER(GD32_DMA1_CH2_HANDLER) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(GD32_DMA2_STREAM3); dmaServeInterrupt(GD32_DMA1_STREAM2);
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
#endif #endif
#if defined(GD32_DMA2_CH4_HANDLER) || defined(__DOXYGEN__) #if defined(GD32_DMA1_CH3_HANDLER) || defined(__DOXYGEN__)
/** /**
* @brief DMA2 stream 4 shared ISR. * @brief DMA1 stream 3 shared ISR.
* *
* @isr * @isr
*/ */
OSAL_IRQ_HANDLER(GD32_DMA2_CH4_HANDLER) { OSAL_IRQ_HANDLER(GD32_DMA1_CH3_HANDLER) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(GD32_DMA2_STREAM4); dmaServeInterrupt(GD32_DMA1_STREAM3);
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
#endif #endif
#if defined(GD32_DMA2_CH5_HANDLER) || defined(__DOXYGEN__) #if defined(GD32_DMA1_CH4_HANDLER) || defined(__DOXYGEN__)
/** /**
* @brief DMA2 stream 5 shared ISR. * @brief DMA1 stream 4 shared ISR.
* *
* @isr * @isr
*/ */
OSAL_IRQ_HANDLER(GD32_DMA2_CH5_HANDLER) { OSAL_IRQ_HANDLER(GD32_DMA1_CH4_HANDLER) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(GD32_DMA2_STREAM5); dmaServeInterrupt(GD32_DMA1_STREAM4);
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
@ -393,7 +391,7 @@ void dmaInit(void) {
dma.streams[i].func = NULL; dma.streams[i].func = NULL;
} }
DMA0->IFCR = 0xFFFFFFFFU; DMA0->IFCR = 0xFFFFFFFFU;
DMA2->IFCR = 0xFFFFFFFFU; DMA1->IFCR = 0xFFFFFFFFU;
} }
/** /**
@ -406,8 +404,8 @@ void dmaInit(void) {
* - @p GD32_DMA_STREAM_ID_ANY for any stream. * - @p GD32_DMA_STREAM_ID_ANY for any stream.
* - @p GD32_DMA_STREAM_ID_ANY_DMA0 for any stream * - @p GD32_DMA_STREAM_ID_ANY_DMA0 for any stream
* on DMA0. * on DMA0.
* - @p GD32_DMA_STREAM_ID_ANY_DMA2 for any stream * - @p GD32_DMA_STREAM_ID_ANY_DMA1 for any stream
* on DMA2. * on DMA1.
* . * .
* @param[in] priority IRQ priority for the DMA stream * @param[in] priority IRQ priority for the DMA stream
* @param[in] func handling function pointer, can be @p NULL * @param[in] func handling function pointer, can be @p NULL
@ -449,8 +447,8 @@ const gd32_dma_stream_t *dmaStreamAllocI(uint32_t id,
rccEnableDMA0(true); rccEnableDMA0(true);
} }
if ((GD32_DMA2_STREAMS_MASK & mask) != 0U) { if ((GD32_DMA1_STREAMS_MASK & mask) != 0U) {
rccEnableDMA2(true); rccEnableDMA1(true);
} }
/* Enables the associated IRQ vector if not already enabled and if a /* Enables the associated IRQ vector if not already enabled and if a
@ -483,8 +481,8 @@ const gd32_dma_stream_t *dmaStreamAllocI(uint32_t id,
* - @p GD32_DMA_STREAM_ID_ANY for any stream. * - @p GD32_DMA_STREAM_ID_ANY for any stream.
* - @p GD32_DMA_STREAM_ID_ANY_DMA0 for any stream * - @p GD32_DMA_STREAM_ID_ANY_DMA0 for any stream
* on DMA0. * on DMA0.
* - @p GD32_DMA_STREAM_ID_ANY_DMA2 for any stream * - @p GD32_DMA_STREAM_ID_ANY_DMA1 for any stream
* on DMA2. * on DMA1.
* . * .
* @param[in] priority IRQ priority for the DMA stream * @param[in] priority IRQ priority for the DMA stream
* @param[in] func handling function pointer, can be @p NULL * @param[in] func handling function pointer, can be @p NULL
@ -544,8 +542,8 @@ void dmaStreamFreeI(const gd32_dma_stream_t *dmastp) {
if ((dma.allocated_mask & GD32_DMA0_STREAMS_MASK) == 0U) { if ((dma.allocated_mask & GD32_DMA0_STREAMS_MASK) == 0U) {
rccDisableDMA0(); rccDisableDMA0();
} }
if ((dma.allocated_mask & GD32_DMA2_STREAMS_MASK) == 0U) { if ((dma.allocated_mask & GD32_DMA1_STREAMS_MASK) == 0U) {
rccDisableDMA2(); rccDisableDMA1();
} }
} }

18
os/hal/ports/GD/GD32VF103/DMA/gd32_dma.h
View File

@ -36,7 +36,7 @@
* @details This is the total number of streams among all the DMA units. * @details This is the total number of streams among all the DMA units.
*/ */
#define GD32_DMA_STREAMS (GD32_DMA0_NUM_CHANNELS + \ #define GD32_DMA_STREAMS (GD32_DMA0_NUM_CHANNELS + \
GD32_DMA2_NUM_CHANNELS) GD32_DMA1_NUM_CHANNELS)
/** /**
* @brief Mask of the ISR bits passed to the DMA callback functions. * @brief Mask of the ISR bits passed to the DMA callback functions.
@ -130,11 +130,11 @@
#define GD32_DMA0_STREAM4 GD32_DMA_STREAM(4) #define GD32_DMA0_STREAM4 GD32_DMA_STREAM(4)
#define GD32_DMA0_STREAM5 GD32_DMA_STREAM(5) #define GD32_DMA0_STREAM5 GD32_DMA_STREAM(5)
#define GD32_DMA0_STREAM6 GD32_DMA_STREAM(6) #define GD32_DMA0_STREAM6 GD32_DMA_STREAM(6)
#define GD32_DMA2_STREAM1 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 0) #define GD32_DMA1_STREAM0 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 0)
#define GD32_DMA2_STREAM2 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 1) #define GD32_DMA1_STREAM1 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 1)
#define GD32_DMA2_STREAM3 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 2) #define GD32_DMA1_STREAM2 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 2)
#define GD32_DMA2_STREAM4 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 3) #define GD32_DMA1_STREAM3 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 3)
#define GD32_DMA2_STREAM5 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 4) #define GD32_DMA1_STREAM4 GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 4)
/** @} */ /** @} */
/** /**
@ -197,15 +197,15 @@
#error "GD32_DMA0_NUM_CHANNELS not defined in registry" #error "GD32_DMA0_NUM_CHANNELS not defined in registry"
#endif #endif
#if !defined(GD32_DMA2_NUM_CHANNELS) #if !defined(GD32_DMA1_NUM_CHANNELS)
#error "GD32_DMA2_NUM_CHANNELS not defined in registry" #error "GD32_DMA1_NUM_CHANNELS not defined in registry"
#endif #endif
#if (GD32_DMA0_NUM_CHANNELS < 0) || (GD32_DMA0_NUM_CHANNELS > 7) #if (GD32_DMA0_NUM_CHANNELS < 0) || (GD32_DMA0_NUM_CHANNELS > 7)
#error "unsupported channels configuration" #error "unsupported channels configuration"
#endif #endif
#if (GD32_DMA2_NUM_CHANNELS < 0) || (GD32_DMA2_NUM_CHANNELS > 5) #if (GD32_DMA1_NUM_CHANNELS < 0) || (GD32_DMA1_NUM_CHANNELS > 5)
#error "unsupported channels configuration" #error "unsupported channels configuration"
#endif #endif

10
os/hal/ports/GD/GD32VF103/gd32_rcc.h
View File

@ -376,21 +376,21 @@
#define rccResetDMA0() #define rccResetDMA0()
/** /**
* @brief Enables the DMA2 peripheral clock. * @brief Enables the DMA1 peripheral clock.
* @note The @p lp parameter is ignored in this family. * @note The @p lp parameter is ignored in this family.
* *
* @param[in] lp low power enable flag * @param[in] lp low power enable flag
* *
* @api * @api
*/ */
#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp) #define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
/** /**
* @brief Disables the DMA2 peripheral clock. * @brief Disables the DMA1 peripheral clock.
* *
* @api * @api
*/ */
#define rccDisableDMA2() rccDisableAHB(RCC_AHBENR_DMA2EN) #define rccDisableDMA1() rccDisableAHB(RCC_AHBENR_DMA1EN)
/** /**
* @brief Resets the DMA0 peripheral. * @brief Resets the DMA0 peripheral.
@ -398,7 +398,7 @@
* *
* @api * @api
*/ */
#define rccResetDMA2() #define rccResetDMA1()
/** @} */ /** @} */
/** /**

22
os/hal/ports/GD/GD32VF103/gd32_registry.h
View File

@ -134,17 +134,17 @@
#define GD32_DMA0_CH5_NUMBER 35 #define GD32_DMA0_CH5_NUMBER 35
#define GD32_DMA0_CH6_NUMBER 36 #define GD32_DMA0_CH6_NUMBER 36
#define GD32_DMA2_NUM_CHANNELS 5 #define GD32_DMA1_NUM_CHANNELS 5
#define GD32_DMA2_CH1_HANDLER vector75 #define GD32_DMA1_CH0_HANDLER vector75
#define GD32_DMA2_CH2_HANDLER vector76 #define GD32_DMA1_CH1_HANDLER vector76
#define GD32_DMA2_CH3_HANDLER vector77 #define GD32_DMA1_CH2_HANDLER vector77
#define GD32_DMA2_CH4_HANDLER vector78 #define GD32_DMA1_CH3_HANDLER vector78
#define GD32_DMA2_CH5_HANDLER vector79 #define GD32_DMA1_CH4_HANDLER vector79
#define GD32_DMA2_CH1_NUMBER 75 #define GD32_DMA1_CH0_NUMBER 75
#define GD32_DMA2_CH2_NUMBER 76 #define GD32_DMA1_CH1_NUMBER 76
#define GD32_DMA2_CH3_NUMBER 77 #define GD32_DMA1_CH2_NUMBER 77
#define GD32_DMA2_CH4_NUMBER 78 #define GD32_DMA1_CH3_NUMBER 78
#define GD32_DMA2_CH5_NUMBER 79 #define GD32_DMA1_CH4_NUMBER 79
/* EXTI attributes.*/ /* EXTI attributes.*/
#define GD32_EXTI_NUM_LINES 19 #define GD32_EXTI_NUM_LINES 19

16
os/hal/ports/GD/GD32VF103/hal_lld.c
View File

@ -99,25 +99,25 @@ static void hal_lld_backup_domain_init(void) {
/*===========================================================================*/ /*===========================================================================*/
#if defined(GD32_DMA_REQUIRED) || defined(__DOXYGEN__) #if defined(GD32_DMA_REQUIRED) || defined(__DOXYGEN__)
#if defined(GD32_DMA2_CH45_HANDLER) || defined(__DOXYGEN__) #if defined(GD32_DMA1_CH35_HANDLER) || defined(__DOXYGEN__)
/** /**
* @brief DMA2 streams 4 and 5 shared ISR. * @brief DMA1 streams 4 and 5 shared ISR.
* *
* @isr * @isr
*/ */
OSAL_IRQ_HANDLER(GD32_DMA2_CH45_HANDLER) { OSAL_IRQ_HANDLER(GD32_DMA1_CH35_HANDLER) {
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
/* Check on channel 4 of DMA2.*/ /* Check on channel 4 of DMA1.*/
dmaServeInterrupt(GD32_DMA2_STREAM4); dmaServeInterrupt(GD32_DMA1_STREAM3);
/* Check on channel 5 of DMA2.*/ /* Check on channel 5 of DMA1.*/
dmaServeInterrupt(GD32_DMA2_STREAM5); dmaServeInterrupt(GD32_DMA1_STREAM4);
OSAL_IRQ_EPILOGUE(); OSAL_IRQ_EPILOGUE();
} }
#endif /* defined(GD32_DMA2_CH45_HANDLER) */ #endif /* defined(GD32_DMA1_CH35_HANDLER) */
#endif /* defined(GD32_DMA_REQUIRED) */ #endif /* defined(GD32_DMA_REQUIRED) */
/*===========================================================================*/ /*===========================================================================*/

100
os/hal/ports/GD/GD32VF103/stm32_registry.h
View File

@ -106,7 +106,7 @@
#define GD32_DMA0_CH5_NUMBER 16 #define GD32_DMA0_CH5_NUMBER 16
#define GD32_DMA0_CH6_NUMBER 17 #define GD32_DMA0_CH6_NUMBER 17
#define GD32_DMA2_NUM_CHANNELS 0 #define GD32_DMA1_NUM_CHANNELS 0
/* ETH attributes.*/ /* ETH attributes.*/
#define GD32_HAS_ETH FALSE #define GD32_HAS_ETH FALSE
@ -259,8 +259,8 @@
/* LTDC attributes.*/ /* LTDC attributes.*/
#define GD32_HAS_LTDC FALSE #define GD32_HAS_LTDC FALSE
/* DMA2D attributes.*/ /* DMA1D attributes.*/
#define GD32_HAS_DMA2D FALSE #define GD32_HAS_DMA1D FALSE
/* FSMC attributes.*/ /* FSMC attributes.*/
#define GD32_HAS_FSMC FALSE #define GD32_HAS_FSMC FALSE
@ -319,7 +319,7 @@
#define GD32_DMA0_CH5_NUMBER 16 #define GD32_DMA0_CH5_NUMBER 16
#define GD32_DMA0_CH6_NUMBER 17 #define GD32_DMA0_CH6_NUMBER 17
#define GD32_DMA2_NUM_CHANNELS 0 #define GD32_DMA1_NUM_CHANNELS 0
/* ETH attributes.*/ /* ETH attributes.*/
#define GD32_HAS_ETH FALSE #define GD32_HAS_ETH FALSE
@ -444,8 +444,8 @@
/* LTDC attributes.*/ /* LTDC attributes.*/
#define GD32_HAS_LTDC FALSE #define GD32_HAS_LTDC FALSE
/* DMA2D attributes.*/ /* DMA1D attributes.*/
#define GD32_HAS_DMA2D FALSE #define GD32_HAS_DMA1D FALSE
/* FSMC attributes.*/ /* FSMC attributes.*/
#define GD32_HAS_FSMC FALSE #define GD32_HAS_FSMC FALSE
@ -504,7 +504,7 @@
#define GD32_DMA0_CH5_NUMBER 16 #define GD32_DMA0_CH5_NUMBER 16
#define GD32_DMA0_CH6_NUMBER 17 #define GD32_DMA0_CH6_NUMBER 17
#define GD32_DMA2_NUM_CHANNELS 0 #define GD32_DMA1_NUM_CHANNELS 0
/* ETH attributes.*/ /* ETH attributes.*/
#define GD32_HAS_ETH FALSE #define GD32_HAS_ETH FALSE
@ -645,8 +645,8 @@
/* LTDC attributes.*/ /* LTDC attributes.*/
#define GD32_HAS_LTDC FALSE #define GD32_HAS_LTDC FALSE
/* DMA2D attributes.*/ /* DMA1D attributes.*/
#define GD32_HAS_DMA2D FALSE #define GD32_HAS_DMA1D FALSE
/* FSMC attributes.*/ /* FSMC attributes.*/
#define GD32_HAS_FSMC FALSE #define GD32_HAS_FSMC FALSE
@ -709,20 +709,20 @@
#define GD32_DMA0_CH5_NUMBER 16 #define GD32_DMA0_CH5_NUMBER 16
#define GD32_DMA0_CH6_NUMBER 17 #define GD32_DMA0_CH6_NUMBER 17
#define GD32_DMA2_NUM_CHANNELS 5 #define GD32_DMA1_NUM_CHANNELS 5
#define GD32_DMA2_CH1_HANDLER Vector120 #define GD32_DMA1_CH0_HANDLER Vector120
#define GD32_DMA2_CH2_HANDLER Vector124 #define GD32_DMA1_CH1_HANDLER Vector124
#define GD32_DMA2_CH3_HANDLER Vector128 #define GD32_DMA1_CH2_HANDLER Vector128
#define GD32_DMA2_CH45_HANDLER Vector12C #define GD32_DMA1_CH35_HANDLER Vector12C
#define GD32_DMA2_CH1_NUMBER 56 #define GD32_DMA1_CH0_NUMBER 56
#define GD32_DMA2_CH2_NUMBER 57 #define GD32_DMA1_CH1_NUMBER 57
#define GD32_DMA2_CH3_NUMBER 58 #define GD32_DMA1_CH2_NUMBER 58
#define GD32_DMA2_CH45_NUMBER 59 #define GD32_DMA1_CH35_NUMBER 59
#define GD32_DMA2_CH4_NUMBER GD32_DMA2_CH45_NUMBER #define GD32_DMA1_CH3_NUMBER GD32_DMA1_CH35_NUMBER
#define GD32_DMA2_CH5_NUMBER GD32_DMA2_CH45_NUMBER #define GD32_DMA1_CH4_NUMBER GD32_DMA1_CH35_NUMBER
#define DMA2_CH4_CMASK 0x00000C00U #define DMA1_CH3_CMASK 0x00000C00U
#define DMA2_CH5_CMASK 0x00000C00U #define DMA1_CH4_CMASK 0x00000C00U
/* ETH attributes.*/ /* ETH attributes.*/
#define GD32_HAS_ETH FALSE #define GD32_HAS_ETH FALSE
@ -885,8 +885,8 @@
/* LTDC attributes.*/ /* LTDC attributes.*/
#define GD32_HAS_LTDC FALSE #define GD32_HAS_LTDC FALSE
/* DMA2D attributes.*/ /* DMA1D attributes.*/
#define GD32_HAS_DMA2D FALSE #define GD32_HAS_DMA1D FALSE
/* FSMC attributes.*/ /* FSMC attributes.*/
#define GD32_HAS_FSMC TRUE #define GD32_HAS_FSMC TRUE
@ -952,17 +952,17 @@
#define GD32_DMA0_CH5_NUMBER 16 #define GD32_DMA0_CH5_NUMBER 16
#define GD32_DMA0_CH6_NUMBER 17 #define GD32_DMA0_CH6_NUMBER 17
#define GD32_DMA2_NUM_CHANNELS 5 #define GD32_DMA1_NUM_CHANNELS 5
#define GD32_DMA2_CH1_HANDLER Vector120 #define GD32_DMA1_CH0_HANDLER Vector120
#define GD32_DMA2_CH2_HANDLER Vector124 #define GD32_DMA1_CH1_HANDLER Vector124
#define GD32_DMA2_CH3_HANDLER Vector128 #define GD32_DMA1_CH2_HANDLER Vector128
#define GD32_DMA2_CH4_HANDLER Vector12C #define GD32_DMA1_CH3_HANDLER Vector12C
#define GD32_DMA2_CH5_HANDLER Vector130 #define GD32_DMA1_CH4_HANDLER Vector130
#define GD32_DMA2_CH1_NUMBER 56 #define GD32_DMA1_CH0_NUMBER 56
#define GD32_DMA2_CH2_NUMBER 57 #define GD32_DMA1_CH1_NUMBER 57
#define GD32_DMA2_CH3_NUMBER 58 #define GD32_DMA1_CH2_NUMBER 58
#define GD32_DMA2_CH4_NUMBER 59 #define GD32_DMA1_CH3_NUMBER 59
#define GD32_DMA2_CH5_NUMBER 60 #define GD32_DMA1_CH4_NUMBER 60
/* ETH attributes.*/ /* ETH attributes.*/
#define GD32_HAS_ETH FALSE #define GD32_HAS_ETH FALSE
@ -1143,8 +1143,8 @@
/* LTDC attributes.*/ /* LTDC attributes.*/
#define GD32_HAS_LTDC FALSE #define GD32_HAS_LTDC FALSE
/* DMA2D attributes.*/ /* DMA1D attributes.*/
#define GD32_HAS_DMA2D FALSE #define GD32_HAS_DMA1D FALSE
/* FSMC attributes.*/ /* FSMC attributes.*/
#define GD32_HAS_FSMC TRUE #define GD32_HAS_FSMC TRUE
@ -1210,17 +1210,17 @@
#define GD32_DMA0_CH5_NUMBER 16 #define GD32_DMA0_CH5_NUMBER 16
#define GD32_DMA0_CH6_NUMBER 17 #define GD32_DMA0_CH6_NUMBER 17
#define GD32_DMA2_NUM_CHANNELS 5 #define GD32_DMA1_NUM_CHANNELS 5
#define GD32_DMA2_CH1_HANDLER Vector120 #define GD32_DMA1_CH0_HANDLER Vector120
#define GD32_DMA2_CH2_HANDLER Vector124 #define GD32_DMA1_CH1_HANDLER Vector124
#define GD32_DMA2_CH3_HANDLER Vector128 #define GD32_DMA1_CH2_HANDLER Vector128
#define GD32_DMA2_CH4_HANDLER Vector12C #define GD32_DMA1_CH3_HANDLER Vector12C
#define GD32_DMA2_CH5_HANDLER Vector130 #define GD32_DMA1_CH4_HANDLER Vector130
#define GD32_DMA2_CH1_NUMBER 56 #define GD32_DMA1_CH0_NUMBER 56
#define GD32_DMA2_CH2_NUMBER 57 #define GD32_DMA1_CH1_NUMBER 57
#define GD32_DMA2_CH3_NUMBER 58 #define GD32_DMA1_CH2_NUMBER 58
#define GD32_DMA2_CH4_NUMBER 59 #define GD32_DMA1_CH3_NUMBER 59
#define GD32_DMA2_CH5_NUMBER 60 #define GD32_DMA1_CH4_NUMBER 60
/* ETH attributes.*/ /* ETH attributes.*/
#define GD32_HAS_ETH TRUE #define GD32_HAS_ETH TRUE
@ -1382,8 +1382,8 @@
/* LTDC attributes.*/ /* LTDC attributes.*/
#define GD32_HAS_LTDC FALSE #define GD32_HAS_LTDC FALSE
/* DMA2D attributes.*/ /* DMA1D attributes.*/
#define GD32_HAS_DMA2D FALSE #define GD32_HAS_DMA1D FALSE
/* FSMC attributes.*/ /* FSMC attributes.*/
#define GD32_HAS_FSMC FALSE #define GD32_HAS_FSMC FALSE

44
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -742,12 +742,12 @@ typedef struct
#define DMA0_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) #define DMA0_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
#define DMA0_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU) #define DMA0_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
#define DMA0_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U) #define DMA0_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400U) #define DMA1_BASE (AHBPERIPH_BASE + 0x00000400U)
#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U) #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U)
#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU) #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU)
#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U) #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U)
#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U) #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U)
#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U) #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U)
#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) #define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
//#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) //#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
@ -823,7 +823,7 @@ typedef struct
#define USART1 ((USART_TypeDef *)USART1_BASE) #define USART1 ((USART_TypeDef *)USART1_BASE)
#define SDIO ((SDIO_TypeDef *)SDIO_BASE) #define SDIO ((SDIO_TypeDef *)SDIO_BASE)
#define DMA0 ((DMA_TypeDef *)DMA0_BASE) #define DMA0 ((DMA_TypeDef *)DMA0_BASE)
#define DMA2 ((DMA_TypeDef *)DMA2_BASE) #define DMA1 ((DMA_TypeDef *)DMA1_BASE)
#define DMA0_Channel1 ((DMA_Channel_TypeDef *)DMA0_Channel1_BASE) #define DMA0_Channel1 ((DMA_Channel_TypeDef *)DMA0_Channel1_BASE)
#define DMA0_Channel2 ((DMA_Channel_TypeDef *)DMA0_Channel2_BASE) #define DMA0_Channel2 ((DMA_Channel_TypeDef *)DMA0_Channel2_BASE)
#define DMA0_Channel3 ((DMA_Channel_TypeDef *)DMA0_Channel3_BASE) #define DMA0_Channel3 ((DMA_Channel_TypeDef *)DMA0_Channel3_BASE)
@ -831,11 +831,11 @@ typedef struct
#define DMA0_Channel5 ((DMA_Channel_TypeDef *)DMA0_Channel5_BASE) #define DMA0_Channel5 ((DMA_Channel_TypeDef *)DMA0_Channel5_BASE)
#define DMA0_Channel6 ((DMA_Channel_TypeDef *)DMA0_Channel6_BASE) #define DMA0_Channel6 ((DMA_Channel_TypeDef *)DMA0_Channel6_BASE)
#define DMA0_Channel7 ((DMA_Channel_TypeDef *)DMA0_Channel7_BASE) #define DMA0_Channel7 ((DMA_Channel_TypeDef *)DMA0_Channel7_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
#define RCC ((RCC_TypeDef *)RCC_BASE) #define RCC ((RCC_TypeDef *)RCC_BASE)
#define CRC ((CRC_TypeDef *)CRC_BASE) #define CRC ((CRC_TypeDef *)CRC_BASE)
#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
@ -1629,9 +1629,9 @@ typedef struct
#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
#define RCC_AHBENR_DMA2EN_Pos (1U) #define RCC_AHBENR_DMA1EN_Pos (1U)
#define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */ #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000002 */
#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */ #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
#define RCC_AHBENR_OTGFSEN_Pos (12U) #define RCC_AHBENR_OTGFSEN_Pos (12U)
@ -14275,11 +14275,11 @@ typedef struct
((INSTANCE) == DMA0_Channel5) || \ ((INSTANCE) == DMA0_Channel5) || \
((INSTANCE) == DMA0_Channel6) || \ ((INSTANCE) == DMA0_Channel6) || \
((INSTANCE) == DMA0_Channel7) || \ ((INSTANCE) == DMA0_Channel7) || \
((INSTANCE) == DMA2_Channel1) || \ ((INSTANCE) == DMA1_Channel1) || \
((INSTANCE) == DMA2_Channel2) || \ ((INSTANCE) == DMA1_Channel2) || \
((INSTANCE) == DMA2_Channel3) || \ ((INSTANCE) == DMA1_Channel3) || \
((INSTANCE) == DMA2_Channel4) || \ ((INSTANCE) == DMA1_Channel4) || \
((INSTANCE) == DMA2_Channel5)) ((INSTANCE) == DMA1_Channel5))
/******************************* GPIO Instances *******************************/ /******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
@ -14608,7 +14608,7 @@ typedef struct
#define USB_LP_IRQn CAN1_RX0_IRQn #define USB_LP_IRQn CAN1_RX0_IRQn
#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn #define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
#define USB_HP_IRQn CAN1_TX_IRQn #define USB_HP_IRQn CAN1_TX_IRQn
#define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_IRQn
#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn #define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
#define CEC_IRQn OTG_FS_WKUP_IRQn #define CEC_IRQn OTG_FS_WKUP_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
@ -14629,7 +14629,7 @@ typedef struct
#define USB_LP_IRQHandler CAN1_RX0_IRQHandler #define USB_LP_IRQHandler CAN1_RX0_IRQHandler
#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler #define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
#define USB_HP_IRQHandler CAN1_TX_IRQHandler #define USB_HP_IRQHandler CAN1_TX_IRQHandler
#define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler #define DMA1_Channel4_5_IRQHandler DMA1_Channel4_IRQHandler
#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler #define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler #define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler