Merge pull request #318 from WestberryTech/chibios-21.11.x-wb
Added New MCU Serial for WB32.
This commit is contained in:
commit
934631adbd
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@ -0,0 +1,194 @@
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##############################################################################
|
||||
# Build global options
|
||||
# NOTE: Can be overridden externally.
|
||||
#
|
||||
|
||||
# Compiler options here.
|
||||
ifeq ($(USE_OPT),)
|
||||
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
|
||||
endif
|
||||
|
||||
# C specific options here (added to USE_OPT).
|
||||
ifeq ($(USE_COPT),)
|
||||
USE_COPT =
|
||||
endif
|
||||
|
||||
# C++ specific options here (added to USE_OPT).
|
||||
ifeq ($(USE_CPPOPT),)
|
||||
USE_CPPOPT = -fno-rtti
|
||||
endif
|
||||
|
||||
# Enable this if you want the linker to remove unused code and data.
|
||||
ifeq ($(USE_LINK_GC),)
|
||||
USE_LINK_GC = yes
|
||||
endif
|
||||
|
||||
# Linker extra options here.
|
||||
ifeq ($(USE_LDOPT),)
|
||||
USE_LDOPT =
|
||||
endif
|
||||
|
||||
# Enable this if you want link time optimizations (LTO).
|
||||
ifeq ($(USE_LTO),)
|
||||
USE_LTO = yes
|
||||
endif
|
||||
|
||||
# Enable this if you want to see the full log while compiling.
|
||||
ifeq ($(USE_VERBOSE_COMPILE),)
|
||||
USE_VERBOSE_COMPILE = yes
|
||||
endif
|
||||
|
||||
# If enabled, this option makes the build process faster by not compiling
|
||||
# modules not used in the current configuration.
|
||||
ifeq ($(USE_SMART_BUILD),)
|
||||
USE_SMART_BUILD = yes
|
||||
endif
|
||||
|
||||
#
|
||||
# Build global options
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Architecture or project specific options
|
||||
#
|
||||
|
||||
# Stack size to be allocated to the Cortex-M process stack. This stack is
|
||||
# the stack used by the main() thread.
|
||||
ifeq ($(USE_PROCESS_STACKSIZE),)
|
||||
USE_PROCESS_STACKSIZE = 0x400
|
||||
endif
|
||||
|
||||
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
|
||||
# stack is used for processing interrupts and exceptions.
|
||||
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
|
||||
USE_EXCEPTIONS_STACKSIZE = 0x400
|
||||
endif
|
||||
|
||||
# Enables the use of FPU (no, softfp, hard).
|
||||
ifeq ($(USE_FPU),)
|
||||
USE_FPU = no
|
||||
endif
|
||||
|
||||
# FPU-related options.
|
||||
ifeq ($(USE_FPU_OPT),)
|
||||
USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16
|
||||
endif
|
||||
|
||||
#
|
||||
# Architecture or project specific options
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Project, target, sources and paths
|
||||
#
|
||||
|
||||
# Define project name here
|
||||
PROJECT = ch
|
||||
|
||||
# Target settings.
|
||||
MCU = cortex-m3
|
||||
|
||||
# Imported source files and paths.
|
||||
CHIBIOS := ../../../../ChibiOS
|
||||
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
|
||||
CONFDIR := ./cfg
|
||||
BUILDDIR := ./build
|
||||
DEPDIR := ./.dep
|
||||
BOARDDIR := ./board
|
||||
|
||||
# Licensing files.
|
||||
include $(CHIBIOS)/os/license/license.mk
|
||||
# Startup files.
|
||||
include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_wb32fq95xx.mk
|
||||
# HAL-OSAL files (optional).
|
||||
include $(CHIBIOS)/os/hal/hal.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/WB32FQ95xx/platform.mk
|
||||
include $(BOARDDIR)/board.mk
|
||||
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
|
||||
# RTOS files (optional).
|
||||
include $(CHIBIOS)/os/rt/rt.mk
|
||||
include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk
|
||||
# Auto-build files in ./source recursively.
|
||||
include $(CHIBIOS)/tools/mk/autobuild.mk
|
||||
# Other files (optional).
|
||||
# include $(CHIBIOS)/test/lib/test.mk
|
||||
# include $(CHIBIOS)/test/rt/rt_test.mk
|
||||
# include $(CHIBIOS)/test/oslib/oslib_test.mk
|
||||
# include $(CHIBIOS)/os/hal/lib/streams/streams.mk
|
||||
# include $(CHIBIOS)/os/various/shell/shell.mk
|
||||
|
||||
# Define linker script file here
|
||||
LDSCRIPT= $(STARTUPLD_CONTRIB)/WB32FQ95xC.ld
|
||||
|
||||
|
||||
# C sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CSRC = $(ALLCSRC) \
|
||||
$(TESTSRC) \
|
||||
main.c
|
||||
|
||||
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CPPSRC = $(ALLCPPSRC)
|
||||
|
||||
# List ASM source files here.
|
||||
ASMSRC = $(ALLASMSRC)
|
||||
|
||||
# List ASM with preprocessor source files here.
|
||||
ASMXSRC = $(ALLXASMSRC)
|
||||
|
||||
# Inclusion directories.
|
||||
INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC)
|
||||
|
||||
# Define C warning options here.
|
||||
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
|
||||
|
||||
# Define C++ warning options here.
|
||||
CPPWARN = -Wall -Wextra -Wundef
|
||||
|
||||
#
|
||||
# Project, target, sources and paths
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Start of user section
|
||||
#
|
||||
|
||||
# List all user C define here, like -D_DEBUG=1
|
||||
UDEFS =
|
||||
|
||||
# Define ASM defines here
|
||||
UADEFS =
|
||||
|
||||
# List all user directories here
|
||||
UINCDIR =
|
||||
|
||||
# List the user directory to look for the libraries here
|
||||
ULIBDIR =
|
||||
|
||||
# List all user libraries here
|
||||
ULIBS =
|
||||
|
||||
#
|
||||
# End of user section
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Common rules
|
||||
#
|
||||
|
||||
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
|
||||
include $(RULESPATH)/arm-none-eabi.mk
|
||||
include $(RULESPATH)/rules.mk
|
||||
|
||||
#
|
||||
# Common rules
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Custom rules
|
||||
#
|
||||
|
||||
#
|
||||
# Custom rules
|
||||
##############################################################################
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
static void wb32_gpio_init(void) {
|
||||
|
||||
#if WB32_HAS_GPIOA
|
||||
rccEnableAPB1(RCC_APB1ENR_GPIOAEN);
|
||||
#endif
|
||||
|
||||
#if WB32_HAS_GPIOB
|
||||
rccEnableAPB1(RCC_APB1ENR_GPIOBEN);
|
||||
#endif
|
||||
|
||||
#if WB32_HAS_GPIOC
|
||||
rccEnableAPB1(RCC_APB1ENR_GPIOCEN);
|
||||
#endif
|
||||
|
||||
#if WB32_HAS_GPIOD
|
||||
rccEnableAPB1(RCC_APB1ENR_GPIODEN);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
/*
|
||||
* Early initialization code.
|
||||
* This initialization must be performed just after stack setup and before
|
||||
* any other initialization.
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
wb32_clock_init();
|
||||
wb32_gpio_init();
|
||||
}
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @note You can add your board-specific code here.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
|
||||
}
|
|
@ -0,0 +1,56 @@
|
|||
#pragma once
|
||||
/*
|
||||
Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Setup board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define WB32FQ95xC
|
||||
#if !defined(WB32FQ95xx)
|
||||
#define WB32FQ95xx
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* BOARD_H */
|
|
@ -0,0 +1,9 @@
|
|||
# List of all the board related files.
|
||||
BOARDSRC = $(BOARDDIR)/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = $(BOARDDIR)
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
ALLINC += $(BOARDINC)
|
|
@ -0,0 +1,834 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file rt/templates/chconf.h
|
||||
* @brief Configuration file template.
|
||||
* @details A copy of this file must be placed in each project directory, it
|
||||
* contains the application specific kernel settings.
|
||||
*
|
||||
* @addtogroup config
|
||||
* @details Kernel related settings and hooks.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef CHCONF_H
|
||||
#define CHCONF_H
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_7_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name System settings
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Handling of instances.
|
||||
* @note If enabled then threads assigned to various instances can
|
||||
* interact each other using the same synchronization objects.
|
||||
* If disabled then each OS instance is a separate world, no
|
||||
* direct interactions are handled by the OS.
|
||||
*/
|
||||
#if !defined(CH_CFG_SMP_MODE)
|
||||
#define CH_CFG_SMP_MODE FALSE
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name System timers settings
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System time counter resolution.
|
||||
* @note Allowed values are 16, 32 or 64 bits.
|
||||
*/
|
||||
#if !defined(CH_CFG_ST_RESOLUTION)
|
||||
#define CH_CFG_ST_RESOLUTION 32
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System tick frequency.
|
||||
* @details Frequency of the system timer that drives the system ticks. This
|
||||
* setting also defines the system tick time unit.
|
||||
*/
|
||||
#if !defined(CH_CFG_ST_FREQUENCY)
|
||||
#define CH_CFG_ST_FREQUENCY 10000
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Time intervals data size.
|
||||
* @note Allowed values are 16, 32 or 64 bits.
|
||||
*/
|
||||
#if !defined(CH_CFG_INTERVALS_SIZE)
|
||||
#define CH_CFG_INTERVALS_SIZE 32
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Time types data size.
|
||||
* @note Allowed values are 16 or 32 bits.
|
||||
*/
|
||||
#if !defined(CH_CFG_TIME_TYPES_SIZE)
|
||||
#define CH_CFG_TIME_TYPES_SIZE 32
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Time delta constant for the tick-less mode.
|
||||
* @note If this value is zero then the system uses the classic
|
||||
* periodic tick. This value represents the minimum number
|
||||
* of ticks that is safe to specify in a timeout directive.
|
||||
* The value one is not valid, timeouts are rounded up to
|
||||
* this value.
|
||||
*/
|
||||
#if !defined(CH_CFG_ST_TIMEDELTA)
|
||||
#define CH_CFG_ST_TIMEDELTA 0
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Kernel parameters and options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Round robin interval.
|
||||
* @details This constant is the number of system ticks allowed for the
|
||||
* threads before preemption occurs. Setting this value to zero
|
||||
* disables the preemption for threads with equal priority and the
|
||||
* round robin becomes cooperative. Note that higher priority
|
||||
* threads can still preempt, the kernel is always preemptive.
|
||||
* @note Disabling the round robin preemption makes the kernel more compact
|
||||
* and generally faster.
|
||||
* @note The round robin preemption is not supported in tickless mode and
|
||||
* must be set to zero in that case.
|
||||
*/
|
||||
#if !defined(CH_CFG_TIME_QUANTUM)
|
||||
#define CH_CFG_TIME_QUANTUM 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Idle thread automatic spawn suppression.
|
||||
* @details When this option is activated the function @p chSysInit()
|
||||
* does not spawn the idle thread. The application @p main()
|
||||
* function becomes the idle thread and must implement an
|
||||
* infinite loop.
|
||||
*/
|
||||
#if !defined(CH_CFG_NO_IDLE_THREAD)
|
||||
#define CH_CFG_NO_IDLE_THREAD FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Kernel hardening level.
|
||||
* @details This option is the level of functional-safety checks enabled
|
||||
* in the kerkel. The meaning is:
|
||||
* - 0: No checks, maximum performance.
|
||||
* - 1: Reasonable checks.
|
||||
* - 2: All checks.
|
||||
* .
|
||||
*/
|
||||
#if !defined(CH_CFG_HARDENING_LEVEL)
|
||||
#define CH_CFG_HARDENING_LEVEL 0
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Performance options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief OS optimization.
|
||||
* @details If enabled then time efficient rather than space efficient code
|
||||
* is used when two possible implementations exist.
|
||||
*
|
||||
* @note This is not related to the compiler optimization options.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_OPTIMIZE_SPEED)
|
||||
#define CH_CFG_OPTIMIZE_SPEED TRUE
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Subsystem options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Time Measurement APIs.
|
||||
* @details If enabled then the time measurement APIs are included in
|
||||
* the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_TM)
|
||||
#define CH_CFG_USE_TM TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Time Stamps APIs.
|
||||
* @details If enabled then the time time stamps APIs are included in
|
||||
* the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_TIMESTAMP)
|
||||
#define CH_CFG_USE_TIMESTAMP TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Threads registry APIs.
|
||||
* @details If enabled then the registry APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_REGISTRY)
|
||||
#define CH_CFG_USE_REGISTRY TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Threads synchronization APIs.
|
||||
* @details If enabled then the @p chThdWait() function is included in
|
||||
* the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_WAITEXIT)
|
||||
#define CH_CFG_USE_WAITEXIT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Semaphores APIs.
|
||||
* @details If enabled then the Semaphores APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_SEMAPHORES)
|
||||
#define CH_CFG_USE_SEMAPHORES TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Semaphores queuing mode.
|
||||
* @details If enabled then the threads are enqueued on semaphores by
|
||||
* priority rather than in FIFO order.
|
||||
*
|
||||
* @note The default is @p FALSE. Enable this if you have special
|
||||
* requirements.
|
||||
* @note Requires @p CH_CFG_USE_SEMAPHORES.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)
|
||||
#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Mutexes APIs.
|
||||
* @details If enabled then the mutexes APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MUTEXES)
|
||||
#define CH_CFG_USE_MUTEXES TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables recursive behavior on mutexes.
|
||||
* @note Recursive mutexes are heavier and have an increased
|
||||
* memory footprint.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)
|
||||
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Conditional Variables APIs.
|
||||
* @details If enabled then the conditional variables APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_CONDVARS)
|
||||
#define CH_CFG_USE_CONDVARS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Conditional Variables APIs with timeout.
|
||||
* @details If enabled then the conditional variables APIs with timeout
|
||||
* specification are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_CONDVARS.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)
|
||||
#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Events Flags APIs.
|
||||
* @details If enabled then the event flags APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_EVENTS)
|
||||
#define CH_CFG_USE_EVENTS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Events Flags APIs with timeout.
|
||||
* @details If enabled then the events APIs with timeout specification
|
||||
* are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_EVENTS.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)
|
||||
#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Synchronous Messages APIs.
|
||||
* @details If enabled then the synchronous messages APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MESSAGES)
|
||||
#define CH_CFG_USE_MESSAGES TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Synchronous Messages queuing mode.
|
||||
* @details If enabled then messages are served by priority rather than in
|
||||
* FIFO order.
|
||||
*
|
||||
* @note The default is @p FALSE. Enable this if you have special
|
||||
* requirements.
|
||||
* @note Requires @p CH_CFG_USE_MESSAGES.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)
|
||||
#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Dynamic Threads APIs.
|
||||
* @details If enabled then the dynamic threads creation APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_WAITEXIT.
|
||||
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_DYNAMIC)
|
||||
#define CH_CFG_USE_DYNAMIC TRUE
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name OSLIB options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Mailboxes APIs.
|
||||
* @details If enabled then the asynchronous messages (mailboxes) APIs are
|
||||
* included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_SEMAPHORES.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MAILBOXES)
|
||||
#define CH_CFG_USE_MAILBOXES TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Memory checks APIs.
|
||||
* @details If enabled then the memory checks APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MEMCHECKS)
|
||||
#define CH_CFG_USE_MEMCHECKS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Core Memory Manager APIs.
|
||||
* @details If enabled then the core memory manager APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MEMCORE)
|
||||
#define CH_CFG_USE_MEMCORE TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Managed RAM size.
|
||||
* @details Size of the RAM area to be managed by the OS. If set to zero
|
||||
* then the whole available RAM is used. The core memory is made
|
||||
* available to the heap allocator and/or can be used directly through
|
||||
* the simplified core memory allocator.
|
||||
*
|
||||
* @note In order to let the OS manage the whole RAM the linker script must
|
||||
* provide the @p __heap_base__ and @p __heap_end__ symbols.
|
||||
* @note Requires @p CH_CFG_USE_MEMCORE.
|
||||
*/
|
||||
#if !defined(CH_CFG_MEMCORE_SIZE)
|
||||
#define CH_CFG_MEMCORE_SIZE 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Heap Allocator APIs.
|
||||
* @details If enabled then the memory heap allocator APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
|
||||
* @p CH_CFG_USE_SEMAPHORES.
|
||||
* @note Mutexes are recommended.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_HEAP)
|
||||
#define CH_CFG_USE_HEAP TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Memory Pools Allocator APIs.
|
||||
* @details If enabled then the memory pools allocator APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MEMPOOLS)
|
||||
#define CH_CFG_USE_MEMPOOLS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Objects FIFOs APIs.
|
||||
* @details If enabled then the objects FIFOs APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_OBJ_FIFOS)
|
||||
#define CH_CFG_USE_OBJ_FIFOS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Pipes APIs.
|
||||
* @details If enabled then the pipes APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_PIPES)
|
||||
#define CH_CFG_USE_PIPES TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Objects Caches APIs.
|
||||
* @details If enabled then the objects caches APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_OBJ_CACHES)
|
||||
#define CH_CFG_USE_OBJ_CACHES TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Delegate threads APIs.
|
||||
* @details If enabled then the delegate threads APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_DELEGATES)
|
||||
#define CH_CFG_USE_DELEGATES TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Jobs Queues APIs.
|
||||
* @details If enabled then the jobs queues APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_JOBS)
|
||||
#define CH_CFG_USE_JOBS TRUE
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Objects factory options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Objects Factory APIs.
|
||||
* @details If enabled then the objects factory APIs are included in the
|
||||
* kernel.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_FACTORY)
|
||||
#define CH_CFG_USE_FACTORY TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Maximum length for object names.
|
||||
* @details If the specified length is zero then the name is stored by
|
||||
* pointer but this could have unintended side effects.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
|
||||
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the registry of generic objects.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
|
||||
#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for generic buffers.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
|
||||
#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for semaphores.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_SEMAPHORES)
|
||||
#define CH_CFG_FACTORY_SEMAPHORES TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for mailboxes.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_MAILBOXES)
|
||||
#define CH_CFG_FACTORY_MAILBOXES TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for objects FIFOs.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
|
||||
#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for Pipes.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)
|
||||
#define CH_CFG_FACTORY_PIPES TRUE
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Debug options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Debug option, kernel statistics.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_STATISTICS)
|
||||
#define CH_DBG_STATISTICS FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, system state check.
|
||||
* @details If enabled the correct call protocol for system APIs is checked
|
||||
* at runtime.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
|
||||
#define CH_DBG_SYSTEM_STATE_CHECK TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, parameters checks.
|
||||
* @details If enabled then the checks on the API functions input
|
||||
* parameters are activated.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_ENABLE_CHECKS)
|
||||
#define CH_DBG_ENABLE_CHECKS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, consistency checks.
|
||||
* @details If enabled then all the assertions in the kernel code are
|
||||
* activated. This includes consistency checks inside the kernel,
|
||||
* runtime anomalies and port-defined checks.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_ENABLE_ASSERTS)
|
||||
#define CH_DBG_ENABLE_ASSERTS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, trace buffer.
|
||||
* @details If enabled then the trace buffer is activated.
|
||||
*
|
||||
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
|
||||
*/
|
||||
#if !defined(CH_DBG_TRACE_MASK)
|
||||
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Trace buffer entries.
|
||||
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
|
||||
* different from @p CH_DBG_TRACE_MASK_DISABLED.
|
||||
*/
|
||||
#if !defined(CH_DBG_TRACE_BUFFER_SIZE)
|
||||
#define CH_DBG_TRACE_BUFFER_SIZE 128
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, stack checks.
|
||||
* @details If enabled then a runtime stack check is performed.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note The stack check is performed in a architecture/port dependent way.
|
||||
* It may not be implemented or some ports.
|
||||
* @note The default failure mode is to halt the system with the global
|
||||
* @p panic_msg variable set to @p NULL.
|
||||
*/
|
||||
#if !defined(CH_DBG_ENABLE_STACK_CHECK)
|
||||
#define CH_DBG_ENABLE_STACK_CHECK TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, stacks initialization.
|
||||
* @details If enabled then the threads working area is filled with a byte
|
||||
* value when a thread is created. This can be useful for the
|
||||
* runtime measurement of the used stack.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_FILL_THREADS)
|
||||
#define CH_DBG_FILL_THREADS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, threads profiling.
|
||||
* @details If enabled then a field is added to the @p thread_t structure that
|
||||
* counts the system ticks occurred while executing the thread.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note This debug option is not currently compatible with the
|
||||
* tickless mode.
|
||||
*/
|
||||
#if !defined(CH_DBG_THREADS_PROFILING)
|
||||
#define CH_DBG_THREADS_PROFILING FALSE
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Kernel hooks
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System structure extension.
|
||||
* @details User fields added to the end of the @p ch_system_t structure.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_EXTRA_FIELDS \
|
||||
/* Add system custom fields here.*/
|
||||
|
||||
/**
|
||||
* @brief System initialization hook.
|
||||
* @details User initialization code added to the @p chSysInit() function
|
||||
* just before interrupts are enabled globally.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_INIT_HOOK() { \
|
||||
/* Add system initialization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief OS instance structure extension.
|
||||
* @details User fields added to the end of the @p os_instance_t structure.
|
||||
*/
|
||||
#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \
|
||||
/* Add OS instance custom fields here.*/
|
||||
|
||||
/**
|
||||
* @brief OS instance initialization hook.
|
||||
*
|
||||
* @param[in] oip pointer to the @p os_instance_t structure
|
||||
*/
|
||||
#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \
|
||||
/* Add OS instance initialization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Threads descriptor structure extension.
|
||||
* @details User fields added to the end of the @p thread_t structure.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXTRA_FIELDS \
|
||||
/* Add threads custom fields here.*/
|
||||
|
||||
/**
|
||||
* @brief Threads initialization hook.
|
||||
* @details User initialization code added to the @p _thread_init() function.
|
||||
*
|
||||
* @note It is invoked from within @p _thread_init() and implicitly from all
|
||||
* the threads creation APIs.
|
||||
*/
|
||||
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
|
||||
/* Add threads initialization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Threads finalization hook.
|
||||
* @details User finalization code added to the @p chThdExit() API.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
|
||||
/* Add threads finalization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Context switch hook.
|
||||
* @details This hook is invoked just before switching between threads.
|
||||
*/
|
||||
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
|
||||
/* Context switch code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ISR enter hook.
|
||||
*/
|
||||
#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
|
||||
/* IRQ prologue code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ISR exit hook.
|
||||
*/
|
||||
#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
|
||||
/* IRQ epilogue code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Idle thread enter hook.
|
||||
* @note This hook is invoked within a critical zone, no OS functions
|
||||
* should be invoked from here.
|
||||
* @note This macro can be used to activate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_ENTER_HOOK() { \
|
||||
/* Idle-enter code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Idle thread leave hook.
|
||||
* @note This hook is invoked within a critical zone, no OS functions
|
||||
* should be invoked from here.
|
||||
* @note This macro can be used to deactivate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_LEAVE_HOOK() { \
|
||||
/* Idle-leave code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Idle Loop hook.
|
||||
* @details This hook is continuously invoked by the idle thread loop.
|
||||
*/
|
||||
#define CH_CFG_IDLE_LOOP_HOOK() { \
|
||||
/* Idle loop code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System tick event hook.
|
||||
* @details This hook is invoked in the system tick handler immediately
|
||||
* after processing the virtual timers queue.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_TICK_HOOK() { \
|
||||
/* System tick event code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System halt hook.
|
||||
* @details This hook is invoked in case to a system halting error before
|
||||
* the system is halted.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
|
||||
/* System halt code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Trace hook.
|
||||
* @details This hook is invoked each time a new record is written in the
|
||||
* trace buffer.
|
||||
*/
|
||||
#define CH_CFG_TRACE_HOOK(tep) { \
|
||||
/* Trace code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Runtime Faults Collection Unit hook.
|
||||
* @details This hook is invoked each time new faults are collected and stored.
|
||||
*/
|
||||
#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \
|
||||
/* Faults handling code here.*/ \
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Port-specific settings (override port settings defaulted in chcore.h). */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* CHCONF_H */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,531 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file templates/halconf.h
|
||||
* @brief HAL configuration header.
|
||||
* @details HAL configuration file, this file allows to enable or disable the
|
||||
* various device drivers from your application. You may also use
|
||||
* this file in order to override the device drivers default settings.
|
||||
*
|
||||
* @addtogroup HAL_CONF
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef HALCONF_H
|
||||
#define HALCONF_H
|
||||
|
||||
#define _CHIBIOS_HAL_CONF_
|
||||
#define _CHIBIOS_HAL_CONF_VER_8_0_
|
||||
|
||||
#include "mcuconf.h"
|
||||
|
||||
/**
|
||||
* @brief Enables the PAL subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_PAL TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ADC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_ADC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the CAN subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CAN FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the cryptographic subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CRY FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the DAC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_DAC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the EFlash subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_EFL FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the GPT subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_GPT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the I2C subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_I2C FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the I2S subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_I2S FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ICU subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_ICU FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the MAC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_MAC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the MMC_SPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_MMC_SPI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the PWM subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_PWM FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the RTC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_RTC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SDC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SDC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SERIAL subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SERIAL FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SERIAL over USB subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SERIAL_USB FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SIO subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SIO FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SPI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the TRNG subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_TRNG FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the UART subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_UART FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the USB subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_USB FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the WDG subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_WDG FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the WSPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_WSPI FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* PAL driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
|
||||
#define PAL_USE_CALLBACKS TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define PAL_USE_WAIT TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* ADC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define ADC_USE_WAIT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define ADC_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* CAN driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Sleep mode related APIs inclusion switch.
|
||||
*/
|
||||
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
|
||||
#define CAN_USE_SLEEP_MODE TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
|
||||
*/
|
||||
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
|
||||
#define CAN_ENFORCE_USE_CALLBACKS FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* CRY driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the SW fall-back of the cryptographic driver.
|
||||
* @details When enabled, this option, activates a fall-back software
|
||||
* implementation for algorithms not supported by the underlying
|
||||
* hardware.
|
||||
* @note Fall-back implementations may not be present for all algorithms.
|
||||
*/
|
||||
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_USE_FALLBACK FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Makes the driver forcibly use the fall-back implementations.
|
||||
*/
|
||||
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_ENFORCE_FALLBACK FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* DAC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define DAC_USE_WAIT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define DAC_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I2C driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the mutual exclusion APIs on the I2C bus.
|
||||
*/
|
||||
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define I2C_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* MAC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the zero-copy API.
|
||||
*/
|
||||
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
|
||||
#define MAC_USE_ZERO_COPY FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables an event sources for incoming packets.
|
||||
*/
|
||||
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
|
||||
#define MAC_USE_EVENTS TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* MMC_SPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Delays insertions.
|
||||
* @details If enabled this options inserts delays into the MMC waiting
|
||||
* routines releasing some extra CPU time for the threads with
|
||||
* lower priority, this may slow down the driver a bit however.
|
||||
* This option is recommended also if the SPI driver does not
|
||||
* use a DMA channel and heavily loads the CPU.
|
||||
*/
|
||||
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||
#define MMC_NICE_WAITING TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SDC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Number of initialization attempts before rejecting the card.
|
||||
* @note Attempts are performed at 10mS intervals.
|
||||
*/
|
||||
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
|
||||
#define SDC_INIT_RETRY 100
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Include support for MMC cards.
|
||||
* @note MMC support is not yet implemented so this option must be kept
|
||||
* at @p FALSE.
|
||||
*/
|
||||
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
|
||||
#define SDC_MMC_SUPPORT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Delays insertions.
|
||||
* @details If enabled this options inserts delays into the MMC waiting
|
||||
* routines releasing some extra CPU time for the threads with
|
||||
* lower priority, this may slow down the driver a bit however.
|
||||
*/
|
||||
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||
#define SDC_NICE_WAITING TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief OCR initialization constant for V20 cards.
|
||||
*/
|
||||
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
|
||||
#define SDC_INIT_OCR_V20 0x50FF8000U
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief OCR initialization constant for non-V20 cards.
|
||||
*/
|
||||
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
|
||||
#define SDC_INIT_OCR 0x80100000U
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SERIAL driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Default bit rate.
|
||||
* @details Configuration parameter, this is the baud rate selected for the
|
||||
* default configuration.
|
||||
*/
|
||||
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_DEFAULT_BITRATE 38400
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Serial buffers size.
|
||||
* @details Configuration parameter, you can change the depth of the queue
|
||||
* buffers depending on the requirements of your application.
|
||||
* @note The default is 16 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_BUFFERS_SIZE 16
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SERIAL_USB driver related setting. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Serial over USB buffers size.
|
||||
* @details Configuration parameter, the buffer size must be a multiple of
|
||||
* the USB data endpoint maximum packet size.
|
||||
* @note The default is 256 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_SIZE 256
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Serial over USB number of buffers.
|
||||
* @note The default is 2 buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_NUMBER 2
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define SPI_USE_WAIT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables circular transfers APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
|
||||
#define SPI_USE_CIRCULAR FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define SPI_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Handling method for SPI CS line.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
|
||||
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* UART driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define UART_USE_WAIT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define UART_USE_MUTUAL_EXCLUSION FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* USB driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define USB_USE_WAIT FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* WSPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define WSPI_USE_WAIT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
#endif /* HALCONF_H */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
#define WB32FQ95xx_MCUCONF TRUE
|
||||
|
||||
/*
|
||||
* WB32FQ95 drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @name Internal clock sources
|
||||
* @{
|
||||
*/
|
||||
#define WB32_HSECLK 12000000
|
||||
#define WB32_LSECLK 32768
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define WB32_NO_INIT FALSE
|
||||
#define WB32_MHSI_ENABLED TRUE
|
||||
#define WB32_FHSI_ENABLED FALSE
|
||||
#define WB32_LSI_ENABLED FALSE
|
||||
#define WB32_HSE_ENABLED TRUE
|
||||
#define WB32_LSE_ENABLED FALSE
|
||||
#define WB32_PLL_ENABLED TRUE
|
||||
#define WB32_MAINCLKSRC WB32_MAINCLKSRC_PLL
|
||||
#define WB32_PLLSRC WB32_PLLSRC_HSE
|
||||
#define WB32_PLLDIV_VALUE 2
|
||||
#define WB32_PLLMUL_VALUE 12 // The allowed range is 12,16,20,24.
|
||||
#define WB32_HPRE 1
|
||||
#define WB32_PPRE1 1
|
||||
#define WB32_PPRE2 1
|
||||
#define WB32_USBPRE WB32_USBPRE_DIV1P5
|
||||
|
||||
/*
|
||||
* EXTI driver system settings.
|
||||
*/
|
||||
#define WB32_IRQ_EXTI0_PRIORITY 6
|
||||
#define WB32_IRQ_EXTI1_PRIORITY 6
|
||||
#define WB32_IRQ_EXTI2_PRIORITY 6
|
||||
#define WB32_IRQ_EXTI3_PRIORITY 6
|
||||
#define WB32_IRQ_EXTI4_PRIORITY 6
|
||||
#define WB32_IRQ_EXTI5_9_PRIORITY 6
|
||||
#define WB32_IRQ_EXTI10_15_PRIORITY 6
|
||||
#define WB32_IRQ_EXTI16_PRIORITY 6
|
||||
#define WB32_IRQ_EXTI17_PRIORITY 6
|
||||
#define WB32_IRQ_EXTI18_PRIORITY 6
|
||||
#define WB32_IRQ_EXTI19_PRIORITY 6
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define WB32_TIM_MAX_CHANNELS 4
|
||||
#define WB32_GPT_USE_TIM1 FALSE
|
||||
#define WB32_GPT_USE_TIM2 FALSE
|
||||
#define WB32_GPT_USE_TIM3 FALSE
|
||||
#define WB32_GPT_USE_TIM4 FALSE
|
||||
#define WB32_GPT_TIM1_IRQ_PRIORITY 7
|
||||
#define WB32_GPT_TIM2_IRQ_PRIORITY 7
|
||||
#define WB32_GPT_TIM3_IRQ_PRIORITY 7
|
||||
#define WB32_GPT_TIM4_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define WB32_ICU_USE_TIM1 FALSE
|
||||
#define WB32_ICU_USE_TIM2 FALSE
|
||||
#define WB32_ICU_USE_TIM3 FALSE
|
||||
#define WB32_ICU_USE_TIM4 FALSE
|
||||
#define WB32_ICU_TIM1_IRQ_PRIORITY 7
|
||||
#define WB32_ICU_TIM2_IRQ_PRIORITY 7
|
||||
#define WB32_ICU_TIM3_IRQ_PRIORITY 7
|
||||
#define WB32_ICU_TIM4_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define WB32_PWM_USE_ADVANCED FALSE
|
||||
#define WB32_PWM_USE_TIM1 FALSE
|
||||
#define WB32_PWM_USE_TIM2 FALSE
|
||||
#define WB32_PWM_USE_TIM3 FALSE
|
||||
#define WB32_PWM_USE_TIM4 FALSE
|
||||
#define WB32_PWM_TIM1_IRQ_PRIORITY 7
|
||||
#define WB32_PWM_TIM2_IRQ_PRIORITY 7
|
||||
#define WB32_PWM_TIM3_IRQ_PRIORITY 7
|
||||
#define WB32_PWM_TIM4_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define WB32_I2C_USE_I2C1 FALSE
|
||||
#define WB32_I2C_USE_I2C2 FALSE
|
||||
#define WB32_I2C_BUSY_TIMEOUT 50
|
||||
#define WB32_I2C_I2C1_IRQ_PRIORITY 5
|
||||
#define WB32_I2C_I2C2_IRQ_PRIORITY 5
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define WB32_SERIAL_USE_UART1 FALSE
|
||||
#define WB32_SERIAL_USE_UART2 FALSE
|
||||
#define WB32_SERIAL_USE_UART3 FALSE
|
||||
#define WB32_SERIAL_USART1_PRIORITY 12
|
||||
#define WB32_SERIAL_USART2_PRIORITY 12
|
||||
#define WB32_SERIAL_USART3_PRIORITY 12
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define WB32_SPI_USE_QSPI FALSE
|
||||
#define WB32_SPI_USE_SPIM2 FALSE
|
||||
#define WB32_SPI_USE_SPIS1 FALSE
|
||||
#define WB32_SPI_USE_SPIS2 FALSE
|
||||
#define WB32_SPI_QSPI_IRQ_PRIORITY 10
|
||||
#define WB32_SPI_SPIM2_IRQ_PRIORITY 10
|
||||
#define WB32_SPI_SPIS1_IRQ_PRIORITY 10
|
||||
#define WB32_SPI_SPIS2_IRQ_PRIORITY 10
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define WB32_ST_IRQ_PRIORITY 8
|
||||
#define WB32_ST_USE_TIMER 2
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define WB32_UART_USE_UART1 FALSE
|
||||
#define WB32_UART_USE_UART2 FALSE
|
||||
#define WB32_UART_USE_UART3 FALSE
|
||||
#define WB32_UART_UART1_IRQ_PRIORITY 12
|
||||
#define WB32_UART_UART2_IRQ_PRIORITY 12
|
||||
#define WB32_UART_UART3_IRQ_PRIORITY 12
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define WB32_USB_USE_USB1 TRUE
|
||||
#define WB32_USB_USB1_IRQ_PRIORITY 13
|
||||
#define WB32_USB_HOST_WAKEUP_DURATION 10
|
||||
|
||||
|
||||
#endif /* MCUCONF_H */
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,124 @@
|
|||
/*
|
||||
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
#include "board.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Private variables. */
|
||||
/*===========================================================================*/
|
||||
/*===========================================================================*/
|
||||
/* Generic code. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#define PORTAB_LINE_LED1 PAL_LINE(GPIOB, 14U)
|
||||
#define PORTAB_LINE_LED2 PAL_LINE(GPIOB, 13U)
|
||||
#define PORTAB_LED_OFF PAL_HIGH
|
||||
#define PORTAB_LED_ON AL_LOW
|
||||
|
||||
#define PORTAB_LINE_BUTTON PAL_LINE(GPIOA, 0U)
|
||||
#define PORTAB_BUTTON_PRESSED PAL_LOW
|
||||
|
||||
#if defined(PORTAB_LINE_LED2)
|
||||
/*
|
||||
* LED blinker thread, times are in milliseconds.
|
||||
*/
|
||||
static THD_WORKING_AREA(waThread1, 128);
|
||||
static THD_FUNCTION(Thread1, arg)
|
||||
{
|
||||
(void)arg;
|
||||
chRegSetThreadName("blinker");
|
||||
while (true)
|
||||
{
|
||||
systime_t time = palReadLine(PORTAB_LINE_BUTTON) == PORTAB_BUTTON_PRESSED ? 250 : 500;
|
||||
palToggleLine(PORTAB_LINE_LED2);
|
||||
chThdSleepMilliseconds(time);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if PAL_USE_WAIT || defined(__DOXYGEN__)
|
||||
|
||||
/**
|
||||
* @brief Configure PORTAB_LINE_BUTTON in interrupt mode
|
||||
* @param None
|
||||
* @return None
|
||||
*/
|
||||
void EXTI0_Config(void)
|
||||
{
|
||||
/*
|
||||
* Init button port and pad.
|
||||
*/
|
||||
palSetPadMode(PAL_PORT(PORTAB_LINE_BUTTON), PAL_PAD(PORTAB_LINE_BUTTON), PAL_WB32_MODE_INPUT | PAL_WB32_PUPDR_PULLDOWN);
|
||||
|
||||
/*
|
||||
* Enabling events on both edges of the button line.
|
||||
*/
|
||||
palEnableLineEvent(PORTAB_LINE_BUTTON, PAL_EVENT_MODE_RISING_EDGE);
|
||||
|
||||
/*
|
||||
* Configure the interrupt priority.
|
||||
*/
|
||||
nvicEnableVector(EXTI0_IRQn, WB32_IRQ_EXTI0_PRIORITY);
|
||||
}
|
||||
|
||||
/*
|
||||
* Application entry point.
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
/*
|
||||
* System initializations.
|
||||
* - HAL initialization, this also initializes the configured device drivers
|
||||
* and performs the board-specific initializations.
|
||||
* - Kernel initialization, the main() function becomes a thread and the
|
||||
* RTOS is active.
|
||||
*/
|
||||
halInit();
|
||||
chSysInit();
|
||||
|
||||
/*
|
||||
* Init LED port and pad.
|
||||
*/
|
||||
palSetPadMode(PAL_PORT(PORTAB_LINE_LED1), PAL_PAD(PORTAB_LINE_LED1), PAL_WB32_MODE_OUTPUT | PAL_WB32_OTYPE_PUSHPULL);
|
||||
palSetPadMode(PAL_PORT(PORTAB_LINE_LED2), PAL_PAD(PORTAB_LINE_LED2), PAL_WB32_MODE_OUTPUT | PAL_WB32_OTYPE_PUSHPULL);
|
||||
|
||||
/*
|
||||
* Configure PA0 in interrupt mode
|
||||
*/
|
||||
EXTI0_Config();
|
||||
|
||||
#if defined(PORTAB_LINE_LED2)
|
||||
/*
|
||||
* Creates the blinker thread.
|
||||
*/
|
||||
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Normal main() thread activity.
|
||||
*/
|
||||
while (true)
|
||||
{
|
||||
/* Waiting for an edge on the button.*/
|
||||
palWaitLineTimeout(PORTAB_LINE_BUTTON, TIME_INFINITE);
|
||||
|
||||
palToggleLine(PORTAB_LINE_LED1);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* PAL_USE_WAIT */
|
|
@ -0,0 +1,4 @@
|
|||
# WB32FQ95xx Serial MCU Demo
|
||||
|
||||
This is an example.
|
||||
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* WB32FQ95x9 memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash0 (rx) : org = 0x08000000, len = 96k
|
||||
flash1 (rx) : org = 0x00000000, len = 0
|
||||
flash2 (rx) : org = 0x00000000, len = 0
|
||||
flash3 (rx) : org = 0x00000000, len = 0
|
||||
flash4 (rx) : org = 0x00000000, len = 0
|
||||
flash5 (rx) : org = 0x00000000, len = 0
|
||||
flash6 (rx) : org = 0x00000000, len = 0
|
||||
flash7 (rx) : org = 0x00000000, len = 0
|
||||
ram0 (wx) : org = 0x20000000, len = 28k
|
||||
ram1 (wx) : org = 0x00000000, len = 0
|
||||
ram2 (wx) : org = 0x00000000, len = 0
|
||||
ram3 (wx) : org = 0x00000000, len = 0
|
||||
ram4 (wx) : org = 0x00000000, len = 0
|
||||
ram5 (wx) : org = 0x00000000, len = 0
|
||||
ram6 (wx) : org = 0x00000000, len = 0
|
||||
ram7 (wx) : org = 0x00000000, len = 0
|
||||
}
|
||||
|
||||
/* For each data/text section two region are defined, a virtual region
|
||||
and a load region (_LMA suffix).*/
|
||||
|
||||
/* Flash region to be used for exception vectors.*/
|
||||
REGION_ALIAS("VECTORS_FLASH", flash0);
|
||||
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for constructors and destructors.*/
|
||||
REGION_ALIAS("XTORS_FLASH", flash0);
|
||||
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for code text.*/
|
||||
REGION_ALIAS("TEXT_FLASH", flash0);
|
||||
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for read only data.*/
|
||||
REGION_ALIAS("RODATA_FLASH", flash0);
|
||||
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for various.*/
|
||||
REGION_ALIAS("VARIOUS_FLASH", flash0);
|
||||
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for RAM(n) initialization data.*/
|
||||
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
|
||||
|
||||
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||
of all exceptions and interrupts.*/
|
||||
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for the process stack. This is the stack used by
|
||||
the main() function.*/
|
||||
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for data segment.*/
|
||||
REGION_ALIAS("DATA_RAM", ram0);
|
||||
REGION_ALIAS("DATA_RAM_LMA", flash0);
|
||||
|
||||
/* RAM region to be used for BSS segment.*/
|
||||
REGION_ALIAS("BSS_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for the default heap.*/
|
||||
REGION_ALIAS("HEAP_RAM", ram0);
|
||||
|
||||
/* Generic rules inclusion.*/
|
||||
INCLUDE rules.ld
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* WB32FQ95xB memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash0 (rx) : org = 0x08000000, len = 128k
|
||||
flash1 (rx) : org = 0x00000000, len = 0
|
||||
flash2 (rx) : org = 0x00000000, len = 0
|
||||
flash3 (rx) : org = 0x00000000, len = 0
|
||||
flash4 (rx) : org = 0x00000000, len = 0
|
||||
flash5 (rx) : org = 0x00000000, len = 0
|
||||
flash6 (rx) : org = 0x00000000, len = 0
|
||||
flash7 (rx) : org = 0x00000000, len = 0
|
||||
ram0 (wx) : org = 0x20000000, len = 28k
|
||||
ram1 (wx) : org = 0x00000000, len = 0
|
||||
ram2 (wx) : org = 0x00000000, len = 0
|
||||
ram3 (wx) : org = 0x00000000, len = 0
|
||||
ram4 (wx) : org = 0x00000000, len = 0
|
||||
ram5 (wx) : org = 0x00000000, len = 0
|
||||
ram6 (wx) : org = 0x00000000, len = 0
|
||||
ram7 (wx) : org = 0x00000000, len = 0
|
||||
}
|
||||
|
||||
/* For each data/text section two region are defined, a virtual region
|
||||
and a load region (_LMA suffix).*/
|
||||
|
||||
/* Flash region to be used for exception vectors.*/
|
||||
REGION_ALIAS("VECTORS_FLASH", flash0);
|
||||
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for constructors and destructors.*/
|
||||
REGION_ALIAS("XTORS_FLASH", flash0);
|
||||
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for code text.*/
|
||||
REGION_ALIAS("TEXT_FLASH", flash0);
|
||||
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for read only data.*/
|
||||
REGION_ALIAS("RODATA_FLASH", flash0);
|
||||
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for various.*/
|
||||
REGION_ALIAS("VARIOUS_FLASH", flash0);
|
||||
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for RAM(n) initialization data.*/
|
||||
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
|
||||
|
||||
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||
of all exceptions and interrupts.*/
|
||||
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for the process stack. This is the stack used by
|
||||
the main() function.*/
|
||||
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for data segment.*/
|
||||
REGION_ALIAS("DATA_RAM", ram0);
|
||||
REGION_ALIAS("DATA_RAM_LMA", flash0);
|
||||
|
||||
/* RAM region to be used for BSS segment.*/
|
||||
REGION_ALIAS("BSS_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for the default heap.*/
|
||||
REGION_ALIAS("HEAP_RAM", ram0);
|
||||
|
||||
/* Generic rules inclusion.*/
|
||||
INCLUDE rules.ld
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* WB32FQ95xC memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash0 (rx) : org = 0x08000000, len = 256k
|
||||
flash1 (rx) : org = 0x00000000, len = 0
|
||||
flash2 (rx) : org = 0x00000000, len = 0
|
||||
flash3 (rx) : org = 0x00000000, len = 0
|
||||
flash4 (rx) : org = 0x00000000, len = 0
|
||||
flash5 (rx) : org = 0x00000000, len = 0
|
||||
flash6 (rx) : org = 0x00000000, len = 0
|
||||
flash7 (rx) : org = 0x00000000, len = 0
|
||||
ram0 (wx) : org = 0x20000000, len = 36k
|
||||
ram1 (wx) : org = 0x00000000, len = 0
|
||||
ram2 (wx) : org = 0x00000000, len = 0
|
||||
ram3 (wx) : org = 0x00000000, len = 0
|
||||
ram4 (wx) : org = 0x00000000, len = 0
|
||||
ram5 (wx) : org = 0x00000000, len = 0
|
||||
ram6 (wx) : org = 0x00000000, len = 0
|
||||
ram7 (wx) : org = 0x00000000, len = 0
|
||||
}
|
||||
|
||||
/* For each data/text section two region are defined, a virtual region
|
||||
and a load region (_LMA suffix).*/
|
||||
|
||||
/* Flash region to be used for exception vectors.*/
|
||||
REGION_ALIAS("VECTORS_FLASH", flash0);
|
||||
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for constructors and destructors.*/
|
||||
REGION_ALIAS("XTORS_FLASH", flash0);
|
||||
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for code text.*/
|
||||
REGION_ALIAS("TEXT_FLASH", flash0);
|
||||
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for read only data.*/
|
||||
REGION_ALIAS("RODATA_FLASH", flash0);
|
||||
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for various.*/
|
||||
REGION_ALIAS("VARIOUS_FLASH", flash0);
|
||||
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for RAM(n) initialization data.*/
|
||||
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
|
||||
|
||||
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||
of all exceptions and interrupts.*/
|
||||
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for the process stack. This is the stack used by
|
||||
the main() function.*/
|
||||
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for data segment.*/
|
||||
REGION_ALIAS("DATA_RAM", ram0);
|
||||
REGION_ALIAS("DATA_RAM_LMA", flash0);
|
||||
|
||||
/* RAM region to be used for BSS segment.*/
|
||||
REGION_ALIAS("BSS_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for the default heap.*/
|
||||
REGION_ALIAS("HEAP_RAM", ram0);
|
||||
|
||||
/* Generic rules inclusion.*/
|
||||
INCLUDE rules.ld
|
|
@ -0,0 +1,19 @@
|
|||
# List of the ChibiOS generic WB32FQ95xx startup and CMSIS files.
|
||||
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
|
||||
|
||||
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
|
||||
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
|
||||
|
||||
STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
|
||||
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \
|
||||
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/WB32FQ95xx \
|
||||
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
|
||||
$(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/WB32/WB32FQ95xx
|
||||
|
||||
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
|
||||
STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
|
||||
|
||||
# Shared variables
|
||||
ALLXASMSRC += $(STARTUPASM)
|
||||
ALLCSRC += $(STARTUPSRC)
|
||||
ALLINC += $(STARTUPINC)
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
|
||||
(C) 2015 RedoX https://github.com/RedoXyde
|
||||
(C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file WB32FQ95xx/cmparams.h
|
||||
* @brief ARM Cortex-M3 parameters for the Westberry WB32FQ95xx
|
||||
*
|
||||
* @defgroup ARMCMx_WB32FQ95xx Westberry WB32FQ95xx Specific Parameters
|
||||
* @ingroup ARMCMx_SPECIFIC
|
||||
* @details This file contains the Cortex-M3 specific parameters for the
|
||||
* Westberry WB32FQ95xx platform.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _CMPARAMS_H_
|
||||
#define _CMPARAMS_H_
|
||||
|
||||
/**
|
||||
* @brief Cortex core model.
|
||||
*/
|
||||
#define CORTEX_MODEL 3
|
||||
|
||||
/**
|
||||
* @brief Systick unit presence.
|
||||
*/
|
||||
#define CORTEX_HAS_ST TRUE
|
||||
|
||||
/**
|
||||
* @brief Floating Point unit presence.
|
||||
*/
|
||||
#define CORTEX_HAS_FPU FALSE
|
||||
|
||||
/**
|
||||
* @brief Number of bits in priority masks.
|
||||
*/
|
||||
#define CORTEX_PRIORITY_BITS 4
|
||||
|
||||
/**
|
||||
* @brief Number of interrupt vectors.
|
||||
* @note This number does not include the 16 system vectors and must be
|
||||
* rounded to a multiple of 8.
|
||||
*/
|
||||
#define CORTEX_NUM_VECTORS 40
|
||||
|
||||
/* The following code is not processed when the file is included from an
|
||||
asm module.*/
|
||||
#if !defined(_FROM_ASM_)
|
||||
|
||||
#if !defined (WB32FQ95xx)
|
||||
#include "board.h"
|
||||
#endif
|
||||
|
||||
/* Including the device CMSIS header. Note, we are not using the definitions
|
||||
from this header because we need this file to be usable also from
|
||||
assembler source files. We verify that the info matches instead.*/
|
||||
#include "wb32fq95xx.h"
|
||||
|
||||
#if CORTEX_MODEL != __CORTEX_M
|
||||
#error "CMSIS __CORTEX_M mismatch"
|
||||
#endif
|
||||
|
||||
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
|
||||
#error "CMSIS __NVIC_PRIO_BITS mismatch"
|
||||
#endif
|
||||
|
||||
#endif /* !defined(_FROM_ASM_) */
|
||||
|
||||
#endif /* _CMPARAMS_H_ */
|
||||
|
||||
/** @} */
|
|
@ -106,7 +106,7 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) {
|
|||
* @notapi
|
||||
*/
|
||||
static void i2c_lld_configuration(I2CDriver *i2cp) {
|
||||
I2C_TypeDef *dp = i2cp->i2c;
|
||||
I2C_TypeDef *dp = i2cp->i2c;
|
||||
float tclk, tval;
|
||||
uint32_t con_reg;
|
||||
i2copmode_t opmode = i2cp->config->op_mode;
|
||||
|
@ -150,7 +150,7 @@ static void i2c_lld_configuration(I2CDriver *i2cp) {
|
|||
dp->FS_SCL_LCNT = (uint32_t)(tval - 1);
|
||||
}
|
||||
|
||||
dp->CON = con_reg;
|
||||
dp->CON = con_reg;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -400,7 +400,7 @@ void i2c_lld_stop(I2CDriver *i2cp) {
|
|||
|
||||
/**
|
||||
* @brief Receives data via the I2C bus as master.
|
||||
* @details Number of receiving bytes must be more than 1 on WB32F3G71x.
|
||||
* @details Number of receiving bytes must be more than 1.
|
||||
* This is hardware restriction.
|
||||
*
|
||||
* @param[in] i2cp pointer to the @p I2CDriver object
|
||||
|
@ -427,7 +427,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
|||
I2C_TypeDef *dp = i2cp->i2c;
|
||||
msg_t msg;
|
||||
|
||||
#if defined(WB32F3G71xx_I2C)
|
||||
#if defined(WB32_I2C)
|
||||
osalDbgCheck(rxbytes > 0);
|
||||
#endif
|
||||
/* Resetting error flags for this transfer.*/
|
||||
|
@ -472,7 +472,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
|||
|
||||
/**
|
||||
* @brief Transmits data via the I2C bus as master.
|
||||
* @details Number of receiving bytes must be 0 or more than 1 on WB32F3G71x.
|
||||
* @details Number of receiving bytes must be 0 or more than 1.
|
||||
* This is hardware restriction.
|
||||
*
|
||||
* @param[in] i2cp pointer to the @p I2CDriver object
|
||||
|
@ -503,7 +503,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
|||
I2C_TypeDef *dp = i2cp->i2c;
|
||||
__IO msg_t msg;
|
||||
|
||||
#if defined(WB32F3G71xx_I2C)
|
||||
#if defined(WB32_I2C)
|
||||
osalDbgCheck((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL)));
|
||||
#endif
|
||||
/* Resetting error flags for this transfer.*/
|
||||
|
|
|
@ -82,8 +82,8 @@
|
|||
#define WB32_I2C_I2C2_IRQ_PRIORITY 10
|
||||
#endif
|
||||
|
||||
#if defined(WB32F3G71xx)
|
||||
#define WB32F3G71xx_I2C
|
||||
#if defined(WB32F3G71xx) || defined(WB32FQ95xx)
|
||||
#define WB32_I2C
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
|
@ -136,22 +136,22 @@ typedef struct {
|
|||
volatile uint32_t rx_cmd_len;
|
||||
uint32_t tx_abrt_source;
|
||||
} i2c_xfer_info_t;
|
||||
|
||||
|
||||
typedef enum {
|
||||
OPMODE_I2C = 1,
|
||||
OPMODE_SMBUS_DEVICE = 2,
|
||||
OPMODE_SMBUS_HOST = 3,
|
||||
} i2copmode_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Type of I2C driver configuration structure.
|
||||
*/
|
||||
typedef struct {
|
||||
/* End of the mandatory fields.*/
|
||||
/* End of the mandatory fields.*/
|
||||
i2copmode_t op_mode; /**< @brief Specifies the I2C mode. */
|
||||
uint32_t clock_speed; /**< @brief Specifies the clock frequency.
|
||||
@note Must be set to a value lower
|
||||
than 400kHz. */
|
||||
than 400kHz. */
|
||||
} I2CConfig;
|
||||
|
||||
/**
|
||||
|
|
|
@ -52,7 +52,7 @@
|
|||
#define ST_NUMBER WB32_TIM2_NUMBER
|
||||
#define ST_CLOCK_SRC WB32_TIMCLK1
|
||||
#define ST_ENABLE_CLOCK() rccEnableTIM2()
|
||||
#if defined(WB32F3G71xx)
|
||||
#if defined(WB32F3G71xx) || defined(WB32FQ95xx)
|
||||
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP
|
||||
#endif
|
||||
|
||||
|
@ -70,7 +70,7 @@
|
|||
#define ST_NUMBER WB32_TIM3_NUMBER
|
||||
#define ST_CLOCK_SRC WB32_TIMCLK1
|
||||
#define ST_ENABLE_CLOCK() rccEnableTIM3()
|
||||
#if defined(WB32F3G71xx)
|
||||
#if defined(WB32F3G71xx) || defined(WB32FQ95xx)
|
||||
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM3_STOP
|
||||
#endif
|
||||
|
||||
|
@ -88,7 +88,7 @@
|
|||
#define ST_NUMBER WB32_TIM4_NUMBER
|
||||
#define ST_CLOCK_SRC WB32_TIMCLK1
|
||||
#define ST_ENABLE_CLOCK() rccEnableTIM4()
|
||||
#if defined(WB32F3G71xx)
|
||||
#if defined(WB32F3G71xx) || defined(WB32FQ95xx)
|
||||
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM4_STOP
|
||||
#endif
|
||||
|
||||
|
|
|
@ -0,0 +1,387 @@
|
|||
/*
|
||||
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file WB32FQ95xx/hal_lld.c
|
||||
* @brief WB32FQ95xx HAL subsystem low level driver source.
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System Clock Frequency (Core Clock)
|
||||
*/
|
||||
uint32_t SystemCoreClock = WB32_MAINCLK;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Low level HAL driver initialization.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void hal_lld_init(void) {
|
||||
|
||||
void SystemCoreClockUpdate(void);
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
* @param None
|
||||
* @return None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void) {
|
||||
|
||||
uint32_t ahbprediv, pllprediv, pllmul, mainclk;
|
||||
|
||||
switch (RCC->MAINCLKSRC) {
|
||||
case 0x00: /* MHSI used as main clock */
|
||||
mainclk = 8000000;
|
||||
break;
|
||||
case 0x01: /* FHSI used as main clock */
|
||||
mainclk = 48000000;
|
||||
break;
|
||||
case 0x03: /* HSE used as main clock */
|
||||
mainclk = WB32_HSECLK;
|
||||
break;
|
||||
case 0x02: /* PLL used as main clock */
|
||||
pllprediv =
|
||||
(((RCC->PLLPRE & (RCC_PLLPRE_RATIO_Msk | RCC_PLLPRE_DIVEN)) + 1) >> 1) + 1;
|
||||
pllmul = (0x03 - ((ANCTL->PLLCR >> 6) & 0x03)) * 4 + 12;
|
||||
if (RCC->PLLSRC == RCC_PLLSRC_HSE) {
|
||||
mainclk = WB32_HSECLK * pllmul / pllprediv;
|
||||
}
|
||||
else {
|
||||
mainclk = 8000000 * pllmul / pllprediv;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
mainclk = 8000000;
|
||||
break;
|
||||
}
|
||||
|
||||
ahbprediv =
|
||||
(((RCC->AHBPRE & (RCC_AHBPRE_RATIO_Msk | RCC_AHBPRE_DIVEN)) + 1) >> 1) + 1;
|
||||
SystemCoreClock = mainclk / ahbprediv;
|
||||
}
|
||||
|
||||
#if defined(WB32FQ95xx)
|
||||
|
||||
/**
|
||||
* @brief Configures the main clock frequency, AHBCLK, APB1CLK and APB2CLK prescalers.
|
||||
* @note This function should be used only after reset.
|
||||
* @param None
|
||||
* @return None
|
||||
*/
|
||||
static void SetSysClock(void) {
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
/* Unlocks write to ANCTL registers */
|
||||
PWR->ANAKEY1 = 0x03;
|
||||
PWR->ANAKEY2 = 0x0C;
|
||||
|
||||
/* APB1CLK = MAINCLK / WB32_PPRE1*/
|
||||
RCC->APB1PRE = RCC_APB1PRE_SRCEN;
|
||||
#if WB32_PPRE1 == 1
|
||||
RCC->APB1PRE |= 0x00;
|
||||
#else
|
||||
RCC->APB1PRE |= (WB32_PPRE1 - 2);
|
||||
RCC->APB1PRE |= 0x01;
|
||||
#endif /* WB32_PPRE1 == 1 */
|
||||
|
||||
#if WB32_HSE_ENABLED == TRUE
|
||||
/* Configure PD0 and PD1 to analog mode */
|
||||
RCC->APB1ENR = RCC_APB1ENR_BMX1EN | RCC_APB1ENR_GPIODEN;
|
||||
GPIOD->CFGMSK = 0xFFFC;
|
||||
GPIOD->MODER = 0x0F;
|
||||
|
||||
/* Enable HSE */
|
||||
ANCTL->HSECR1 = ANCTL_HSECR1_PADOEN;
|
||||
ANCTL->HSECR0 = ANCTL_HSECR0_HSEON;
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do {
|
||||
HSEStatus = ANCTL->HSESR & ANCTL_HSESR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if (HSEStatus == 0) {
|
||||
/* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error */
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
#endif /* WB32_HSE_ENABLED == TRUE */
|
||||
/* Configure Flash prefetch, Cache and wait state */
|
||||
#if WB32_MAINCLK <= 32000000
|
||||
CACHE->CR = CACHE_CR_LATENCY_0WS;
|
||||
#elif WB32_MAINCLK <= 48000000
|
||||
CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_1WS;
|
||||
#elif WB32_MAINCLK <= 72000000
|
||||
CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_2WS;
|
||||
#else
|
||||
CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_3WS;
|
||||
#endif
|
||||
|
||||
/* AHBCLK = WB32_HPRE */
|
||||
#if WB32_HPRE == 1
|
||||
RCC->AHBPRE = 0x00;
|
||||
#else
|
||||
RCC->AHBPRE = (WB32_HPRE - 2);
|
||||
RCC->AHBPRE |= 0x01;
|
||||
#endif /* WB32_HPRE == 1 */
|
||||
|
||||
/* APB2CLK = MAINCLK / WB32_PPRE2 */
|
||||
RCC->APB2PRE = RCC_APB2PRE_SRCEN;
|
||||
#if WB32_PPRE2 == 1
|
||||
RCC->APB2PRE |= 0x00;
|
||||
#else
|
||||
RCC->APB2PRE |= (WB32_PPRE2 - 2);
|
||||
RCC->APB2PRE |= 0x01;
|
||||
#endif /* WB32_PPRE2 == 1 */
|
||||
|
||||
#if WB32_PLL_ENABLED == TRUE
|
||||
/* PLL configuration:
|
||||
PLLCLK = WB32_HSECLK / WB32_PLLDIV_VALUE * WB32_PLLMUL_VALUE*/
|
||||
RCC->PLLSRC = WB32_PLLSRC;
|
||||
RCC->PLLPRE = RCC_PLLPRE_SRCEN;
|
||||
|
||||
#if WB32_PLLDIV_VALUE == 1
|
||||
RCC->PLLPRE |= 0x00;
|
||||
#else
|
||||
RCC->PLLPRE |= (WB32_PLLDIV_VALUE - 2);
|
||||
RCC->PLLPRE |= 0x01;
|
||||
#endif /* WB32_PLLDIV_VALUE == 1 */
|
||||
|
||||
#if WB32_PLLMUL_VALUE == 12
|
||||
ANCTL->PLLCR = (0x3U << 6);
|
||||
#elif WB32_PLLMUL_VALUE == 16
|
||||
ANCTL->PLLCR = (0x2U << 6);
|
||||
#elif WB32_PLLMUL_VALUE == 20
|
||||
ANCTL->PLLCR = (0x1U << 6);
|
||||
#elif WB32_PLLMUL_VALUE == 24
|
||||
ANCTL->PLLCR = (0x0U << 6);
|
||||
#endif
|
||||
|
||||
/* Enable PLL */
|
||||
ANCTL->PLLENR = ANCTL_PLLENR_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while (ANCTL->PLLSR != 0x03) {
|
||||
}
|
||||
#endif /* WB32_PLL_ENABLED == TRUE */
|
||||
|
||||
/* Select WB32_MAINCLKSRC as system clock source */
|
||||
RCC->MAINCLKSRC = WB32_MAINCLKSRC;
|
||||
RCC->MAINCLKUEN = RCC_MAINCLKUEN_ENA;
|
||||
|
||||
/* Locks write to ANCTL registers */
|
||||
PWR->ANAKEY1 = 0x00;
|
||||
PWR->ANAKEY2 = 0x00;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clocks initialization.
|
||||
* @note None
|
||||
* @param None
|
||||
* @return None
|
||||
*/
|
||||
void wb32_clock_init(void) {
|
||||
|
||||
#if WB32_NO_INIT == FALSE
|
||||
/* Unlocks write to ANCTL registers */
|
||||
PWR->ANAKEY1 = 0x03;
|
||||
PWR->ANAKEY2 = 0x0C;
|
||||
|
||||
/* Turn off POR */
|
||||
ANCTL->PORCR = 0x7BE;
|
||||
|
||||
/* Locks write to ANCTL registers */
|
||||
PWR->ANAKEY1 = 0x00;
|
||||
PWR->ANAKEY2 = 0x00;
|
||||
|
||||
SetSysClock();
|
||||
|
||||
rccEnableAPB1(RCC_APB1ENR_BMX1EN);
|
||||
rccEnableAPB2(RCC_APB2ENR_BMX2EN);
|
||||
|
||||
SCB->VTOR = FLASH_BASE; /* Vector Table Relocation in Internal FLASH. */
|
||||
|
||||
#endif /* WB32_NO_INIT == FALSE */
|
||||
}
|
||||
|
||||
#if HAL_USE_USB || defined(__DOXYGEN__)
|
||||
|
||||
/**
|
||||
* @brief wb32 usb initialization.
|
||||
* @param[in] usbp pointer to the @p USBDriver object
|
||||
* @return None
|
||||
*/
|
||||
void wb32_usb_init(USBDriver *usbp) {
|
||||
|
||||
/* Clock activation.*/
|
||||
#if WB32_USB_USE_USB1
|
||||
if (&USBD1 == usbp) {
|
||||
RCC->AHBENR1 |= RCC_AHBENR1_CRCSFMEN;
|
||||
|
||||
/* Enable USB peripheral clock */
|
||||
RCC->AHBENR1 |= RCC_AHBENR1_USBEN;
|
||||
|
||||
/* Configure USB FIFO clock source */
|
||||
RCC->USBFIFOCLKSRC = RCC_USBFIFOCLKSRC_USBCLK;
|
||||
|
||||
/* Enable USB FIFO clock */
|
||||
RCC->USBFIFOCLKENR = RCC_USBFIFOCLKENR_CLKEN;
|
||||
|
||||
/* Configure and enable USB PHY */
|
||||
SFM->USBPCON = 0x02;
|
||||
|
||||
/* Configure and enable USBCLK */
|
||||
#if (WB32_USBPRE == WB32_USBPRE_DIV1P5)
|
||||
RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
|
||||
RCC->USBPRE = RCC_USBPRE_SRCEN;
|
||||
RCC->USBPRE |= RCC_USBPRE_RATIO_1_5;
|
||||
RCC->USBPRE |= RCC_USBPRE_DIVEN;
|
||||
#elif (WB32_USBPRE == WB32_USBPRE_DIV1)
|
||||
RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
|
||||
RCC->USBPRE = RCC_USBPRE_SRCEN;
|
||||
RCC->USBPRE |= 0x00;
|
||||
#elif (WB32_USBPRE == WB32_USBPRE_DIV2)
|
||||
RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
|
||||
RCC->USBPRE = RCC_USBPRE_SRCEN;
|
||||
RCC->USBPRE |= RCC_USBPRE_RATIO_2;
|
||||
RCC->USBPRE |= RCC_USBPRE_DIVEN;
|
||||
#elif (WB32_USBPRE == WB32_USBPRE_DIV3)
|
||||
RCC->USBCLKENR = RCC_USBCLKENR_CLKEN;
|
||||
RCC->USBPRE = RCC_USBPRE_SRCEN;
|
||||
RCC->USBPRE |= RCC_USBPRE_RATIO_3;
|
||||
RCC->USBPRE |= RCC_USBPRE_DIVEN;
|
||||
#else
|
||||
#error "invalid WB32_USBPRE value specified"
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief wb32 usb deinitialization.
|
||||
* @param[in] usbp pointer to the @p USBDriver object
|
||||
* @return None
|
||||
*/
|
||||
void wb32_usb_deinit(USBDriver *usbp) {
|
||||
|
||||
#if WB32_USB_USE_USB1
|
||||
if (&USBD1 == usbp) {
|
||||
/* Disable USBCLK */
|
||||
RCC->USBPRE &= RCC_USBPRE_SRCEN;
|
||||
RCC->USBPRE = 0x00;
|
||||
RCC->USBCLKENR = 0x00;
|
||||
|
||||
/* Disable USB FIFO clock */
|
||||
RCC->USBFIFOCLKENR = 0x0000;
|
||||
|
||||
/* Disable USB peripheral clock */
|
||||
RCC->AHBENR1 &= ~RCC_AHBENR1_USBEN;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief wb32 usb connect.
|
||||
* @param[in] usbp pointer to the @p USBDriver object
|
||||
* @return None
|
||||
*/
|
||||
void wb32_usb_connect(USBDriver *usbp) {
|
||||
|
||||
/* Enable BMX1, GPIOA clock */
|
||||
RCC->APB1ENR |= RCC_APB1ENR_BMX1EN | RCC_APB1ENR_GPIOAEN;
|
||||
|
||||
GPIOA->CFGMSK = (~(GPIO_CFGMSK_CFGMSK11 | GPIO_CFGMSK_CFGMSK12));
|
||||
/* Configure the drive current of PA11 and PA12 */
|
||||
GPIOA->CURRENT = (0x3 << 22) | (0x3 << 24);
|
||||
/* Configure PA11 and PA12 as Alternate function mode */
|
||||
GPIOA->MODER = (0x2 << 22) | (0x2 << 24);
|
||||
GPIOA->OTYPER = 0x00;
|
||||
GPIOA->OSPEEDR = 0x00;
|
||||
GPIOA->PUPDR = 0x00;
|
||||
GPIOA->AFRH = (3 << 12) | (3 << 16);
|
||||
|
||||
USB->POWER = USB_POWER_SUSEN;
|
||||
USB->INTRUSBE = USB_INTRUSBE_RSTIE | USB_INTRUSBE_RSUIE | USB_INTRUSBE_SUSIE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief wb32 usb disconnect.
|
||||
* @param[in] usbp pointer to the @p USBDriver object
|
||||
* @return None
|
||||
*/
|
||||
void wb32_usb_disconnect(USBDriver *usbp) {
|
||||
|
||||
/* Enable BMX1, GPIOA clock */
|
||||
RCC->APB1ENR |= RCC_APB1ENR_BMX1EN | RCC_APB1ENR_GPIOAEN;
|
||||
|
||||
GPIOA->CFGMSK = (~(GPIO_CFGMSK_CFGMSK11 | GPIO_CFGMSK_CFGMSK12));
|
||||
/* Configure PA11 and PA12 as input mode */
|
||||
GPIOA->MODER = 0x00;
|
||||
GPIOA->OSPEEDR = 0x00;
|
||||
GPIOA->PUPDR = 0x00;
|
||||
/* Configure PA12(D+) as open-drain output mode and output low level */
|
||||
GPIOA->CFGMSK = (~GPIO_CFGMSK_CFGMSK12);
|
||||
GPIOA->MODER = (0x1 << 24);
|
||||
GPIOA->OTYPER = (0x1 << 12);
|
||||
GPIOA->AFRH = 0x00;
|
||||
GPIOA->BSRR = (0x1000 << 16);
|
||||
}
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#error "not defined wb32_clock_init"
|
||||
|
||||
#endif
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,509 @@
|
|||
/*
|
||||
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file WB32FQ95xx/hal_lld.h
|
||||
* @brief WB32FQ95xx HAL subsystem low level driver header.
|
||||
* @pre This module requires the following macros to be defined in the
|
||||
* @p board.h file:
|
||||
* - WB32_LSECLK.
|
||||
* - WB32_LSE_BYPASS (optionally).
|
||||
* - WB32_HSECLK.
|
||||
* - WB32_HSE_BYPASS (optionally).
|
||||
* .
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef HAL_LLD_H
|
||||
#define HAL_LLD_H
|
||||
|
||||
#include "wb32_registry.h"
|
||||
#include "wb32_tim.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Platform identification
|
||||
* @{
|
||||
*/
|
||||
#define PLATFORM_NAME "WB32FQ95xx"
|
||||
|
||||
/**
|
||||
* @brief Sub-family identifier.
|
||||
*/
|
||||
#if !defined(WB32FQ95xx) || defined(__DOXYGEN__)
|
||||
#define WB32FQ95xx TRUE
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Absolute Maximum Ratings
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Maximum HSE clock frequency.
|
||||
*/
|
||||
#define WB32_HSECLK_MAX 16000000
|
||||
|
||||
/**
|
||||
* @brief Minimum HSE clock frequency.
|
||||
*/
|
||||
#define WB32_HSECLK_MIN 4000000
|
||||
|
||||
/**
|
||||
* @brief Maximum LSE clock frequency.
|
||||
*/
|
||||
#define WB32_LSECLK_MAX 1000000
|
||||
|
||||
/**
|
||||
* @brief Minimum LSE clock frequency.
|
||||
*/
|
||||
#define WB32_LSECLK_MIN 32768
|
||||
|
||||
/**
|
||||
* @brief Maximum PLLs input clock frequency.
|
||||
*/
|
||||
#define WB32_PLLIN_MAX 16000000
|
||||
|
||||
/**
|
||||
* @brief Minimum PLLs input clock frequency.
|
||||
*/
|
||||
#define WB32_PLLIN_MIN 2000000
|
||||
|
||||
/**
|
||||
* @brief Maximum PLL output clock frequency.
|
||||
*/
|
||||
#define WB32_PLLOUT_MAX 96000000
|
||||
|
||||
/**
|
||||
* @brief Minimum PLL output clock frequency.
|
||||
*/
|
||||
#define WB32_PLLOUT_MIN 48000000
|
||||
|
||||
/**
|
||||
* @brief Maximum APB1 clock frequency.
|
||||
*/
|
||||
#define WB32_PCLK1_MAX 96000000
|
||||
|
||||
/**
|
||||
* @brief Maximum APB2 clock frequency.
|
||||
*/
|
||||
#define WB32_PCLK2_MAX 96000000
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name RCC_MAINCLKSRC register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define WB32_MAINCLKSRC_MHSI (0)
|
||||
#define WB32_MAINCLKSRC_FHSI (1)
|
||||
#define WB32_MAINCLKSRC_PLL (2)
|
||||
#define WB32_MAINCLKSRC_HSE (3)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RCC_PLLSRC register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define WB32_PLLSRC_MHSI (0x0U)
|
||||
#define WB32_PLLSRC_HSE (0x1U)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RCC_USBPRE register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define WB32_USBPRE_MASK (0x3U << 1)
|
||||
#define WB32_USBPRE_DIV1 (0x0U)
|
||||
#define WB32_USBPRE_DIV1P5 (0x5U)
|
||||
#define WB32_USBPRE_DIV2 (0x1U)
|
||||
#define WB32_USBPRE_DIV3 (0x3U)
|
||||
/** @} */
|
||||
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Disables the PWR/RCC initialization in the HAL.
|
||||
*/
|
||||
#if !defined(WB32_NO_INIT) || defined(__DOXYGEN__)
|
||||
#define WB32_NO_INIT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the MHSI clock source.
|
||||
*/
|
||||
#if !defined(WB32_MHSI_ENABLED) || defined(__DOXYGEN__)
|
||||
#define WB32_MHSI_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the FHSI clock source.
|
||||
*/
|
||||
#if !defined(WB32_FHSI_ENABLED) || defined(__DOXYGEN__)
|
||||
#define WB32_FHSI_ENABLED FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the LSI clock source.
|
||||
*/
|
||||
#if !defined(WB32_LSI_ENABLED) || defined(__DOXYGEN__)
|
||||
#define WB32_LSI_ENABLED FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the HSE clock source.
|
||||
*/
|
||||
#if !defined(WB32_HSE_ENABLED) || defined(__DOXYGEN__)
|
||||
#define WB32_HSE_ENABLED FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the LSE clock source.
|
||||
*/
|
||||
#if !defined(WB32_LSE_ENABLED) || defined(__DOXYGEN__)
|
||||
#define WB32_LSE_ENABLED FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the PLL clock source.
|
||||
*/
|
||||
#if !defined(WB32_PLL_ENABLED) || defined(__DOXYGEN__)
|
||||
#define WB32_PLL_ENABLED FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Main clock source selection.
|
||||
* @note If the selected clock source is not the PLL then the PLL is not
|
||||
* initialized and started.
|
||||
* @note The default value is calculated for a 96MHz system clock from
|
||||
* a 8MHz crystal using the PLL.
|
||||
*/
|
||||
#if !defined(WB32_MAINCLKSRC) || defined(__DOXYGEN__)
|
||||
#define WB32_MAINCLKSRC WB32_MAINCLKSRC_PLL
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clock source for the PLL.
|
||||
* @note This setting has only effect if the PLL is selected as the
|
||||
* system clock source.
|
||||
*/
|
||||
#if !defined(WB32_PLLSRC) || defined(__DOXYGEN__)
|
||||
#define WB32_PLLSRC WB32_PLLSRC_HSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Crystal PLL pre-divider.
|
||||
* @note This setting has only effect if the PLL is selected as the
|
||||
* system clock source.
|
||||
*/
|
||||
#if !defined(WB32_PLLDIV_VALUE) || defined(__DOXYGEN__)
|
||||
#define WB32_PLLDIV_VALUE 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL multiplier value.
|
||||
* @note The allowed value is 12, 16, 20, 24.
|
||||
*/
|
||||
#if !defined(WB32_PLLMUL_VALUE) || defined(__DOXYGEN__)
|
||||
#define WB32_PLLMUL_VALUE 12
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief AHB prescaler value.
|
||||
* @note The default value is calculated for a 96MHz system clock from
|
||||
* a 8MHz crystal using the PLL.
|
||||
*/
|
||||
#if !defined(WB32_HPRE) || defined(__DOXYGEN__)
|
||||
#define WB32_HPRE 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB1 prescaler value.
|
||||
*/
|
||||
#if !defined(WB32_PPRE1) || defined(__DOXYGEN__)
|
||||
#define WB32_PPRE1 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB2 prescaler value.
|
||||
*/
|
||||
#if !defined(WB32_PPRE2) || defined(__DOXYGEN__)
|
||||
#define WB32_PPRE2 1
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Configuration-related checks.
|
||||
*/
|
||||
#if !defined(WB32FQ95xx_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, WB32FQ95xx_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MHSI related checks.
|
||||
*/
|
||||
#if WB32_MHSI_ENABLED
|
||||
#else /* !WB32_MHSI_ENABLED */
|
||||
|
||||
#if (WB32_MAINCLKSRC == WB32_MAINCLKSRC_MHSI)
|
||||
#error "MHSI not enabled, required by WB32_MAINCLKSRC"
|
||||
#endif
|
||||
|
||||
#if (WB32_MAINCLKSRC == WB32_MAINCLKSRC_PLL) && \
|
||||
(WB32_PLLSRC == WB32_PLLSRC_MHSI)
|
||||
#error "MHSI not enabled, required by WB32_MAINCLKSRC and WB32_PLLSRC"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* FHSI related checks.
|
||||
*/
|
||||
#if WB32_FHSI_ENABLED
|
||||
#else /* !WB32_FHSI_ENABLED */
|
||||
|
||||
#if (WB32_MAINCLKSRC == WB32_MAINCLKSRC_FHSI)
|
||||
#error "FHSI not enabled, required by WB32_MAINCLKSRC"
|
||||
#endif
|
||||
|
||||
#endif /* !WB32_FHSI_ENABLED */
|
||||
|
||||
/*
|
||||
* HSE related checks.
|
||||
*/
|
||||
#if WB32_HSE_ENABLED
|
||||
|
||||
#if WB32_HSECLK == 0
|
||||
#error "HSE frequency not defined"
|
||||
#elif (WB32_HSECLK < WB32_HSECLK_MIN) || (WB32_HSECLK > WB32_HSECLK_MAX)
|
||||
#error "WB32_HSECLK outside acceptable range (WB32_HSECLK_MIN...WB32_HSECLK_MAX)"
|
||||
#endif
|
||||
|
||||
#else /* !WB32_HSE_ENABLED */
|
||||
|
||||
#if (WB32_MAINCLKSRC == WB32_MAINCLKSRC_HSE)
|
||||
#error "HSE not enabled, required by WB32_MAINCLKSRC"
|
||||
#endif
|
||||
|
||||
#if ((WB32_MAINCLKSRC == WB32_MAINCLKSRC_PLL) && (WB32_PLLSRC == WB32_PLLSRC_HSE))
|
||||
#error "HSE not enabled, required by WB32_MAINCLKSRC and WB32_PLLSRC"
|
||||
#endif
|
||||
|
||||
#endif /* !WB32_HSE_ENABLED */
|
||||
|
||||
/*
|
||||
* LSI related checks.
|
||||
*/
|
||||
#if WB32_LSI_ENABLED
|
||||
#else /* !WB32_LSI_ENABLED */
|
||||
#endif /* !WB32_LSI_ENABLED */
|
||||
|
||||
/*
|
||||
* LSE related checks.
|
||||
*/
|
||||
#if WB32_LSE_ENABLED
|
||||
|
||||
#if (WB32_LSECLK == 0)
|
||||
#error "LSE frequency not defined"
|
||||
#endif
|
||||
|
||||
#if (WB32_LSECLK < WB32_LSECLK_MIN) || (WB32_LSECLK > WB32_LSECLK_MAX)
|
||||
#error "WB32_LSECLK outside acceptable range (WB32_LSECLK_MIN...WB32_LSECLK_MAX)"
|
||||
#endif
|
||||
|
||||
#else /* !WB32_LSE_ENABLED */
|
||||
#endif /* !WB32_LSE_ENABLED */
|
||||
|
||||
/**
|
||||
* @brief PLLDIV field.
|
||||
*/
|
||||
#if ((WB32_PLLDIV_VALUE >= 1) && (WB32_PLLDIV_VALUE <= 16)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define WB32_PLLDIV WB32_PLLDIV_VALUE
|
||||
#else
|
||||
#error "invalid WB32_PLLDIV_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLMUL field.
|
||||
*/
|
||||
#if (WB32_PLLMUL_VALUE == 12) || (WB32_PLLMUL_VALUE == 16) || \
|
||||
(WB32_PLLMUL_VALUE == 20) || (WB32_PLLMUL_VALUE == 24) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define WB32_PLLMUL WB32_PLLMUL_VALUE
|
||||
#else
|
||||
#error "invalid WB32_PLLMUL_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL input clock frequency.
|
||||
*/
|
||||
#if (WB32_PLLSRC == WB32_PLLSRC_HSE) || defined(__DOXYGEN__)
|
||||
#define WB32_PLLCLKIN (WB32_HSECLK / WB32_PLLDIV_VALUE)
|
||||
#elif (WB32_PLLSRC == WB32_PLLSRC_MHSI)
|
||||
#define WB32_PLLCLKIN (8000000 / WB32_PLLDIV_VALUE)
|
||||
#else
|
||||
#error "invalid WB32_PLLSRC value specified"
|
||||
#endif
|
||||
|
||||
/* PLL input frequency range check.*/
|
||||
#if (WB32_PLLCLKIN < WB32_PLLIN_MIN) || (WB32_PLLCLKIN > WB32_PLLIN_MAX)
|
||||
#error "WB32_PLLCLKIN outside acceptable range (WB32_PLLIN_MIN...WB32_PLLIN_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL output clock frequency.
|
||||
*/
|
||||
#define WB32_PLLCLKOUT (WB32_PLLCLKIN * WB32_PLLMUL_VALUE)
|
||||
|
||||
/* PLL output frequency range check.*/
|
||||
#if (WB32_PLLCLKOUT < WB32_PLLOUT_MIN) || (WB32_PLLCLKOUT > WB32_PLLOUT_MAX)
|
||||
#error "WB32_PLLCLKOUT outside acceptable range (WB32_PLLOUT_MIN...WB32_PLLOUT_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System clock source.
|
||||
*/
|
||||
#if (WB32_MAINCLKSRC == WB32_MAINCLKSRC_PLL) || defined(__DOXYGEN__)
|
||||
#define WB32_MAINCLK WB32_PLLCLKOUT
|
||||
#elif (WB32_MAINCLKSRC == WB32_MAINCLKSRC_MHSI)
|
||||
#define WB32_MAINCLK 8000000
|
||||
#elif (WB32_MAINCLKSRC == WB32_MAINCLKSRC_FHSI)
|
||||
#define WB32_MAINCLK 48000000
|
||||
#elif (WB32_MAINCLKSRC == WB32_MAINCLKSRC_HSE)
|
||||
#define WB32_MAINCLK WB32_HSECLK
|
||||
#else
|
||||
#error "invalid WB32_MAINCLKSRC value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief AHB frequency.
|
||||
*/
|
||||
#if ((WB32_HPRE >= 1) && (WB32_HPRE <= 64)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define WB32_HCLK (WB32_MAINCLK / WB32_HPRE)
|
||||
#else
|
||||
#error "invalid WB32_HPRE value specified"
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief APB1 frequency.
|
||||
*/
|
||||
#if ((WB32_PPRE1 >= 1) && (WB32_PPRE1 <= 64)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define WB32_PCLK1 (WB32_MAINCLK / WB32_PPRE1)
|
||||
#else
|
||||
#error "invalid WB32_PPRE1 value specified"
|
||||
#endif
|
||||
|
||||
/* APB1 frequency check.*/
|
||||
#if WB32_PCLK1 > WB32_PCLK1_MAX
|
||||
#error "WB32_PCLK1 exceeding maximum frequency (WB32_PCLK1_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB2 frequency.
|
||||
*/
|
||||
#if ((WB32_PPRE2 >= 1) && (WB32_PPRE2 <= 64)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define WB32_PCLK2 (WB32_MAINCLK / WB32_PPRE2)
|
||||
#else
|
||||
#error "invalid WB32_PPRE2 value specified"
|
||||
#endif
|
||||
|
||||
/* APB2 frequency check.*/
|
||||
#if WB32_PCLK2 > WB32_PCLK2_MAX
|
||||
#error "WB32_PCLK2 exceeding maximum frequency (WB32_PCLK2_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief USB frequency.
|
||||
*/
|
||||
#if (WB32_USBPRE == WB32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
|
||||
#define WB32_USBCLK ((WB32_MAINCLK * 2) / 3)
|
||||
#elif (WB32_USBPRE == WB32_USBPRE_DIV1)
|
||||
#define WB32_USBCLK WB32_MAINCLK
|
||||
#elif (WB32_USBPRE == WB32_USBPRE_DIV2)
|
||||
#define WB32_USBCLK (WB32_MAINCLK / 2)
|
||||
#elif (WB32_USBPRE == WB32_USBPRE_DIV3)
|
||||
#define WB32_USBCLK (WB32_MAINCLK / 3)
|
||||
#else
|
||||
#error "invalid WB32_USBPRE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Timers 1, 2, 3, 4 clock.
|
||||
*/
|
||||
#define WB32_TIMCLK1 WB32_PCLK1
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* Various helpers.*/
|
||||
#include "nvic.h"
|
||||
#include "wb32_isr.h"
|
||||
#include "wb32_rcc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void hal_lld_init(void);
|
||||
void wb32_clock_init(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_LLD_H */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,35 @@
|
|||
# Required platform files.
|
||||
PLATFORMSRC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
|
||||
$(CHIBIOS_CONTRIB)/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c \
|
||||
$(CHIBIOS_CONTRIB)/os/hal/ports/WB32/WB32FQ95xx/wb32_isr.c
|
||||
|
||||
# Required include directories.
|
||||
PLATFORMINC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
|
||||
$(CHIBIOS_CONTRIB)/os/hal/ports/WB32/WB32FQ95xx
|
||||
|
||||
|
||||
ifeq ($(USE_SMART_BUILD),yes)
|
||||
|
||||
# Configuration files directory
|
||||
ifeq ($(HALCONFDIR),)
|
||||
ifeq ($(CONFDIR),)
|
||||
HALCONFDIR = .
|
||||
else
|
||||
HALCONFDIR := $(CONFDIR)
|
||||
endif
|
||||
endif
|
||||
|
||||
HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
|
||||
endif #ifeq ($(USE_SMART_BUILD), yes)
|
||||
|
||||
# Drivers compatible with the platform.
|
||||
include ${CHIBIOS_CONTRIB}/os/hal/ports/WB32/LLD/GPIOv1/driver.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/TIMv1/driver.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/I2Cv1/driver.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/UARTv1/driver.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/SPIv1/driver.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/USBv1/driver.mk
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(PLATFORMSRC_CONTRIB)
|
||||
ALLINC += $(PLATFORMINC_CONTRIB)
|
|
@ -0,0 +1,254 @@
|
|||
/*
|
||||
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file WB32FQ95xx/wb32_isr.c
|
||||
* @brief WB32FQ95xx ISR handler code.
|
||||
*
|
||||
* @addtogroup WB32FQ95xx_ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#define exti_serve_irq(pr, channel) { \
|
||||
if ((pr) & (1U << (channel))) { \
|
||||
_pal_isr_code(channel); \
|
||||
} \
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__)
|
||||
#if !defined(WB32_DISABLE_EXTI0_HANDLER)
|
||||
/**
|
||||
* @brief EXTI[0] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(WB32_EXTI0_IRQ_VECTOR) {
|
||||
uint32_t pr;
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
pr = EXTI->PR;
|
||||
pr &= EXTI->IMR & EXTI_IMR_MR0;
|
||||
EXTI->PR = pr;
|
||||
|
||||
exti_serve_irq(pr, 0);
|
||||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(WB32_DISABLE_EXTI1_HANDLER)
|
||||
/**
|
||||
* @brief EXTI[1] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(WB32_EXTI1_IRQ_VECTOR) {
|
||||
uint32_t pr;
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
pr = EXTI->PR;
|
||||
pr &= EXTI->IMR & EXTI_IMR_MR1;
|
||||
EXTI->PR = pr;
|
||||
|
||||
exti_serve_irq(pr, 1);
|
||||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(WB32_DISABLE_EXTI2_HANDLER)
|
||||
/**
|
||||
* @brief EXTI[2] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(WB32_EXTI2_IRQ_VECTOR) {
|
||||
uint32_t pr;
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
pr = EXTI->PR;
|
||||
pr &= EXTI->IMR & EXTI_IMR_MR2;
|
||||
EXTI->PR = pr;
|
||||
|
||||
exti_serve_irq(pr, 2);
|
||||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(WB32_DISABLE_EXTI3_HANDLER)
|
||||
/**
|
||||
* @brief EXTI[3] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(WB32_EXTI3_IRQ_VECTOR) {
|
||||
uint32_t pr;
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
pr = EXTI->PR;
|
||||
pr &= EXTI->IMR & EXTI_IMR_MR3;
|
||||
EXTI->PR = pr;
|
||||
|
||||
exti_serve_irq(pr, 3);
|
||||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(WB32_DISABLE_EXTI4_HANDLER)
|
||||
/**
|
||||
* @brief EXTI[4] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(WB32_EXTI4_IRQ_VECTOR) {
|
||||
uint32_t pr;
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
pr = EXTI->PR;
|
||||
pr &= EXTI->IMR & EXTI_IMR_MR4;
|
||||
EXTI->PR = pr;
|
||||
|
||||
exti_serve_irq(pr, 4);
|
||||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(WB32_DISABLE_EXTI9_5_HANDLER)
|
||||
/**
|
||||
* @brief EXTI[5]...EXTI[9] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(WB32_EXTI9_5_IRQ_VECTOR) {
|
||||
uint32_t pr;
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
pr = EXTI->PR;
|
||||
pr &= EXTI->IMR & (EXTI_IMR_MR5 | EXTI_IMR_MR6 | EXTI_IMR_MR7 | EXTI_IMR_MR8 |
|
||||
EXTI_IMR_MR9);
|
||||
EXTI->PR = pr;
|
||||
|
||||
exti_serve_irq(pr, 5);
|
||||
exti_serve_irq(pr, 6);
|
||||
exti_serve_irq(pr, 7);
|
||||
exti_serve_irq(pr, 8);
|
||||
exti_serve_irq(pr, 9);
|
||||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(WB32_DISABLE_EXTI15_10_HANDLER)
|
||||
/**
|
||||
* @brief EXTI[10]...EXTI[15] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(WB32_EXTI15_10_IRQ_VECTOR) {
|
||||
uint32_t pr;
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
pr = EXTI->PR;
|
||||
pr &= EXTI->IMR & (EXTI_IMR_MR10 | EXTI_IMR_MR11 | EXTI_IMR_MR12 |
|
||||
EXTI_IMR_MR13 | EXTI_IMR_MR14 | EXTI_IMR_MR15);
|
||||
EXTI->PR = pr;
|
||||
|
||||
exti_serve_irq(pr, 10);
|
||||
exti_serve_irq(pr, 11);
|
||||
exti_serve_irq(pr, 12);
|
||||
exti_serve_irq(pr, 13);
|
||||
exti_serve_irq(pr, 14);
|
||||
exti_serve_irq(pr, 15);
|
||||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_PAL */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables IRQ sources.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void irqInit(void) {
|
||||
|
||||
#if HAL_USE_PAL
|
||||
nvicEnableVector(EXTI0_IRQn, WB32_IRQ_EXTI0_PRIORITY);
|
||||
nvicEnableVector(EXTI1_IRQn, WB32_IRQ_EXTI1_PRIORITY);
|
||||
nvicEnableVector(EXTI2_IRQn, WB32_IRQ_EXTI2_PRIORITY);
|
||||
nvicEnableVector(EXTI3_IRQn, WB32_IRQ_EXTI3_PRIORITY);
|
||||
nvicEnableVector(EXTI4_IRQn, WB32_IRQ_EXTI4_PRIORITY);
|
||||
nvicEnableVector(EXTI9_5_IRQn, WB32_IRQ_EXTI5_9_PRIORITY);
|
||||
nvicEnableVector(EXTI15_10_IRQn, WB32_IRQ_EXTI10_15_PRIORITY);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables IRQ sources.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void irqDeinit(void) {
|
||||
|
||||
#if HAL_USE_PAL
|
||||
nvicDisableVector(EXTI0_IRQn);
|
||||
nvicDisableVector(EXTI1_IRQn);
|
||||
nvicDisableVector(EXTI2_IRQn);
|
||||
nvicDisableVector(EXTI3_IRQn);
|
||||
nvicDisableVector(EXTI4_IRQn);
|
||||
nvicDisableVector(EXTI9_5_IRQn);
|
||||
nvicDisableVector(EXTI15_10_IRQn);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,306 @@
|
|||
/*
|
||||
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file WB32FQ95xx/wb32_isr.h
|
||||
* @brief WB32FQ95xx ISR handler header.
|
||||
*
|
||||
* @addtogroup WB32FQ95xx_ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef WB32_ISR_H
|
||||
#define WB32_ISR_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name ISR names and numbers remapping
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*
|
||||
* IWDG units.
|
||||
*/
|
||||
#define WB32_WWDG_IRQ_VECTOR Vector40
|
||||
#define WB32_WWDG_NUMBER 0
|
||||
|
||||
/*
|
||||
* PVD units.
|
||||
*/
|
||||
#define WB32_PVD_IRQ_VECTOR Vector44
|
||||
#define WB32_PVD_NUMBER 1
|
||||
|
||||
/*
|
||||
* TAMPER units.
|
||||
*/
|
||||
#define WB32_TAMPER_IRQ_VECTOR Vector48
|
||||
#define WB32_TAMPER_NUMBER 2
|
||||
|
||||
/*
|
||||
* RTC units.
|
||||
*/
|
||||
#define WB32_RTC_IRQ_VECTOR Vector4C
|
||||
#define WB32_RTC_NUMBER 3
|
||||
|
||||
#define WB32_RTCAlarm_IRQ_VECTOR VectorC8
|
||||
#define WB32_RTCAlarm_NUMBER 34
|
||||
|
||||
/*
|
||||
* FMC units.
|
||||
*/
|
||||
#define WB32_FMC_IRQ_VECTOR Vector50
|
||||
#define WB32_FMC_NUMBER 4
|
||||
#define WB32_RCC_IRQ_VECTOR Vector54
|
||||
#define WB32_RCC_NUMBER 5
|
||||
|
||||
/*
|
||||
* EXTI units.
|
||||
*/
|
||||
#define WB32_EXTI0_IRQ_VECTOR Vector58
|
||||
#define WB32_EXTI0_NUMBER 6
|
||||
|
||||
#define WB32_EXTI1_IRQ_VECTOR Vector5C
|
||||
#define WB32_EXTI1_NUMBER 7
|
||||
|
||||
#define WB32_EXTI2_IRQ_VECTOR Vector60
|
||||
#define WB32_EXTI2_NUMBER 8
|
||||
|
||||
#define WB32_EXTI3_IRQ_VECTOR Vector64
|
||||
#define WB32_EXTI3_NUMBER 9
|
||||
|
||||
#define WB32_EXTI4_IRQ_VECTOR Vector68
|
||||
#define WB32_EXTI4_NUMBER 10
|
||||
|
||||
#define WB32_EXTI9_5_IRQ_VECTOR Vector80
|
||||
#define WB32_EXTI9_5_NUMBER 16
|
||||
|
||||
#define WB32_EXTI15_10_IRQ_VECTOR VectorC4
|
||||
#define WB32_EXTI15_10_NUMBER 33
|
||||
|
||||
/*
|
||||
* DMAC units.
|
||||
*/
|
||||
#define WB32_DMAC1_IRQ_VECTOR Vector6C
|
||||
#define WB32_DMAC1_NUMBER 11
|
||||
|
||||
#define WB32_DMAC2_IRQ_VECTOR Vector70
|
||||
#define WB32_DMAC2_NUMBER 12
|
||||
|
||||
/*
|
||||
* ADC units.
|
||||
*/
|
||||
#define WB32_ADC_IRQ_VECTOR Vector74
|
||||
#define WB32_ADC_NUMBER 13
|
||||
|
||||
/*
|
||||
* USB units.
|
||||
*/
|
||||
#define WB32_USB1_IRQ_VECTOR Vector78
|
||||
#define WB32_USB1_DMA_IRQ_VECTOR Vector7C
|
||||
#define WB32_USBP1_WKUP_IRQ_VECTOR VectorCC
|
||||
|
||||
#define WB32_USB1_NUMBER 14
|
||||
#define WB32_USB1_DMA_NUMBER 15
|
||||
#define WB32_USBP1_WKUP_NUMBER 35
|
||||
|
||||
/*
|
||||
* I2C units.
|
||||
*/
|
||||
#define WB32_I2C1_IRQ_VECTOR VectorA0
|
||||
#define WB32_I2C1_NUMBER 24
|
||||
|
||||
#define WB32_I2C2_IRQ_VECTOR VectorA4
|
||||
#define WB32_I2C2_NUMBER 25
|
||||
|
||||
/*
|
||||
* I2S units.
|
||||
*/
|
||||
#define WB32_I2S_IRQ_VECTOR VectorD0
|
||||
#define WB32_I2S_NUMBER 36
|
||||
|
||||
/*
|
||||
* SPI units.
|
||||
*/
|
||||
#define WB32_QSPI_IRQ_VECTOR VectorA8
|
||||
#define WB32_QSPI_NUMBER 26
|
||||
|
||||
#define WB32_SPIM2_IRQ_VECTOR VectorAC
|
||||
#define WB32_SPIM2_NUMBER 27
|
||||
|
||||
#define WB32_SPIS1_IRQ_VECTOR VectorB0
|
||||
#define WB32_SPIS1_NUMBER 28
|
||||
|
||||
#define WB32_SPIS2_IRQ_VECTOR VectorB4
|
||||
#define WB32_SPIS2_NUMBER 29
|
||||
|
||||
/*
|
||||
* TIM units.
|
||||
*/
|
||||
#define WB32_TIM1_BRK_IRQ_VECTOR Vector84
|
||||
#define WB32_TIM1_UP_IRQ_VECTOR Vector88
|
||||
#define WB32_TIM1_TRG_COM_IRQ_VECTOR Vector8C
|
||||
#define WB32_TIM1_CC_IRQ_VECTOR Vector90
|
||||
#define WB32_TIM1_BRK_NUMBER 17
|
||||
#define WB32_TIM1_UP_NUMBER 18
|
||||
#define WB32_TIM1_TRG_COM_NUMBER 19
|
||||
#define WB32_TIM1_CC_NUMBER 20
|
||||
|
||||
#define WB32_TIM2_IRQ_VECTOR Vector94
|
||||
#define WB32_TIM2_NUMBER 21
|
||||
|
||||
#define WB32_TIM3_IRQ_VECTOR Vector98
|
||||
#define WB32_TIM3_NUMBER 22
|
||||
|
||||
#define WB32_TIM4_IRQ_VECTOR Vector9C
|
||||
#define WB32_TIM4_NUMBER 23
|
||||
|
||||
/*
|
||||
* USART units.
|
||||
*/
|
||||
#define WB32_UART1_IRQ_VECTOR VectorB8
|
||||
#define WB32_UART1_NUMBER 30
|
||||
|
||||
#define WB32_UART2_IRQ_VECTOR VectorBC
|
||||
#define WB32_UART2_NUMBER 31
|
||||
|
||||
#define WB32_UART3_IRQ_VECTOR VectorC0
|
||||
#define WB32_UART3_NUMBER 32
|
||||
|
||||
/*
|
||||
* ISO units.
|
||||
*/
|
||||
#define WB32_ISO_IRQ_VECTOR VectorD4
|
||||
#define WB32_ISO_NUMBER 37
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI0 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(WB32_IRQ_EXTI0_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define WB32_IRQ_EXTI0_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI1 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(WB32_IRQ_EXTI1_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define WB32_IRQ_EXTI1_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI2 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(WB32_IRQ_EXTI2_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define WB32_IRQ_EXTI2_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI3 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(WB32_IRQ_EXTI3_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define WB32_IRQ_EXTI3_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI4 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(WB32_IRQ_EXTI4_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define WB32_IRQ_EXTI4_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI9..5 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(WB32_IRQ_EXTI5_9_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define WB32_IRQ_EXTI5_9_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI15..10 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(WB32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define WB32_IRQ_EXTI10_15_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI16 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(WB32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define WB32_IRQ_EXTI16_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI17 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(WB32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define WB32_IRQ_EXTI17_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI18 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(WB32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define WB32_IRQ_EXTI18_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI19 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(WB32_IRQ_EXTI19_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define WB32_IRQ_EXTI19_PRIORITY 6
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void irqInit(void);
|
||||
void irqDeinit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* WB32_ISR_H */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,518 @@
|
|||
/*
|
||||
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file WB32FQ95xx/wb32_rcc.h
|
||||
* @brief RCC helper driver header.
|
||||
* @note This file requires definitions from the WB header file
|
||||
* @p WB32fq95xx.h.
|
||||
*
|
||||
* @addtogroup WB32FQ95xx_RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef WB32_RCC_H
|
||||
#define WB32_RCC_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Generic RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the clock of one or more peripheral on the APB1 bus.
|
||||
*
|
||||
* @param[in] mask APB1 peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableAPB1(mask) { \
|
||||
RCC->APB1ENR |= (mask); \
|
||||
(void)RCC->APB1ENR; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the clock of one or more peripheral on the APB1 bus.
|
||||
*
|
||||
* @param[in] mask APB1 peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableAPB1(mask) { \
|
||||
RCC->APB1ENR &= ~(mask); \
|
||||
(void)RCC->APB1ENR; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets one or more peripheral on the APB1 bus.
|
||||
*
|
||||
* @param[in] mask APB1 peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetAPB1(mask) { \
|
||||
RCC->APB1RSTR |= (mask); \
|
||||
RCC->APB1RSTR &= ~(mask); \
|
||||
(void)RCC->APB1RSTR; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the clock of one or more peripheral on the APB2 bus.
|
||||
*
|
||||
* @param[in] mask APB2 peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableAPB2(mask) { \
|
||||
RCC->APB2ENR |= (mask); \
|
||||
(void)RCC->APB2ENR; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the clock of one or more peripheral on the APB2 bus.
|
||||
*
|
||||
* @param[in] mask APB2 peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableAPB2(mask) { \
|
||||
RCC->APB2ENR &= ~(mask); \
|
||||
(void)RCC->APB2ENR; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets one or more peripheral on the APB2 bus.
|
||||
*
|
||||
* @param[in] mask APB2 peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetAPB2(mask) { \
|
||||
RCC->APB2RSTR |= (mask); \
|
||||
RCC->APB2RSTR &= ~(mask); \
|
||||
(void)RCC->APB2RSTR; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the clock of one or more peripheral on the AHB bus.
|
||||
*
|
||||
* @param[in] mask AHB peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableAHB(mask) { \
|
||||
RCC->AHBENR |= (mask); \
|
||||
(void)RCC->AHBENR; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the clock of one or more peripheral on the AHB bus.
|
||||
*
|
||||
* @param[in] mask AHB peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableAHB(mask) { \
|
||||
RCC->AHBENR &= ~(mask); \
|
||||
(void)RCC->AHBENR; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets one or more peripheral on the AHB bus.
|
||||
*
|
||||
* @param[in] mask AHB peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetAHB(mask) { \
|
||||
RCC->AHBRSTR |= (mask); \
|
||||
RCC->AHBRSTR &= ~(mask); \
|
||||
(void)RCC->AHBRSTR; \
|
||||
}
|
||||
/** @} */
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @name EXTI peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the EXTI peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableEXTI() rccEnableAPB1(RCC_APB1ENR_EXTIEN | RCC_APB1ENR_AFIOEN)
|
||||
|
||||
/**
|
||||
* @brief Disables the EXTI peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableEXTI() rccDisableAPB1(RCC_APB1ENR_EXTIEN | RCC_APB1ENR_AFIOEN)
|
||||
|
||||
/**
|
||||
* @brief Resets the EXTI peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetEXTI() rccResetAPB1(RCC_APB1RSTR_EXTIRST | RCC_APB1RSTR_AFIORST)
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name I2C peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the I2C1 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableI2C1() rccEnableAPB2(RCC_APB2ENR_I2C1EN)
|
||||
|
||||
/**
|
||||
* @brief Disables the I2C1 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableI2C1() rccDisableAPB2(RCC_APB2ENR_I2C1EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the I2C1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetI2C1() rccResetAPB2(RCC_APB2RSTR_I2C1RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the I2C2 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableI2C2() rccEnableAPB2(RCC_APB2ENR_I2C2EN)
|
||||
|
||||
/**
|
||||
* @brief Disables the I2C2 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableI2C2() rccDisableAPB2(RCC_APB2ENR_I2C2EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the I2C2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetI2C2() rccResetAPB2(RCC_APB2RSTR_I2C2RST)
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name SPI peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the QSPI peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableQSPI() rccEnableAPB1(RCC_APB1ENR_QSPIEN)
|
||||
|
||||
/**
|
||||
* @brief Disables the QSPI peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableQSPI() rccDisableAPB1(RCC_APB1ENR_QSPIEN)
|
||||
|
||||
/**
|
||||
* @brief Resets the QSPI peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetQSPI() rccResetAPB1(RCC_APB1RSTR_QSPIRST)
|
||||
|
||||
/**
|
||||
* @brief Enables the SPIS1 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableSPIS1() do { \
|
||||
rccEnableAPB1(RCC_APB1ENR_SPIS1EN); \
|
||||
RCC->SPIS1CLKENR = RCC_SPIS1CLKENR_CLKEN; \
|
||||
} while (false)
|
||||
|
||||
/**
|
||||
* @brief Disables the SPIS1 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableSPIS1() do { \
|
||||
RCC->SPIS1CLKENR = 0x00; \
|
||||
rccDisableAPB1(RCC_APB1ENR_SPIS1EN); \
|
||||
} while (false)
|
||||
|
||||
/**
|
||||
* @brief Resets the SPIS1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetSPIS1() rccResetAPB1(RCC_APB1RSTR_SPIS1RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the SPIM2 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableSPIM2() rccEnableAPB2(RCC_APB2ENR_SPIM2EN)
|
||||
|
||||
/**
|
||||
* @brief Disables the SPIM2 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableSPIM2() rccDisableAPB2(RCC_APB2ENR_SPIM2EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the SPIM2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetSPIM2() rccResetAPB2(RCC_APB2RSTR_SPIM2RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the SPIS2 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableSPIS2() do { \
|
||||
rccEnableAPB2(RCC_APB2ENR_SPIS2EN); \
|
||||
RCC->SPIS2CLKENR = RCC_SPIS2CLKENR_CLKEN; \
|
||||
} while (false)
|
||||
|
||||
/**
|
||||
* @brief Disables the SPIS2 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableSPIS2() do { \
|
||||
RCC->SPIS2CLKENR = 0x00; \
|
||||
rccDisableAPB2(RCC_APB2ENR_SPIS2EN); \
|
||||
} while (false)
|
||||
|
||||
/**
|
||||
* @brief Resets the SPIS2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetSPIS2() rccResetAPB2(RCC_APB2RSTR_SPIS2RST)
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name TIM peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the TIM1 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableTIM1() rccEnableAPB1(RCC_APB1ENR_TIM1EN)
|
||||
|
||||
/**
|
||||
* @brief Disables the TIM1 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableTIM1() rccDisableAPB1(RCC_APB1ENR_TIM1EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetTIM1() rccResetAPB1(RCC_APB1RSTR_TIM1RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the TIM2 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableTIM2() rccEnableAPB1(RCC_APB1ENR_TIM2EN)
|
||||
|
||||
/**
|
||||
* @brief Disables the TIM2 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableTIM2() rccDisableAPB1(RCC_APB1ENR_TIM2EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the TIM3 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableTIM3() rccEnableAPB1(RCC_APB1ENR_TIM3EN)
|
||||
|
||||
/**
|
||||
* @brief Disables the TIM3 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableTIM3() rccDisableAPB1(RCC_APB1ENR_TIM3EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM3 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the TIM4 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableTIM4() rccEnableAPB1(RCC_APB1ENR_TIM4EN)
|
||||
|
||||
/**
|
||||
* @brief Disables the TIM4 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableTIM4() rccDisableAPB1(RCC_APB1ENR_TIM4EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM4 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name UART peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the UART1 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableUART1() rccEnableAPB1(RCC_APB1ENR_UART1EN)
|
||||
|
||||
/**
|
||||
* @brief Disables the UART1 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableUART1() rccDisableAPB1(RCC_APB1ENR_UART1EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the UART1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetUART1() rccResetAPB1(RCC_APB1RSTR_UART1RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the UART2 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableUART2() rccEnableAPB2(RCC_APB2ENR_UART2EN)
|
||||
|
||||
/**
|
||||
* @brief Disables the UART2 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableUART2() rccDisableAPB2(RCC_APB2ENR_UART2EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the UART2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetUART2() rccResetAPB2(RCC_APB2RSTR_UART2RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the UART3 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableUART3() rccEnableAPB2(RCC_APB2ENR_UART3EN)
|
||||
|
||||
/**
|
||||
* @brief Disables the UART3 peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableUART3() rccDisableAPB2(RCC_APB2ENR_UART3EN)
|
||||
|
||||
/**
|
||||
* @brief Resets the UART3 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetUART3() rccResetAPB2(RCC_APB2RSTR_UART3RST)
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* WB32_RCC_H */
|
||||
|
||||
/** @} */
|
|
@ -0,0 +1,138 @@
|
|||
/*
|
||||
Copyright (C) 2022 Westberry Technology (ChangZhou) Corp., Ltd
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file WB32FQ95xx/wb32_registry.h
|
||||
* @brief WB32FQ95xx capabilities registry.
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef WB32_REGISTRY_H
|
||||
#define WB32_REGISTRY_H
|
||||
|
||||
#if !defined(WB32FQ95xx)
|
||||
#error "unsupported or unrecognized WB32FQ95xx member"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
#if defined(WB32FQ95xx) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @name WB32FQ95xx capabilities
|
||||
* @{
|
||||
*/
|
||||
/* GPIO attributes.*/
|
||||
#define WB32_HAS_GPIOA TRUE
|
||||
#define WB32_HAS_GPIOB TRUE
|
||||
#define WB32_HAS_GPIOC TRUE
|
||||
#define WB32_HAS_GPIOD TRUE
|
||||
|
||||
/* WWDG attributes */
|
||||
#define WB32_HAS_WWDG TRUE
|
||||
|
||||
/* PVD attributes */
|
||||
#define WB32_HAS_PVD TRUE
|
||||
|
||||
/* TAMPER attributes */
|
||||
#define WB32_HAS_TAMPER TRUE
|
||||
|
||||
/* RTC attributes */
|
||||
#define WB32_HAS_RTC TRUE
|
||||
|
||||
/* FMC attributes */
|
||||
#define WB32_HAS_FMC TRUE
|
||||
|
||||
/* EXTI attributes */
|
||||
#define WB32_HAS_EXTI TRUE
|
||||
#define WB32_HAS_EXTI0 TRUE
|
||||
#define WB32_HAS_EXTI1 TRUE
|
||||
#define WB32_HAS_EXTI2 TRUE
|
||||
#define WB32_HAS_EXTI3 TRUE
|
||||
#define WB32_HAS_EXTI4 TRUE
|
||||
#define WB32_HAS_EXTI9_5 TRUE
|
||||
#define WB32_HAS_EXTI15_10 TRUE
|
||||
#define WB32_EXTI_NUM_LINES 19
|
||||
|
||||
/* DMAC1 attributes */
|
||||
#define WB32_HAS_DMAC TRUE
|
||||
#define WB32_HAS_DMAC1 TRUE
|
||||
#define WB32_DMAC1_NUM_CHANNELS 3
|
||||
#define WB32_HAS_DMAC2 TRUE
|
||||
#define WB32_DMAC2_NUM_CHANNELS 3
|
||||
|
||||
/* ADC attributes */
|
||||
#define WB32_HAS_ADC TRUE
|
||||
|
||||
/* USB attributes */
|
||||
#define WB32_HAS_USB TRUE
|
||||
#define WB32_HAS_USB1 TRUE
|
||||
#define WB32_HAS_USB1_DMA TRUE
|
||||
#define WB32_HAS_USB1_WKUP TRUE
|
||||
|
||||
/* TIM attributes */
|
||||
#define WB32_HAS_TIM TRUE
|
||||
#define WB32_HAS_TIM1 TRUE
|
||||
#define WB32_HAS_TIM2 TRUE
|
||||
#define WB32_HAS_TIM3 TRUE
|
||||
#define WB32_HAS_TIM4 TRUE
|
||||
|
||||
#define WB32_TIM1_IS_32BITS TRUE
|
||||
#define WB32_TIM1_CHANNELS 4
|
||||
#define WB32_TIM2_IS_32BITS TRUE
|
||||
#define WB32_TIM2_CHANNELS 4
|
||||
#define WB32_TIM3_IS_32BITS TRUE
|
||||
#define WB32_TIM3_CHANNELS 4
|
||||
#define WB32_TIM4_IS_32BITS TRUE
|
||||
#define WB32_TIM4_CHANNELS 4
|
||||
|
||||
/* I2C attributes */
|
||||
#define WB32_HAS_I2C TRUE
|
||||
#define WB32_HAS_I2C1 TRUE
|
||||
#define WB32_HAS_I2C2 TRUE
|
||||
|
||||
/* SPI attributes */
|
||||
#define WB32_HAS_SPI TRUE
|
||||
#define WB32_HAS_QSPI TRUE
|
||||
#define WB32_HAS_SPIM2 TRUE
|
||||
#define WB32_HAS_SPIS1 TRUE
|
||||
#define WB32_HAS_SPIS2 TRUE
|
||||
|
||||
/* UART attributes */
|
||||
#define WB32_HAS_UART TRUE
|
||||
#define WB32_HAS_UART1 TRUE
|
||||
#define WB32_HAS_UART2 TRUE
|
||||
#define WB32_HAS_UART3 TRUE
|
||||
|
||||
/* I2S attributes */
|
||||
#define WB32_HAS_I2S TRUE
|
||||
|
||||
/* ISO attributes */
|
||||
#define WB32_HAS_ISO TRUE
|
||||
|
||||
/* IWDG attributes.*/
|
||||
#define WB32_HAS_IWDG TRUE
|
||||
|
||||
/* CRC attributes.*/
|
||||
#define WB32_HAS_CRC TRUE
|
||||
/** @} */
|
||||
#endif /* defined(WB32FQ95xx) */
|
||||
|
||||
#endif /* WB32_REGISTRY_H */
|
||||
|
||||
/** @} */
|
Loading…
Reference in New Issue