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Updating FSMC driver (SDRAM part first)

This commit is contained in:
Fabien Poussin 2019-10-29 19:38:09 +01:00
parent 63bc192217
commit 97b7064031
18 changed files with 807 additions and 157 deletions
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6
os/hal/hal.mk
View File

@ -10,8 +10,8 @@ endif
HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define"))
HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c
ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),)
HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c
ifneq ($(findstring HAL_USE_FSMC_SDRAM TRUE,$(HALCONF)), $(findstring HAL_USE_FSMC_SRAM TRUE,$(HALCONF)), $(findstring HAL_USE_FSMC_NAND TRUE,$(HALCONF)))
HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c
endif
ifneq ($(findstring HAL_USE_ONEWIRE TRUE,$(HALCONF)),)
HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c
@ -75,7 +75,7 @@ HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_opamp.c
endif
else
HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c \

27
os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h → os/hal/include/fsmc/nand.h
View File

@ -22,13 +22,12 @@
* @{
*/
#ifndef HAL_NAND_LLD_H_
#define HAL_NAND_LLD_H_
#ifndef NAND_H_
#define NAND_H_
#include "hal_fsmc.h"
#include "bitmap.h"
#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__)
#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@ -55,16 +54,16 @@
* @brief NAND driver enable switch.
* @details If set to @p TRUE the support for NAND1 is included.
*/
#if !defined(STM32_NAND_USE_NAND1) || defined(__DOXYGEN__)
#define STM32_NAND_USE_NAND1 FALSE
#if !defined(STM32_FSMC_USE_NAND1) || defined(__DOXYGEN__)
#define STM32_FSMC_USE_NAND1 FALSE
#endif
/**
* @brief NAND driver enable switch.
* @details If set to @p TRUE the support for NAND2 is included.
*/
#if !defined(STM32_NAND_USE_NAND2) || defined(__DOXYGEN__)
#define STM32_NAND_USE_NAND2 FALSE
#if !defined(STM32_FSMC_USE_NAND2) || defined(__DOXYGEN__)
#define STM32_FSMC_USE_NAND2 FALSE
#endif
/**
@ -112,11 +111,11 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !STM32_NAND_USE_FSMC_NAND1 && !STM32_NAND_USE_FSMC_NAND2
#if !STM32_FSMC_USE_NAND1 && !STM32_FSMC_USE_NAND2
#error "NAND driver activated but no NAND peripheral assigned"
#endif
#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && !STM32_HAS_FSMC
#if (STM32_FSMC_USE_NAND1 || STM32_FSMC_USE_NAND2) && !STM32_HAS_FSMC
#error "FSMC not present in the selected device"
#endif
@ -260,11 +259,11 @@ struct NANDDriver {
/* External declarations. */
/*===========================================================================*/
#if STM32_NAND_USE_FSMC_NAND1 && !defined(__DOXYGEN__)
#if STM32_FSMC_USE_NAND1 && !defined(__DOXYGEN__)
extern NANDDriver NANDD1;
#endif
#if STM32_NAND_USE_FSMC_NAND2 && !defined(__DOXYGEN__)
#if STM32_FSMC_USE_NAND2 && !defined(__DOXYGEN__)
extern NANDDriver NANDD2;
#endif
@ -287,8 +286,8 @@ extern "C" {
}
#endif
#endif /* HAL_USE_NAND */
#endif /* HAL_USE_FSMC_NAND */
#endif /* HAL_NAND_LLD_H_ */
#endif /* NAND_H_ */
/** @} */

24
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h → os/hal/include/fsmc/sdram.h
View File

@ -25,8 +25,8 @@
* @{
*/
#ifndef HAL_FMC_SDRAM_H_
#define HAL_FMC_SDRAM_H_
#ifndef SDRAM_H_
#define SDRAM_H_
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
@ -35,9 +35,7 @@
defined(STM32F769xx) || defined(STM32F777xx) || \
defined(STM32F779xx))
#include "hal_fsmc.h"
#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__)
#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@ -55,8 +53,8 @@
* @brief SDRAM driver enable switch.
* @details If set to @p TRUE the support for SDRAM1 is included.
*/
#if !defined(STM32_SDRAM_USE_FSMC_SDRAM1) || defined(__DOXYGEN__)
#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE
#if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__)
#define STM32_FSMC_USE_SDRAM1 FALSE
#else
#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE
#endif
@ -65,8 +63,8 @@
* @brief SDRAM driver enable switch.
* @details If set to @p TRUE the support for SDRAM2 is included.
*/
#if !defined(STM32_SDRAM_USE_FSMC_SDRAM2) || defined(__DOXYGEN__)
#define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE
#if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__)
#define STM32_FSMC_USE_SDRAM2 FALSE
#else
#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE
#endif
@ -77,11 +75,11 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !STM32_SDRAM_USE_FSMC_SDRAM1 && !STM32_SDRAM_USE_FSMC_SDRAM2
#if !STM32_FSMC_USE_SDRAM1 && !STM32_FSMC_USE_SDRAM2
#error "SDRAM driver activated but no SDRAM peripheral assigned"
#endif
#if (STM32_SDRAM_USE_FSMC_SDRAM1 || STM32_SDRAM_USE_FSMC_SDRAM2) && !STM32_HAS_FSMC
#if (STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2) && !STM32_HAS_FSMC
#error "FMC not present in the selected device"
#endif
@ -166,10 +164,10 @@ extern "C" {
}
#endif
#endif /* STM32_USE_FSMC_SDRAM */
#endif /* HAL_USE_FSMC_SDRAM */
#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */
#endif /* HAL_FMC_SDRAM_H_ */
#endif /* SDRAM_H_ */
/** @} */

170
os/hal/include/fsmc/sram.h Normal file
View File

@ -0,0 +1,170 @@
/*
ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_fsmc_sram.h
* @brief SRAM Driver subsystem low level driver header.
*
* @addtogroup SRAM
* @{
*/
#ifndef SRAM_H_
#define SRAM_H_
#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief SRAM driver enable switch.
* @details If set to @p TRUE the support for SRAM1 is included.
*/
#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__)
#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
#endif
/**
* @brief SRAM driver enable switch.
* @details If set to @p TRUE the support for SRAM2 is included.
*/
#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__)
#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
#endif
/**
* @brief SRAM driver enable switch.
* @details If set to @p TRUE the support for SRAM3 is included.
*/
#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__)
#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
#endif
/**
* @brief SRAM driver enable switch.
* @details If set to @p TRUE the support for SRAM4 is included.
*/
#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__)
#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \
!STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4
#error "SRAM driver activated but no SRAM peripheral assigned"
#endif
#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \
STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC
#error "FSMC not present in the selected device"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Driver state machine possible states.
*/
typedef enum {
SRAM_UNINIT = 0, /**< Not initialized. */
SRAM_STOP = 1, /**< Stopped. */
SRAM_READY = 2, /**< Ready. */
} sramstate_t;
/**
* @brief Type of a structure representing an NAND driver.
*/
typedef struct SRAMDriver SRAMDriver;
/**
* @brief Driver configuration structure.
* @note It could be empty on some architectures.
* @note Some bits in BCR register will be forced by driver.
*/
typedef struct {
uint32_t bcr;
uint32_t btr;
uint32_t bwtr;
} SRAMConfig;
/**
* @brief Structure representing an NAND driver.
*/
struct SRAMDriver {
/**
* @brief Driver state.
*/
sramstate_t state;
/**
* @brief Pointer to the FSMC SRAM registers block.
*/
FSMC_SRAM_NOR_TypeDef *sram;
};
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__)
extern SRAMDriver SRAMD1;
#endif
#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__)
extern SRAMDriver SRAMD2;
#endif
#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__)
extern SRAMDriver SRAMD3;
#endif
#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__)
extern SRAMDriver SRAMD4;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void fsmcSramInit(void);
void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp);
void fsmcSramStop(SRAMDriver *sramp);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_FSMC_SRAM */
#endif /* SRAM_H_ */
/** @} */

5
os/hal/include/hal_community.h
View File

@ -79,6 +79,10 @@
#define HAL_USE_OPAMP FALSE
#endif
#if !defined(HAL_USE_FSMC)
#define HAL_USE_FSMC FALSE
#endif
/* Abstract interfaces.*/
/* Shared headers.*/
@ -99,6 +103,7 @@
#include "hal_eeprom.h"
#include "hal_usb_hid.h"
#include "hal_usb_msd.h"
#include "hal_fsmc.h"
/*===========================================================================*/
/* Driver constants. */

81
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h → os/hal/include/hal_fsmc.h
View File

@ -25,7 +25,9 @@
#ifndef HAL_FSMC_H_
#define HAL_FSMC_H_
#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__)
#include "hal.h"
#if (HAL_USE_FSMC_SDRAM == TRUE) || (HAL_USE_FSMC_SRAM == TRUE) || (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
@ -246,6 +248,10 @@ typedef struct {
/* Driver pre-compile time settings. */
/*===========================================================================*/
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
/**
* @name Configuration options
* @{
@ -258,6 +264,31 @@ typedef struct {
#define STM32_FSMC_USE_FSMC1 FALSE
#endif
/**
* @brief SDRAM driver enable switch.
* @details If set to @p TRUE the support for SDRAM is included.
*/
#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_FSMC_SDRAM FALSE
#endif
/**
* @brief SRAM driver enable switch.
* @details If set to @p TRUE the support for SRAM is included.
*/
#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_FSMC_SRAM FALSE
#endif
/**
* @brief NAND driver enable switch.
* @details If set to @p TRUE the support for NAND is included.
*/
#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__)
#define HAL_USE_FSMC_NAND FALSE
#endif
/** @} */
/*===========================================================================*/
@ -295,29 +326,35 @@ struct FSMCDriver {
fsmcstate_t state;
/* End of the mandatory fields.*/
#if STM32_SRAM_USE_FSMC_SRAM1
#if HAL_USE_FSMC_SRAM
#if STM32_SRAM_USE_FSMC_SRAM1
FSMC_SRAM_NOR_TypeDef *sram1;
#endif
#if STM32_SRAM_USE_FSMC_SRAM2
#endif
#if STM32_SRAM_USE_FSMC_SRAM2
FSMC_SRAM_NOR_TypeDef *sram2;
#endif
#if STM32_SRAM_USE_FSMC_SRAM3
#endif
#if STM32_SRAM_USE_FSMC_SRAM3
FSMC_SRAM_NOR_TypeDef *sram3;
#endif
#if STM32_SRAM_USE_FSMC_SRAM4
#endif
#if STM32_SRAM_USE_FSMC_SRAM4
FSMC_SRAM_NOR_TypeDef *sram4;
#endif
#endif
#if STM32_NAND_USE_FSMC_NAND1
#if HAL_USE_FSMC_NAND
#if STM32_NAND_USE_FSMC_NAND1
FSMC_NAND_TypeDef *nand1;
#endif
#if STM32_NAND_USE_FSMC_NAND2
#endif
#if STM32_NAND_USE_FSMC_NAND2
FSMC_NAND_TypeDef *nand2;
#endif
#endif
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F7))
#if STM32_USE_FSMC_SDRAM
FSMC_SDRAM_TypeDef *sdram;
#if HAL_USE_FSMC_SDRAM
FSMC_SDRAM_TypeDef *sdram;
#endif
#endif
};
@ -337,13 +374,25 @@ extern FSMCDriver FSMCD1;
#ifdef __cplusplus
extern "C" {
#endif
void fsmc_init(void);
void fsmc_start(FSMCDriver *fsmcp);
void fsmc_stop(FSMCDriver *fsmcp);
void fsmcInit(void);
void fsmcStart(FSMCDriver *fsmcp);
void fsmcStop(FSMCDriver *fsmcp);
#ifdef __cplusplus
}
#endif
#if HAL_USE_FSMC_SDRAM == TRUE
#include "fsmc/sdram.h"
#endif
#if HAL_USE_FSMC_SRAM == TRUE
#include "fsmc/sram.h"
#endif
#if HAL_USE_FSMC_NAND == TRUE
#include "fsmc/nand.h"
#endif
#endif /* HAL_USE_FSMC */
#endif /* HAL_FSMC_H_ */

20
os/hal/ports/STM32/LLD/FSMCv1/driver.mk
View File

@ -1,17 +1,17 @@
ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_FSMC TRUE,$(HALCONF)),)
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
ifneq ($(findstring HAL_USE_FSMC_SDRAM TRUE,$(HALCONF)),)
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c
endif
ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),)
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
ifneq ($(findstring HAL_USE_FSMC_SRAM TRUE,$(HALCONF)),)
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c
endif
ifneq ($(findstring HAL_USE_FSMC_NAND TRUE,$(HALCONF)),)
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c
endif
else
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c
PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c
endif
PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1

6
os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c → os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c
View File

@ -15,8 +15,8 @@
*/
/**
* @file hal_nand_lld.c
* @brief NAND Driver subsystem low level driver source.
* @file hal_fsmc_nand_lld.c
* @brief FSMC NAND Driver subsystem low level driver source.
*
* @addtogroup NAND
* @{
@ -24,7 +24,7 @@
#include "hal.h"
#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__)
#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */

289
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h Normal file
View File

@ -0,0 +1,289 @@
/*
ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_fsmc_nand_lld.h
* @brief FSMC NAND Driver subsystem low level driver header.
*
* @addtogroup NAND
* @{
*/
#ifndef HAL_FSMC_NAND_LLD_H_
#define HAL_FSMC_NAND_LLD_H_
#include "bitmap.h"
#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
#define NAND_MIN_PAGE_SIZE 256
#define NAND_MAX_PAGE_SIZE 8192
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief FSMC1 interrupt priority level setting.
*/
#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EMC_FSMC1_IRQ_PRIORITY 10
#endif
/**
* @brief NAND driver enable switch.
* @details If set to @p TRUE the support for NAND1 is included.
*/
#if !defined(STM32_FSMC_USE_NAND1) || defined(__DOXYGEN__)
#define STM32_FSMC_USE_NAND1 FALSE
#endif
/**
* @brief NAND driver enable switch.
* @details If set to @p TRUE the support for NAND2 is included.
*/
#if !defined(STM32_FSMC_USE_NAND2) || defined(__DOXYGEN__)
#define STM32_FSMC_USE_NAND2 FALSE
#endif
/**
* @brief NAND DMA error hook.
* @note The default action for DMA errors is a system halt because DMA
* error can only happen because programming errors.
*/
#if !defined(STM32_FSMC_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
#endif
/**
* @brief NAND interrupt enable switch.
* @details If set to @p TRUE the support for internal FSMC interrupt included.
*/
#if !defined(STM32_FSMC_NAND_USE_INT) || defined(__DOXYGEN__)
#define STM32_FSMC_NAND_USE_INT FALSE
#endif
/**
* @brief NAND1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_FSMC_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_FSMC_NAND1_DMA_PRIORITY 0
#endif
/**
* @brief NAND2 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_FSMC_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_FSMC_NAND2_DMA_PRIORITY 0
#endif
/**
* @brief DMA stream used for NAND operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_FSMC_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if !STM32_FSMC_USE_NAND1 && !STM32_FSMC_USE_NAND2
#error "NAND driver activated but no NAND peripheral assigned"
#endif
#if (STM32_FSMC_USE_NAND1 || STM32_FSMC_USE_NAND2) && !STM32_HAS_FSMC
#error "FSMC not present in the selected device"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Type of a structure representing an NAND driver.
*/
typedef struct NANDDriver NANDDriver;
/**
* @brief Type of interrupt handler function.
*/
typedef void (*nandisrhandler_t)(NANDDriver *nandp);
/**
* @brief Driver configuration structure.
* @note It could be empty on some architectures.
*/
typedef struct {
/**
* @brief Number of erase blocks in NAND device.
*/
uint32_t blocks;
/**
* @brief Number of data bytes in page.
*/
uint32_t page_data_size;
/**
* @brief Number of spare bytes in page.
*/
uint32_t page_spare_size;
/**
* @brief Number of pages in block.
*/
uint32_t pages_per_block;
/**
* @brief Number of write cycles for row addressing.
*/
uint8_t rowcycles;
/**
* @brief Number of write cycles for column addressing.
*/
uint8_t colcycles;
/* End of the mandatory fields.*/
/**
* @brief Number of wait cycles. This value will be used both for
* PMEM and PATTR registers
*
* @note For proper calculation procedure please look at AN2784 document
* from STMicroelectronics.
*/
uint32_t pmem;
} NANDConfig;
/**
* @brief Structure representing an NAND driver.
*/
struct NANDDriver {
/**
* @brief Driver state.
*/
nandstate_t state;
/**
* @brief Current configuration data.
*/
const NANDConfig *config;
/**
* @brief Array to store bad block map.
*/
#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the bus.
*/
mutex_t mutex;
#elif CH_CFG_USE_SEMAPHORES
semaphore_t semaphore;
#endif
#endif /* NAND_USE_MUTUAL_EXCLUSION */
/* End of the mandatory fields.*/
/**
* @brief Function enabling interrupts from FSMC.
*/
nandisrhandler_t isr_handler;
/**
* @brief Pointer to current transaction buffer.
*/
void *rxdata;
/**
* @brief Current transaction length in bytes.
*/
size_t datalen;
/**
* @brief DMA mode bit mask.
*/
uint32_t dmamode;
/**
* @brief DMA channel.
*/
const stm32_dma_stream_t *dma;
/**
* @brief Thread waiting for I/O completion.
*/
thread_t *thread;
/**
* @brief Pointer to the FSMC NAND registers block.
*/
FSMC_NAND_TypeDef *nand;
/**
* @brief Memory mapping for data.
*/
uint16_t *map_data;
/**
* @brief Memory mapping for commands.
*/
uint16_t *map_cmd;
/**
* @brief Memory mapping for addresses.
*/
uint16_t *map_addr;
/**
* @brief Pointer to bad block map.
* @details One bit per block. All memory allocation is user's responsibility.
*/
bitmap_t *bb_map;
};
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if STM32_FSMC_USE_NAND1 && !defined(__DOXYGEN__)
extern NANDDriver NANDD1;
#endif
#if STM32_FSMC_USE_NAND2 && !defined(__DOXYGEN__)
extern NANDDriver NANDD2;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void nand_lld_init(void);
void nand_lld_start(NANDDriver *nandp);
void nand_lld_stop(NANDDriver *nandp);
uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen);
void nand_lld_read_data(NANDDriver *nandp, uint16_t *data,
size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc);
void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len);
void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd);
uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data,
size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc);
uint8_t nand_lld_read_status(NANDDriver *nandp);
void nand_lld_reset(NANDDriver *nandp);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_FSMC_NAND */
#endif /* HAL_FSMC_NAND_LLD_H_ */
/** @} */

91
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c → os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c
View File

@ -34,9 +34,9 @@
defined(STM32F769xx) || defined(STM32F777xx) || \
defined(STM32F779xx))
#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__)
#if (STM32_FSMC_USE_SDRAM1 == TRUE) || (STM32_FSMC_USE_SDRAM2 == TRUE) || defined(__DOXYGEN__)
#include "hal_fsmc_sdram.h"
#include "hal_fsmc_sdram_lld.h"
/*===========================================================================*/
/* Driver local definitions. */
@ -78,7 +78,7 @@ SDRAMDriver SDRAMD;
*
* @notapi
*/
static void _sdram_wait_ready(void) {
static void lld_sdram_wait_ready(void) {
/* Wait until the SDRAM controller is ready */
while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY);
}
@ -90,48 +90,48 @@ static void _sdram_wait_ready(void) {
*
* @notapi
*/
static void _sdram_init_sequence(const SDRAMConfig *cfgp) {
static void lld_sdram_init_sequence(const SDRAMConfig *cfgp) {
uint32_t command_target = 0;
#if STM32_SDRAM_USE_FSMC_SDRAM1
#if STM32_FSMC_USE_SDRAM1
command_target |= FMC_SDCMR_CTB1;
#endif
#if STM32_SDRAM_USE_FSMC_SDRAM2
#if STM32_FSMC_USE_SDRAM2
command_target |= FMC_SDCMR_CTB2;
#endif
/* Step 3: Configure a clock configuration enable command.*/
_sdram_wait_ready();
lld_sdram_wait_ready();
SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target;
/* Step 4: Insert delay (tipically 100uS).*/
osalThreadSleepMilliseconds(1);
/* Step 5: Configure a PALL (precharge all) command.*/
_sdram_wait_ready();
lld_sdram_wait_ready();
SDRAMD.sdram->SDCMR = FMCCM_PALL | command_target;
/* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
_sdram_wait_ready();
lld_sdram_wait_ready();
SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
(cfgp->sdcmr & FMC_SDCMR_NRFS);
/* Step 6.2: Send the second command.*/
_sdram_wait_ready();
lld_sdram_wait_ready();
SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
(cfgp->sdcmr & FMC_SDCMR_NRFS);
/* Step 7: Program the external memory mode register.*/
_sdram_wait_ready();
lld_sdram_wait_ready();
SDRAMD.sdram->SDCMR = FMCCM_LOAD_MODE | command_target |
(cfgp->sdcmr & FMC_SDCMR_MRD);
/* Step 8: Set clock.*/
_sdram_wait_ready();
lld_sdram_wait_ready();
SDRAMD.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT;
_sdram_wait_ready();
lld_sdram_wait_ready();
}
/*===========================================================================*/
@ -142,71 +142,28 @@ static void _sdram_init_sequence(const SDRAMConfig *cfgp) {
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level SDRAM driver initialization.
*/
void fsmcSdramInit(void) {
void lld_sdram_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp)
{
sdramp->sdram->SDCR1 = cfgp->sdcr;
sdramp->sdram->SDTR1 = cfgp->sdtr;
sdramp->sdram->SDCR2 = cfgp->sdcr;
sdramp->sdram->SDTR2 = cfgp->sdtr;
fsmc_init();
SDRAMD.sdram = FSMCD1.sdram;
SDRAMD.state = SDRAM_STOP;
lld_sdram_init_sequence(cfgp);
}
/**
* @brief Configures and activates the SDRAM peripheral.
*
* @param[in] sdramp pointer to the @p SDRAMDriver object
* @param[in] cfgp pointer to the @p SDRAMConfig object
*/
void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) {
if (FSMCD1.state == FSMC_STOP)
fsmc_start(&FSMCD1);
osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY),
"SDRAM. Invalid state.");
if (sdramp->state == SDRAM_STOP) {
/* Even if you need only bank2 you must properly set up SDCR and SDTR
regitsters for bank1 too. Both banks will be tuned equally assuming
connected memory ICs are equal.*/
sdramp->sdram->SDCR1 = cfgp->sdcr;
sdramp->sdram->SDTR1 = cfgp->sdtr;
sdramp->sdram->SDCR2 = cfgp->sdcr;
sdramp->sdram->SDTR2 = cfgp->sdtr;
_sdram_init_sequence(cfgp);
sdramp->state = SDRAM_READY;
}
}
/**
* @brief Deactivates the SDRAM peripheral.
*
* @param[in] sdramp pointer to the @p SDRAMDriver object
*
* @notapi
*/
void fsmcSdramStop(SDRAMDriver *sdramp) {
void lld_sdram_stop(SDRAMDriver *sdramp) {
uint32_t command_target = 0;
#if STM32_SDRAM_USE_FSMC_SDRAM1
#if STM32_FSMC_USE_SDRAM1
command_target |= FMC_SDCMR_CTB1;
#endif
#if STM32_SDRAM_USE_FSMC_SDRAM2
#if STM32_FSMC_USE_SDRAM2
command_target |= FMC_SDCMR_CTB2;
#endif
if (sdramp->state == SDRAM_READY) {
SDRAMD.sdram->SDCMR = FMCCM_POWER_DOWN | command_target;
sdramp->state = SDRAM_STOP;
}
sdramp->sdram->SDCMR = FMCCM_POWER_DOWN | command_target;
}
#endif /* STM32_USE_FSMC_SDRAM */
#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */

117
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h Normal file
View File

@ -0,0 +1,117 @@
/*
ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
SDRAM routines added by Nick Klimov aka progfin.
*/
/**
* @file hal_fsmc_sdram.h
* @brief SDRAM Driver subsystem low level driver header.
*
* @addtogroup SDRAM
* @{
*/
#ifndef HAL_FMC_SDRAM_H_
#define HAL_FMC_SDRAM_H_
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F745xx) || defined(STM32F746xx) || \
defined(STM32F756xx) || defined(STM32F767xx) || \
defined(STM32F769xx) || defined(STM32F777xx) || \
defined(STM32F779xx))
#include "hal_fsmc.h"
#if (STM32_FSMC_USE_SDRAM1 == TRUE) || (STM32_FSMC_USE_SDRAM2 == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief SDRAM driver enable switch.
* @details If set to @p TRUE the support for SDRAM1 is included.
*/
#if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__)
#define STM32_FSMC_USE_SDRAM1 FALSE
#else
#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE
#endif
/**
* @brief SDRAM driver enable switch.
* @details If set to @p TRUE the support for SDRAM2 is included.
*/
#if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__)
#define STM32_FSMC_USE_SDRAM2 FALSE
#else
#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if !STM32_FSMC_USE_SDRAM1 && !STM32_FSMC_USE_SDRAM2
#error "SDRAM driver activated but no SDRAM peripheral assigned"
#endif
#if (STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2) && !STM32_HAS_FSMC
#error "FMC not present in the selected device"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
extern SDRAMDriver SDRAMD;
#ifdef __cplusplus
extern "C" {
#endif
void lld_sdram_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp);
void lld_sdram_stop(SDRAMDriver *sdramp);
#ifdef __cplusplus
}
#endif
#endif /* STM32_FSMC_USE_SDRAM */
#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */
#endif /* HAL_FSMC_SDRAM_H_ */
/** @} */

0
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c → os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c
View File

0
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h → os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h
View File

4
os/hal/src/hal_community.c
View File

@ -84,6 +84,10 @@ void halCommunityInit(void) {
#if HAL_USE_COMP || defined(__DOXYGEN__)
compInit();
#endif
#if HAL_USE_FSMC || defined(__DOXYGEN__)
fsmcInit();
#endif
}
#endif /* HAL_USE_COMMUNITY */

79
os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c → os/hal/src/hal_fsmc.c
View File

@ -22,14 +22,15 @@
* @{
*/
#include "hal.h"
#include "hal_fsmc.h"
#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__)
#if (HAL_USE_FSMC_SDRAM == TRUE) || (HAL_USE_FSMC_SRAM == TRUE) || (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@ -61,37 +62,39 @@ FSMCDriver FSMCD1;
/* Driver exported functions. */
/*===========================================================================*/
#include "hal_fsmc_sdram_lld.h"
/**
* @brief Low level FSMC driver initialization.
*
* @notapi
*/
void fsmc_init(void) {
void fsmcInit(void) {
if (FSMCD1.state == FSMC_UNINIT) {
FSMCD1.state = FSMC_STOP;
#if STM32_SRAM_USE_FSMC_SRAM1
#if STM32_FSMC_USE_SRAM1
FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE);
#endif
#if STM32_SRAM_USE_FSMC_SRAM2
#if STM32_FSMC_USE_SRAM2
FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8);
#endif
#if STM32_SRAM_USE_FSMC_SRAM3
#if STM32_FSMC_USE_SRAM3
FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2);
#endif
#if STM32_SRAM_USE_FSMC_SRAM4
#if STM32_FSMC_USE_SRAM4
FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3);
#endif
#if STM32_NAND_USE_FSMC_NAND1
#if STM32_FSMC_USE_NAND1
FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE;
#endif
#if STM32_NAND_USE_FSMC_NAND2
#if STM32_FSMC_USE_NAND2
FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE;
#endif
@ -101,7 +104,7 @@ void fsmc_init(void) {
defined(STM32F756xx) || defined(STM32F767xx) || \
defined(STM32F769xx) || defined(STM32F777xx) || \
defined(STM32F779xx))
#if STM32_USE_FSMC_SDRAM
#if STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2
FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE;
#endif
#endif
@ -115,7 +118,7 @@ void fsmc_init(void) {
*
* @notapi
*/
void fsmc_start(FSMCDriver *fsmcp) {
void fsmcStart(FSMCDriver *fsmcp) {
osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY),
"invalid state");
@ -145,7 +148,7 @@ void fsmc_start(FSMCDriver *fsmcp) {
*
* @notapi
*/
void fsmc_stop(FSMCDriver *fsmcp) {
void fsmcStop(FSMCDriver *fsmcp) {
if (fsmcp->state == FSMC_READY) {
/* Resets the peripheral.*/
@ -175,12 +178,12 @@ void fsmc_stop(FSMCDriver *fsmcp) {
CH_IRQ_HANDLER(STM32_FSMC_HANDLER) {
CH_IRQ_PROLOGUE();
#if STM32_NAND_USE_FSMC_NAND1
#if STM32_FSMC_USE_NAND1
if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) {
NANDD1.isr_handler(&NANDD1);
}
#endif
#if STM32_NAND_USE_FSMC_NAND2
#if STM32_FSMC_USE_NAND2
if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) {
NANDD2.isr_handler(&NANDD2);
}
@ -188,6 +191,54 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) {
CH_IRQ_EPILOGUE();
}
/**
* @brief FSMC SDRAM Driver init
*/
void fsmcSdramInit(void) {
fsmcInit();
SDRAMD.sdram = FSMCD1.sdram;
SDRAMD.state = SDRAM_STOP;
}
/**
* @brief Configures and activates the SDRAM peripheral.
*
* @param[in] sdramp pointer to the @p SDRAMDriver object
* @param[in] cfgp pointer to the @p SDRAMConfig object
*/
void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) {
if (FSMCD1.state == FSMC_STOP)
fsmcStart(&FSMCD1);
osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY),
"SDRAM. Invalid state.");
if (sdramp->state == SDRAM_STOP) {
lld_sdram_start(sdramp, cfgp);
sdramp->state = SDRAM_READY;
}
}
/**
* @brief Deactivates the SDRAM peripheral.
*
* @param[in] sdramp pointer to the @p SDRAMDriver object
*
* @notapi
*/
void fsmcSdramStop(SDRAMDriver *sdramp) {
if (sdramp->state == SDRAM_READY) {
lld_sdram_stop(sdramp);
sdramp->state = SDRAM_STOP;
}
}
#endif /* HAL_USE_FSMC */
/** @} */

18
testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h
View File

@ -27,8 +27,22 @@
/**
* @brief Enables the FSMC subsystem.
*/
#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__)
#define HAL_USE_FSMC TRUE
#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__)
#define HAL_USE_FSMC_SDRAM TRUE
#endif
/**
* @brief Enables the FSMC subsystem.
*/
#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__)
#define HAL_USE_FSMC_SRAM FALSE
#endif
/**
* @brief Enables the FSMC subsystem.
*/
#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__)
#define HAL_USE_FSMC_NAND FALSE
#endif
/**

1
testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c
View File

@ -23,7 +23,6 @@
#include "string.h"
#include "hal_fsmc_sdram.h"
#include "membench.h"
#include "memtest.h"

26
testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h
View File

@ -22,32 +22,30 @@
#define STM32_FSMC_USE_FSMC1 TRUE
#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10
#define STM32_FSMC_DMA_CHN 0x03010201
#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_FSMC_DMA_PRIORITY 0
#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("FSMC DMA failure")
/*
* FSMC NAND driver system settings.
*/
#define STM32_NAND_USE_FSMC_NAND1 FALSE
#define STM32_NAND_USE_FSMC_NAND2 FALSE
#define STM32_NAND_USE_EXT_INT FALSE
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_NAND_DMA_PRIORITY 0
#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
#define STM32_FSMC_USE_NAND1 FALSE
#define STM32_FSMC_USE_NAND2 FALSE
#define STM32_FSMC_USE_NAND_EXT_INT FALSE
/*
* FSMC SRAM driver system settings.
*/
#define STM32_USE_FSMC_SRAM FALSE
#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
#define STM32_FSMC_USE_SRAM1 FALSE
#define STM32_FSMC_USE_SRAM2 FALSE
#define STM32_FSMC_USE_SRAM3 FALSE
#define STM32_FSMC_USE_SRAM4 FALSE
/*
* FSMC SDRAM driver system settings.
*/
#define STM32_USE_FSMC_SDRAM TRUE
#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE
#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE
#define STM32_FSMC_USE_SDRAM1 FALSE
#define STM32_FSMC_USE_SDRAM2 TRUE
/*
* TIMCAP driver system settings.