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Centralize clocks handling for sn32f2xx (#38) 

* sn32: 2xx: centralize peripheral clock functions

* sn32: export HCLK for all boards

* sn32: support tickless mode for systick

* sn32: CT: cleanup inclusions

* Revert "sn32: export HCLK for all boards"

This reverts commit 1cae8892e3ce908ef89774a7e83bb921ecd810fc.

* sn32: export HCLK in hal level

* ST: inherit the SN32_HCLK

* 2xx lld: include ct header

* ST: fix systime type

* ST: interrupt should be disabled on init

* st: cleanup

* debug it

* Revert "debug it"

This reverts commit 1dd78e81019aa1233f3402ed251428085470ab79.

* sn32f2xx: make sure clocks match and proper timer init

* add more checks

* always read 32 bits from the counter

* read the first 16 bits directly

* systime_t is 16bits, but MR0 lives in a 32bit register

* testing: use ILRC

* testing: hack

* Revert "testing: hack"

This reverts commit 3821173dd9a6180e3f91a3e81e73e9f92385e273.

* Revert "testing: use ILRC"
we can't do this because hardware limits
This reverts commit 19d3ffefbce8cdd5cd34859cd8befccda6353e58.

* fix assert

* test: hardcode it

* Revert "test: hardcode it"

This reverts commit a75777c44d12844eb0be44c650a1de1602cadaed.
This commit is contained in:
dexter93 2022-01-23 12:30:49 +02:00 committed by Dimitris Mantzouranis
parent c704bbd34d
commit 99bd79f7c9
19 changed files with 956 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
os/common/ext/SONiX/SN32F2xx/system_SN32F240B.c
View File

@ -26,7 +26,7 @@
#include <stdint.h>
#include <system_SN32F2xx.h>
#include <mcuconf.h>
#include <sn32_sys1.h>
/*
@ -122,7 +122,7 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
case 0: //IHRC
if(SN_SYS0->ANBCTRL == 1)
SystemCoreClock = __IHRC48_FREQ;
SystemCoreClock = __IHRC48_FREQ;
break;
case 1: //ILRC
SystemCoreClock = __ILRC_FREQ;
@ -212,11 +212,9 @@ void SystemInit (void)
#endif
SN_SYS0->AHBCP_b.AHBPRE = AHB_PRESCALAR;
#if (CLKOUT_SEL_VAL > 0) //CLKOUT
SN_SYS1->AHBCLKEN_b.CLKOUTSEL = CLKOUT_SEL_VAL;
SN_SYS1->APBCP1_b.CLKOUTPRE = CLKOUT_PRESCALAR;
#endif
sys1EnableCLKOUT(CLKOUT_SEL_VAL);
sys1SelectCLKOUTPRE(CLKOUT_PRESCALAR);
#endif //(SYS_CLOCK_SETUP)
}

7
os/common/ext/SONiX/SN32F2xx/system_SN32F260.c
View File

@ -26,7 +26,7 @@
#include <stdint.h>
#include <system_SN32F2xx.h>
#include <mcuconf.h>
#include <sn32_sys1.h>
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
@ -166,10 +166,7 @@ void SystemInit (void)
#if (CLKOUT_SEL_VAL > 0) //CLKOUT
SN_SYS1->AHBCLKEN |= (CLKOUT_SEL_VAL<<28);
#endif
sys1EnableCLKOUT(CLKOUT_SEL_VAL);
#endif //(SYS_CLOCK_SETUP)
}

1
os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16.h
View File

@ -3,6 +3,7 @@
/*_____ I N C L U D E S ____________________________________________________*/
#include <sn32_sys1.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
/*

6
os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.c
View File

@ -18,9 +18,7 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F2xx.h>
#include "CT16.h"
#include "CT16B0.h"
#include "sn32_ct.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
@ -48,7 +46,7 @@ void CT16B0_NvicDisable (void);
void CT16B0_Init (void)
{
//Enable P_CLOCK for CT16B0.
__CT16B0_ENABLE;
sys1EnableCT16B0();
//CT16B0 PCLK prescalar setting
// SN_SYS1->APBCP1_b.CT16B0PRE = 0x00; //PCLK = HCLK/1

8
os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B0.h
View File

@ -9,13 +9,7 @@
/*_____ D E F I N I T I O N S ______________________________________________*/
#define CT16B0_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B0 timer and interrupt
//POLLING_METHOD: Enable CT16B0 timer ONLY
/*_____ M A C R O S ________________________________________________________*/
// Enable CT16B0 PCLK
#define __CT16B0_ENABLE SN_SYS1->AHBCLKEN_b.CT16B0CLKEN = ENABLE
// Disable CT16B0 PCLK
#define __CT16B0_DISABLE SN_SYS1->AHBCLKEN_b.CT16B0CLKEN = DISABLE
//POLLING_METHOD: Enable CT16B0 timer ONLY
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern volatile uint32_t iwCT16B0_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS

5
os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.c
View File

@ -18,10 +18,7 @@
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F2xx.h>
#include "sn32_ct.h"
#include "CT16.h"
#include "CT16B1.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
@ -49,7 +46,7 @@ void CT16B1_NvicDisable (void);
void CT16B1_Init (void)
{
//Enable P_CLOCK for CT16B1.
__CT16B1_ENABLE;
sys1EnableCT16B1();
//CT16B1 PCLK prescalar setting
//SN_SYS1->APBCP1_b.CT16B1PRE = 0x00; //PCLK = HCLK/1

8
os/hal/ports/SN32/LLD/SN32F2xx/CT/CT16B1.h
View File

@ -9,13 +9,7 @@
/*_____ D E F I N I T I O N S ______________________________________________*/
#define CT16B1_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B1 timer and interrupt
//POLLING_METHOD: Enable CT16B1 timer ONLY
/*_____ M A C R O S ________________________________________________________*/
// Enable CT16B1 PCLK
#define __CT16B1_ENABLE SN_SYS1->AHBCLKEN_b.CT16B1CLKEN = ENABLE
// Disable CT16B1 PCLK
#define __CT16B1_DISABLE SN_SYS1->AHBCLKEN_b.CT16B1CLKEN = DISABLE
//POLLING_METHOD: Enable CT16B1 timer ONLY
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern volatile uint32_t iwCT16B1_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS

14
os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_gpt_lld.c
View File

@ -29,7 +29,7 @@
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define GPT_CLK SN32_HCLK
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@ -142,23 +142,23 @@ void gpt_lld_start(GPTDriver *gptp) {
/* Clock activation.*/
#if SN32_GPT_USE_CT16B0
if (&GPTD1 == gptp) {
CT16B0_Init();
sys1EnableCT16B0();
CT16B0_ResetTimer();
#if !defined(SN32_CT16B0_SUPPRESS_ISR)
nvicEnableVector(SN32_CT16B0_NUMBER, SN32_GPT_CT16B0_IRQ_PRIORITY);
#endif
gptp->clock = SystemCoreClock;
gptp->clock = GPT_CLK;
}
#endif
#if SN32_GPT_USE_CT16B1
if (&GPTD2 == gptp) {
CT16B1_Init();
sys1EnableCT16B1();
CT16B1_ResetTimer();
#if !defined(SN32_CT16B1_SUPPRESS_ISR)
nvicEnableVector(SN32_CT16B1_NUMBER, SN32_GPT_CT16B1_IRQ_PRIORITY);
#endif
gptp->clock = SystemCoreClock;
gptp->clock = GPT_CLK;
}
#endif
}
@ -193,7 +193,7 @@ void gpt_lld_stop(GPTDriver *gptp) {
#if !defined(SN32_CT16B0_SUPPRESS_ISR)
nvicDisableVector(SN32_CT16B0_NUMBER);
#endif
SN_SYS1->AHBCLKEN_b.CT16B0CLKEN = DISABLE;
sys1DisableCT16B0();
}
#endif
@ -202,7 +202,7 @@ void gpt_lld_stop(GPTDriver *gptp) {
#if !defined(SN32_CT16B1_SUPPRESS_ISR)
nvicDisableVector(SN32_CT16B1_NUMBER);
#endif
SN_SYS1->AHBCLKEN_b.CT16B1CLKEN = DISABLE;
sys1DisableCT16B1();
}
#endif
}

8
os/hal/ports/SN32/LLD/SN32F2xx/CT/hal_pwm_lld.c
View File

@ -29,7 +29,7 @@
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define PWM_CLK SN32_HCLK
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@ -114,12 +114,12 @@ void pwm_lld_start(PWMDriver *pwmp) {
/* Clock activation and timer reset.*/
#if SN32_PWM_USE_CT16B1
if (&PWMD1 == pwmp) {
CT16B1_Init();
sys1EnableCT16B1();
CT16B1_ResetTimer();
#if !defined(SN32_CT16B1_SUPPRESS_ISR)
nvicEnableVector(SN32_CT16B1_NUMBER, SN32_PWM_CT16B1_IRQ_PRIORITY);
#endif
pwmp->clock = SystemCoreClock;
pwmp->clock = PWM_CLK;
}
#endif
@ -488,7 +488,7 @@ void pwm_lld_stop(PWMDriver *pwmp) {
#if !defined(SN32_CT16B1_SUPPRESS_ISR)
nvicDisableVector(SN32_CT16B1_NUMBER);
#endif
SN_SYS1->AHBCLKEN_b.CT16B1CLKEN = DISABLE;
sys1DisableCT16B1();
}
#endif
}

4
os/hal/ports/SN32/LLD/SN32F2xx/CT/sn32_ct.h
View File

@ -25,7 +25,11 @@
#ifndef SN32_CT_H
#define SN32_CT_H
#include <SN32F2xx.h>
#include "CT16.h"
#include "CT16B0.h"
#include "CT16B1.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/

105
os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.c
View File

@ -29,6 +29,63 @@
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define SYSTICK_CK SN32_HCLK
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
#if (OSAL_ST_RESOLUTION == 32)
#error "Tickless mode on SN32 supports only 16bit timers"
#endif
#if SN32_ST_USE_TIMER == CT16B0
#if !SN32_HAS_CT16B0
#error "CT16B0 not present in the selected device"
#endif
#define ST_HANDLER SN32_CT16B0_HANDLER
#define ST_NUMBER SN32_CT16B0_NUMBER
#define ST_ENABLE_CLOCK() sys1EnableCT16B0()
#define ST_INIT_CLOCK() CT16B0_ResetTimer()
#elif SN32_ST_USE_TIMER == CT16B1
#if !SN32_HAS_CT16B1
#error "CT16B1 not present in the selected device"
#endif
#define ST_HANDLER SN32_CT16B1_HANDLER
#define ST_NUMBER SN32_CT16B1_NUMBER
#define ST_ENABLE_CLOCK() sys1EnableCT16B1()
#define ST_INIT_CLOCK() CT16B1_ResetTimer()
#else
#error "SN32_ST_USE_TIMER specifies an unsupported timer"
#endif
#if SYSTICK_CK % OSAL_ST_FREQUENCY != 0
#error "the selected ST frequency is not obtainable because integer rounding"
#endif
#if (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1 > 0xFF
#error "the selected ST frequency is not obtainable because CT16 timer prescaler limits"
#endif
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
#define ST_HANDLER SysTick_Handler
#if SYSTICK_CK % OSAL_ST_FREQUENCY != 0
#error "the selected ST frequency is not obtainable because integer rounding"
#endif
#if (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1 > 0xFFFFFF
#error "the selected ST frequency is not obtainable because SysTick timer counter limits"
#endif
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
/*===========================================================================*/
/* Driver exported variables. */
@ -50,14 +107,10 @@
/* Driver interrupt handlers. */
/*===========================================================================*/
OSAL_IRQ_HANDLER(SysTick_Handler) {
OSAL_IRQ_HANDLER(ST_HANDLER) {
OSAL_IRQ_PROLOGUE();
osalSysLockFromISR();
osalOsTimerHandlerI();
osalSysUnlockFromISR();
st_lld_serve_interrupt();
OSAL_IRQ_EPILOGUE();
}
@ -71,18 +124,54 @@ OSAL_IRQ_HANDLER(SysTick_Handler) {
* @notapi
*/
void st_lld_init(void) {
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
/* Free running counter mode.*/
/* Enabling timer clock.*/
ST_ENABLE_CLOCK();
ST_INIT_CLOCK();
/* Initializing the counter in free running mode.*/
SN32_ST_TIM->PRE = (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1;
SN32_ST_TIM->IC &= 0x1FFFFFF;
SN32_ST_TIM->TMRCTRL |= mskCT16_CEN_EN;
/* IRQ enabled.*/
nvicEnableVector(ST_NUMBER, SN32_ST_IRQ_PRIORITY);
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
/* Periodic systick mode, the Cortex-Mx internal systick timer is used
in this mode.*/
SysTick->LOAD = (SystemCoreClock / OSAL_ST_FREQUENCY) - 1;
SysTick->LOAD = (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1;
SysTick->VAL = 0;
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk |
SysTick_CTRL_TICKINT_Msk;
/* IRQ enabled.*/
nvicSetSystemHandlerPriority(HANDLER_SYSTICK, 8);
nvicSetSystemHandlerPriority(HANDLER_SYSTICK, SN32_ST_IRQ_PRIORITY);
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
}
/**
* @brief IRQ handling code.
*/
void st_lld_serve_interrupt(void) {
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
uint32_t ris;
sn32_ct_t *ct = SN32_ST_TIM;
ris = ct->RIS;
if ((ris & mskCT16_MR0IF) != 0U)
#endif
{
osalSysLockFromISR();
osalOsTimerHandlerI();
osalSysUnlockFromISR();
}
}
#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
/** @} */

80
os/hal/ports/SN32/LLD/SN32F2xx/SysTick/hal_st_lld.h
View File

@ -27,8 +27,6 @@
#ifndef HAL_ST_LLD_H
#define HAL_ST_LLD_H
#include "CT16B1.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
@ -37,9 +35,66 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief SysTick timer IRQ priority.
*/
#if !defined(SN32_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SN32_ST_IRQ_PRIORITY 8
#endif
/**
* @brief CT16Bx unit (by number) to be used for free running operations.
* @note You must select a 16 bits timer if a 16 bits @p systick_t type
* is required.
* @note Timers CT16B0 and CT16B1 are supported.
*/
#if !defined(SN32_ST_USE_TIMER) || defined(__DOXYGEN__)
#define SN32_ST_USE_TIMER CT16B0
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if !defined(SN32_HAS_CT16B0)
#define SN32_HAS_CT16B0 FALSE
#endif
#if !defined(SN32_HAS_CT16B1)
#define SN32_HAS_CT16B1 FALSE
#endif
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
#if SN32_ST_USE_TIMER == CT16B0
#if defined(SN32_CT16B0_IS_USED)
#error "ST requires CT16B0 but the timer is already used"
#else
#define SN32_CT16B0_IS_USED
#endif
#define SN32_ST_TIM SN32_CT16B0
#define ST_LLD_NUM_ALARMS 1
#elif SN32_ST_USE_TIMER == CT16B1
#if defined(SN32_CT16B1_IS_USED)
#error "ST requires CT16B1 but the timer is already used"
#else
#define SN32_CT16B1_IS_USED
#endif
#define SN32_ST_TIM SN32_CT16B1
#define ST_LLD_NUM_ALARMS 1
#else
#error "SN32_ST_USE_TIMER specifies an unsupported timer"
#endif
#endif
/*===========================================================================*/
/* Driver data structures and types. */
@ -57,6 +112,7 @@
extern "C" {
#endif
void st_lld_init(void);
void st_lld_serve_interrupt(void);
#ifdef __cplusplus
}
#endif
@ -65,6 +121,8 @@ extern "C" {
/* Driver inline functions. */
/*===========================================================================*/
#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)
/**
* @brief Returns the time counter value.
*
@ -73,7 +131,7 @@ extern "C" {
* @notapi
*/
static inline systime_t st_lld_get_counter(void) {
return (systime_t)0;
return (systime_t)(SN32_ST_TIM->TC & 0x0000FFFF);
}
/**
@ -86,8 +144,9 @@ static inline systime_t st_lld_get_counter(void) {
* @notapi
*/
static inline void st_lld_start_alarm(systime_t abstime) {
(void)abstime;
SN32_ST_TIM->MR0 = (uint32_t)abstime;
SN32_ST_TIM->IC &= 0x1FFFFFF;
SN32_ST_TIM->MCTRL |= mskCT16_MR0IE_EN;
}
/**
@ -96,7 +155,7 @@ static inline void st_lld_start_alarm(systime_t abstime) {
* @notapi
*/
static inline void st_lld_stop_alarm(void) {
SN32_ST_TIM->MCTRL &= ~mskCT16_MR0IE_EN;
}
/**
@ -107,8 +166,7 @@ static inline void st_lld_stop_alarm(void) {
* @notapi
*/
static inline void st_lld_set_alarm(systime_t abstime) {
(void)abstime;
SN32_ST_TIM->MR0 = (uint32_t)abstime;
}
/**
@ -120,7 +178,7 @@ static inline void st_lld_set_alarm(systime_t abstime) {
*/
static inline systime_t st_lld_get_alarm(void) {
return (systime_t)0;
return (systime_t)(SN32_ST_TIM->MR0 & 0x0000FFFF);
}
/**
@ -134,9 +192,11 @@ static inline systime_t st_lld_get_alarm(void) {
*/
static inline bool st_lld_is_alarm_active(void) {
return false;
return (bool)((SN32_ST_TIM->MCTRL & mskCT16_MR0IE_EN) != 0);
}
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
#endif /* HAL_ST_LLD_H */
/** @} */

4
os/hal/ports/SN32/LLD/SN32F2xx/USB/usbhw.c
View File

@ -8,7 +8,7 @@
*------------------------------------------------------------------------------*/
#include <SN32F2xx.h>
#include "SN32F200_Def.h"
#include <sn32_sys1.h>
#include "usbhw.h"
const uint32_t wUSB_EPnOffset[5] = {
@ -50,7 +50,7 @@ void USB_Init(void)
/* Initialize clock and Enable USB PHY. */
SystemInit();
SystemCoreClockUpdate();
SN_SYS1->AHBCLKEN |= mskUSBCLK_EN; // Enable USBCLKEN
sys1EnableUSB(); // Enable USB Clock
/* Initialize USB EP1~EP4 RAM Start address base on 64-bytes. */
USB_EPnBufferOffset(1, EP1_BUFFER_OFFSET_VALUE);

16
os/hal/ports/SN32/LLD/SN32F2xx/USB/usbhw.h
View File

@ -26,22 +26,6 @@
/* USB SOF interrupt */
#define SOF_IE DISABLE
/* AHB Clock Enable register <SYS1_AHBCLKEN> */
#define mskP0CLK_EN (0x1<<0)
#define mskP1CLK_EN (0x1<<1)
#define mskP2CLK_EN (0x1<<2)
#define mskP3CLK_EN (0x1<<3)
#define mskUSBCLK_EN (0x1<<4)
#define mskCT16B0CLK_EN (0x1<<6)
#define mskCT16B1CLK_EN (0x1<<7)
#define mskADCCLK_EN (0x1<<11)
#define mskSPI0CLK_EN (0x1<<12)
#define mskUART0CLK_EN (0x1<<16)
#define mskUART1CLK_EN (0x1<<17)
#define mskUART2CLK_EN (0x1<<18)
#define mskI2C0CLK_EN (0x1<<21)
#define mskWDTCLK_EN (0x1<<24)
/* USB Interrupt Enable Bit Definitions <USB_INTEN> */
#define mskEP1_NAK_EN (0x1<<0)
#define mskEP2_NAK_EN (0x1<<1)

1
os/hal/ports/SN32/SN32F240/hal_lld.h
View File

@ -46,6 +46,7 @@
* @name PLATFORM configuration options
* @{
*/
#define SN32_HCLK SystemCoreClock
/** @} */
/*===========================================================================*/

2
os/hal/ports/SN32/SN32F240B/hal_lld.h
View File

@ -46,6 +46,7 @@
* @name PLATFORM configuration options
* @{
*/
#define SN32_HCLK SystemCoreClock
/** @} */
/*===========================================================================*/
@ -73,6 +74,7 @@
/* Various helpers.*/
#include "nvic.h"
#include "sn32_ct.h"
#ifdef __cplusplus
extern "C" {

407
os/hal/ports/SN32/SN32F240B/sn32_sys1.h Normal file
View File

@ -0,0 +1,407 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SN32F240B/sn32_sys1.h
* @brief SYS1 helper driver header.
* @note This file requires definitions from the SN32 header file
* @p SN32F240B.h.
*
* @addtogroup SN32F24xB_SYS1
* @{
*/
#ifndef SN32_SYS1_H
#define SN32_SYS1_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @name Generic AHB operations
* @{
*/
/**
* @brief Enables the clock of one or more peripheral on the AHB bus.
*
* @param[in] mask AHB peripherals mask
*
* @api
*/
#define sys1EnableAHB(mask) { \
SN_SYS1->AHBCLKEN |= (mask); \
(void)SN_SYS1->AHBCLKEN; \
}
/**
* @brief Disables the clock of one or more peripheral on the AHB bus.
*
* @param[in] mask AHB peripherals mask
*
* @api
*/
#define sys1DisableAHB(mask) { \
SN_SYS1->AHBCLKEN &= ~(mask); \
(void)SN_SYS1->AHBCLKEN; \
}
/**
* @brief Selects the clock prescaler of one or more peripheral on the APB bus.
*
* @param[in] mask APB peripherals mask
*
* @api
*/
#define sys1SelectAPB(mask) { \
SN_SYS1->APBCP1 |= (mask); \
(void)SN_SYS1->APBCP1; \
}
/** @} */
/**
* @name P0 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the P0 peripheral clock.
*
*
* @api
*/
#define sys1EnableP0() sys1EnableAHB(0x1<<0)
/**
* @brief Disables the P0 peripheral clock.
*
* @api
*/
#define sys1DisableP0() sys1DisableAHB(0x1<<0)
/**
* @name P1 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the P1 peripheral clock.
*
* @api
*/
#define sys1EnableP1() sys1EnableAHB(0x1<<1)
/**
* @brief Disables the P1 peripheral clock.
*
* @api
*/
#define sys1DisableP1() sys1DisableAHB(0x1<<1)
/**
* @name P2 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the P2 peripheral clock.
*
* @api
*/
#define sys1EnableP2() sys1EnableAHB(0x1<<2)
/**
* @brief Disables the P2 peripheral clock.
*
* @api
*/
#define sys1DisableP2() sys1DisableAHB(0x1<<2)
/**
* @name P3 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the P3 peripheral clock.
*
* @api
*/
#define sys1EnableP3() sys1EnableAHB(0x1<<3)
/**
* @brief Disables the P3 peripheral clock.
*
* @api
*/
#define sys1DisableP3() sys1DisableAHB(0x1<<3)
/**
* @name USB peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the USB peripheral clock.
*
* @api
*/
#define sys1EnableUSB() sys1EnableAHB(0x1<<4)
/**
* @brief Disables the USB peripheral clock.
*
* @api
*/
#define sys1DisableUSB() sys1DisableAHB(0x1<<4)
/**
* @name CT16B0 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the CT16B0 peripheral clock.
*
* @api
*/
#define sys1EnableCT16B0() sys1EnableAHB(0x1<<6)
/**
* @brief Disables the CT16B0 peripheral clock.
*
* @api
*/
#define sys1DisableCT16B0() sys1DisableAHB(0x1<<6)
/**
* @name CT16B1 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the CT16B1 peripheral clock.
*
* @api
*/
#define sys1EnableCT16B1() sys1EnableAHB(0x1<<7)
/**
* @brief Disables the CT16B0 peripheral clock.
*
* @api
*/
#define sys1DisableCT16B1() sys1DisableAHB(0x1<<7)
/**
* @name ADC peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the ADC peripheral clock.
*
* @api
*/
#define sys1EnableADC() sys1EnableAHB(0x1<<11)
/**
* @brief Disables the ADC peripheral clock.
*
* @api
*/
#define sys1DisableADC() sys1DisableAHB(0x1<<11)
/**
* @name SPI0 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the SPI0 peripheral clock.
*
* @api
*/
#define sys1EnableSPI0() sys1EnableAHB(0x1<<12)
/**
* @brief Disables the SPI0 peripheral clock.
*
* @api
*/
#define sys1DisableSPI0() sys1DisableAHB(0x1<<12)
/**
* @name UART0 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the UART0 peripheral clock.
*
* @api
*/
#define sys1EnableUART0() sys1EnableAHB(0x1<<16)
/**
* @brief Disables the UART0 peripheral clock.
*
* @api
*/
#define sys1DisableUART0() sys1DisableAHB(0x1<<16)
/**
* @name UART1 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the UART1 peripheral clock.
*
* @api
*/
#define sys1EnableUART1() sys1EnableAHB(0x1<<17)
/**
* @brief Disables the UART1 peripheral clock.
*
* @api
*/
#define sys1DisableUART1() sys1DisableAHB(0x1<<17)
/**
* @name UART2 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the UART2 peripheral clock.
*
* @api
*/
#define sys1EnableUART2() sys1EnableAHB(0x1<<18)
/**
* @brief Disables the UART2 peripheral clock.
*
* @api
*/
#define sys1DisableUART2() sys1DisableAHB(0x1<<18)
/**
* @name I2C0 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the I2C0 peripheral clock.
*
* @api
*/
#define sys1EnableI2C0() sys1EnableAHB(0x1<<21)
/**
* @brief Disables the I2C0 peripheral clock.
*
* @api
*/
#define sys1DisableI2C0() sys1DisableAHB(0x1<<21)
/**
* @name WDT peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the WDT peripheral clock.
*
* @api
*/
#define sys1EnableWDT() sys1EnableAHB(0x1<<24)
/**
* @brief Disables the WDT peripheral clock.
*
* @api
*/
#define sys1DisableWDT() sys1DisableAHB(0x1<<24)
/**
* @brief Configures the WDT peripheral clock.
*
* @param[in] pre clock source prescaler
* * @api
*/
#define sys1SelectWDTPRE(pre) { \
if(pre > 0) \
sys1SelectAPB(pre<<20) \
}
/**
* @name CLKOUT peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the CLKOUT peripheral clock.
*
* @param[in] clkval clock output source
* * @api
*/
#define sys1EnableCLKOUT(clkval) { \
if(clkval > 0) \
sys1EnableAHB(clkval<<28) \
}
/**
* @brief Disables the CLKOUT peripheral clock.
*
* @api
*/
#define sys1DisableCLKOUT() { \
SN_SYS1->AHBCLKEN_b.CLKOUTSEL= 0; \
(void)SN_SYS1->AHBCLKEN; \
}
/**
* @brief Configures the CLKOUT peripheral clock.
*
* @param[in] pre clock source prescaler
* * @api
*/
#define sys1SelectCLKOUTPRE(pre) { \
if(pre > 0) \
sys1SelectAPB(pre<<28) \
}
/** @} */
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* SN32_SYS1_H */
/** @} */

2
os/hal/ports/SN32/SN32F260/hal_lld.h
View File

@ -46,6 +46,7 @@
* @name PLATFORM configuration options
* @{
*/
#define SN32_HCLK SystemCoreClock
/** @} */
/*===========================================================================*/
@ -73,6 +74,7 @@
/* Various helpers.*/
#include "nvic.h"
#include "sn32_ct.h"
#ifdef __cplusplus
extern "C" {

347
os/hal/ports/SN32/SN32F260/sn32_sys1.h Normal file
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@ -0,0 +1,347 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SN32F260B/sn32_sys1.h
* @brief SYS1 helper driver header.
* @note This file requires definitions from the SN32 header file
* @p SN32F260.h.
*
* @addtogroup SN32F26x_SYS1
* @{
*/
#ifndef SN32_SYS1_H
#define SN32_SYS1_H
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @name Generic AHB operations
* @{
*/
/**
* @brief Enables the clock of one or more peripheral on the AHB bus.
*
* @param[in] mask AHB peripherals mask
*
* @api
*/
#define sys1EnableAHB(mask) { \
SN_SYS1->AHBCLKEN |= (mask); \
(void)SN_SYS1->AHBCLKEN; \
}
/**
* @brief Disables the clock of one or more peripheral on the AHB bus.
*
* @param[in] mask AHB peripherals mask
*
* @api
*/
#define sys1DisableAHB(mask) { \
SN_SYS1->AHBCLKEN &= ~(mask); \
(void)SN_SYS1->AHBCLKEN; \
}
/**
* @brief Selects the clock prescaler of one or more peripheral on the APB bus.
*
* @param[in] mask APB peripherals mask
*
* @api
*/
#define sys1SelectAPB(mask) { \
SN_SYS1->APBCP1 |= (mask); \
(void)SN_SYS1->APBCP1; \
}
/** @} */
/**
* @name P0 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the P0 peripheral clock.
*
*
* @api
*/
#define sys1EnableP0() sys1EnableAHB(0x1<<0)
/**
* @brief Disables the P0 peripheral clock.
*
* @api
*/
#define sys1DisableP0() sys1DisableAHB(0x1<<0)
/**
* @name P1 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the P1 peripheral clock.
*
* @api
*/
#define sys1EnableP1() sys1EnableAHB(0x1<<1)
/**
* @brief Disables the P1 peripheral clock.
*
* @api
*/
#define sys1DisableP1() sys1DisableAHB(0x1<<1)
/**
* @name P2 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the P2 peripheral clock.
*
* @api
*/
#define sys1EnableP2() sys1EnableAHB(0x1<<2)
/**
* @brief Disables the P2 peripheral clock.
*
* @api
*/
#define sys1DisableP2() sys1DisableAHB(0x1<<2)
/**
* @name P3 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the P3 peripheral clock.
*
* @api
*/
#define sys1EnableP3() sys1EnableAHB(0x1<<3)
/**
* @brief Disables the P3 peripheral clock.
*
* @api
*/
#define sys1DisableP3() sys1DisableAHB(0x1<<3)
/**
* @name USB peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the USB peripheral clock.
*
* @api
*/
#define sys1EnableUSB() sys1EnableAHB(0x1<<4)
/**
* @brief Disables the USB peripheral clock.
*
* @api
*/
#define sys1DisableUSB() sys1DisableAHB(0x1<<4)
/**
* @name CT16B0 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the CT16B0 peripheral clock.
*
* @api
*/
#define sys1EnableCT16B0() sys1EnableAHB(0x1<<6)
/**
* @brief Disables the CT16B0 peripheral clock.
*
* @api
*/
#define sys1DisableCT16B0() sys1DisableAHB(0x1<<6)
/**
* @name CT16B1 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the CT16B1 peripheral clock.
*
* @api
*/
#define sys1EnableCT16B1() sys1EnableAHB(0x1<<7)
/**
* @brief Disables the CT16B0 peripheral clock.
*
* @api
*/
#define sys1DisableCT16B1() sys1DisableAHB(0x1<<7)
/**
* @name SPI0 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the SPI0 peripheral clock.
*
* @api
*/
#define sys1EnableSPI0() sys1EnableAHB(0x1<<12)
/**
* @brief Disables the SPI0 peripheral clock.
*
* @api
*/
#define sys1DisableSPI0() sys1DisableAHB(0x1<<12)
/**
* @name I2C0 peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the I2C0 peripheral clock.
*
* @api
*/
#define sys1EnableI2C0() sys1EnableAHB(0x1<<21)
/**
* @brief Disables the I2C0 peripheral clock.
*
* @api
*/
#define sys1DisableI2C0() sys1DisableAHB(0x1<<21)
/**
* @name WDT peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the WDT peripheral clock.
*
* @api
*/
#define sys1EnableWDT() sys1EnableAHB(0x1<<24)
/**
* @brief Disables the WDT peripheral clock.
*
* @api
*/
#define sys1DisableWDT() sys1DisableAHB(0x1<<24)
/**
* @brief Configures the WDT peripheral clock.
*
* @param[in] pre clock source prescaler
* * @api
*/
#define sys1SelectWDTPRE(pre) { \
if(pre > 0) \
sys1SelectAPB(pre<<20) \
}
/**
* @name CLKOUT peripherals specific SYS1 operations
* @{
*/
/**
* @brief Enables the CLKOUT peripheral clock.
*
* @param[in] clkval clock output source
* * @api
*/
#define sys1EnableCLKOUT(clkval) { \
if(clkval > 0) \
sys1EnableAHB(clkval<<28) \
}
/**
* @brief Disables the CLKOUT peripheral clock.
*
* @api
*/
#define sys1DisableCLKOUT() { \
SN_SYS1->AHBCLKEN_b.CLKOUTSEL= 0; \
(void)SN_SYS1->AHBCLKEN; \
}
/**
* @brief Configures the CLKOUT peripheral clock.
*
* @param[in] pre clock source prescaler
* * @api
*/
#define sys1SelectCLKOUTPRE(pre) { \
if(pre > 0) \
sys1SelectAPB(pre<<28) \
}
/**
* @brief Configures the SysTick peripheral clock.
*
* @param[in] pre clock source prescaler
* * @api
*/
#define sys1SelectSYSTICKPRE(pre) { \
if(pre > 0) \
sys1SelectAPB(pre<<16) \
}
/** @} */
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* SN32_SYS1_H */
/** @} */