Merge pull request #232 from alexclewontin/integration
[HAL] [NUC123SD4AN0] FIX: NUC123SD4AN0 does not build
This commit is contained in:
commit
9cd5012f22
|
@ -26,3 +26,6 @@ USB Host stack author
|
||||||
|
|
||||||
Yaotian Feng aka Codetector
|
Yaotian Feng aka Codetector
|
||||||
https://github.com/Codetector1374
|
https://github.com/Codetector1374
|
||||||
|
|
||||||
|
Alex Lewontin aka alexclewontin
|
||||||
|
https://github.com/alexclewontin
|
||||||
|
|
|
@ -173,6 +173,35 @@ for i in *.7z; do 7z x -y $i; done'''
|
||||||
sh '''export CH_PATH=$WORKSPACE/ChibiOS
|
sh '''export CH_PATH=$WORKSPACE/ChibiOS
|
||||||
export CHC_PATH=$WORKSPACE
|
export CHC_PATH=$WORKSPACE
|
||||||
./tools/chbuild.sh ./demos/LPC/
|
./tools/chbuild.sh ./demos/LPC/
|
||||||
|
'''
|
||||||
|
}
|
||||||
|
}
|
||||||
|
stage('Build NUMICRO') {
|
||||||
|
agent {
|
||||||
|
docker {
|
||||||
|
image 'fpoussin/jenkins:ubuntu-18.04-chibios'
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
steps {
|
||||||
|
sh '''arm-none-eabi-gcc -v
|
||||||
|
cd $WORKSPACE/ext
|
||||||
|
for i in *.7z; do 7z x -y $i; done
|
||||||
|
cd $WORKSPACE
|
||||||
|
rm -rf $CH_PATH
|
||||||
|
git clone /var/lib/git/ChibiOS $CH_PATH
|
||||||
|
cd $CH_PATH
|
||||||
|
git remote set-url origin https://github.com/ChibiOS/ChibiOS.git
|
||||||
|
git fetch --all
|
||||||
|
git checkout -b $CH_BRANCH origin/$CH_BRANCH
|
||||||
|
git pull --rebase origin $CH_BRANCH
|
||||||
|
cd ext
|
||||||
|
for i in *.7z; do 7z x -y $i; done'''
|
||||||
|
sh '''export CH_PATH=$WORKSPACE/ChibiOS
|
||||||
|
export CHC_PATH=$WORKSPACE
|
||||||
|
|
||||||
|
./tools/chbuild.sh ./testhal/NUMICRO/
|
||||||
|
./tools/chbuild.sh ./demos/NUMICRO/
|
||||||
'''
|
'''
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -0,0 +1,81 @@
|
||||||
|
# script for Nuvoton MuMicro Cortex-M0 Series
|
||||||
|
|
||||||
|
# Adapt based on what transport is active.
|
||||||
|
if [catch {transport select}] {
|
||||||
|
echo "Error: unable to select a session transport. Can't continue."
|
||||||
|
shutdown
|
||||||
|
}
|
||||||
|
|
||||||
|
proc swj_newdap {chip tag args} {
|
||||||
|
if [using_hla] {
|
||||||
|
eval hla newtap $chip $tag $args
|
||||||
|
} elseif [using_jtag] {
|
||||||
|
eval jtag newtap $chip $tag $args
|
||||||
|
} elseif [using_swd] {
|
||||||
|
eval swd newdap $chip $tag $args
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
# Set Chipname
|
||||||
|
if { [info exists CHIPNAME] } {
|
||||||
|
set _CHIPNAME $CHIPNAME
|
||||||
|
} else {
|
||||||
|
set _CHIPNAME NuMicro
|
||||||
|
}
|
||||||
|
|
||||||
|
# SWD DP-ID Nuvoton NuMicro Cortex-M0 has SWD Transport only.
|
||||||
|
if { [info exists CPUDAPID] } {
|
||||||
|
set _CPUDAPID $CPUDAPID
|
||||||
|
} else {
|
||||||
|
set _CPUDAPID 0x0BB11477
|
||||||
|
}
|
||||||
|
|
||||||
|
# Work-area is a space in RAM used for flash programming
|
||||||
|
# By default use 2kB
|
||||||
|
if { [info exists WORKAREASIZE] } {
|
||||||
|
set _WORKAREASIZE $WORKAREASIZE
|
||||||
|
} else {
|
||||||
|
set _WORKAREASIZE 0x800
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
# Debug Adapter Target Settings
|
||||||
|
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
|
||||||
|
set _TARGETNAME $_CHIPNAME.cpu
|
||||||
|
dap create $_CHIPNAME.dap -chain-position $_TARGETNAME
|
||||||
|
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
|
||||||
|
|
||||||
|
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||||
|
|
||||||
|
# flash bank <name> numicro <base> <size(autodetect,set to 0)> 0 0 <target#>
|
||||||
|
#set _FLASHNAME $_CHIPNAME.flash
|
||||||
|
#flash bank $_FLASHNAME numicro 0 $_FLASHSIZE 0 0 $_TARGETNAME
|
||||||
|
# flash size will be probed
|
||||||
|
set _FLASHNAME $_CHIPNAME.flash_aprom
|
||||||
|
flash bank $_FLASHNAME numicro 0x00000000 0 0 0 $_TARGETNAME
|
||||||
|
set _FLASHNAME $_CHIPNAME.flash_data
|
||||||
|
flash bank $_FLASHNAME numicro 0x0001F000 0 0 0 $_TARGETNAME
|
||||||
|
set _FLASHNAME $_CHIPNAME.flash_ldrom
|
||||||
|
flash bank $_FLASHNAME numicro 0x00100000 0 0 0 $_TARGETNAME
|
||||||
|
set _FLASHNAME $_CHIPNAME.flash_config
|
||||||
|
flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME
|
||||||
|
|
||||||
|
# set default SWCLK frequency
|
||||||
|
adapter speed 1000
|
||||||
|
|
||||||
|
# set default srst setting "none"
|
||||||
|
reset_config none
|
||||||
|
|
||||||
|
# HLA doesn't have cortex_m commands
|
||||||
|
if {![using_hla]} {
|
||||||
|
# if srst is not fitted use SYSRESETREQ to
|
||||||
|
# perform a soft reset
|
||||||
|
cortex_m reset_config sysresetreq
|
||||||
|
}
|
||||||
|
|
||||||
|
proc exitDebugging {} {
|
||||||
|
hla_close
|
||||||
|
shutdown
|
||||||
|
}
|
||||||
|
|
||||||
|
$_TARGETNAME configure -event gdb-detach { exitDebugging }
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,66 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file system_NUC123.h
|
||||||
|
* @version V3.0
|
||||||
|
* $Revision: 5 $
|
||||||
|
* $Date: 15/07/02 11:21a $
|
||||||
|
* @brief NUC123 Series CMSIS System Header File
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
* Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef __SYSTEM_NUC123_H
|
||||||
|
#define __SYSTEM_NUC123_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Macro Definition */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#ifndef DEBUG_PORT
|
||||||
|
# define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
Define SYSCLK
|
||||||
|
*----------------------------------------------------------------------------*/
|
||||||
|
#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
|
||||||
|
#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
|
||||||
|
#define __HIRC (22118400UL) /*!< Internal 22M RC Oscillator Frequency */
|
||||||
|
#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */
|
||||||
|
#define __HSI (50000000UL) /*!< PLL default output is 50MHz */
|
||||||
|
|
||||||
|
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||||
|
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
|
||||||
|
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Initialize the system
|
||||||
|
*
|
||||||
|
* @param none
|
||||||
|
* @return none
|
||||||
|
*
|
||||||
|
* @brief Setup the microcontroller system
|
||||||
|
* Initialize GPIO directions and values
|
||||||
|
*/
|
||||||
|
extern void SystemInit(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Update SystemCoreClock variable
|
||||||
|
*
|
||||||
|
* @param none
|
||||||
|
* @return none
|
||||||
|
*
|
||||||
|
* @brief Updates the SystemCoreClock with current core Clock
|
||||||
|
* retrieved from CPU registers.
|
||||||
|
*/
|
||||||
|
extern void SystemCoreClockUpdate(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
|
@ -1,75 +0,0 @@
|
||||||
/**************************************************************************//**
|
|
||||||
* @file system_NUC123SD4AN0.h
|
|
||||||
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for
|
|
||||||
* Device NUC123SD4AN0
|
|
||||||
* @version V5.00
|
|
||||||
* @date 13. May 2019
|
|
||||||
******************************************************************************/
|
|
||||||
/*
|
|
||||||
* Copyright (c) 2019 /u/KeepItUnder. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*
|
|
||||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
|
||||||
* not use this file except in compliance with the License.
|
|
||||||
* You may obtain a copy of the License at
|
|
||||||
*
|
|
||||||
* www.apache.org/licenses/LICENSE-2.0
|
|
||||||
*
|
|
||||||
* Unless required by applicable law or agreed to in writing, software
|
|
||||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
* See the License for the specific language governing permissions and
|
|
||||||
* limitations under the License.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef SYSTEM_NUC123SD4AN0_H /* ToDo: replace '<Device>' with your device name */
|
|
||||||
#define SYSTEM_NUC123SD4AN0_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include <stdint.h>
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Frequency Defines
|
|
||||||
*
|
|
||||||
* See NUC123 Technical Reference Manual 5.4.2, page 103
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define __HXT (12000000ul) // PCB-mounted High Frequency Crystal (12MHz)
|
|
||||||
#define __HIRC (22118400ul) // Internal MCU-block HF Oscillator Frequency (22.1184MHz)
|
|
||||||
#define __LXT (32768ul) // PCB-mounted Low Frequency Crystal (32kHz)
|
|
||||||
#define __LIRC (10000ul) // Internal MCU-block LF Oscillator Frequency (10kHz)
|
|
||||||
#define __HSI (50000000ul) // PLL clock (50MHz)
|
|
||||||
|
|
||||||
|
|
||||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
|
||||||
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
|
|
||||||
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
\brief Setup the microcontroller system.
|
|
||||||
|
|
||||||
Initialize the System and update the SystemCoreClock variable.
|
|
||||||
*/
|
|
||||||
extern void SystemInit (void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
\brief Update SystemCoreClock variable.
|
|
||||||
|
|
||||||
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
|
|
||||||
*/
|
|
||||||
extern void SystemCoreClockUpdate (void);
|
|
||||||
|
|
||||||
extern void SystemUnlockReg (void);
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* SYSTEM_NUC123SD4AN0_H */
|
|
|
@ -64,8 +64,7 @@
|
||||||
/* Including the device CMSIS header. Note, we are not using the definitions
|
/* Including the device CMSIS header. Note, we are not using the definitions
|
||||||
from this header because we need this file to be usable also from
|
from this header because we need this file to be usable also from
|
||||||
assembler source files. We verify that the info matches instead.*/
|
assembler source files. We verify that the info matches instead.*/
|
||||||
// #include "NUC123.h"
|
#include "NUC123.h"
|
||||||
#include "NUC123SD4AN0.h"
|
|
||||||
|
|
||||||
/*lint -save -e9029 [10.4] Signedness comes from external files, it is
|
/*lint -save -e9029 [10.4] Signedness comes from external files, it is
|
||||||
unpredictable but gives no problems.*/
|
unpredictable but gives no problems.*/
|
||||||
|
|
|
@ -0,0 +1,29 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2020 Alex Lewontin
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "hal.h"
|
||||||
|
|
||||||
|
const PALConfig pal_default_config;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Board-specific initialization code.
|
||||||
|
*/
|
||||||
|
void boardInit(void)
|
||||||
|
{
|
||||||
|
#if HAL_USE_PAL
|
||||||
|
OnboardLED_Init();
|
||||||
|
#endif
|
||||||
|
}
|
|
@ -0,0 +1,63 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2020 Alex Lewontin
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef BOARD_H
|
||||||
|
#define BOARD_H
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Setup for a generic board.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Board identifier.
|
||||||
|
*/
|
||||||
|
#define NUC123SD4AN0
|
||||||
|
#define BOARD_NAME "NUTINY SDK NUC123 V2.0"
|
||||||
|
|
||||||
|
|
||||||
|
#define NUC123_LSE_BYPASS TRUE
|
||||||
|
/*
|
||||||
|
* Board specific settings.
|
||||||
|
*/
|
||||||
|
/*
|
||||||
|
* External XTAL speed.
|
||||||
|
*/
|
||||||
|
#define NUC123_HSECLK 12000000UL
|
||||||
|
|
||||||
|
/*
|
||||||
|
* LED macros.
|
||||||
|
*/
|
||||||
|
#define ONBOARD_LED_LINE PAL_LINE(GPIOB, 4)
|
||||||
|
|
||||||
|
#define OnboardLED_Init() \
|
||||||
|
palSetGroupMode(GPIOB, 1, 4, PAL_MODE_OUTPUT_PUSHPULL)
|
||||||
|
#define OnboardLED_On() palClearLine(ONBOARD_LED_LINE)
|
||||||
|
#define OnboardLED_Off() palSetLine(ONBOARD_LED_LINE)
|
||||||
|
#define OnboardLED_Toggle() palToggleLine(ONBOARD_LED_LINE)
|
||||||
|
|
||||||
|
#define ONBOARD_SERIAL_DRIVER SD0
|
||||||
|
|
||||||
|
#if !defined(_FROM_ASM_)
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
void boardInit(void);
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif /* _FROM_ASM_ */
|
||||||
|
|
||||||
|
#endif /* BOARD_H */
|
|
@ -0,0 +1,12 @@
|
||||||
|
# List of all the board related files.
|
||||||
|
BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.c
|
||||||
|
|
||||||
|
# Required include directories
|
||||||
|
BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/NUTINY-SDK-NUC123-V2.0
|
||||||
|
|
||||||
|
# Define linker script file here, as the linker script is per chip variant, which should
|
||||||
|
# remain constant per board
|
||||||
|
LDSCRIPT = $(STARTUPLD_CONTRIB)/NUC123SD4AN0.ld
|
||||||
|
|
||||||
|
ALLCSRC += $(BOARDSRC)
|
||||||
|
ALLINC += $(BOARDINC)
|
|
@ -1,2 +0,0 @@
|
||||||
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/CLKv1/hal_clks_lld.c
|
|
||||||
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/CLKv1
|
|
|
@ -1,511 +0,0 @@
|
||||||
/*
|
|
||||||
Copyright (C) 2019 /u/KeepItUnder
|
|
||||||
|
|
||||||
Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
you may not use this file except in compliance with the License.
|
|
||||||
You may obtain a copy of the License at
|
|
||||||
|
|
||||||
http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
|
|
||||||
Unless required by applicable law or agreed to in writing, software
|
|
||||||
distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
See the License for the specific language governing permissions and
|
|
||||||
limitations under the License.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @file CLKv1/hal_clks_lld.c
|
|
||||||
* @brief CLK subsystem low level driver code.
|
|
||||||
*
|
|
||||||
* @addtogroup CLKS
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "hal.h"
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Driver local definitions. */
|
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Driver exported variables. */
|
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Driver local types. */
|
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Driver local variables and types. */
|
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* WDT_ModuleNum
|
|
||||||
* ADC_ModuleNum
|
|
||||||
* SPI0_ModuleNum
|
|
||||||
* SPI1_ModuleNum
|
|
||||||
* SPI2_ModuleNum
|
|
||||||
* TMR0_ModuleNum
|
|
||||||
* TMR1_ModuleNum
|
|
||||||
* TMR2_ModuleNum
|
|
||||||
* TMR3_ModuleNum
|
|
||||||
* UART0_ModuleNum
|
|
||||||
* UART1_ModuleNum
|
|
||||||
* PWM01_ModuleNum
|
|
||||||
* PWM23_ModuleNum
|
|
||||||
* I2S_ModuleNum
|
|
||||||
* FDIV_ModuleNum
|
|
||||||
* WWDT_ModuleNum
|
|
||||||
* USBD_ModuleNum
|
|
||||||
* I2C0_ModuleNum
|
|
||||||
* I2C1_ModuleNum
|
|
||||||
* PS2_ModuleNum
|
|
||||||
* PDMA_ModuleNum
|
|
||||||
* ISP_ModuleNum
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
bool clks_module_hxt_source[22] = { 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
|
|
||||||
bool clks_module_hirc_source[22] = { 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 };
|
|
||||||
bool clks_module_lirc_source[22] = { 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0 };
|
|
||||||
bool clks_module_hclk_source[22] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 };
|
|
||||||
bool clks_module_pll_source[22] = { 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
|
|
||||||
bool clks_module_ext_source[22] = { 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
|
|
||||||
bool clks_module_divider[22] = { 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 };
|
|
||||||
uint32_t clks_module_enable[22] = { CLK_APBCLK_WDT_EN_Msk,
|
|
||||||
CLK_APBCLK_ADC_EN_Msk,
|
|
||||||
CLK_APBCLK_SPI0_EN_Msk,
|
|
||||||
CLK_APBCLK_SPI1_EN_Msk,
|
|
||||||
CLK_APBCLK_SPI2_EN_Msk,
|
|
||||||
CLK_APBCLK_TMR0_EN_Msk,
|
|
||||||
CLK_APBCLK_TMR1_EN_Msk,
|
|
||||||
CLK_APBCLK_TMR2_EN_Msk,
|
|
||||||
CLK_APBCLK_TMR3_EN_Msk,
|
|
||||||
CLK_APBCLK_UART0_EN_Msk,
|
|
||||||
CLK_APBCLK_UART1_EN_Msk,
|
|
||||||
CLK_APBCLK_PWM01_EN_Msk,
|
|
||||||
CLK_APBCLK_PWM23_EN_Msk,
|
|
||||||
CLK_APBCLK_I2S_EN_Msk,
|
|
||||||
CLK_APBCLK_FDIV_EN_Msk,
|
|
||||||
0,
|
|
||||||
CLK_APBCLK_USBD_EN_Msk,
|
|
||||||
CLK_APBCLK_I2C0_EN_Msk,
|
|
||||||
CLK_APBCLK_I2C1_EN_Msk,
|
|
||||||
CLK_APBCLK_PS2_EN_Msk,
|
|
||||||
CLK_AHBCLK_PDMA_EN_Msk,
|
|
||||||
CLK_AHBCLK_ISP_EN_Msk };
|
|
||||||
uint32_t clks_module_sel1_mask[22] = { CLK_CLKSEL1_WDT_S_Msk,
|
|
||||||
CLK_CLKSEL1_ADC_S_Msk,
|
|
||||||
CLK_CLKSEL1_SPI0_S_Msk,
|
|
||||||
CLK_CLKSEL1_SPI1_S_Msk,
|
|
||||||
CLK_CLKSEL1_SPI2_S_Msk,
|
|
||||||
CLK_CLKSEL1_TMR0_S_Msk,
|
|
||||||
CLK_CLKSEL1_TMR1_S_Msk,
|
|
||||||
CLK_CLKSEL1_TMR2_S_Msk,
|
|
||||||
CLK_CLKSEL1_TMR3_S_Msk,
|
|
||||||
CLK_CLKSEL1_UART_S_Msk,
|
|
||||||
CLK_CLKSEL1_UART_S_Msk,
|
|
||||||
CLK_CLKSEL1_PWM01_S_Msk,
|
|
||||||
CLK_CLKSEL1_PWM23_S_Msk,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0, 0 };
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Driver local functions. */
|
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Driver interrupt handlers. */
|
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Driver exported functions. */
|
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Low level CLK driver initialization.
|
|
||||||
*
|
|
||||||
* @notapi
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Set Core Clock
|
|
||||||
*
|
|
||||||
* @description Set the core system clock some reference speed (Hz).
|
|
||||||
* This should be between 25MHz and 72MHz for the NUC123SD4AN0.
|
|
||||||
*
|
|
||||||
* Use either the HXT (exact) or HIRC (nearest using 22.1184MHz)
|
|
||||||
* as the clock source.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
uint32_t clks_lld_set_core_clock(uint32_t clkCore)
|
|
||||||
{
|
|
||||||
uint32_t stableHIRC;
|
|
||||||
|
|
||||||
/* Read HIRC clock source stable flag */
|
|
||||||
stableHIRC = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk;
|
|
||||||
|
|
||||||
/* Setup __HIRC */
|
|
||||||
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
|
|
||||||
|
|
||||||
clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk);
|
|
||||||
|
|
||||||
/* Use __HIRC as HCLK temporarily */
|
|
||||||
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_Msk;
|
|
||||||
CLK->CLKDIV &= (~CLK_CLKDIV_HCLK_N_Msk);
|
|
||||||
|
|
||||||
/* Is HXT stable ? */
|
|
||||||
if(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk) {
|
|
||||||
/* Use __HXT as PLL source */
|
|
||||||
clkCore = clks_lld_enable_pll(CLK_PLLCON_PLL_SRC_HXT, (clkCore << 1));
|
|
||||||
} else {
|
|
||||||
/* Use __HIRC as PLL source */
|
|
||||||
clkCore = clks_lld_enable_pll(CLK_PLLCON_PLL_SRC_HIRC, (clkCore << 1));
|
|
||||||
|
|
||||||
/* Read HIRC clock source stable flag again (since we're using it now) */
|
|
||||||
stableHIRC = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set HCLK clock source to PLL */
|
|
||||||
clks_lld_set_HCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(2));
|
|
||||||
|
|
||||||
/* Disable HIRC if HIRC was disabled before we started */
|
|
||||||
if (stableHIRC == 0) {
|
|
||||||
CLK->PWRCON &= ~CLK_PWRCON_OSC22M_EN_Msk;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Return actual HCLK frequency is PLL frequency divide 2 */
|
|
||||||
return (clkCore >> 1);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/** @brief Set system HCLK
|
|
||||||
*
|
|
||||||
* @description Setup HCLK source and divider
|
|
||||||
*
|
|
||||||
* Always switch to a known stable clock source before changing a
|
|
||||||
* system clock, to avoid issues related to the original clock's
|
|
||||||
* speed/settings.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void clks_lld_set_HCLK(uint32_t clkSource, uint32_t clkDivider)
|
|
||||||
{
|
|
||||||
uint32_t stableHIRC;
|
|
||||||
|
|
||||||
/* Read HIRC clock source stable flag */
|
|
||||||
stableHIRC = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk;
|
|
||||||
|
|
||||||
/* Setup __HIRC */
|
|
||||||
CLK->PWRCON |= CLK_CLKSTATUS_OSC22M_STB_Msk;
|
|
||||||
|
|
||||||
clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk);
|
|
||||||
|
|
||||||
/* Use __HIRC as HCLK, temporarily */
|
|
||||||
CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | CLK_CLKSEL0_HCLK_S_HIRC;
|
|
||||||
|
|
||||||
/* Set new clock divider */
|
|
||||||
CLK->CLKDIV = (CLK->CLKDIV & (~CLK_CLKDIV_HCLK_N_Msk)) | clkDivider;
|
|
||||||
|
|
||||||
/* Switch HCLK to new HCLK source */
|
|
||||||
CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | clkSource;
|
|
||||||
|
|
||||||
/* Update System Core Clock */
|
|
||||||
SystemCoreClockUpdate();
|
|
||||||
|
|
||||||
/* Disable HIRC if HIRC was disabled before we started */
|
|
||||||
if (stableHIRC == 0) {
|
|
||||||
CLK->PWRCON &= ~CLK_CLKSTATUS_OSC22M_STB_Msk;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
void clks_lld_set_module_clock(uint32_t module, uint32_t clkSource, uint32_t clkDivider)
|
|
||||||
{
|
|
||||||
/* Set clock source */
|
|
||||||
CLK->CLKSEL1 = (CLK->CLKSEL1 & (~(clks_module_sel1_mask[module]))) | clkSource;
|
|
||||||
|
|
||||||
/* Set secondary clock source bit for PWM01/PWM23 */
|
|
||||||
if (module == PWM01_ModuleNum) {
|
|
||||||
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_PWM01_S_Msk)) | (clkSource & CLK_CLKSEL2_PWM01_S_Msk);
|
|
||||||
} else if (module == PWM23_ModuleNum) {
|
|
||||||
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_PWM23_S_Msk)) | (clkSource & CLK_CLKSEL2_PWM23_S_Msk);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set clock divider */
|
|
||||||
if (clks_module_divider[module]) {
|
|
||||||
switch (module) {
|
|
||||||
case ADC_ModuleNum:
|
|
||||||
CLK->CLKDIV = (CLK->CLKDIV & ~CLK_CLKDIV_ADC_N_Msk) | clkDivider;
|
|
||||||
break;
|
|
||||||
case UART0_ModuleNum:
|
|
||||||
case UART1_ModuleNum:
|
|
||||||
CLK->CLKDIV = (CLK->CLKDIV & ~CLK_CLKDIV_UART_N_Msk) | clkDivider;
|
|
||||||
break;
|
|
||||||
case USBD_ModuleNum:
|
|
||||||
CLK->CLKDIV = (CLK->CLKDIV & ~CLK_CLKDIV_USB_N_Msk) | clkDivider;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
void clks_lld_enable_ck0(uint32_t clkSource, uint32_t clkDivider)
|
|
||||||
{
|
|
||||||
CLK->FRQDIV = (CLK_FRQDIV_DIVIDER_EN_Msk | clkDivider) ;
|
|
||||||
|
|
||||||
clks_lld_enable_module_clock(FDIV_ModuleNum);
|
|
||||||
|
|
||||||
clks_lld_set_module_clock(FDIV_ModuleNum, clkSource, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable module clock
|
|
||||||
*
|
|
||||||
* @description Module clock enables are all in either AHBCLK or APBCLK
|
|
||||||
* Register masks are stored in a table to save knowing bit width
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void clks_lld_enable_module_clock(uint32_t clkModule) {
|
|
||||||
switch (clkModule) {
|
|
||||||
case PDMA_ModuleNum:
|
|
||||||
case ISP_ModuleNum:
|
|
||||||
/* AHB Clocks */
|
|
||||||
CLK->AHBCLK |= clks_module_enable[clkModule];
|
|
||||||
break;
|
|
||||||
case WWDT_ModuleNum:
|
|
||||||
/* No Module Clock */
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
/* APB Clocks */
|
|
||||||
CLK->APBCLK |= clks_module_enable[clkModule];
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable module clock
|
|
||||||
*
|
|
||||||
* @description Module clock enables are all in either AHBCLK or APBCLK
|
|
||||||
* Register masks are stored in a table to save knowing bit width
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void clks_lld_disable_module_clock(uint32_t clkModule) {
|
|
||||||
switch (clkModule) {
|
|
||||||
case PDMA_ModuleNum:
|
|
||||||
case ISP_ModuleNum:
|
|
||||||
/* AHB Clocks */
|
|
||||||
CLK->AHBCLK &= ~clks_module_enable[clkModule];
|
|
||||||
break;
|
|
||||||
case WWDT_ModuleNum:
|
|
||||||
/* No Module Clock */
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
/* APB Clocks */
|
|
||||||
CLK->APBCLK &= ~clks_module_enable[clkModule];
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
uint32_t clks_lld_enable_pll(uint32_t pllSrc, uint32_t pllFreq)
|
|
||||||
{
|
|
||||||
/* Disable PLL first to avoid unstable when setting PLL. */
|
|
||||||
CLK->PLLCON = CLK_PLLCON_PD_Msk;
|
|
||||||
|
|
||||||
/* Check and setup correct clock source */
|
|
||||||
switch (pllSrc) {
|
|
||||||
case CLK_PLLCON_PLL_SRC_HXT:
|
|
||||||
/* Use HXT clock */
|
|
||||||
CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk;
|
|
||||||
|
|
||||||
/* Wait for stable HXT */
|
|
||||||
clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_XTL12M_STB_Msk);
|
|
||||||
|
|
||||||
|
|
||||||
break;
|
|
||||||
case CLK_PLLCON_PLL_SRC_HIRC:
|
|
||||||
/* Use HIRC clock */
|
|
||||||
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
|
|
||||||
|
|
||||||
/* Wait for stable HIRC */
|
|
||||||
clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk);
|
|
||||||
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Calculate best PLL variables from requested frequency
|
|
||||||
*
|
|
||||||
* See NUC123 Technical Reference Manual 5.4.8 PLL Control Register Description, page 124
|
|
||||||
*
|
|
||||||
* NF 1
|
|
||||||
* FOUT = FIN x -- x --
|
|
||||||
* NR NO
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
uint32_t NO = 0;
|
|
||||||
uint32_t NR = 0;
|
|
||||||
uint32_t clkCalc = 0;
|
|
||||||
|
|
||||||
/* Set "NO" for requested frequency */
|
|
||||||
/* We're using "NO" first to set the PLLCON - so make it "NO" - 1; */
|
|
||||||
if (pllFreq >= FREQ_25MHZ && pllFreq <= FREQ_50MHZ) {
|
|
||||||
/* Low frequency - use full variable headroom */
|
|
||||||
pllFreq <<= 2;
|
|
||||||
NO = 3;
|
|
||||||
} else if (pllFreq > FREQ_50MHZ && pllFreq <= FREQ_100MHZ) {
|
|
||||||
/* Medium frequency - use full variable headroom */
|
|
||||||
pllFreq <<= 1;
|
|
||||||
NO = 1;
|
|
||||||
} else if (pllFreq > FREQ_100MHZ && pllFreq <= FREQ_200MHZ) {
|
|
||||||
/* High frequency - full variable headroom already used */
|
|
||||||
NO = 0;
|
|
||||||
} else {
|
|
||||||
/* Frequency out of range - use default PLL settings
|
|
||||||
*
|
|
||||||
* See NUC123 Technical Reference Manual PLL COntrol Register Description, page 124
|
|
||||||
* The default value: 0xC22E
|
|
||||||
* FIN = 12 MHz
|
|
||||||
* NR = (1+2) = 3
|
|
||||||
* NF = (46+2) = 48
|
|
||||||
* NO = 4
|
|
||||||
* FOUT = 12/4 x 48 x 1/3 = 48 MHz
|
|
||||||
*/
|
|
||||||
if (pllSrc == CLK_PLLCON_PLL_SRC_HXT) {
|
|
||||||
CLK->PLLCON = 0xC22E;
|
|
||||||
} else {
|
|
||||||
CLK->PLLCON = 0xD66F;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Wait for stable PLL clock */
|
|
||||||
clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_PLL_STB_Msk);
|
|
||||||
|
|
||||||
return clks_lld_get_pll_clock_freq();
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Setup "NR" and clkCalc */
|
|
||||||
switch (pllSrc) {
|
|
||||||
case CLK_PLLCON_PLL_SRC_HXT:
|
|
||||||
NR = 2;
|
|
||||||
clkCalc = __HXT;
|
|
||||||
break;
|
|
||||||
case CLK_PLLCON_PLL_SRC_HIRC:
|
|
||||||
NR = 4;
|
|
||||||
clkCalc = __HIRC;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Loop to calculate best/lowest NR (between 0 or 2 and 31) and best/lowest NF (between 0 and 511)
|
|
||||||
*
|
|
||||||
* Best results are off-by-2 until final equation calculation (to allow use in PLLCON)
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
uint32_t bestNR = 0;
|
|
||||||
uint32_t bestNF = 0;
|
|
||||||
uint32_t minLimit = -1;
|
|
||||||
|
|
||||||
while (NR <= 33) {
|
|
||||||
uint32_t tmpCalc1 = clkCalc / NR;
|
|
||||||
|
|
||||||
if (tmpCalc1 > 1600000 && tmpCalc1 < 16000000) {
|
|
||||||
uint32_t NF = 2;
|
|
||||||
|
|
||||||
while (NF <= 513) {
|
|
||||||
uint32_t tmpCalc2 = tmpCalc1 * NF;
|
|
||||||
|
|
||||||
if (tmpCalc2 >= 100000000 && tmpCalc2 <= 200000000) {
|
|
||||||
uint32_t tmpCalc3;
|
|
||||||
|
|
||||||
if (tmpCalc2 > pllFreq) {
|
|
||||||
tmpCalc3 = tmpCalc2 - pllFreq;
|
|
||||||
} else {
|
|
||||||
tmpCalc3 = pllFreq - tmpCalc2;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (tmpCalc3 < minLimit) {
|
|
||||||
minLimit = tmpCalc3;
|
|
||||||
bestNF = NF;
|
|
||||||
bestNR = NR;
|
|
||||||
|
|
||||||
/* Stop NF calc loop when minLimit tends back to 0 */
|
|
||||||
if(minLimit == 0)
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
NF++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
NR++;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Enable and apply new PLL setting. */
|
|
||||||
CLK->PLLCON = pllSrc | (NO << 14) | ((bestNR - 2) << 9) | (bestNF - 2);
|
|
||||||
|
|
||||||
/* Wait for stable PLL clock */
|
|
||||||
clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_PLL_STB_Msk);
|
|
||||||
|
|
||||||
/* Return equation result */
|
|
||||||
return (clkCalc / ((NO + 1) * bestNR) * bestNF);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Wait for stable clock
|
|
||||||
*
|
|
||||||
* @description Always wait around 300ms for clock to be stable
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
uint32_t clks_lld_wait_for_clock_ready(uint32_t clkMask)
|
|
||||||
{
|
|
||||||
int32_t timeout = 2180000;
|
|
||||||
|
|
||||||
while (timeout-- > 0) {
|
|
||||||
if ((CLK->CLKSTATUS & clkMask) == clkMask) {
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
void clks_lld_enable_SysTick(uint32_t clkSrc, uint32_t count) {
|
|
||||||
|
|
||||||
// Disable the counter
|
|
||||||
clks_lld_disable_SysTick();
|
|
||||||
|
|
||||||
// Clear current values/flags
|
|
||||||
SysTick->VAL = 0;
|
|
||||||
|
|
||||||
// Set SysTick Clock Source
|
|
||||||
switch (clkSrc) {
|
|
||||||
case CLK_CLKSEL0_STCLK_S_HCLK:
|
|
||||||
SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLK_S_Msk) | clkSrc;
|
|
||||||
// CLK->CLKSEL0 |= SysTick_CTRL_CLKSOURCE_Msk;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Set reload value
|
|
||||||
SysTick->LOAD = count;
|
|
||||||
|
|
||||||
// Enable Interrupt and Counter
|
|
||||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
void clks_lld_disable_SysTick(void) {
|
|
||||||
/* Disable System Tick counter */
|
|
||||||
SysTick->CTRL = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/** @} */
|
|
|
@ -1,222 +0,0 @@
|
||||||
/*
|
|
||||||
Copyright (C) 2019 /u/KeepItUnder
|
|
||||||
|
|
||||||
Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
you may not use this file except in compliance with the License.
|
|
||||||
You may obtain a copy of the License at
|
|
||||||
|
|
||||||
http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
|
|
||||||
Unless required by applicable law or agreed to in writing, software
|
|
||||||
distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
See the License for the specific language governing permissions and
|
|
||||||
limitations under the License.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @file hal_clks_lld.h
|
|
||||||
* @brief Clock/Timer subsystem low level header.
|
|
||||||
*
|
|
||||||
* @addtogroup CLKS
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef HAL_CLKS_LLD_H
|
|
||||||
#define HAL_CLKS_LLD_H
|
|
||||||
|
|
||||||
// #if HAL_USE_CLKS || defined(__DOXYGEN__)
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Driver constants. */
|
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
#define FREQ_25MHZ 25000000
|
|
||||||
#define FREQ_50MHZ 50000000
|
|
||||||
#define FREQ_72MHZ 72000000
|
|
||||||
#define FREQ_100MHZ 100000000
|
|
||||||
#define FREQ_200MHZ 200000000
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------------------------*/
|
|
||||||
/* CLKSEL0 */
|
|
||||||
/*---------------------------------------------------------------------------------------------------------*/
|
|
||||||
#define CLK_CLKSEL0_HCLK_S_HXT (0x0ul<<CLK_CLKSEL0_HCLK_S_Pos) /*!< Set HCLK clock source as HXT */
|
|
||||||
#define CLK_CLKSEL0_HCLK_S_PLL_DIV2 (0x1ul<<CLK_CLKSEL0_HCLK_S_Pos) /*!< Set HCLK clock source as PLL/2 */
|
|
||||||
#define CLK_CLKSEL0_HCLK_S_PLL (0x2ul<<CLK_CLKSEL0_HCLK_S_Pos) /*!< Set HCLK clock source as PLL */
|
|
||||||
#define CLK_CLKSEL0_HCLK_S_LIRC (0x3ul<<CLK_CLKSEL0_HCLK_S_Pos) /*!< Set HCLK clock source as LIRC */
|
|
||||||
#define CLK_CLKSEL0_HCLK_S_HIRC (0x7ul<<CLK_CLKSEL0_HCLK_S_Pos) /*!< Set HCLK clock source as HIRC */
|
|
||||||
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------------------------*/
|
|
||||||
/* CLKSEL1 */
|
|
||||||
/*---------------------------------------------------------------------------------------------------------*/
|
|
||||||
#define CLK_CLKSEL1_TMR0_S_HXT (0x0ul<<CLK_CLKSEL1_TMR0_S_Pos) /*!< Set TMR0 clock source as HXT */
|
|
||||||
#define CLK_CLKSEL1_TMR0_S_HCLK (0x2ul<<CLK_CLKSEL1_TMR0_S_Pos) /*!< Set TMR0 clock source as HCLK */
|
|
||||||
#define CLK_CLKSEL1_TMR0_S_EXT_TRG (0x3ul<<CLK_CLKSEL1_TMR0_S_Pos) /*!< Set TMR0 clock source as external trigger */
|
|
||||||
#define CLK_CLKSEL1_TMR0_S_LIRC (0x5ul<<CLK_CLKSEL1_TMR0_S_Pos) /*!< Set TMR0 clock source as LIRC */
|
|
||||||
#define CLK_CLKSEL1_TMR0_S_HIRC (0x7ul<<CLK_CLKSEL1_TMR0_S_Pos) /*!< Set TMR0 clock source as HIRC */
|
|
||||||
#define CLK_CLKSEL1_TMR1_S_HXT (0x0ul<<CLK_CLKSEL1_TMR1_S_Pos) /*!< Set TMR1 clock source as HXT */
|
|
||||||
#define CLK_CLKSEL1_TMR1_S_HCLK (0x2ul<<CLK_CLKSEL1_TMR1_S_Pos) /*!< Set TMR1 clock source as HCLK */
|
|
||||||
#define CLK_CLKSEL1_TMR1_S_EXT_TRG (0x3ul<<CLK_CLKSEL1_TMR1_S_Pos) /*!< Set TMR1 clock source as external trigger */
|
|
||||||
#define CLK_CLKSEL1_TMR1_S_LIRC (0x5ul<<CLK_CLKSEL1_TMR1_S_Pos) /*!< Set TMR1 clock source as LIRC */
|
|
||||||
#define CLK_CLKSEL1_TMR1_S_HIRC (0x7ul<<CLK_CLKSEL1_TMR1_S_Pos) /*!< Set TMR1 clock source as HIRC*/
|
|
||||||
#define CLK_CLKSEL1_TMR2_S_HXT (0x0ul<<CLK_CLKSEL1_TMR2_S_Pos) /*!< Set TMR2 clock source as external X'tal */
|
|
||||||
#define CLK_CLKSEL1_TMR2_S_HCLK (0x2ul<<CLK_CLKSEL1_TMR2_S_Pos) /*!< Set TMR2 clock source as HCLK */
|
|
||||||
#define CLK_CLKSEL1_TMR2_S_EXT_TRG (0x3ul<<CLK_CLKSEL1_TMR2_S_Pos) /*!< Set TMR2 clock source as external trigger */
|
|
||||||
#define CLK_CLKSEL1_TMR2_S_LIRC (0x5ul<<CLK_CLKSEL1_TMR2_S_Pos) /*!< Set TMR2 clock source as LIRC */
|
|
||||||
#define CLK_CLKSEL1_TMR2_S_HIRC (0x7ul<<CLK_CLKSEL1_TMR2_S_Pos) /*!< Set TMR2 clock source as HIRC */
|
|
||||||
#define CLK_CLKSEL1_TMR3_S_HXT (0x0ul<<CLK_CLKSEL1_TMR3_S_Pos) /*!< Set TMR3 clock source as HXT */
|
|
||||||
#define CLK_CLKSEL1_TMR3_S_HCLK (0x2ul<<CLK_CLKSEL1_TMR3_S_Pos) /*!< Set TMR3 clock source as HCLK */
|
|
||||||
#define CLK_CLKSEL1_TMR3_S_EXT_TRG (0x3ul<<CLK_CLKSEL1_TMR3_S_Pos) /*!< Set TMR3 clock source as external trigger */
|
|
||||||
#define CLK_CLKSEL1_TMR3_S_LIRC (0x5ul<<CLK_CLKSEL1_TMR3_S_Pos) /*!< Set TMR3 clock source as LIRC */
|
|
||||||
#define CLK_CLKSEL1_TMR3_S_HIRC (0x7ul<<CLK_CLKSEL1_TMR3_S_Pos) /*!< Set TMR3 clock source as HIRC */
|
|
||||||
#define CLK_CLKSEL1_PWM01_S_HXT (0x0ul<<CLK_CLKSEL1_PWM01_S_Pos) /*!< Set PWM01 clock source as HXT */
|
|
||||||
#define CLK_CLKSEL1_PWM01_S_HCLK (0x2ul<<CLK_CLKSEL1_PWM01_S_Pos) /*!< Set PWM01 clock source as HCLK */
|
|
||||||
#define CLK_CLKSEL1_PWM01_S_HIRC (0x3ul<<CLK_CLKSEL1_PWM01_S_Pos) /*!< Set PWM01 clock source as HIRC */
|
|
||||||
#define CLK_CLKSEL1_PWM01_S_LIRC (0x3ul<<CLK_CLKSEL1_PWM01_S_Pos) /*!< Set PWM01 clock source as LIRC */
|
|
||||||
#define CLK_CLKSEL1_PWM23_S_HXT (0x0ul<<CLK_CLKSEL1_PWM23_S_Pos) /*!< Set PWM23 clock source as HXT */
|
|
||||||
#define CLK_CLKSEL1_PWM23_S_HCLK (0x2ul<<CLK_CLKSEL1_PWM23_S_Pos) /*!< Set PWM23 clock source as HCLK */
|
|
||||||
#define CLK_CLKSEL1_PWM23_S_HIRC (0x3ul<<CLK_CLKSEL1_PWM23_S_Pos) /*!< Set PWM23 clock source as HIRC */
|
|
||||||
#define CLK_CLKSEL1_PWM23_S_LIRC (0x3ul<<CLK_CLKSEL1_PWM23_S_Pos) /*!< Set PWM23 clock source as LIRC */
|
|
||||||
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------------------------*/
|
|
||||||
/* CLKSEL2 */
|
|
||||||
/*---------------------------------------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
#define CLK_CLKSEL2_PWM01_EXT_HXT (0x0ul<<CLK_CLKSEL2_PWM01_S_Pos) /*!< Set PWM01 clock source as HXT */
|
|
||||||
#define CLK_CLKSEL2_PWM01_EXT_HCLK (0x0ul<<CLK_CLKSEL2_PWM01_S_Pos) /*!< Set PWM01 clock source as HCLK */
|
|
||||||
#define CLK_CLKSEL2_PWM01_EXT_HIRC (0x0ul<<CLK_CLKSEL2_PWM01_S_Pos) /*!< Set PWM01 clock source as HIRC */
|
|
||||||
#define CLK_CLKSEL2_PWM01_EXT_LIRC (0x1ul<<CLK_CLKSEL2_PWM01_S_Pos) /*!< Set PWM01 clock source as LIRC */
|
|
||||||
#define CLK_CLKSEL2_PWM23_EXT_HXT (0x0ul<<CLK_CLKSEL2_PWM23_S_Pos) /*!< Set PWM23 clock source as HXT */
|
|
||||||
#define CLK_CLKSEL2_PWM23_EXT_HCLK (0x0ul<<CLK_CLKSEL2_PWM23_S_Pos) /*!< Set PWM23 clock source as HCLK */
|
|
||||||
#define CLK_CLKSEL2_PWM23_EXT_HIRC (0x0ul<<CLK_CLKSEL2_PWM23_S_Pos) /*!< Set PWM23 clock source as HIRC */
|
|
||||||
#define CLK_CLKSEL2_PWM23_EXT_LIRC (0x1ul<<CLK_CLKSEL2_PWM23_S_Pos) /*!< Set PWM23 clock source as LIRC */
|
|
||||||
|
|
||||||
#define CLK_CLKSEL2_FRQDIV_S_HXT (0x0ul<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!< Set FRQDIV clock source as HXT */
|
|
||||||
#define CLK_CLKSEL2_FRQDIV_S_HCLK (0x2ul<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!< Set FRQDIV clock source as HCLK */
|
|
||||||
#define CLK_CLKSEL2_FRQDIV_S_HIRC (0x3ul<<CLK_CLKSEL2_FRQDIV_S_Pos) /*!< Set FRQDIV clock source as HIRC */
|
|
||||||
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------------------------*/
|
|
||||||
/* CLKDIV */
|
|
||||||
/*---------------------------------------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
#define CLK_CLKDIV_HCLK(x) ((x)-1) /*!< HCLK clock divider (1~16) */
|
|
||||||
#define CLK_CLKDIV_USB(x) (((x)-1) << CLK_CLKDIV_USB_N_Pos) /*!< USB clock divider (1~16) */
|
|
||||||
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------------------------*/
|
|
||||||
/* PLLCON */
|
|
||||||
/*---------------------------------------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
#define CLK_PLLCON_PLL_SRC_HXT 0x00000000ul /*!< Set PLL clock source as HXT */
|
|
||||||
#define CLK_PLLCON_PLL_SRC_HIRC 0x00080000ul /*!< Set PLL clock source as HIRC */
|
|
||||||
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Driver pre-compile time settings. */
|
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @name Configuration options
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @} */
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Derived constants and error checks. */
|
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Driver data structures and types. */
|
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* Driver macros. */
|
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
|
||||||
/* External declarations. */
|
|
||||||
/*===========================================================================*/
|
|
||||||
|
|
||||||
// extern DACDriver DACD1;
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
// void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
|
|
||||||
// void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
|
|
||||||
// void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
|
|
||||||
// uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
|
|
||||||
// void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
|
|
||||||
// void CLK_DisableSysTick(void);
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get PLL clock frequency
|
|
||||||
* @param None
|
|
||||||
* @return PLL frequency
|
|
||||||
* @details This function get PLL frequency. The frequency unit is Hz.
|
|
||||||
*/
|
|
||||||
static inline uint32_t clks_lld_get_pll_clock_freq(void) {
|
|
||||||
uint32_t PllReg;
|
|
||||||
uint32_t pllFIN, pllNF, pllNR, pllNO;
|
|
||||||
|
|
||||||
PllReg = CLK->PLLCON;
|
|
||||||
|
|
||||||
if(PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) {
|
|
||||||
PllClock = 0; /* PLL is in power down mode or fix low */
|
|
||||||
} else {
|
|
||||||
|
|
||||||
if (PllReg & CLK_PLLCON_PLL_SRC_HIRC) {
|
|
||||||
pllFIN = __HIRC; /* Use HXT for PLL clock */
|
|
||||||
} else {
|
|
||||||
pllFIN = __HXT; /* Use HXT for PLL clock */
|
|
||||||
}
|
|
||||||
|
|
||||||
if (PllReg & CLK_PLLCON_BP_Msk) {
|
|
||||||
PllClock = pllFIN;
|
|
||||||
} else {
|
|
||||||
switch (((PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)) {
|
|
||||||
case 0b00: // OUT_DIV == 00 : NO = 1
|
|
||||||
pllNO = 1;
|
|
||||||
break;
|
|
||||||
case 0b11: // OUT_DIV == 11 : NO = 4
|
|
||||||
pllNO = 4;
|
|
||||||
break;
|
|
||||||
default: // OUT_DIV == 01 or 10 : NO = 2
|
|
||||||
pllNO = 2;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
pllNF = ((PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2;
|
|
||||||
pllNR = ((PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2;
|
|
||||||
|
|
||||||
/* shift to avoid overflow condition */
|
|
||||||
PllClock = (((pllFIN >> 2) * pllNF) / (pllNR * pllNO) << 2);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return PllClock;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint32_t clks_lld_set_core_clock(uint32_t clkCore);
|
|
||||||
void clks_lld_set_HCLK(uint32_t clkSource, uint32_t clkDivider);
|
|
||||||
void clks_lld_set_module_clock(uint32_t module, uint32_t clkSource, uint32_t clkDivider);
|
|
||||||
void clks_lld_enable_ck0(uint32_t clkSource, uint32_t clkDivider);
|
|
||||||
void clks_lld_enable_module_clock(uint32_t moduleIdx);
|
|
||||||
void clks_lld_disable_module_clock(uint32_t moduleIdx);
|
|
||||||
uint32_t clks_lld_enable_pll(uint32_t pllSrc, uint32_t pllFreq);
|
|
||||||
uint32_t clks_lld_wait_for_clock_ready(uint32_t clkMask);
|
|
||||||
void clks_lld_enable_SysTick(uint32_t clkSource, uint32_t count);
|
|
||||||
void clks_lld_disable_SysTick(void);
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* HAL_CLK_LLD_H */
|
|
||||||
|
|
||||||
/** @} */
|
|
|
@ -1,10 +1,10 @@
|
||||||
# PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/gpio.c
|
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c
|
||||||
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1
|
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1
|
||||||
|
|
||||||
ifeq ($(USE_SMART_BUILD),yes)
|
# ifeq ($(USE_SMART_BUILD),yes)
|
||||||
ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
|
# ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
|
||||||
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c
|
# PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c
|
||||||
endif
|
# endif
|
||||||
else
|
# else
|
||||||
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c
|
# PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c
|
||||||
endif
|
# endif
|
||||||
|
|
|
@ -143,7 +143,7 @@ void _pal_lld_init(const PALConfig *config) {
|
||||||
GPIOF->DOUT = config->PFData.DOUT;
|
GPIOF->DOUT = config->PFData.DOUT;
|
||||||
|
|
||||||
/* Set DeBounce conditions */
|
/* Set DeBounce conditions */
|
||||||
GPIO_DBNCE->DBNCECON = 0x04u;
|
GPIO->DBNCECON = 0x04u;
|
||||||
|
|
||||||
/* Enable External Crystal Oscillator pins */
|
/* Enable External Crystal Oscillator pins */
|
||||||
SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN;
|
SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN;
|
||||||
|
|
|
@ -214,11 +214,11 @@
|
||||||
#define SYS_ALT_MFP1_PB0_GPIO NULL
|
#define SYS_ALT_MFP1_PB0_GPIO NULL
|
||||||
|
|
||||||
/* UART0 RXD */
|
/* UART0 RXD */
|
||||||
#define SYS_GPB_MFP_PB0_UART0_RXD (0x01ul<<GPB_MFP0)
|
#define SYS_GPB_MFP_PB0_UART0_RXD (0x01ul << 0)
|
||||||
#define SYS_ALT_MFP_PB0_UART0_RXD NULL
|
#define SYS_ALT_MFP_PB0_UART0_RXD NULL
|
||||||
#define SYS_ALT_MFP1_PB0_UART0_RXD NULL
|
#define SYS_ALT_MFP1_PB0_UART0_RXD NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB0_Msk (0x01ul<<GPB_MFP0)
|
#define SYS_GPB_MFP_PB0_Msk (0x01ul << 0)
|
||||||
#define SYS_ALT_MFP_PB0_Msk NULL
|
#define SYS_ALT_MFP_PB0_Msk NULL
|
||||||
#define SYS_ALT_MFP1_PB0_Msk NULL
|
#define SYS_ALT_MFP1_PB0_Msk NULL
|
||||||
|
|
||||||
|
@ -229,11 +229,11 @@
|
||||||
#define SYS_ALT_MFP1_PB1_GPIO NULL
|
#define SYS_ALT_MFP1_PB1_GPIO NULL
|
||||||
|
|
||||||
/* UART0 TXD */
|
/* UART0 TXD */
|
||||||
#define SYS_GPB_MFP_PB1_UART0_TXD (0x01ul<<GPB_MFP1)
|
#define SYS_GPB_MFP_PB1_UART0_TXD (0x01ul << 1)
|
||||||
#define SYS_ALT_MFP_PB1_UART0_TXD NULL
|
#define SYS_ALT_MFP_PB1_UART0_TXD NULL
|
||||||
#define SYS_ALT_MFP1_PB1_UART0_TXD NULL
|
#define SYS_ALT_MFP1_PB1_UART0_TXD NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB1_Msk (0x01ul<<GPB_MFP1)
|
#define SYS_GPB_MFP_PB1_Msk (0x01ul<< 1)
|
||||||
#define SYS_ALT_MFP_PB1_Msk NULL
|
#define SYS_ALT_MFP_PB1_Msk NULL
|
||||||
#define SYS_ALT_MFP1_PB1_Msk NULL
|
#define SYS_ALT_MFP1_PB1_Msk NULL
|
||||||
|
|
||||||
|
@ -244,16 +244,16 @@
|
||||||
#define SYS_ALT_MFP1_PB2_GPIO NULL
|
#define SYS_ALT_MFP1_PB2_GPIO NULL
|
||||||
|
|
||||||
/* UART0 nRTS */
|
/* UART0 nRTS */
|
||||||
#define SYS_GPB_MFP_PB2_UART0_nRTS (0x01ul<<GPB_MFP2)
|
#define SYS_GPB_MFP_PB2_UART0_nRTS (0x01ul<<2)
|
||||||
#define SYS_ALT_MFP_PB2_UART0_nRTS 0x0ul
|
#define SYS_ALT_MFP_PB2_UART0_nRTS 0x0ul
|
||||||
#define SYS_ALT_MFP1_PB2_UART0_nRTS NULL
|
#define SYS_ALT_MFP1_PB2_UART0_nRTS NULL
|
||||||
|
|
||||||
/* TM2_EXT */
|
/* TM2_EXT */
|
||||||
#define SYS_GPB_MFP_PB2_TM2_EXT (0x01ul<<GPB_MFP2)
|
#define SYS_GPB_MFP_PB2_TM2_EXT (0x01ul<<2)
|
||||||
#define SYS_ALT_MFP_PB2_TM2_EXT (0x01ul<<SYS_ALT_MFP_PB2_MFP1_Pos)
|
#define SYS_ALT_MFP_PB2_TM2_EXT (0x01ul<<SYS_ALT_MFP_PB2_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB2_TM2_EXT NULL
|
#define SYS_ALT_MFP1_PB2_TM2_EXT NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB2_Msk (0x01ul<<GPB_MFP2)
|
#define SYS_GPB_MFP_PB2_Msk (0x01ul<<2)
|
||||||
#define SYS_ALT_MFP_PB2_Msk (0x01ul<<SYS_ALT_MFP_PB2_MFP1_Pos)
|
#define SYS_ALT_MFP_PB2_Msk (0x01ul<<SYS_ALT_MFP_PB2_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB2_Msk NULL
|
#define SYS_ALT_MFP1_PB2_Msk NULL
|
||||||
|
|
||||||
|
@ -264,16 +264,16 @@
|
||||||
#define SYS_ALT_MFP1_PB3_GPIO NULL
|
#define SYS_ALT_MFP1_PB3_GPIO NULL
|
||||||
|
|
||||||
/* UART0 nCTS */
|
/* UART0 nCTS */
|
||||||
#define SYS_GPB_MFP_PB3_UART0_nCTS (0x01ul<<GPB_MFP3)
|
#define SYS_GPB_MFP_PB3_UART0_nCTS (0x01ul<<3)
|
||||||
#define SYS_ALT_MFP_PB3_UART0_nCTS 0x0ul
|
#define SYS_ALT_MFP_PB3_UART0_nCTS 0x0ul
|
||||||
#define SYS_ALT_MFP1_PB3_UART0_nCTS NULL
|
#define SYS_ALT_MFP1_PB3_UART0_nCTS NULL
|
||||||
|
|
||||||
/* TM3_EXT */
|
/* TM3_EXT */
|
||||||
#define SYS_GPB_MFP_PB3_TM3_EXT (0x01ul<<GPB_MFP3)
|
#define SYS_GPB_MFP_PB3_TM3_EXT (0x01ul<<3)
|
||||||
#define SYS_ALT_MFP_PB3_TM3_EXT (0x01ul<<SYS_ALT_MFP_PB3_MFP1_Pos)
|
#define SYS_ALT_MFP_PB3_TM3_EXT (0x01ul<<SYS_ALT_MFP_PB3_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB3_TM3_EXT NULL
|
#define SYS_ALT_MFP1_PB3_TM3_EXT NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB3_Msk (0x01ul<<GPB_MFP3)
|
#define SYS_GPB_MFP_PB3_Msk (0x01ul<<3)
|
||||||
#define SYS_ALT_MFP_PB3_Msk (0x01ul<<SYS_ALT_MFP_PB3_MFP1_Pos)
|
#define SYS_ALT_MFP_PB3_Msk (0x01ul<<SYS_ALT_MFP_PB3_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB3_Msk NULL
|
#define SYS_ALT_MFP1_PB3_Msk NULL
|
||||||
|
|
||||||
|
@ -284,7 +284,7 @@
|
||||||
#define SYS_ALT_MFP1_PB4_GPIO NULL
|
#define SYS_ALT_MFP1_PB4_GPIO NULL
|
||||||
|
|
||||||
/* UART1 RXD */
|
/* UART1 RXD */
|
||||||
#define SYS_GPB_MFP_PB4_UART1_RXD (0x01ul<<GPB_MFP4)
|
#define SYS_GPB_MFP_PB4_UART1_RXD (0x01ul<<4)
|
||||||
#define SYS_ALT_MFP_PB4_UART1_RXD 0x0ul
|
#define SYS_ALT_MFP_PB4_UART1_RXD 0x0ul
|
||||||
#define SYS_ALT_MFP1_PB4_UART1_RXD NULL
|
#define SYS_ALT_MFP1_PB4_UART1_RXD NULL
|
||||||
|
|
||||||
|
@ -294,11 +294,11 @@
|
||||||
#define SYS_ALT_MFP1_PB4_SPI2_SS0 NULL
|
#define SYS_ALT_MFP1_PB4_SPI2_SS0 NULL
|
||||||
|
|
||||||
/* SPI1 SS1 */
|
/* SPI1 SS1 */
|
||||||
#define SYS_GPB_MFP_PB4_SPI1_SS1 (0x01ul<<GPB_MFP4)
|
#define SYS_GPB_MFP_PB4_SPI1_SS1 (0x01ul<<4)
|
||||||
#define SYS_ALT_MFP_PB4_SPI1_SS1 (0x01ul<<SYS_ALT_MFP_PB4_MFP1_Pos)
|
#define SYS_ALT_MFP_PB4_SPI1_SS1 (0x01ul<<SYS_ALT_MFP_PB4_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB4_SPI1_SS1 NULL
|
#define SYS_ALT_MFP1_PB4_SPI1_SS1 NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB4_Msk (0x01ul<<GPB_MFP4)
|
#define SYS_GPB_MFP_PB4_Msk (0x01ul<<4)
|
||||||
#define SYS_ALT_MFP_PB4_Msk (0x01ul<<SYS_ALT_MFP_PB4_MFP1_Pos)
|
#define SYS_ALT_MFP_PB4_Msk (0x01ul<<SYS_ALT_MFP_PB4_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB4_Msk NULL
|
#define SYS_ALT_MFP1_PB4_Msk NULL
|
||||||
|
|
||||||
|
@ -309,16 +309,16 @@
|
||||||
#define SYS_ALT_MFP1_PB5_GPIO NULL
|
#define SYS_ALT_MFP1_PB5_GPIO NULL
|
||||||
|
|
||||||
/* UART1 TXD */
|
/* UART1 TXD */
|
||||||
#define SYS_GPB_MFP_PB5_UART1_TXD (0x01ul<<GPB_MFP5)
|
#define SYS_GPB_MFP_PB5_UART1_TXD (0x01ul<<5)
|
||||||
#define SYS_ALT_MFP_PB5_UART1_TXD 0x0ul
|
#define SYS_ALT_MFP_PB5_UART1_TXD 0x0ul
|
||||||
#define SYS_ALT_MFP1_PB5_UART1_TXD NULL
|
#define SYS_ALT_MFP1_PB5_UART1_TXD NULL
|
||||||
|
|
||||||
/* SPI2 CLK */
|
/* SPI2 CLK */
|
||||||
#define SYS_GPB_MFP_PB5_SPI2_CLK (0x01ul<<GPB_MFP5)
|
#define SYS_GPB_MFP_PB5_SPI2_CLK (0x01ul<<5)
|
||||||
#define SYS_ALT_MFP_PB5_SPI2_CLK (0x01ul<<SYS_ALT_MFP_PB5_MFP1_Pos)
|
#define SYS_ALT_MFP_PB5_SPI2_CLK (0x01ul<<SYS_ALT_MFP_PB5_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB5_SPI2_CLK NULL
|
#define SYS_ALT_MFP1_PB5_SPI2_CLK NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB5_Msk (0x01ul<<GPB_MFP5)
|
#define SYS_GPB_MFP_PB5_Msk (0x01ul<<5)
|
||||||
#define SYS_ALT_MFP_PB5_Msk (0x01ul<<SYS_ALT_MFP_PB5_MFP1_Pos)
|
#define SYS_ALT_MFP_PB5_Msk (0x01ul<<SYS_ALT_MFP_PB5_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB5_Msk NULL
|
#define SYS_ALT_MFP1_PB5_Msk NULL
|
||||||
|
|
||||||
|
@ -329,16 +329,16 @@
|
||||||
#define SYS_ALT_MFP1_PB6_GPIO NULL
|
#define SYS_ALT_MFP1_PB6_GPIO NULL
|
||||||
|
|
||||||
/* UART1 nRTS */
|
/* UART1 nRTS */
|
||||||
#define SYS_GPB_MFP_PB6_UART1_nRTS (0x01ul<<GPB_MFP6)
|
#define SYS_GPB_MFP_PB6_UART1_nRTS (0x01ul<<6)
|
||||||
#define SYS_ALT_MFP_PB6_UART1_nRTS 0x0ul
|
#define SYS_ALT_MFP_PB6_UART1_nRTS 0x0ul
|
||||||
#define SYS_ALT_MFP1_PB6_UART1_nRTS NULL
|
#define SYS_ALT_MFP1_PB6_UART1_nRTS NULL
|
||||||
|
|
||||||
/* SPI2 MOSI0 */
|
/* SPI2 MOSI0 */
|
||||||
#define SYS_GPB_MFP_PB6_SPI2_MOSI0 (0x01ul<<GPB_MFP6)
|
#define SYS_GPB_MFP_PB6_SPI2_MOSI0 (0x01ul<<6)
|
||||||
#define SYS_ALT_MFP_PB6_SPI2_MOSI0 (0x01ul<<SYS_ALT_MFP_PB6_MFP1_Pos)
|
#define SYS_ALT_MFP_PB6_SPI2_MOSI0 (0x01ul<<SYS_ALT_MFP_PB6_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB6_SPI2_MOSI0 NULL
|
#define SYS_ALT_MFP1_PB6_SPI2_MOSI0 NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB6_Msk (0x01ul<<GPB_MFP6)
|
#define SYS_GPB_MFP_PB6_Msk (0x01ul<<6)
|
||||||
#define SYS_ALT_MFP_PB6_Msk (0x01ul<<SYS_ALT_MFP_PB6_MFP1_Pos)
|
#define SYS_ALT_MFP_PB6_Msk (0x01ul<<SYS_ALT_MFP_PB6_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB6_Msk NULL
|
#define SYS_ALT_MFP1_PB6_Msk NULL
|
||||||
|
|
||||||
|
@ -349,16 +349,16 @@
|
||||||
#define SYS_ALT_MFP1_PB7_GPIO NULL
|
#define SYS_ALT_MFP1_PB7_GPIO NULL
|
||||||
|
|
||||||
/* UART1 nCTS */
|
/* UART1 nCTS */
|
||||||
#define SYS_GPB_MFP_PB7_UART1_nCTS (0x01ul<<GPB_MFP7)
|
#define SYS_GPB_MFP_PB7_UART1_nCTS (0x01ul<<7)
|
||||||
#define SYS_ALT_MFP_PB7_UART1_nCTS 0x0ul
|
#define SYS_ALT_MFP_PB7_UART1_nCTS 0x0ul
|
||||||
#define SYS_ALT_MFP1_PB7_UART1_nCTS NULL
|
#define SYS_ALT_MFP1_PB7_UART1_nCTS NULL
|
||||||
|
|
||||||
/* SPI2 MISO0 */
|
/* SPI2 MISO0 */
|
||||||
#define SYS_GPB_MFP_PB7_SPI2_MISO0 (0x01ul<<GPB_MFP7)
|
#define SYS_GPB_MFP_PB7_SPI2_MISO0 (0x01ul<<7)
|
||||||
#define SYS_ALT_MFP_PB7_SPI2_MISO0 (0x01ul<<SYS_ALT_MFP_PB7_MFP1_Pos)
|
#define SYS_ALT_MFP_PB7_SPI2_MISO0 (0x01ul<<SYS_ALT_MFP_PB7_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB7_SPI2_MISO0 NULL
|
#define SYS_ALT_MFP1_PB7_SPI2_MISO0 NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB7_Msk (0x01ul<<GPB_MFP7)
|
#define SYS_GPB_MFP_PB7_Msk (0x01ul<<7)
|
||||||
#define SYS_ALT_MFP_PB7_Msk (0x01ul<<SYS_ALT_MFP_PB7_MFP1_Pos)
|
#define SYS_ALT_MFP_PB7_Msk (0x01ul<<SYS_ALT_MFP_PB7_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB7_Msk NULL
|
#define SYS_ALT_MFP1_PB7_Msk NULL
|
||||||
|
|
||||||
|
@ -369,11 +369,11 @@
|
||||||
#define SYS_ALT_MFP1_PB8_GPIO NULL
|
#define SYS_ALT_MFP1_PB8_GPIO NULL
|
||||||
|
|
||||||
/* TM0 */
|
/* TM0 */
|
||||||
#define SYS_GPB_MFP_PB8_TM0 (0x01ul<<GPB_MFP8)
|
#define SYS_GPB_MFP_PB8_TM0 (0x01ul<<8)
|
||||||
#define SYS_ALT_MFP_PB8_TM0 NULL
|
#define SYS_ALT_MFP_PB8_TM0 NULL
|
||||||
#define SYS_ALT_MFP1_PB8_TM0 NULL
|
#define SYS_ALT_MFP1_PB8_TM0 NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB8_Msk (0x01ul<<GPB_MFP8)
|
#define SYS_GPB_MFP_PB8_Msk (0x01ul<<8)
|
||||||
#define SYS_ALT_MFP_PB8_Msk NULL
|
#define SYS_ALT_MFP_PB8_Msk NULL
|
||||||
#define SYS_ALT_MFP1_PB8_Msk NULL
|
#define SYS_ALT_MFP1_PB8_Msk NULL
|
||||||
|
|
||||||
|
@ -384,12 +384,12 @@
|
||||||
#define SYS_ALT_MFP1_PB9_GPIO NULL
|
#define SYS_ALT_MFP1_PB9_GPIO NULL
|
||||||
|
|
||||||
/* TM1 */
|
/* TM1 */
|
||||||
#define SYS_GPB_MFP_PB9_TM1 (0x01ul<<GPB_MFP9)
|
#define SYS_GPB_MFP_PB9_TM1 (0x01ul<<9)
|
||||||
#define SYS_ALT_MFP_PB9_TM1 0x0ul
|
#define SYS_ALT_MFP_PB9_TM1 0x0ul
|
||||||
#define SYS_ALT_MFP1_PB9_TM1 NULL
|
#define SYS_ALT_MFP1_PB9_TM1 NULL
|
||||||
|
|
||||||
/* SPI1 SS1 */
|
/* SPI1 SS1 */
|
||||||
#define SYS_GPB_MFP_PB9_SPI1_SS1 (0x01ul<<GPB_MFP9)
|
#define SYS_GPB_MFP_PB9_SPI1_SS1 (0x01ul<<9)
|
||||||
#define SYS_ALT_MFP_PB9_SPI1_SS1 (0x01ul<<SYS_ALT_MFP_PB9_MFP1_Pos)
|
#define SYS_ALT_MFP_PB9_SPI1_SS1 (0x01ul<<SYS_ALT_MFP_PB9_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB9_SPI1_SS1 NULL
|
#define SYS_ALT_MFP1_PB9_SPI1_SS1 NULL
|
||||||
|
|
||||||
|
@ -398,7 +398,7 @@
|
||||||
#define SYS_ALT_MFP_PB9_PWM1 (0x01ul<<SYS_ALT_MFP_PB9_MFP1_Pos)
|
#define SYS_ALT_MFP_PB9_PWM1 (0x01ul<<SYS_ALT_MFP_PB9_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB9_PWM1 NULL
|
#define SYS_ALT_MFP1_PB9_PWM1 NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB9_Msk (0x01ul<<GPB_MFP9)
|
#define SYS_GPB_MFP_PB9_Msk (0x01ul<<9)
|
||||||
#define SYS_ALT_MFP_PB9_Msk (0x01ul<<SYS_ALT_MFP_PB9_MFP1_Pos)
|
#define SYS_ALT_MFP_PB9_Msk (0x01ul<<SYS_ALT_MFP_PB9_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB9_Msk NULL
|
#define SYS_ALT_MFP1_PB9_Msk NULL
|
||||||
|
|
||||||
|
@ -409,16 +409,16 @@
|
||||||
#define SYS_ALT_MFP1_PB10_GPIO NULL
|
#define SYS_ALT_MFP1_PB10_GPIO NULL
|
||||||
|
|
||||||
/* TM2 */
|
/* TM2 */
|
||||||
#define SYS_GPB_MFP_PB10_TM2 (0x01ul<<GPB_MFP10)
|
#define SYS_GPB_MFP_PB10_TM2 (0x01ul<<10)
|
||||||
#define SYS_ALT_MFP_PB10_TM2 0x0ul
|
#define SYS_ALT_MFP_PB10_TM2 0x0ul
|
||||||
#define SYS_ALT_MFP1_PB10_TM2 NULL
|
#define SYS_ALT_MFP1_PB10_TM2 NULL
|
||||||
|
|
||||||
/* SPI0 SS1 */
|
/* SPI0 SS1 */
|
||||||
#define SYS_GPB_MFP_PB10_SPI0_SS1 (0x01ul<<GPB_MFP10)
|
#define SYS_GPB_MFP_PB10_SPI0_SS1 (0x01ul<<10)
|
||||||
#define SYS_ALT_MFP_PB10_SPI0_SS1 (0x01ul<<SYS_ALT_MFP_PB10_MFP1_Pos)
|
#define SYS_ALT_MFP_PB10_SPI0_SS1 (0x01ul<<SYS_ALT_MFP_PB10_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB10_SPI0_SS1 NULL
|
#define SYS_ALT_MFP1_PB10_SPI0_SS1 NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB10_Msk (0x01ul<<GPB_MFP10)
|
#define SYS_GPB_MFP_PB10_Msk (0x01ul<<10)
|
||||||
#define SYS_ALT_MFP_PB10_Msk (0x01ul<<SYS_ALT_MFP_PB10_MFP1_Pos)
|
#define SYS_ALT_MFP_PB10_Msk (0x01ul<<SYS_ALT_MFP_PB10_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB10_Msk NULL
|
#define SYS_ALT_MFP1_PB10_Msk NULL
|
||||||
|
|
||||||
|
@ -429,16 +429,16 @@
|
||||||
#define SYS_ALT_MFP1_PB12_GPIO NULL
|
#define SYS_ALT_MFP1_PB12_GPIO NULL
|
||||||
|
|
||||||
/* SPI1 SS0 */
|
/* SPI1 SS0 */
|
||||||
#define SYS_GPB_MFP_PB12_SPI1_SS0 (0x01ul<<GPB_MFP12)
|
#define SYS_GPB_MFP_PB12_SPI1_SS0 (0x01ul<<12)
|
||||||
#define SYS_ALT_MFP_PB12_SPI1_SS0 0x0ul
|
#define SYS_ALT_MFP_PB12_SPI1_SS0 0x0ul
|
||||||
#define SYS_ALT_MFP1_PB12_SPI1_SS0 NULL
|
#define SYS_ALT_MFP1_PB12_SPI1_SS0 NULL
|
||||||
|
|
||||||
/* CLK0 */
|
/* CLK0 */
|
||||||
#define SYS_GPB_MFP_PB12_CLKO (0x01ul<<GPB_MFP12)
|
#define SYS_GPB_MFP_PB12_CLKO (0x01ul<<12)
|
||||||
#define SYS_ALT_MFP_PB12_CLKO (0x01ul<<SYS_ALT_MFP_PB12_MFP1_Pos)
|
#define SYS_ALT_MFP_PB12_CLKO (0x01ul<<SYS_ALT_MFP_PB12_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB12_CLKO NULL
|
#define SYS_ALT_MFP1_PB12_CLKO NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB12_Msk (0x01ul<<GPB_MFP12)
|
#define SYS_GPB_MFP_PB12_Msk (0x01ul<<12)
|
||||||
#define SYS_ALT_MFP_PB12_Msk (0x01ul<<SYS_ALT_MFP_PB12_MFP1_Pos)
|
#define SYS_ALT_MFP_PB12_Msk (0x01ul<<SYS_ALT_MFP_PB12_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB12_Msk NULL
|
#define SYS_ALT_MFP1_PB12_Msk NULL
|
||||||
|
|
||||||
|
@ -448,7 +448,7 @@
|
||||||
#define SYS_ALT_MFP_PB13_GPIO NULL
|
#define SYS_ALT_MFP_PB13_GPIO NULL
|
||||||
#define SYS_ALT_MFP1_PB13_GPIO NULL
|
#define SYS_ALT_MFP1_PB13_GPIO NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB13_Msk (0x01ul<<GPB_MFP13)
|
#define SYS_GPB_MFP_PB13_Msk (0x01ul<<13)
|
||||||
#define SYS_ALT_MFP_PB13_Msk NULL
|
#define SYS_ALT_MFP_PB13_Msk NULL
|
||||||
#define SYS_ALT_MFP1_PB13_Msk NULL
|
#define SYS_ALT_MFP1_PB13_Msk NULL
|
||||||
|
|
||||||
|
@ -459,11 +459,11 @@
|
||||||
#define SYS_ALT_MFP1_PB14_GPIO NULL
|
#define SYS_ALT_MFP1_PB14_GPIO NULL
|
||||||
|
|
||||||
/* INT0 */
|
/* INT0 */
|
||||||
#define SYS_GPB_MFP_PB14_INT0 (0x01ul<<GPB_MFP14)
|
#define SYS_GPB_MFP_PB14_INT0 (0x01ul<<14)
|
||||||
#define SYS_ALT_MFP_PB14_INT0 NULL
|
#define SYS_ALT_MFP_PB14_INT0 NULL
|
||||||
#define SYS_ALT_MFP1_PB14_INT0 NULL
|
#define SYS_ALT_MFP1_PB14_INT0 NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB14_Msk (0x01ul<<GPB_MFP14)
|
#define SYS_GPB_MFP_PB14_Msk (0x01ul<<14)
|
||||||
#define SYS_ALT_MFP_PB14_Msk NULL
|
#define SYS_ALT_MFP_PB14_Msk NULL
|
||||||
#define SYS_ALT_MFP1_PB14_Msk NULL
|
#define SYS_ALT_MFP1_PB14_Msk NULL
|
||||||
|
|
||||||
|
@ -474,16 +474,16 @@
|
||||||
#define SYS_ALT_MFP1_PB15_GPIO NULL
|
#define SYS_ALT_MFP1_PB15_GPIO NULL
|
||||||
|
|
||||||
/* INT1 */
|
/* INT1 */
|
||||||
#define SYS_GPB_MFP_PB15_INT1 (0x01ul<<GPB_MFP15)
|
#define SYS_GPB_MFP_PB15_INT1 (0x01ul<<15)
|
||||||
#define SYS_ALT_MFP_PB15_INT1 0x0ul
|
#define SYS_ALT_MFP_PB15_INT1 0x0ul
|
||||||
#define SYS_ALT_MFP1_PB15_INT1 NULL
|
#define SYS_ALT_MFP1_PB15_INT1 NULL
|
||||||
|
|
||||||
/* TM0_EXT */
|
/* TM0_EXT */
|
||||||
#define SYS_GPB_MFP_PB15_TM0_EXT (0x01ul<<GPB_MFP15)
|
#define SYS_GPB_MFP_PB15_TM0_EXT (0x01ul<<15)
|
||||||
#define SYS_ALT_MFP_PB15_TM0_EXT (0x01ul<<SYS_ALT_MFP_PB15_MFP1_Pos)
|
#define SYS_ALT_MFP_PB15_TM0_EXT (0x01ul<<SYS_ALT_MFP_PB15_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB15_TM0_EXT NULL
|
#define SYS_ALT_MFP1_PB15_TM0_EXT NULL
|
||||||
|
|
||||||
#define SYS_GPB_MFP_PB15_Msk (0x01ul<<GPB_MFP15)
|
#define SYS_GPB_MFP_PB15_Msk (0x01ul<<15)
|
||||||
#define SYS_ALT_MFP_PB15_Msk (0x01ul<<SYS_ALT_MFP_PB15_MFP1_Pos)
|
#define SYS_ALT_MFP_PB15_Msk (0x01ul<<SYS_ALT_MFP_PB15_MFP1_Pos)
|
||||||
#define SYS_ALT_MFP1_PB15_Msk NULL
|
#define SYS_ALT_MFP1_PB15_Msk NULL
|
||||||
|
|
||||||
|
@ -937,11 +937,11 @@
|
||||||
#define SYS_ALT_MFP1_PF0_GPIO NULL
|
#define SYS_ALT_MFP1_PF0_GPIO NULL
|
||||||
|
|
||||||
/* XT1 OUT */
|
/* XT1 OUT */
|
||||||
#define SYS_GPF_MFP_PF0_XT1_OUT (0x01ul<<GPF_MFP0)
|
#define SYS_GPF_MFP_PF0_XT1_OUT SYS_GPF_MFP_GPF_MFP0_Msk
|
||||||
#define SYS_ALT_MFP_PF0_XT1_OUT NULL
|
#define SYS_ALT_MFP_PF0_XT1_OUT NULL
|
||||||
#define SYS_ALT_MFP1_PF0_XT1_OUT NULL
|
#define SYS_ALT_MFP1_PF0_XT1_OUT NULL
|
||||||
|
|
||||||
#define SYS_GPF_MFP_PF0_Msk (0x01ul<<GPF_MFP0)
|
#define SYS_GPF_MFP_PF0_Msk SYS_GPF_MFP_GPF_MFP0_Msk
|
||||||
#define SYS_ALT_MFP_PF0_Msk NULL
|
#define SYS_ALT_MFP_PF0_Msk NULL
|
||||||
#define SYS_ALT_MFP1_PF0_Msk NULL
|
#define SYS_ALT_MFP1_PF0_Msk NULL
|
||||||
|
|
||||||
|
@ -952,11 +952,11 @@
|
||||||
#define SYS_ALT_MFP1_PF1_GPIO NULL
|
#define SYS_ALT_MFP1_PF1_GPIO NULL
|
||||||
|
|
||||||
/* XT1 IN */
|
/* XT1 IN */
|
||||||
#define SYS_GPF_MFP_PF1_XT1_IN (0x01ul<<GPF_MFP1)
|
#define SYS_GPF_MFP_PF1_XT1_IN SYS_GPF_MFP_GPF_MFP1_Msk
|
||||||
#define SYS_ALT_MFP_PF1_XT1_IN NULL
|
#define SYS_ALT_MFP_PF1_XT1_IN NULL
|
||||||
#define SYS_ALT_MFP1_PF1_XT1_IN NULL
|
#define SYS_ALT_MFP1_PF1_XT1_IN NULL
|
||||||
|
|
||||||
#define SYS_GPF_MFP_PF1_Msk (0x01ul<<GPF_MFP1)
|
#define SYS_GPF_MFP_PF1_Msk SYS_GPF_MFP_GPF_MFP1_Msk
|
||||||
#define SYS_ALT_MFP_PF1_Msk NULL
|
#define SYS_ALT_MFP_PF1_Msk NULL
|
||||||
#define SYS_ALT_MFP1_PF1_Msk NULL
|
#define SYS_ALT_MFP1_PF1_Msk NULL
|
||||||
|
|
||||||
|
@ -967,21 +967,21 @@
|
||||||
#define SYS_ALT_MFP1_PF2_GPIO 0x0ul
|
#define SYS_ALT_MFP1_PF2_GPIO 0x0ul
|
||||||
|
|
||||||
/* PS2 DAT */
|
/* PS2 DAT */
|
||||||
#define SYS_GPF_MFP_PF2_PS2_DAT (0x01ul<<GPF_MFP2)
|
#define SYS_GPF_MFP_PF2_PS2_DAT SYS_GPF_MFP_GPF_MFP2_Msk
|
||||||
#define SYS_ALT_MFP_PF2_PS2_DAT NULL
|
#define SYS_ALT_MFP_PF2_PS2_DAT NULL
|
||||||
#define SYS_ALT_MFP1_PF2_PS2_DAT 0x0ul
|
#define SYS_ALT_MFP1_PF2_PS2_DAT 0x0ul
|
||||||
|
|
||||||
/* I2C0 SDA */
|
/* I2C0 SDA */
|
||||||
#define SYS_GPF_MFP_PF2_I2C0_SDA (0x01ul<<GPF_MFP2)
|
#define SYS_GPF_MFP_PF2_I2C0_SDA SYS_GPF_MFP_GPF_MFP2_Msk
|
||||||
#define SYS_ALT_MFP_PF2_I2C0_SDA NULL
|
#define SYS_ALT_MFP_PF2_I2C0_SDA NULL
|
||||||
#define SYS_ALT_MFP1_PF2_I2C0_SDA (0x02ul<<SYS_ALT_MFP1_PF2_MFP1_Pos)
|
#define SYS_ALT_MFP1_PF2_I2C0_SDA (0x02ul<<SYS_ALT_MFP1_PF2_MFP1_Pos)
|
||||||
|
|
||||||
/* ADC6 */
|
/* ADC6 */
|
||||||
#define SYS_GPF_MFP_PF2_ADC6 (0x01ul<<GPF_MFP2)
|
#define SYS_GPF_MFP_PF2_ADC6 SYS_GPF_MFP_GPF_MFP2_Msk
|
||||||
#define SYS_ALT_MFP_PF2_ADC6 NULL
|
#define SYS_ALT_MFP_PF2_ADC6 NULL
|
||||||
#define SYS_ALT_MFP1_PF2_ADC6 (0x03ul<<SYS_ALT_MFP1_PF2_MFP1_Pos)
|
#define SYS_ALT_MFP1_PF2_ADC6 (0x03ul<<SYS_ALT_MFP1_PF2_MFP1_Pos)
|
||||||
|
|
||||||
#define SYS_GPF_MFP_PF2_Msk (0x01ul<<GPF_MFP2)
|
#define SYS_GPF_MFP_PF2_Msk SYS_GPF_MFP_GPF_MFP2_Msk
|
||||||
#define SYS_ALT_MFP_PF2_Msk NULL
|
#define SYS_ALT_MFP_PF2_Msk NULL
|
||||||
#define SYS_ALT_MFP1_PF2_Msk (0x03ul<<SYS_ALT_MFP1_PF2_MFP1_Pos)
|
#define SYS_ALT_MFP1_PF2_Msk (0x03ul<<SYS_ALT_MFP1_PF2_MFP1_Pos)
|
||||||
|
|
||||||
|
@ -992,21 +992,21 @@
|
||||||
#define SYS_ALT_MFP1_PF3_GPIO 0x0ul
|
#define SYS_ALT_MFP1_PF3_GPIO 0x0ul
|
||||||
|
|
||||||
/* PS2 CLK */
|
/* PS2 CLK */
|
||||||
#define SYS_GPF_MFP_PF3_PS2_CLK (0x01ul<<GPF_MFP3)
|
#define SYS_GPF_MFP_PF3_PS2_CLK SYS_GPF_MFP_GPF_MFP3_Msk
|
||||||
#define SYS_ALT_MFP_PF3_PS2_CLK NULL
|
#define SYS_ALT_MFP_PF3_PS2_CLK NULL
|
||||||
#define SYS_ALT_MFP1_PF3_PS2_CLK 0x0ul
|
#define SYS_ALT_MFP1_PF3_PS2_CLK 0x0ul
|
||||||
|
|
||||||
/* I2C0 SCL */
|
/* I2C0 SCL */
|
||||||
#define SYS_GPF_MFP_PF3_I2C0_SCL (0x01ul<<GPF_MFP3)
|
#define SYS_GPF_MFP_PF3_I2C0_SCL SYS_GPF_MFP_GPF_MFP3_Msk
|
||||||
#define SYS_ALT_MFP_PF3_I2C0_SCL NULL
|
#define SYS_ALT_MFP_PF3_I2C0_SCL NULL
|
||||||
#define SYS_ALT_MFP1_PF3_I2C0_SCL (0x2UL<<SYS_ALT_MFP1_PF3_MFP1_Pos)
|
#define SYS_ALT_MFP1_PF3_I2C0_SCL (0x2UL<<SYS_ALT_MFP1_PF3_MFP1_Pos)
|
||||||
|
|
||||||
/* ADC7 */
|
/* ADC7 */
|
||||||
#define SYS_GPF_MFP_PF3_ADC7 (0x01ul<<GPF_MFP3)
|
#define SYS_GPF_MFP_PF3_ADC7 (SYS_GPF_MFP_GPF_MFP3_Msk
|
||||||
#define SYS_ALT_MFP_PF3_ADC7 NULL
|
#define SYS_ALT_MFP_PF3_ADC7 NULL
|
||||||
#define SYS_ALT_MFP1_PF3_ADC7 (0x03ul<<SYS_ALT_MFP1_PF3_MFP1_Pos)
|
#define SYS_ALT_MFP1_PF3_ADC7 (0x03ul<<SYS_ALT_MFP1_PF3_MFP1_Pos)
|
||||||
|
|
||||||
#define SYS_GPF_MFP_PF3_Msk (0x01ul<<GPF_MFP3)
|
#define SYS_GPF_MFP_PF3_Msk SYS_GPF_MFP_GPF_MFP3_Msk
|
||||||
#define SYS_ALT_MFP_PF3_Msk NULL
|
#define SYS_ALT_MFP_PF3_Msk NULL
|
||||||
#define SYS_ALT_MFP1_PF3_Msk (0x03ul<<SYS_ALT_MFP1_PF3_MFP1_Pos)
|
#define SYS_ALT_MFP1_PF3_Msk (0x03ul<<SYS_ALT_MFP1_PF3_MFP1_Pos)
|
||||||
|
|
||||||
|
|
|
@ -24,7 +24,7 @@
|
||||||
|
|
||||||
#include "hal.h"
|
#include "hal.h"
|
||||||
|
|
||||||
// #if HAL_USE_PWM || defined(__DOXYGEN__)
|
#if (HAL_USE_PWM == TRUE) || defined(__DOXYGEN__)
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver local definitions. */
|
/* Driver local definitions. */
|
||||||
|
@ -226,6 +226,6 @@ uint32_t pwm_lld_config_output_channel(PWM_T *pwm, uint32_t channel, uint32_t fr
|
||||||
return(pwmClk);
|
return(pwmClk);
|
||||||
}
|
}
|
||||||
|
|
||||||
// #endif /* HAL_USE_PWM */
|
#endif /* HAL_USE_PWM */
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
|
@ -1,5 +1,6 @@
|
||||||
/*
|
/*
|
||||||
Copyright (C) 2019 /u/KeepItUnder
|
Copyright (C) 2019 /u/KeepItUnder
|
||||||
|
Copyright (C) 2020 Alex Lewontin
|
||||||
|
|
||||||
Licensed under the Apache License, Version 2.0 (the "License");
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
you may not use this file except in compliance with the License.
|
you may not use this file except in compliance with the License.
|
||||||
|
@ -30,7 +31,7 @@
|
||||||
/* Driver local definitions. */
|
/* Driver local definitions. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
|
#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING)
|
||||||
|
|
||||||
#if (OSAL_ST_RESOLUTION == 32)
|
#if (OSAL_ST_RESOLUTION == 32)
|
||||||
#define ST_ARR_INIT 0xFFFFFFFF
|
#define ST_ARR_INIT 0xFFFFFFFF
|
||||||
|
@ -156,91 +157,6 @@ OSAL_IRQ_HANDLER(ST_HANDLER) {
|
||||||
}
|
}
|
||||||
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
|
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
|
||||||
|
|
||||||
/* DEBUG - Catch unused Interrupt Vectors and output to test pins
|
|
||||||
|
|
||||||
OSAL_IRQ_HANDLER(Vector7C){
|
|
||||||
OSAL_IRQ_PROLOGUE();
|
|
||||||
|
|
||||||
GPIO_TOGGLE(PB8);
|
|
||||||
GPIO_TOGGLE(PB11);
|
|
||||||
|
|
||||||
OSAL_IRQ_EPILOGUE();
|
|
||||||
}
|
|
||||||
|
|
||||||
OSAL_IRQ_HANDLER(NUC123_TIM3_HANDLER){
|
|
||||||
|
|
||||||
OSAL_IRQ_PROLOGUE();
|
|
||||||
|
|
||||||
GPIO_TOGGLE(PB4);
|
|
||||||
GPIO_TOGGLE(PB5);
|
|
||||||
GPIO_TOGGLE(PB6);
|
|
||||||
GPIO_TOGGLE(PB7);
|
|
||||||
GPIO_TOGGLE(PB8);
|
|
||||||
|
|
||||||
OSAL_IRQ_EPILOGUE();
|
|
||||||
}
|
|
||||||
|
|
||||||
OSAL_IRQ_HANDLER(NUC123_TIM4_HANDLER){
|
|
||||||
|
|
||||||
OSAL_IRQ_PROLOGUE();
|
|
||||||
|
|
||||||
GPIO_TOGGLE(PB4);
|
|
||||||
GPIO_TOGGLE(PB5);
|
|
||||||
GPIO_TOGGLE(PB6);
|
|
||||||
GPIO_TOGGLE(PB7);
|
|
||||||
GPIO_TOGGLE(PB8);
|
|
||||||
|
|
||||||
OSAL_IRQ_EPILOGUE();
|
|
||||||
}
|
|
||||||
|
|
||||||
OSAL_IRQ_HANDLER(NUC123_ADC_HANDLER){
|
|
||||||
|
|
||||||
OSAL_IRQ_PROLOGUE();
|
|
||||||
|
|
||||||
GPIO_TOGGLE(PB4);
|
|
||||||
GPIO_TOGGLE(PB5);
|
|
||||||
GPIO_TOGGLE(PB6);
|
|
||||||
GPIO_TOGGLE(PB7);
|
|
||||||
GPIO_TOGGLE(PB8);
|
|
||||||
|
|
||||||
OSAL_IRQ_EPILOGUE();
|
|
||||||
}
|
|
||||||
|
|
||||||
OSAL_IRQ_HANDLER(NUC123_USB1_HANDLER){
|
|
||||||
|
|
||||||
OSAL_IRQ_PROLOGUE();
|
|
||||||
|
|
||||||
GPIO_TOGGLE(PB4);
|
|
||||||
GPIO_TOGGLE(PB5);
|
|
||||||
GPIO_TOGGLE(PB6);
|
|
||||||
GPIO_TOGGLE(PB7);
|
|
||||||
GPIO_TOGGLE(PB8);
|
|
||||||
|
|
||||||
OSAL_IRQ_EPILOGUE();
|
|
||||||
}
|
|
||||||
|
|
||||||
OSAL_IRQ_HANDLER(NUC123_PDMA_HANDLER){
|
|
||||||
|
|
||||||
OSAL_IRQ_PROLOGUE();
|
|
||||||
|
|
||||||
GPIO_TOGGLE(PB4);
|
|
||||||
GPIO_TOGGLE(PB5);
|
|
||||||
GPIO_TOGGLE(PB6);
|
|
||||||
GPIO_TOGGLE(PB7);
|
|
||||||
GPIO_TOGGLE(PB8);
|
|
||||||
|
|
||||||
OSAL_IRQ_EPILOGUE();
|
|
||||||
}
|
|
||||||
|
|
||||||
//OSAL_IRQ_HANDLER(HardFault_Handler){
|
|
||||||
// OSAL_IRQ_PROLOGUE();
|
|
||||||
|
|
||||||
// NVIC_SystemReset();
|
|
||||||
|
|
||||||
// OSAL_IRQ_EPILOGUE();
|
|
||||||
//}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver exported functions. */
|
/* Driver exported functions. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
@ -284,9 +200,12 @@ void st_lld_init(void) {
|
||||||
#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
|
#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
|
||||||
/* Periodic systick mode, the Cortex-Mx internal systick timer is used
|
/* Periodic systick mode, the Cortex-Mx internal systick timer is used
|
||||||
in this mode.*/
|
in this mode.*/
|
||||||
|
SystemUnlockReg();
|
||||||
|
CLK->CLKSEL0 &= ~CLK_CLKSEL0_STCLK_S_Msk;
|
||||||
|
CLK->CLKSEL0 |= CLK_CLKSEL0_STCLK_S_HCLK_DIV2;
|
||||||
|
LOCKREG();
|
||||||
|
|
||||||
// CLK_EnableSysTick(CLK_CLKSEL0_STCLK_S_HCLK, (NUC123_HCLK / OSAL_ST_FREQUENCY) - 1);
|
SysTick->LOAD = ((NUC123_HCLK / 2) / OSAL_ST_FREQUENCY) - 1;
|
||||||
SysTick->LOAD = (NUC123_HCLK / OSAL_ST_FREQUENCY) - 1;
|
|
||||||
SysTick->VAL = 0;
|
SysTick->VAL = 0;
|
||||||
SysTick->CTRL = (~SysTick_CTRL_CLKSOURCE_Msk) &
|
SysTick->CTRL = (~SysTick_CTRL_CLKSOURCE_Msk) &
|
||||||
(SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk);
|
(SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk);
|
||||||
|
|
|
@ -42,7 +42,6 @@
|
||||||
#define CLK_CLKSEL0_STCLK_S_HXT_DIV2 (0x2ul<<CLK_CLKSEL0_STCLK_S_Pos) /*!< Set HXT/2 as STCLK clock source */
|
#define CLK_CLKSEL0_STCLK_S_HXT_DIV2 (0x2ul<<CLK_CLKSEL0_STCLK_S_Pos) /*!< Set HXT/2 as STCLK clock source */
|
||||||
#define CLK_CLKSEL0_STCLK_S_HCLK_DIV2 (0x3ul<<CLK_CLKSEL0_STCLK_S_Pos) /*!< Set HCLK/2 as STCLK clock source */
|
#define CLK_CLKSEL0_STCLK_S_HCLK_DIV2 (0x3ul<<CLK_CLKSEL0_STCLK_S_Pos) /*!< Set HCLK/2 as STCLK clock source */
|
||||||
#define CLK_CLKSEL0_STCLK_S_HIRC_DIV2 (0x7ul<<CLK_CLKSEL0_STCLK_S_Pos) /*!< Set HIRC/2 as STCLK clock source */
|
#define CLK_CLKSEL0_STCLK_S_HIRC_DIV2 (0x7ul<<CLK_CLKSEL0_STCLK_S_Pos) /*!< Set HIRC/2 as STCLK clock source */
|
||||||
#define CLK_CLKSEL0_STCLK_S_HCLK (0x1ul<<SysTick_CTRL_CLKSOURCE_Pos) /*!< Set HCLK as STCLK clock source */
|
|
||||||
|
|
||||||
#define TIMER_MODE_PERIODIC (0x01ul << TIMER_TCSR_MODE_Pos)
|
#define TIMER_MODE_PERIODIC (0x01ul << TIMER_TCSR_MODE_Pos)
|
||||||
#define TIMER_MODE_CONTINUOUS (0x03ul << TIMER_TCSR_MODE_Pos)
|
#define TIMER_MODE_CONTINUOUS (0x03ul << TIMER_TCSR_MODE_Pos)
|
||||||
|
@ -78,19 +77,19 @@
|
||||||
/* Derived constants and error checks. */
|
/* Derived constants and error checks. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
#if NUC123_ST_USE_TIMER == 2
|
#if (NUC123_ST_USE_TIMER == 2)
|
||||||
#if !NUC123_HAS_TIM2
|
#if !NUC123_HAS_TIM2
|
||||||
#error "TIM2 not present"
|
#error "TIM2 not present"
|
||||||
#endif
|
#endif
|
||||||
#define NUC123_ST_TIM TIMER1
|
#define NUC123_ST_TIM TIMER1
|
||||||
|
|
||||||
#elif NUC123_ST_USE_TIMER == 3
|
#elif (NUC123_ST_USE_TIMER == 3)
|
||||||
#if !NUC123_HAS_TIM3
|
#if !NUC123_HAS_TIM3
|
||||||
#error "TIM3 not present"
|
#error "TIM3 not present"
|
||||||
#endif
|
#endif
|
||||||
#define NUC123_ST_TIM TIMER2
|
#define NUC123_ST_TIM TIMER2
|
||||||
|
|
||||||
#elif NUC123_ST_USE_TIMER == 4
|
#elif (NUC123_ST_USE_TIMER == 4)
|
||||||
#if !NUC123_HAS_TIM4
|
#if !NUC123_HAS_TIM4
|
||||||
#error "TIM4 not present"
|
#error "TIM4 not present"
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -1,22 +1,23 @@
|
||||||
/*
|
/*
|
||||||
Copyright (C) 2019 /u/KeepItUnder
|
Copyright (C) 2020 Alex Lewontin
|
||||||
|
Copyright (C) 2019 /u/KeepItUnder
|
||||||
|
|
||||||
Licensed under the Apache License, Version 2.0 (the "License");
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
you may not use this file except in compliance with the License.
|
you may not use this file except in compliance with the License.
|
||||||
You may obtain a copy of the License at
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
http://www.apache.org/licenses/LICENSE-2.0
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
Unless required by applicable law or agreed to in writing, software
|
Unless required by applicable law or agreed to in writing, software
|
||||||
distributed under the License is distributed on an "AS IS" BASIS,
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
See the License for the specific language governing permissions and
|
See the License for the specific language governing permissions and
|
||||||
limitations under the License.
|
limitations under the License.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @file NUC123SD4AN0/hal_lld.c
|
* @file hal_lld.c
|
||||||
* @brief NUC123SD4AN0 HAL subsystem low level driver source.
|
* @brief NUC123xxxANx HAL subsystem low level driver source.
|
||||||
*
|
*
|
||||||
* @addtogroup HAL
|
* @addtogroup HAL
|
||||||
* @{
|
* @{
|
||||||
|
@ -27,151 +28,413 @@
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver local definitions. */
|
/* Driver local definitions. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
#define FREQ_25MHZ 25000000
|
||||||
|
#define FREQ_50MHZ 50000000
|
||||||
|
#define FREQ_72MHZ 72000000
|
||||||
|
#define FREQ_100MHZ 100000000
|
||||||
|
#define FREQ_200MHZ 200000000
|
||||||
|
|
||||||
#define NUC123_PLLXTPRE_OFFSET 17 /**< PLLXTPRE offset */
|
#define CLK_CLKDIV_HCLK(x) (((x)-1) << CLK_CLKDIV_HCLK_N_Pos)
|
||||||
#define NUC123_PLLXTPRE_MASK 0x01 /**< PLLXTPRE mask */
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver exported variables. */
|
/* Driver exported variables. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief CMSIS system core clock variable.
|
|
||||||
* @note It is declared in system_NUC123SD4AN0.h.
|
|
||||||
*/
|
|
||||||
//uint32_t SystemCoreClock = NUC123_HCLK;
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver local variables and types. */
|
/* Driver local variables and types. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
_Bool clock_initialized = FALSE;
|
||||||
|
|
||||||
|
uint32_t SystemCoreClock = __HSI; /* System Clock Frequency (Core Clock)*/
|
||||||
|
uint32_t CyclesPerUs = (__HSI / 1000000); /* Cycles per micro second */
|
||||||
|
uint32_t PllClock = __HSI; /*!< PLL Clock Frequency */
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver local functions. */
|
/* Driver local functions. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
|
||||||
|
{
|
||||||
|
/* ToDo: add code to calculate the system frequency based upon the current
|
||||||
|
register settings.
|
||||||
|
This function can be used to retrieve the system core clock frequeny
|
||||||
|
after user changed register sittings. */
|
||||||
|
// SystemCoreClock = SYSTEM_CLOCK;
|
||||||
|
|
||||||
|
uint32_t clkFreq;
|
||||||
|
uint32_t PllReg;
|
||||||
|
|
||||||
|
uint32_t pllFIN, pllNF, pllNR, pllNO;
|
||||||
|
|
||||||
|
/* Update PLL Clock */
|
||||||
|
// PllClock = clks_lld_get_pll_clock_freq();
|
||||||
|
PllReg = CLK->PLLCON;
|
||||||
|
|
||||||
|
if (PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) {
|
||||||
|
PllClock = 0; /* PLL is off. */
|
||||||
|
} else {
|
||||||
|
|
||||||
|
if (PllReg & 0x00080000ul) {
|
||||||
|
pllFIN = __HIRC; /* Use HXT for PLL clock */
|
||||||
|
} else {
|
||||||
|
pllFIN = __HXT; /* Use HXT for PLL clock */
|
||||||
|
}
|
||||||
|
|
||||||
|
if (PllReg & CLK_PLLCON_BP_Msk) {
|
||||||
|
PllClock = pllFIN;
|
||||||
|
} else {
|
||||||
|
switch (((PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)) {
|
||||||
|
case 0: /* OUT_DIV == 00 : NO = 1 */
|
||||||
|
pllNO = 1;
|
||||||
|
break;
|
||||||
|
case 3: /* OUT_DIV == 11 : NO = 4 */
|
||||||
|
pllNO = 4;
|
||||||
|
break;
|
||||||
|
default: /* OUT_DIV == 01 or 10 : NO = 2 */
|
||||||
|
pllNO = 2;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
pllNF = ((PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2;
|
||||||
|
pllNR = ((PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2;
|
||||||
|
|
||||||
|
/* Shift right to avoid overflow condition */
|
||||||
|
PllClock = (((pllFIN >> 2) * pllNF) / (pllNR * pllNO) << 2);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Pick Clock Source */
|
||||||
|
switch (CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk) {
|
||||||
|
case 0: // External HF Xtal
|
||||||
|
clkFreq = __HXT;
|
||||||
|
break;
|
||||||
|
case 1: // PLL clock / 2
|
||||||
|
clkFreq = PllClock >> 1;
|
||||||
|
break;
|
||||||
|
case 3: // Internal 10kHz
|
||||||
|
clkFreq = __LIRC;
|
||||||
|
break;
|
||||||
|
case 2: // PLL clock
|
||||||
|
clkFreq = PllClock;
|
||||||
|
break;
|
||||||
|
case 7: // Internal 22.184MHz
|
||||||
|
clkFreq = __HIRC;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
clkFreq = 0;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
SystemCoreClock = clkFreq / ((CLK->CLKDIV & CLK_CLKDIV_HCLK_N_Msk) + 1);
|
||||||
|
CyclesPerUs = SystemCoreClock / 1000000;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get PLL clock frequency
|
||||||
|
* @param None
|
||||||
|
* @return PLL frequency
|
||||||
|
* @details This function get PLL frequency. The frequency unit is Hz.
|
||||||
|
*/
|
||||||
|
static inline uint32_t get_pll_clock_freq(void)
|
||||||
|
{
|
||||||
|
uint32_t PllReg;
|
||||||
|
uint32_t pllFIN, pllNF, pllNR, pllNO;
|
||||||
|
|
||||||
|
PllReg = CLK->PLLCON;
|
||||||
|
|
||||||
|
if (PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) {
|
||||||
|
PllClock = 0; /* PLL is in power down mode or fix low */
|
||||||
|
} else {
|
||||||
|
|
||||||
|
if (PllReg & NUC123_PLLSRC_HSI) {
|
||||||
|
pllFIN = __HIRC; /* Use HXT for PLL clock */
|
||||||
|
} else {
|
||||||
|
pllFIN = __HXT; /* Use HXT for PLL clock */
|
||||||
|
}
|
||||||
|
|
||||||
|
if (PllReg & CLK_PLLCON_BP_Msk) {
|
||||||
|
PllClock = pllFIN;
|
||||||
|
} else {
|
||||||
|
switch (((PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)) {
|
||||||
|
case 0: // OUT_DIV == 00 : NO = 1
|
||||||
|
pllNO = 1;
|
||||||
|
break;
|
||||||
|
case 3: // OUT_DIV == 11 : NO = 4
|
||||||
|
pllNO = 4;
|
||||||
|
break;
|
||||||
|
default: // OUT_DIV == 01 or 10 : NO = 2
|
||||||
|
pllNO = 2;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
pllNF = ((PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2;
|
||||||
|
pllNR = ((PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2;
|
||||||
|
|
||||||
|
/* shift to avoid overflow condition */
|
||||||
|
PllClock = (((pllFIN >> 2) * pllNF) / (pllNR * pllNO) << 2);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return PllClock;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Wait for stable clock
|
||||||
|
*
|
||||||
|
* @description Always wait around 300ms for clock to be stable
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static uint32_t wait_for_clock_ready(uint32_t clkMask)
|
||||||
|
{
|
||||||
|
int32_t timeout = 2180000;
|
||||||
|
|
||||||
|
while (timeout-- > 0) {
|
||||||
|
if ((CLK->CLKSTATUS & clkMask) == clkMask) {
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** @brief Set system HCLK
|
||||||
|
*
|
||||||
|
* @description Setup HCLK source and divider
|
||||||
|
*
|
||||||
|
* Always switch to a known stable clock source before changing a
|
||||||
|
* system clock, to avoid issues related to the original clock's
|
||||||
|
* speed/settings.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static void set_HCLK(uint32_t clkSource, uint32_t clkDivider)
|
||||||
|
{
|
||||||
|
uint32_t stableHIRC;
|
||||||
|
|
||||||
|
/* Read HIRC clock source stable flag */
|
||||||
|
stableHIRC = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk;
|
||||||
|
|
||||||
|
/* Setup __HIRC */
|
||||||
|
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
|
||||||
|
|
||||||
|
wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk);
|
||||||
|
|
||||||
|
/* Use __HIRC as HCLK, temporarily */
|
||||||
|
CLK->CLKSEL0 =
|
||||||
|
(CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | NUC123_HCLKSRC_HSI;
|
||||||
|
|
||||||
|
/* Set new clock divider */
|
||||||
|
CLK->CLKDIV = (CLK->CLKDIV & (~CLK_CLKDIV_HCLK_N_Msk)) | clkDivider;
|
||||||
|
|
||||||
|
/* Switch HCLK to new HCLK source */
|
||||||
|
CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | clkSource;
|
||||||
|
|
||||||
|
/* Update System Core Clock */
|
||||||
|
SystemCoreClockUpdate();
|
||||||
|
|
||||||
|
/* Disable HIRC if HIRC was disabled before we started */
|
||||||
|
if (stableHIRC == 0) {
|
||||||
|
CLK->PWRCON &= ~CLK_PWRCON_OSC22M_EN_Msk;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint32_t enable_pll(uint32_t pllSrc, uint32_t pllFreq)
|
||||||
|
{
|
||||||
|
/* Disable PLL first to avoid unstable when setting PLL. */
|
||||||
|
CLK->PLLCON = CLK_PLLCON_PD_Msk;
|
||||||
|
|
||||||
|
/* Check and setup correct clock source */
|
||||||
|
switch (pllSrc) {
|
||||||
|
case NUC123_PLLSRC_HSE:
|
||||||
|
/* Use HXT clock */
|
||||||
|
CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk;
|
||||||
|
|
||||||
|
/* Wait for stable HXT */
|
||||||
|
wait_for_clock_ready(CLK_CLKSTATUS_XTL12M_STB_Msk);
|
||||||
|
|
||||||
|
break;
|
||||||
|
case NUC123_PLLSRC_HSI:
|
||||||
|
/* Use HIRC clock */
|
||||||
|
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
|
||||||
|
|
||||||
|
/* Wait for stable HIRC */
|
||||||
|
wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk);
|
||||||
|
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Calculate best PLL variables from requested frequency
|
||||||
|
*
|
||||||
|
* See NUC123 Technical Reference Manual 5.4.8 PLL Control Register Description, page 124
|
||||||
|
*
|
||||||
|
* NF 1
|
||||||
|
* FOUT = FIN x -- x --
|
||||||
|
* NR NO
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
uint32_t NO = 0;
|
||||||
|
uint32_t NR = 0;
|
||||||
|
uint32_t clkCalc = 0;
|
||||||
|
|
||||||
|
/* Set "NO" for requested frequency */
|
||||||
|
/* We're using "NO" first to set the PLLCON - so make it "NO" - 1; */
|
||||||
|
if (pllFreq >= FREQ_25MHZ && pllFreq <= FREQ_50MHZ) {
|
||||||
|
/* Low frequency - use full variable headroom */
|
||||||
|
pllFreq <<= 2;
|
||||||
|
NO = 3;
|
||||||
|
} else if (pllFreq > FREQ_50MHZ && pllFreq <= FREQ_100MHZ) {
|
||||||
|
/* Medium frequency - use full variable headroom */
|
||||||
|
pllFreq <<= 1;
|
||||||
|
NO = 1;
|
||||||
|
} else if (pllFreq > FREQ_100MHZ && pllFreq <= FREQ_200MHZ) {
|
||||||
|
/* High frequency - full variable headroom already used */
|
||||||
|
NO = 0;
|
||||||
|
} else {
|
||||||
|
/* Frequency out of range - use default PLL settings
|
||||||
|
*
|
||||||
|
* See NUC123 Technical Reference Manual PLL COntrol Register Description, page 124
|
||||||
|
* The default value: 0xC22E
|
||||||
|
* FIN = 12 MHz
|
||||||
|
* NR = (1+2) = 3
|
||||||
|
* NF = (46+2) = 48
|
||||||
|
* NO = 4
|
||||||
|
* FOUT = 12/4 x 48 x 1/3 = 48 MHz
|
||||||
|
*/
|
||||||
|
if (pllSrc == NUC123_PLLSRC_HSE) {
|
||||||
|
CLK->PLLCON = 0xC22E;
|
||||||
|
} else {
|
||||||
|
CLK->PLLCON = 0xD66F;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Wait for stable PLL clock */
|
||||||
|
wait_for_clock_ready(CLK_CLKSTATUS_PLL_STB_Msk);
|
||||||
|
|
||||||
|
return get_pll_clock_freq();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Setup "NR" and clkCalc */
|
||||||
|
switch (pllSrc) {
|
||||||
|
case NUC123_PLLSRC_HSE:
|
||||||
|
NR = 2;
|
||||||
|
clkCalc = __HXT;
|
||||||
|
break;
|
||||||
|
case NUC123_PLLSRC_HSI:
|
||||||
|
NR = 4;
|
||||||
|
clkCalc = __HIRC;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Loop to calculate best/lowest NR (between 0 or 2 and 31) and best/lowest NF (between 0 and 511)
|
||||||
|
*
|
||||||
|
* Best results are off-by-2 until final equation calculation (to allow use in PLLCON)
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
uint32_t bestNR = 0;
|
||||||
|
uint32_t bestNF = 0;
|
||||||
|
uint32_t minLimit = -1;
|
||||||
|
|
||||||
|
while (NR <= 33) {
|
||||||
|
uint32_t tmpCalc1 = clkCalc / NR;
|
||||||
|
|
||||||
|
if (tmpCalc1 > 1600000 && tmpCalc1 < 16000000) {
|
||||||
|
uint32_t NF = 2;
|
||||||
|
|
||||||
|
while (NF <= 513) {
|
||||||
|
uint32_t tmpCalc2 = tmpCalc1 * NF;
|
||||||
|
|
||||||
|
if (tmpCalc2 >= 100000000 && tmpCalc2 <= 200000000) {
|
||||||
|
uint32_t tmpCalc3;
|
||||||
|
|
||||||
|
if (tmpCalc2 > pllFreq) {
|
||||||
|
tmpCalc3 = tmpCalc2 - pllFreq;
|
||||||
|
} else {
|
||||||
|
tmpCalc3 = pllFreq - tmpCalc2;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (tmpCalc3 < minLimit) {
|
||||||
|
minLimit = tmpCalc3;
|
||||||
|
bestNF = NF;
|
||||||
|
bestNR = NR;
|
||||||
|
|
||||||
|
/* Stop NF calc loop when minLimit tends back to 0 */
|
||||||
|
if (minLimit == 0)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
NF++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
NR++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable and apply new PLL setting. */
|
||||||
|
CLK->PLLCON = pllSrc | (NO << 14) | ((bestNR - 2) << 9) | (bestNF - 2);
|
||||||
|
|
||||||
|
/* Wait for stable PLL clock */
|
||||||
|
wait_for_clock_ready(CLK_CLKSTATUS_PLL_STB_Msk);
|
||||||
|
|
||||||
|
/* Return equation result */
|
||||||
|
return (clkCalc / ((NO + 1) * bestNR) * bestNF);
|
||||||
|
}
|
||||||
|
|
||||||
|
/** @brief Set Core Clock
|
||||||
|
*
|
||||||
|
* @description Set the core system clock some reference speed (Hz).
|
||||||
|
* This should be between 25MHz and 72MHz for the NUC123SD4AN0.
|
||||||
|
*
|
||||||
|
* Use either the HXT (exact) or HIRC (nearest using 22.1184MHz)
|
||||||
|
* as the clock source.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static uint32_t set_core_clock(uint32_t clkCore)
|
||||||
|
{
|
||||||
|
uint32_t stableHIRC;
|
||||||
|
|
||||||
|
/* Read HIRC clock source stable flag */
|
||||||
|
stableHIRC = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk;
|
||||||
|
|
||||||
|
/* Setup __HIRC */
|
||||||
|
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
|
||||||
|
|
||||||
|
wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk);
|
||||||
|
|
||||||
|
/* Use __HIRC as HCLK temporarily */
|
||||||
|
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_Msk;
|
||||||
|
CLK->CLKDIV &= (~CLK_CLKDIV_HCLK_N_Msk);
|
||||||
|
|
||||||
|
/* Is HXT stable ? */
|
||||||
|
if (CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk) {
|
||||||
|
/* Use __HXT as PLL source */
|
||||||
|
clkCore = enable_pll(NUC123_PLLSRC_HSE, (clkCore));
|
||||||
|
} else {
|
||||||
|
/* Use __HIRC as PLL source */
|
||||||
|
clkCore = enable_pll(NUC123_PLLSRC_HSI, (clkCore));
|
||||||
|
|
||||||
|
/* Read HIRC clock source stable flag again (since we're using it now) */
|
||||||
|
stableHIRC = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set HCLK clock source to PLL */
|
||||||
|
set_HCLK(NUC123_HCLKSRC_PLL, CLK_CLKDIV_HCLK(1));
|
||||||
|
|
||||||
|
/* Disable HIRC if HIRC was disabled before we started */
|
||||||
|
if (stableHIRC == 0) {
|
||||||
|
CLK->PWRCON &= ~CLK_PWRCON_OSC22M_EN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Return actual HCLK frequency is PLL frequency divide 2 */
|
||||||
|
return (clkCore >> 1);
|
||||||
|
}
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver interrupt handlers. */
|
/* Driver interrupt handlers. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
#if defined(NUC123_DMA_REQUIRED) || defined(__DOXYGEN__)
|
|
||||||
#if defined(NUC123_DMA1_CH23_HANDLER) || defined(__DOXYGEN__)
|
|
||||||
/**
|
|
||||||
* @brief DMA1 streams 2 and 3 shared ISR.
|
|
||||||
* @note It is declared here because this device has a non-standard
|
|
||||||
* DMA shared IRQ handler.
|
|
||||||
*
|
|
||||||
* @isr
|
|
||||||
*/
|
|
||||||
OSAL_IRQ_HANDLER(NUC123_DMA1_CH23_HANDLER) {
|
|
||||||
|
|
||||||
OSAL_IRQ_PROLOGUE();
|
|
||||||
|
|
||||||
/* Check on channel 2.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA1_STREAM2);
|
|
||||||
|
|
||||||
/* Check on channel 3.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA1_STREAM3);
|
|
||||||
|
|
||||||
OSAL_IRQ_EPILOGUE();
|
|
||||||
}
|
|
||||||
#endif /* defined(NUC123_DMA1_CH23_HANDLER) */
|
|
||||||
|
|
||||||
#if defined(NUC123_DMA1_CH4567_HANDLER) || defined(__DOXYGEN__)
|
|
||||||
/**
|
|
||||||
* @brief DMA1 streams 4, 5, 6 and 7 shared ISR.
|
|
||||||
*
|
|
||||||
* @isr
|
|
||||||
*/
|
|
||||||
OSAL_IRQ_HANDLER(NUC123_DMA1_CH4567_HANDLER) {
|
|
||||||
|
|
||||||
OSAL_IRQ_PROLOGUE();
|
|
||||||
|
|
||||||
/* Check on channel 4.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA1_STREAM4);
|
|
||||||
|
|
||||||
/* Check on channel 5.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA1_STREAM5);
|
|
||||||
|
|
||||||
#if NUC123_DMA1_NUM_CHANNELS > 5
|
|
||||||
/* Check on channel 6.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA1_STREAM6);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if NUC123_DMA1_NUM_CHANNELS > 6
|
|
||||||
/* Check on channel 7.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA1_STREAM7);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
OSAL_IRQ_EPILOGUE();
|
|
||||||
}
|
|
||||||
#endif /* defined(NUC123_DMA1_CH4567_HANDLER) */
|
|
||||||
|
|
||||||
#if defined(NUC123_DMA12_CH23_CH12_HANDLER) || defined(__DOXYGEN__)
|
|
||||||
/**
|
|
||||||
* @brief DMA1 streams 2 and 3, DMA2 streams 1 and 1 shared ISR.
|
|
||||||
* @note It is declared here because this device has a non-standard
|
|
||||||
* DMA shared IRQ handler.
|
|
||||||
*
|
|
||||||
* @isr
|
|
||||||
*/
|
|
||||||
OSAL_IRQ_HANDLER(NUC123_DMA12_CH23_CH12_HANDLER) {
|
|
||||||
|
|
||||||
OSAL_IRQ_PROLOGUE();
|
|
||||||
|
|
||||||
/* Check on channel 2 of DMA1.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA1_STREAM2);
|
|
||||||
|
|
||||||
/* Check on channel 3 of DMA1.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA1_STREAM3);
|
|
||||||
|
|
||||||
/* Check on channel 1 of DMA2.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA2_STREAM1);
|
|
||||||
|
|
||||||
/* Check on channel 2 of DMA2.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA2_STREAM2);
|
|
||||||
|
|
||||||
OSAL_IRQ_EPILOGUE();
|
|
||||||
}
|
|
||||||
#endif /* defined(NUC123_DMA12_CH23_CH12_HANDLER) */
|
|
||||||
|
|
||||||
#if defined(NUC123_DMA12_CH4567_CH345_HANDLER) || defined(__DOXYGEN__)
|
|
||||||
/**
|
|
||||||
* @brief DMA1 streams 4, 5, 6 and 7, DMA2 streams 3, 4 and 5 shared ISR.
|
|
||||||
* @note It is declared here because this device has a non-standard
|
|
||||||
* DMA shared IRQ handler.
|
|
||||||
*
|
|
||||||
* @isr
|
|
||||||
*/
|
|
||||||
OSAL_IRQ_HANDLER(NUC123_DMA12_CH4567_CH345_HANDLER) {
|
|
||||||
|
|
||||||
OSAL_IRQ_PROLOGUE();
|
|
||||||
|
|
||||||
/* Check on channel 4 of DMA1.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA1_STREAM4);
|
|
||||||
|
|
||||||
/* Check on channel 5 of DMA1.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA1_STREAM5);
|
|
||||||
|
|
||||||
/* Check on channel 6 of DMA1.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA1_STREAM6);
|
|
||||||
|
|
||||||
/* Check on channel 7 of DMA1.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA1_STREAM7);
|
|
||||||
|
|
||||||
/* Check on channel 3 of DMA2.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA2_STREAM3);
|
|
||||||
|
|
||||||
/* Check on channel 4 of DMA2.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA2_STREAM4);
|
|
||||||
|
|
||||||
/* Check on channel 5 of DMA2.*/
|
|
||||||
dmaServeInterrupt(NUC123_DMA2_STREAM5);
|
|
||||||
|
|
||||||
OSAL_IRQ_EPILOGUE();
|
|
||||||
}
|
|
||||||
#endif /* defined(NUC123_DMA12_CH4567_CH345_HANDLER) */
|
|
||||||
#endif /* defined(NUC123_DMA_REQUIRED) */
|
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver exported functions. */
|
/* Driver exported functions. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
@ -181,76 +444,45 @@ OSAL_IRQ_HANDLER(NUC123_DMA12_CH4567_CH345_HANDLER) {
|
||||||
*
|
*
|
||||||
* @notapi
|
* @notapi
|
||||||
*/
|
*/
|
||||||
void hal_lld_init(void) {
|
void hal_lld_init(void)
|
||||||
|
{
|
||||||
/* Reset of all peripherals.*/
|
if (!clock_initialized) {
|
||||||
// **NUC123TODO
|
NUC123_clock_init();
|
||||||
#if defined(NUC123_DMA_REQUIRED)
|
}
|
||||||
//dmaInit();
|
|
||||||
//usbInit();
|
|
||||||
//uartInit();
|
|
||||||
//spiInit();
|
|
||||||
#endif
|
|
||||||
//usbInit();
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
void NUC123_clock_init(void)
|
||||||
* @brief NUC123 clocks and PLL initialization.
|
{
|
||||||
* @note All the involved constants come from the file @p board.h.
|
clock_initialized = TRUE;
|
||||||
* @note This function should be invoked just after the system reset.
|
UNLOCKREG();
|
||||||
*
|
|
||||||
* @special
|
|
||||||
*/
|
|
||||||
void NUC123_clock_init(void) {
|
|
||||||
SystemUnlockReg();
|
|
||||||
|
|
||||||
/* Enable XT1_OUT (PF.0) and XT1_IN (PF.1) */
|
/* Always initialize HSI and go from there, things can change later */
|
||||||
SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN;
|
/* TODO: Technically this could also be the crystal, figure out how to allow
|
||||||
|
* config in linker? */
|
||||||
|
/* Enable HSI */
|
||||||
|
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
|
||||||
|
wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk);
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------------------------------------*/
|
set_HCLK(NUC123_HCLKSRC_HSI, CLK_CLKDIV_HCLK(1));
|
||||||
/* Init System Clock */
|
|
||||||
/*---------------------------------------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/* Enable Internal RC 22.1184 MHz clock */
|
#if NUC123_HSE_ENABLED
|
||||||
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
|
|
||||||
|
|
||||||
/* Waiting for Internal RC clock ready */
|
SYS->GPF_MFP |= (SYS_GPF_MFP_GPF_MFP0_Msk | SYS_GPF_MFP_GPF_MFP1_Msk);
|
||||||
clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_OSC22M_STB_Msk);
|
|
||||||
|
|
||||||
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
|
CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk;
|
||||||
clks_lld_set_HCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
|
wait_for_clock_ready(CLK_CLKSTATUS_XTL12M_STB_Msk);
|
||||||
|
|
||||||
/* Enable external XTAL 12 MHz clock */
|
#endif /* NUC123_HSE_ENABLED */
|
||||||
CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk;
|
|
||||||
|
|
||||||
/* Waiting for external XTAL clock ready */
|
#if NUC123_LSI_ENABLED
|
||||||
clks_lld_wait_for_clock_ready(CLK_CLKSTATUS_XTL12M_STB_Msk);
|
CLK->PWRCON |= CLK_PWRCON_IRC10K_EN_Msk;
|
||||||
|
wait_for_clock_ready(CLK_CLKSTATUS_IRC10K_STB_Msk);
|
||||||
|
#endif /* NUC123_LSI_ENABLED */
|
||||||
|
|
||||||
/* Set core clock */
|
set_core_clock(NUC123_HCLK);
|
||||||
clks_lld_set_core_clock(FREQ_72MHZ);
|
SystemCoreClock = NUC123_HCLK;
|
||||||
|
|
||||||
SystemCoreClock = NUC123_HCLK;
|
LOCKREG();
|
||||||
|
|
||||||
clks_lld_enable_SysTick(CLK_CLKSEL0_STCLK_S_HCLK_DIV2, (NUC123_HCLK / OSAL_ST_FREQUENCY) - 1);
|
|
||||||
|
|
||||||
/* Enable module clock */
|
|
||||||
clks_lld_enable_module_clock(USBD_ModuleNum);
|
|
||||||
|
|
||||||
/* Select module clock source */
|
|
||||||
clks_lld_set_module_clock(USBD_ModuleNum, 0, CLK_CLKDIV_USB(3));
|
|
||||||
|
|
||||||
/* TEMPORARY!!! */
|
|
||||||
/* Set GPB multi-function pins for UART0 RXD and TXD */
|
|
||||||
SYS->GPB_MFP = (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD);
|
|
||||||
/* Set PC.13 as CLKO function pin */
|
|
||||||
//SYS->GPC_MFP = SYS_GPC_MFP_PC13_CLKO;
|
|
||||||
//SYS->ALT_MFP = SYS_ALT_MFP_PC13_CLKO;
|
|
||||||
|
|
||||||
/* Enable CLKO (PC.13) for monitor HCLK. CLKO = HCLK/8 Hz*/
|
|
||||||
// clks_lld_enable_ck0(CLK_CLKSEL2_FRQDIV_S_HCLK, 2, 0);
|
|
||||||
|
|
||||||
LOCKREG();
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
|
@ -1,5 +1,6 @@
|
||||||
/*
|
/*
|
||||||
Copyright (C) 2019 /u/KeepItUnder
|
Copyright (C) 2020 Alex Lewontin
|
||||||
|
Copyright (C) 2019 /u/KeepItUnder
|
||||||
|
|
||||||
Licensed under the Apache License, Version 2.0 (the "License");
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
you may not use this file except in compliance with the License.
|
you may not use this file except in compliance with the License.
|
||||||
|
@ -19,13 +20,9 @@
|
||||||
* @brief NUC123SD4AN0 HAL subsystem low level driver header.
|
* @brief NUC123SD4AN0 HAL subsystem low level driver header.
|
||||||
* @pre This module requires the following macros to be defined in the
|
* @pre This module requires the following macros to be defined in the
|
||||||
* @p board.h file:
|
* @p board.h file:
|
||||||
* - NUC123_LSECLK.
|
|
||||||
* - NUC123_LSEDRV.
|
|
||||||
* - NUC123_LSE_BYPASS (optionally).
|
|
||||||
* - NUC123_HSECLK.
|
* - NUC123_HSECLK.
|
||||||
* - NUC123_HSE_BYPASS (optionally).
|
* - NUC123_HSE_BYPASS (optionally).
|
||||||
* .
|
* .
|
||||||
* .
|
|
||||||
*
|
*
|
||||||
* @addtogroup HAL
|
* @addtogroup HAL
|
||||||
* @{
|
* @{
|
||||||
|
@ -44,20 +41,19 @@
|
||||||
*/
|
*/
|
||||||
#if defined(NUC123SD4AN0) || defined(__DOXYGEN__)
|
#if defined(NUC123SD4AN0) || defined(__DOXYGEN__)
|
||||||
#define PLATFORM_NAME "NUC123SD4AN0 NUC123 Cortex M0 USB Micro"
|
#define PLATFORM_NAME "NUC123SD4AN0 NUC123 Cortex M0 USB Micro"
|
||||||
|
|
||||||
#else
|
#else
|
||||||
#error "NUC123 device unsupported or not specified"
|
#error "NUC123 device unsupported or not specified"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#define NUC123xxxANx
|
||||||
|
#undef NUC123xxxAEx
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @name Absolute Maximum Ratings
|
* @name Absolute Maximum Ratings
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/**
|
|
||||||
* @brief Maximum system clock frequency.
|
|
||||||
*/
|
|
||||||
#define NUC123_SYSCLK_MAX FREQ_72MHZ
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Maximum HSE clock frequency.
|
* @brief Maximum HSE clock frequency.
|
||||||
|
@ -70,39 +66,24 @@
|
||||||
#define NUC123_HSECLK_MIN 4000000
|
#define NUC123_HSECLK_MIN 4000000
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Maximum LSE clock frequency.
|
* @brief Minimum PLL frequency.
|
||||||
*/
|
*/
|
||||||
#define NUC123_LSECLK_MAX 10000
|
#define NUC123_PLLCLK_MIN 25000000UL
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Minimum LSE clock frequency.
|
* @brief Maximum PLL frequency.
|
||||||
*/
|
*/
|
||||||
#define NUC123_LSECLK_MIN 10000
|
#define NUC123_PLLCLK_MAX 144000000UL
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Maximum PLLs input clock frequency.
|
* @brief Minimum HCLK divider value.
|
||||||
*/
|
*/
|
||||||
#define NUC123_PLLIN_MAX 24000000
|
#define NUC123_HCLKDIV_MIN 1
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Minimum PLLs input clock frequency.
|
* @brief Maximum HCLK divider value.
|
||||||
*/
|
*/
|
||||||
#define NUC123_PLLIN_MIN 4000000
|
#define NUC123_HCLKDIV_MAX 16
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Maximum PLL output clock frequency.
|
|
||||||
*/
|
|
||||||
#define NUC123_PLLOUT_MAX FREQ_72MHZ
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Minimum PLL output clock frequency.
|
|
||||||
*/
|
|
||||||
#define NUC123_PLLOUT_MIN 4000000
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Maximum APB clock frequency.
|
|
||||||
*/
|
|
||||||
#define NUC123_PCLK_MAX FREQ_72MHZ
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -110,126 +91,26 @@
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define NUC123_HSICLK __HIRC /**< High speed internal clock. */
|
#define NUC123_HSICLK __HIRC /**< High speed internal clock. */
|
||||||
#define NUC123_HSI_69CLK 691200 /**< ~0.69MHz High speed internal clock. */
|
|
||||||
#define NUC123_HSI1_38CLK 1382400 /**< ~1.375MHz High speed internal clock. */
|
|
||||||
#define NUC123_HSI2_76CLK 2764800 /**< ~2.75MHz High speed internal clock. */
|
|
||||||
#define NUC123_HSI5_5CLK 5529600 /**< ~5.5MHz speed internal clock.*/
|
|
||||||
#define NUC123_HSI11CLK 11059200 /**< ~11MHz speed internal clock.*/
|
|
||||||
#define NUC123_LSICLK __LIRC /**< Low speed internal clock. */
|
#define NUC123_LSICLK __LIRC /**< Low speed internal clock. */
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @name CLKSEL0 register bits definitions
|
* @name HCLK_S bit definitions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
#define NUC123_HCLKSRC_HSE (0 << CLK_CLKSEL0_HCLK_S_Pos) /**< HCLK source is HSE. */
|
||||||
#define NUC123_HCLKSRC_HSE (0 << 0) /**< HCLK source is HSE */
|
#define NUC123_HCLKSRC_PLL_2 (1 << CLK_CLKSEL0_HCLK_S_Pos) /**< HCLK source is PLL/2. */
|
||||||
#define NUC123_HCLKSRC_PLL_2 (1 << 0) /**< HCLK source is PLL/2 */
|
#define NUC123_HCLKSRC_PLL (2 << CLK_CLKSEL0_HCLK_S_Pos) /**< HCLK source is PLL. */
|
||||||
#define NUC123_HCLKSRC_PLL (2 << 0) /**< HCLK source is PLL */
|
#define NUC123_HCLKSRC_LSI (3 << CLK_CLKSEL0_HCLK_S_Pos) /**< HCLK source is LSI. */
|
||||||
#define NUC123_HCLKSRC_LSI (3 << 0) /**< HCLK source is LSI */
|
#define NUC123_HCLKSRC_HSI (7 << CLK_CLKSEL0_HCLK_S_Pos) /**< HCLK source is HSI. */
|
||||||
#define NUC123_HCLKSRC_HSI (7 << 0) /**< HCLK source is HSI */
|
|
||||||
|
|
||||||
#define NUC123_SW_HSE (0 << 3) /**< SYSCLK source is HSE. */
|
|
||||||
#define NUC123_SW_HSE_2 (1 << 3) /**< SYSCLK source is HSE/2. */
|
|
||||||
#define NUC123_SW_HCLK_2 (3 << 3) /**< SYSCLK source is HCLK/2. */
|
|
||||||
#define NUC123_SW_HSI_2 (7 << 3) /**< SYSCLK source is HSI. */
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @name CLKSEL1 register bits definitions
|
* @name PLL_SRC bit definitions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define NUC123_WDTSRC_MASK (3 << 0) /**< WDT source mask */
|
#define NUC123_PLLSRC_HSE (0 << CLK_PLLCON_PLL_SRC_Pos) /**< PLL source is HSE. */
|
||||||
#define NUC123_WDTSRC_HCLK_2048 (2 << 0) /**< WDT source is HCLK/2048 */
|
#define NUC123_PLLSRC_HSI (1 << CLK_PLLCON_PLL_SRC_Pos) /**< PLL source is HSI. */
|
||||||
#define NUC123_WDTSRC_LSI (3 << 0) /**< WDT source is LSI */
|
|
||||||
|
|
||||||
#define NUC123_ADCSRC_MASK (3 << 2) /**< ADC source mask */
|
|
||||||
#define NUC123_ADCSRC_HSE (0 << 2) /**< ADC source is HSE */
|
|
||||||
#define NUC123_ADCSRC_PLL (1 << 2) /**< ADC source is PLL */
|
|
||||||
#define NUC123_ADCSRC_HCLK (2 << 2) /**< ADC source is HCLK */
|
|
||||||
#define NUC123_ADCSRC_HSI (3 << 2) /**< ADC source is HSI */
|
|
||||||
|
|
||||||
#define NUC123_SPI0SRC_MASK (1 << 4) /**< SPI0 source mask */
|
|
||||||
#define NUC123_SPI0SRC_PLL (0 << 4) /**< SPI0 source is PLL */
|
|
||||||
#define NUC123_SPI0SRC_HCLK (1 << 4) /**< SPI0 source is HCLK */
|
|
||||||
#define NUC123_SPI1SRC_MASK (1 << 5) /**< SPI1 source MASK */
|
|
||||||
#define NUC123_SPI1SRC_PLL (0 << 5) /**< SPI1 source is PLL */
|
|
||||||
#define NUC123_SPI1SRC_HCLK (1 << 5) /**< SPI1 source is HCLK */
|
|
||||||
#define NUC123_SPI2SRC_MASK (1 << 6) /**< SPI2 source mask */
|
|
||||||
#define NUC123_SPI2SRC_PLL (0 << 6) /**< SPI2 source is PLL */
|
|
||||||
#define NUC123_SPI2SRC_HCLK (1 << 6) /**< SPI2 source is HCLK */
|
|
||||||
|
|
||||||
#define NUC123_TMR0SRC_MASK (7 << 8) /**< TMR0 source mask */
|
|
||||||
#define NUC123_TMR0SRC_HSE (0 << 8) /**< TMR0 source is HSE */
|
|
||||||
#define NUC123_TMR0SRC_HCLK (2 << 8) /**< TMR0 source is HCLK */
|
|
||||||
#define NUC123_TMR0SRC_TM0 (3 << 8) /**< TMR0 source is TM0 pin */
|
|
||||||
#define NUC123_TMR0SRC_LSI (5 << 8) /**< TMR0 source is LSI */
|
|
||||||
#define NUC123_TMR0SRC_HSI (7 << 8) /**< TMR0 source is HSI */
|
|
||||||
|
|
||||||
#define NUC123_TMR1SRC_MASK (7 << 12) /**< TMR1 source mask */
|
|
||||||
#define NUC123_TMR1SRC_HSE (0 << 12) /**< TMR1 source is HSE */
|
|
||||||
#define NUC123_TMR1SRC_HCLK (2 << 12) /**< TMR1 source is HCLK */
|
|
||||||
#define NUC123_TMR1SRC_TM1 (3 << 12) /**< TMR1 source is TM1 pin */
|
|
||||||
#define NUC123_TMR1SRC_LSI (5 << 12) /**< TMR1 source is LSI */
|
|
||||||
#define NUC123_TMR1SRC_HSI (7 << 12) /**< TMR1 source is HSI */
|
|
||||||
|
|
||||||
#define NUC123_TMR2SRC_MASK (7 << 16) /**< TMR2 source mask */
|
|
||||||
#define NUC123_TMR2SRC_HSE (0 << 16) /**< TMR2 source is HSE */
|
|
||||||
#define NUC123_TMR2SRC_HCLK (2 << 16) /**< TMR2 source is HCLK */
|
|
||||||
#define NUC123_TMR2SRC_TM2 (3 << 16) /**< TMR2 source is TM2 pin */
|
|
||||||
#define NUC123_TMR2SRC_LSI (5 << 16) /**< TMR2 source is LSI */
|
|
||||||
#define NUC123_TMR2SRC_HSI (7 << 16) /**< TMR2 source is HSI */
|
|
||||||
|
|
||||||
#define NUC123_TMR3SRC_MASK (7 << 20) /**< TMR3 source mask */
|
|
||||||
#define NUC123_TMR3SRC_HSE (0 << 20) /**< TMR3 source is HSE */
|
|
||||||
#define NUC123_TMR3SRC_HCLK (2 << 20) /**< TMR3 source is HCLK */
|
|
||||||
#define NUC123_TMR3SRC_LSI (5 << 20) /**< TMR3 source is LSI */
|
|
||||||
#define NUC123_TMR3SRC_HSI (7 << 20) /**< TMR3 source is HSI */
|
|
||||||
|
|
||||||
#define NUC123_USARTSRC_MASK (3 << 24) /**< UART source mask. */
|
|
||||||
#define NUC123_USARTSRC_HS3 (0 << 24) /**< UART source is HSE. */
|
|
||||||
#define NUC123_USARTSRC_PLL (1 << 24) /**< UART source is PLL. */
|
|
||||||
#define NUC123_USARTSRC_HSI (3 << 24) /**< UART source is HSI. */
|
|
||||||
|
|
||||||
#define NUC123_PWM01SRCA_MASK (3 << 28) /**< PWM0/1 source [1:0] mask */
|
|
||||||
#define NUC123_PWM01SRCA_HSE (0 << 28) /**< PWM0/1 source [1:0] is HSE */
|
|
||||||
#define NUC123_PWM01SRCA_HCLK (2 << 28) /**< PWM0/1 source [1:0] is HCLK*/
|
|
||||||
#define NUC123_PWM01SRCA_HSI (3 << 28) /**< PWM0/1 source [1:0] is HSI */
|
|
||||||
#define NUC123_PWM01SRCA_LSI (3 << 28) /**< PWM0/1 source [1:0] is LSI */
|
|
||||||
|
|
||||||
#define NUC123_PWM23SRCA_MASK (3 << 30) /**< PWM2/3 source [1:0] mask */
|
|
||||||
#define NUC123_PWM23SRCA_HSE (0 << 30) /**< PWM2/3 source [1:0] is HSE */
|
|
||||||
#define NUC123_PWM23SRCA_HCLK (2 << 30) /**< PWM2/3 source [1:0] is HCLK*/
|
|
||||||
#define NUC123_PWM23SRCA_HSI (3 << 30) /**< PWM2/3 source [1:0] is HSI */
|
|
||||||
#define NUC123_PWM23SRCA_LSI (3 << 30) /**< PWM2/3 source [1:0] is LSI */
|
|
||||||
/** @} */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @name CLKSEL2 register bits definitions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define NUC123_I2SSRC_MASK (3 << 0) /**< I2S clock source mask. */
|
|
||||||
#define NUC123_I2SSRC_HSE (0 << 0) /**< I2S clock source is HSE. */
|
|
||||||
#define NUC123_I2SSRC_PLL (1 << 0) /**< I2S clock source is PLL. */
|
|
||||||
#define NUC123_I2SSRC_HCLK (2 << 0) /**< I2S clock source is HCLK. */
|
|
||||||
#define NUC123_I2SSRC_HSI (3 << 0) /**< I2S clock source is HSI. */
|
|
||||||
|
|
||||||
#define NUC123_FREQDIVSRC_MASK (3 << 2) /**< FRQDIV clock source mask */
|
|
||||||
#define NUC123_FREQDIVSRC_HSE (0 << 2) /**< FRQDIV clock source is HSE */
|
|
||||||
#define NUC123_FREQDIVSRC_HCLK (2 << 2) /**< FRQDIV clock source is HCLK*/
|
|
||||||
#define NUC123_FREQDIVSRC_HSI (3 << 2) /**< FRQDIV clock source is LSI */
|
|
||||||
|
|
||||||
#define NUC123_PWM01SRCB_MASK (1 << 8) /**< PWM0/1 source [2] mask */
|
|
||||||
#define NUC123_PWM01SRCB_HSI (0 << 8) /**< PWM0/1 source [2] is HSI */
|
|
||||||
#define NUC123_PWM01SRCB_LSI (1 << 8) /**< PWM0/1 source [2] is LSI */
|
|
||||||
|
|
||||||
#define NUC123_PWM23SRCB_MASK (1 << 9) /**< PWM2/3 source [2] mask */
|
|
||||||
#define NUC123_PWM23SRCB_HSI (0 << 9) /**< PWM2/3 source [2] is HSI */
|
|
||||||
#define NUC123_PWM23SRCB_LSI (1 << 9) /**< PWM2/3 source [2] is LSI */
|
|
||||||
|
|
||||||
#define NUC123_WWDTSRC_MASK (3 << 16) /**< WWDT source mask */
|
|
||||||
#define NUC123_WWDTSRC_HCLK_2048 (2 << 16) /**< WWDT source is HCLK/2048 */
|
|
||||||
#define NUC123_WWDTSRC_LSI (3 << 16) /**< WWDT source is LSI */
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
@ -237,9 +118,10 @@
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @name Configuration options
|
* @name NUMICRO configuration options
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Disables the PWR/RCC initialization in the HAL.
|
* @brief Disables the PWR/RCC initialization in the HAL.
|
||||||
*/
|
*/
|
||||||
|
@ -258,7 +140,7 @@
|
||||||
* @brief Enables or disables the LSI clock source.
|
* @brief Enables or disables the LSI clock source.
|
||||||
*/
|
*/
|
||||||
#if !defined(NUC123_LSI_ENABLED) || defined(__DOXYGEN__)
|
#if !defined(NUC123_LSI_ENABLED) || defined(__DOXYGEN__)
|
||||||
#define NUC123_LSI_ENABLED TRUE
|
#define NUC123_LSI_ENABLED FALSE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -269,118 +151,31 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Enables or disables the LSE clock source.
|
* @brief Enables or disables PLL
|
||||||
*/
|
*/
|
||||||
#if !defined(NUC123_LSE_ENABLED) || defined(__DOXYGEN__)
|
#if !defined(NUC123_PLL_ENABLED) || defined(__DOXYGEN__)
|
||||||
#define NUC123_LSE_ENABLED FALSE
|
#define NUC123_PLL_ENABLED FALSE
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Main clock source selection.
|
* @brief Main clock source selection.
|
||||||
* @note If the selected clock source is not the PLL then the PLL is not
|
|
||||||
* initialized and started.
|
|
||||||
* @note The default value is calculated for a 72MHz system clock from
|
|
||||||
* a 12MHz crystal using the PLL.
|
|
||||||
*/
|
*/
|
||||||
#if !defined(NUC123_SW) || defined(__DOXYGEN__)
|
#if !defined(NUC123_HCLKSRC) || defined(__DOXYGEN__)
|
||||||
#define NUC123_SW NUC123_SW_HCLK_2
|
#define NUC123_HCLKSRC NUC123_HCLKSRC_HSI
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Main clock divider value.
|
||||||
|
*/
|
||||||
|
#if !defined(NUC123_HCLKDIV) || defined(__DOXYGEN__)
|
||||||
|
#define NUC123_HCLKDIV 1
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Clock source for the PLL.
|
* @brief Clock source for the PLL.
|
||||||
* @note This setting has only effect if the PLL is selected as the
|
|
||||||
* system clock source.
|
|
||||||
* @note The default value is calculated for a 72MHz system clock from
|
|
||||||
* a 12MHz crystal using the PLL.
|
|
||||||
*/
|
*/
|
||||||
#if !defined(NUC123_PLLSRC) || defined(__DOXYGEN__)
|
#if !defined(NUC123_PLLCLK) || defined(__DOXYGEN__)
|
||||||
#define NUC123_PLLSRC NUC123_PLLSRC_HSE
|
#define NUC123_PLLCLK 72000000UL
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Crystal PLL pre-divider.
|
|
||||||
* @note This setting has only effect if the PLL is selected as the
|
|
||||||
* system clock source.
|
|
||||||
* @note The default value is calculated for a 72MHz system clock from
|
|
||||||
* a 21MHz crystal using the PLL.
|
|
||||||
*/
|
|
||||||
#if !defined(NUC123_PREDIV_VALUE) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_PREDIV_VALUE 1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief PLL multiplier value.
|
|
||||||
* @note The allowed range is 2...16.
|
|
||||||
* @note The default value is calculated for a 72MHz system clock from
|
|
||||||
* a 12MHz crystal using the PLL.
|
|
||||||
*/
|
|
||||||
#if !defined(NUC123_PLLMUL_VALUE) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_PLLMUL_VALUE 6
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AHB prescaler value.
|
|
||||||
* @note The default value is calculated for a 72MHz system clock from
|
|
||||||
* a 12MHz crystal using the PLL.
|
|
||||||
*/
|
|
||||||
#if !defined(NUC123_HPRE) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_HPRE NUC123_HPRE_DIV1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief APB1 prescaler value.
|
|
||||||
*/
|
|
||||||
#if !defined(NUC123_PPRE) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_PPRE NUC123_PPRE_DIV1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief MCO pin setting.
|
|
||||||
*/
|
|
||||||
#if !defined(NUC123_MCOSEL) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_MCOSEL NUC123_MCOSEL_NOCLOCK
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief MCO divider setting.
|
|
||||||
*/
|
|
||||||
#if !defined(NUC123_MCOPRE) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_MCOPRE NUC123_MCOPRE_DIV1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief MCO PLL divider setting.
|
|
||||||
*/
|
|
||||||
#if !defined(NUC123_PLLNODIV) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_PLLNODIV NUC123_PLLNODIV_DIV2
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief USB Clock source.
|
|
||||||
*/
|
|
||||||
#if !defined(NUC123_USBSW) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_USBSW NUC123_USBSW_HSI48
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief CEC clock source.
|
|
||||||
*/
|
|
||||||
#if !defined(NUC123_CECSW) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_CECSW NUC123_CECSW_HSI
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief I2C1 clock source.
|
|
||||||
*/
|
|
||||||
#if !defined(NUC123_I2C1SW) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_I2C1SW NUC123_I2C1SW_HSI
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief USART1 clock source.
|
|
||||||
*/
|
|
||||||
#if !defined(NUC123_USART1SW) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_USART1SW NUC123_USART1SW_PCLK
|
|
||||||
#endif
|
#endif
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
|
@ -396,335 +191,84 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* HSI related checks.
|
* HSE checks.
|
||||||
*/
|
|
||||||
#if NUC123_HSI_ENABLED
|
|
||||||
|
|
||||||
/*#if NUC123_SW == NUC123_SW_HSE
|
|
||||||
#error "HSI not enabled, required by NUC123_SW"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if NUC123_CECSW == NUC123_CECSW_HSI
|
|
||||||
#error "HSI not enabled, required by NUC123_CECSW"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if NUC123_I2C1SW == NUC123_I2C1SW_HSI
|
|
||||||
#error "HSI not enabled, required by NUC123_I2C1SW"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if NUC123_USART1SW == NUC123_USART1SW_HSI
|
|
||||||
#error "HSI not enabled, required by NUC123_USART1SW"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (NUC123_SW == NUC123_SW_PLL) && \
|
|
||||||
(NUC123_PLLSRC == NUC123_PLLSRC_HSI_DIV2) || \
|
|
||||||
(NUC123_PLLSRC == NUC123_PLLSRC_HSI)
|
|
||||||
#error "HSI not enabled, required by NUC123_SW and NUC123_PLLSRC"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (NUC123_MCOSEL == NUC123_MCOSEL_HSI) || \
|
|
||||||
((NUC123_MCOSEL == NUC123_MCOSEL_PLLDIV2) && \
|
|
||||||
((NUC123_PLLSRC == NUC123_PLLSRC_HSI_DIV2) || \
|
|
||||||
(NUC123_PLLSRC == NUC123_PLLSRC_HSI)))
|
|
||||||
#error "HSI not enabled, required by NUC123_MCOSEL"
|
|
||||||
#endif
|
|
||||||
*/
|
|
||||||
#endif /* !NUC123_HSI_ENABLED */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* HSE related checks.
|
|
||||||
*/
|
*/
|
||||||
#if NUC123_HSE_ENABLED
|
#if NUC123_HSE_ENABLED
|
||||||
|
|
||||||
#if NUC123_HSECLK == 0
|
#if !defined(NUC123_HSECLK)
|
||||||
#error "HSE frequency not defined"
|
#error "HSE frequency not defined"
|
||||||
#elif (NUC123_HSECLK < NUC123_HSECLK_MIN) || (NUC123_HSECLK > NUC123_HSECLK_MAX)
|
#elif (NUC123_HSECLK < NUC123_HSECLK_MIN) || (NUC123_HSECLK > NUC123_HSECLK_MAX)
|
||||||
#error "NUC123_HSECLK outside acceptable range (NUC123_HSECLK_MIN...NUC123_HSECLK_MAX)"
|
#error "NUC123_HSECLK outside acceptable range (NUC123_HSECLK_MIN...NUC123_HSECLK_MAX)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#else /* !NUC123_HSE_ENABLED */
|
|
||||||
|
|
||||||
#if (NUC123_SW == NUC123_SW_HSE) || (NUC123_SW == NUC123_SW_HSE_2)
|
|
||||||
#error "HSE not enabled, required by NUC123_SW"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (NUC123_SW == NUC123_SW_HCL) && (NUC123_PLLSRC == NUC123_PLLSRC_HSE)
|
|
||||||
#error "HSE not enabled, required by NUC123_SW and NUC123_PLLSRC"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (NUC123_MCOSEL == NUC123_MCOSEL_HSE) || \
|
|
||||||
((NUC123_MCOSEL == NUC123_MCOSEL_PLLDIV2) && \
|
|
||||||
(NUC123_PLLSRC == NUC123_PLLSRC_HSE))
|
|
||||||
#error "HSE not enabled, required by NUC123_MCOSEL"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* !NUC123_HSE_ENABLED */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* LSI related checks.
|
|
||||||
*/
|
|
||||||
#if NUC123_LSI_ENABLED
|
|
||||||
#else /* !NUC123_LSI_ENABLED */
|
|
||||||
|
|
||||||
#if NUC123_RTCSEL == NUC123_RTCSEL_LSI
|
|
||||||
#error "LSI not enabled, required by NUC123_RTCSEL"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* !NUC123_LSI_ENABLED */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* LSE related checks.
|
|
||||||
*/
|
|
||||||
#if NUC123_LSE_ENABLED
|
|
||||||
|
|
||||||
#if (NUC123_LSECLK == 0)
|
|
||||||
#error "LSE frequency not defined"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (NUC123_LSECLK < NUC123_LSECLK_MIN) || (NUC123_LSECLK > NUC123_LSECLK_MAX)
|
|
||||||
#error "NUC123_LSECLK outside acceptable range (NUC123_LSECLK_MIN...NUC123_LSECLK_MAX)"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(NUC123_LSEDRV)
|
|
||||||
#error "NUC123_LSEDRV not defined"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (NUC123_LSEDRV >> 3) > 3
|
|
||||||
#error "NUC123_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#else /* !NUC123_LSE_ENABLED */
|
|
||||||
|
|
||||||
#endif /* !NUC123_LSE_ENABLED */
|
|
||||||
|
|
||||||
/* PLL activation conditions.*/
|
|
||||||
#if (NUC123_SW == NUC123_SW_PLL) || \
|
|
||||||
(NUC123_USBSW == NUC123_USBSW_PCLK) || \
|
|
||||||
(NUC123_MCOSEL == NUC123_MCOSEL_PLLDIV2) || \
|
|
||||||
defined(__DOXYGEN__)
|
|
||||||
/**
|
|
||||||
* @brief PLL activation flag.
|
|
||||||
*/
|
|
||||||
#define NUC123_ACTIVATE_PLL TRUE
|
|
||||||
#else
|
|
||||||
#define NUC123_ACTIVATE_PLL FALSE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* HSE, HSI prescaler setting check.*/
|
|
||||||
#if ((NUC123_PREDIV_VALUE >= 1) || (NUC123_PREDIV_VALUE <= 16))
|
|
||||||
#define NUC123_PREDIV ((NUC123_PREDIV_VALUE - 1) << 0)
|
|
||||||
#else
|
|
||||||
#error "invalid NUC123_PREDIV value specified"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief PLLMUL field.
|
|
||||||
*/
|
|
||||||
#if ((NUC123_PLLMUL_VALUE >= 2) && (NUC123_PLLMUL_VALUE <= 16)) || \
|
|
||||||
defined(__DOXYGEN__)
|
|
||||||
#define NUC123_PLLMUL ((NUC123_PLLMUL_VALUE - 2) << 18)
|
|
||||||
#else
|
|
||||||
#error "invalid NUC123_PLLMUL_VALUE value specified"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief PLL input clock frequency.
|
|
||||||
*/
|
|
||||||
#if (NUC123_PLLSRC == NUC123_PLLSRC_HSE) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_PLLCLKIN (NUC123_HSECLK / NUC123_PREDIV_VALUE)
|
|
||||||
#elif NUC123_PLLSRC == NUC123_PLLSRC_HSI_DIV2
|
|
||||||
#define NUC123_PLLCLKIN (NUC123_HSICLK / 2)
|
|
||||||
#elif NUC123_PLLSRC == NUC123_PLLSRC_HSI
|
|
||||||
#define NUC123_PLLCLKIN (NUC123_HSICLK / NUC123_PREDIV_VALUE)
|
|
||||||
#else
|
|
||||||
#error "invalid NUC123_PLLSRC value specified"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* PLL input frequency range check.*/
|
|
||||||
#if (NUC123_PLLCLKIN < NUC123_PLLIN_MIN) || (NUC123_PLLCLKIN > NUC123_PLLIN_MAX)
|
|
||||||
#error "NUC123_PLLCLKIN outside acceptable range (NUC123_PLLIN_MIN...NUC123_PLLIN_MAX)"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief PLL output clock frequency.
|
|
||||||
*/
|
|
||||||
#define NUC123_PLLCLKOUT (NUC123_PLLCLKIN * NUC123_PLLMUL_VALUE)
|
|
||||||
|
|
||||||
/* PLL output frequency range check.
|
|
||||||
#if (NUC123_PLLCLKOUT < NUC123_PLLOUT_MIN) || (NUC123_PLLCLKOUT > NUC123_PLLOUT_MAX)
|
|
||||||
#error "NUC123_PLLCLKOUT outside acceptable range (NUC123_PLLOUT_MIN...NUC123_PLLOUT_MAX)"
|
|
||||||
#endif
|
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @brief System clock source.
|
|
||||||
*/
|
|
||||||
#if (NUC123_SW == NUC123_SW_HSE) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_SYSCLK NUC123_HSECLK
|
|
||||||
#elif (NUC123_SW == NUC123_SW_HSE_2)
|
|
||||||
#define NUC123_SYSCLK NUC123_HSECLK >> 1
|
|
||||||
#elif (NUC123_SW == NUC123_SW_HCLK_2)
|
|
||||||
#define NUC123_SYSCLK FREQ_72MHZ >> 1
|
|
||||||
#elif (NUC123_SW == NUC123_SW_HSI_2)
|
|
||||||
#define NUC123_SYSCLK NUC123_HSI11CLK
|
|
||||||
#else
|
|
||||||
#error "invalid NUC123_SW value specified"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Check on the system clock.*/
|
|
||||||
#if NUC123_SYSCLK > NUC123_SYSCLK_MAX
|
|
||||||
#error "NUC123_SYSCLK above maximum rated frequency (NUC123_SYSCLK_MAX)"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief AHB frequency.
|
|
||||||
*
|
|
||||||
#if (NUC123_HPRE == NUC123_HPRE_DIV1) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_HCLK (NUC123_SYSCLK / 1)
|
|
||||||
#elif NUC123_HPRE == NUC123_HPRE_DIV2
|
|
||||||
#define NUC123_HCLK (NUC123_SYSCLK / 2)
|
|
||||||
#elif NUC123_HPRE == NUC123_HPRE_DIV4
|
|
||||||
#define NUC123_HCLK (NUC123_SYSCLK / 4)
|
|
||||||
#elif NUC123_HPRE == NUC123_HPRE_DIV8
|
|
||||||
#define NUC123_HCLK (NUC123_SYSCLK / 8)
|
|
||||||
#elif NUC123_HPRE == NUC123_HPRE_DIV16
|
|
||||||
#define NUC123_HCLK (NUC123_SYSCLK / 16)
|
|
||||||
#elif NUC123_HPRE == NUC123_HPRE_DIV64
|
|
||||||
#define NUC123_HCLK (NUC123_SYSCLK / 64)
|
|
||||||
#elif NUC123_HPRE == NUC123_HPRE_DIV128
|
|
||||||
#define NUC123_HCLK (NUC123_SYSCLK / 128)
|
|
||||||
#elif NUC123_HPRE == NUC123_HPRE_DIV256
|
|
||||||
#define NUC123_HCLK (NUC123_SYSCLK / 256)
|
|
||||||
#elif NUC123_HPRE == NUC123_HPRE_DIV512
|
|
||||||
#define NUC123_HCLK (NUC123_SYSCLK / 512)
|
|
||||||
#else
|
|
||||||
#error "invalid NUC123_HPRE value specified"
|
|
||||||
#endif
|
|
||||||
*/
|
|
||||||
#define NUC123_HCLK (NUC123_SYSCLK / 1)
|
|
||||||
|
|
||||||
/* AHB frequency check.*/
|
|
||||||
#if NUC123_HCLK > NUC123_SYSCLK_MAX
|
|
||||||
#error "NUC123_HCLK exceeding maximum frequency (NUC123_SYSCLK_MAX)"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief APB frequency.
|
|
||||||
*/
|
|
||||||
#if (NUC123_PPRE == NUC123_PPRE_DIV1) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_PCLK (NUC123_HCLK / 1)
|
|
||||||
#elif NUC123_PPRE == NUC123_PPRE_DIV2
|
|
||||||
#define NUC123_PCLK (NUC123_HCLK / 2)
|
|
||||||
#elif NUC123_PPRE == NUC123_PPRE_DIV4
|
|
||||||
#define NUC123_PCLK (NUC123_HCLK / 4)
|
|
||||||
#elif NUC123_PPRE == NUC123_PPRE_DIV8
|
|
||||||
#define NUC123_PCLK (NUC123_HCLK / 8)
|
|
||||||
#elif NUC123_PPRE == NUC123_PPRE_DIV16
|
|
||||||
#define NUC123_PCLK (NUC123_HCLK / 16)
|
|
||||||
#else
|
|
||||||
#error "invalid NUC123_PPRE value specified"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* APB frequency check.*/
|
|
||||||
#if NUC123_PCLK > NUC123_PCLK_MAX
|
|
||||||
#error "NUC123_PCLK exceeding maximum frequency (NUC123_PCLK_MAX)"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* NUC123_PLLNODIV check.*/
|
|
||||||
#if (NUC123_PLLNODIV != NUC123_PLLNODIV_DIV2) && \
|
|
||||||
(NUC123_PLLNODIV != NUC123_PLLNODIV_DIV1)
|
|
||||||
#error "invalid NUC123_PLLNODIV value specified"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief CEC frequency.
|
|
||||||
*/
|
|
||||||
#if (NUC123_CECSW == NUC123_CECSW_HSI) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_CECCLK NUC123_HSICLK
|
|
||||||
#elif NUC123_CECSW == NUC123_CECSW_LSE
|
|
||||||
#define NUC123_CECCLK NUC123_LSECLK
|
|
||||||
#elif NUC123_CECSW == NUC123_CECSW_OFF
|
|
||||||
#define NUC123_CECCLK 0
|
|
||||||
#else
|
|
||||||
#error "invalid source selected for CEC clock"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief I2C1 frequency.
|
|
||||||
*/
|
|
||||||
#if (NUC123_I2C1SW == NUC123_I2C1SW_HSI) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_I2C1CLK NUC123_HSICLK
|
|
||||||
#elif NUC123_I2C1SW == NUC123_I2C1SW_SYSCLK
|
|
||||||
#define NUC123_I2C1CLK NUC123_SYSCLK
|
|
||||||
#else
|
|
||||||
#error "invalid source selected for I2C1 clock"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief USART1 frequency.
|
|
||||||
*/
|
|
||||||
#if (NUC123_USART1SW == NUC123_USART1SW_PCLK) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_USART1CLK NUC123_PCLK
|
|
||||||
#elif NUC123_USART1SW == NUC123_USART1SW_SYSCLK
|
|
||||||
#define NUC123_USART1CLK NUC123_SYSCLK
|
|
||||||
#elif NUC123_USART1SW == NUC123_USART1SW_LSE
|
|
||||||
#define NUC123_USART1CLK NUC123_LSECLK
|
|
||||||
#elif NUC123_USART1SW == NUC123_USART1SW_HSI
|
|
||||||
#define NUC123_USART1CLK NUC123_HSICLK
|
|
||||||
#else
|
|
||||||
#error "invalid source selected for USART1 clock"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// /**
|
|
||||||
// * @brief USART2 frequency.
|
|
||||||
// */
|
|
||||||
// #define NUC123_USART2CLK NUC123_PCLK
|
|
||||||
|
|
||||||
// /**
|
|
||||||
// * @brief USART3 frequency.
|
|
||||||
// */
|
|
||||||
// #define NUC123_USART3CLK NUC123_PCLK
|
|
||||||
|
|
||||||
// /**
|
|
||||||
// * @brief USART4 frequency.
|
|
||||||
// */
|
|
||||||
// #define NUC123_UART4CLK NUC123_PCLK
|
|
||||||
|
|
||||||
// /**
|
|
||||||
// * @brief USART5 frequency.
|
|
||||||
// */
|
|
||||||
// #define NUC123_UART5CLK NUC123_PCLK
|
|
||||||
|
|
||||||
// /**
|
|
||||||
// * @brief USART6 frequency.
|
|
||||||
// */
|
|
||||||
// #define NUC123_USART6CLK NUC123_PCLK
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Timers clock.
|
|
||||||
*/
|
|
||||||
#if (NUC123_PPRE == NUC123_PPRE_DIV1) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_TIMCLK1 (NUC123_PCLK * 1)
|
|
||||||
#define NUC123_TIMCLK2 (NUC123_PCLK * 1)
|
|
||||||
#else
|
|
||||||
#define NUC123_TIMCLK1 (NUC123_PCLK * 2)
|
|
||||||
#define NUC123_TIMCLK2 (NUC123_PCLK * 2)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Flash settings.
|
|
||||||
*/
|
|
||||||
#if (NUC123_HCLK <= 24000000) || defined(__DOXYGEN__)
|
|
||||||
#define NUC123_FLASHBITS 0x00000010
|
|
||||||
#else
|
|
||||||
#define NUC123_FLASHBITS 0x00000011
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* For compatibility with driver assuming a specific PPRE clock.
|
* PLL checks
|
||||||
*/
|
*/
|
||||||
#define NUC123_PCLK1 NUC123_PCLK
|
|
||||||
#define NUC123_PCLK2 NUC123_PCLK
|
#if NUC123_PLL_ENABLED
|
||||||
|
|
||||||
|
#if !defined(NUC123_PLLCLK)
|
||||||
|
#error "PLL frequency not defined"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (NUC123_PLLCLK < NUC123_PLLCLK_MIN) || \
|
||||||
|
(NUC123_PLLCLK > NUC123_PLLCLK_MAX)
|
||||||
|
#error \
|
||||||
|
"NUC123_PLLCLK outside acceptable range (NUC123_PLLCLK_MIN...NUC123_PLLCLK_MAX)"
|
||||||
|
#endif
|
||||||
|
#endif /* NUC123_PLL_ENABLED */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* HCLK checks.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if (NUC123_HCLKDIV < NUC123_HCLKDIV_MIN || \
|
||||||
|
NUC123_HCLKDIV > NUC123_HCLKDIV_MAX)
|
||||||
|
#error \
|
||||||
|
"NUC123_HCLKDIV outside acceptable range (NUC123_HCLKDIV_MIN...NUC123_HCLDIV_MAX)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if NUC123_HCLKSRC == NUC123_HCLKSRC_HSE
|
||||||
|
|
||||||
|
#if !NUC123_HSE_ENABLED
|
||||||
|
#error "Cannot use HSE as a HCLK source if it is disabled."
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define NUC123_HCLK (NUC123_HSECLK / NUC123_HCLKDIV)
|
||||||
|
|
||||||
|
#elif NUC123_HCLKSRC == NUC123_HCLKSRC_PLL_2
|
||||||
|
|
||||||
|
#if !NUC123_PLL_ENABLED
|
||||||
|
#error "Cannot use PLL as a HCLK source if it is disabled."
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define NUC123_HCLK (NUC123_PLLCLK / 2)
|
||||||
|
|
||||||
|
#elif NUC123_HCLKSRC == NUC123_HCLKSRC_PLL
|
||||||
|
|
||||||
|
#if !NUC123_PLL_ENABLED
|
||||||
|
#error "Cannot use PLL as a HCLK source if it is disabled."
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define NUC123_HCLK (NUC123_PLLCLK / NUC123_HCLKDIV)
|
||||||
|
|
||||||
|
#elif NUC123_HCLKSRC == NUC123_HCLKSRC_LSI
|
||||||
|
|
||||||
|
#if !NUC123_LSI_ENABLED
|
||||||
|
#error "Cannot use LSI as a HCLK source if it is disabled."
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define NUC123_HCLK (NUC123_LSICLK / NUC123_HCLKDIV)
|
||||||
|
|
||||||
|
#elif NUC123_HCLKSRC == NUC123_HCLKSRC_HSI
|
||||||
|
#if !NUC123_HSI_ENABLED
|
||||||
|
#error "Cannot use HSI as a HCLK source if it is disabled."
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define NUC123_HCLK (NUC123_HSICLK / NUC123_HCLKDIV)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver data structures and types. */
|
/* Driver data structures and types. */
|
||||||
|
@ -733,17 +277,18 @@
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver macros. */
|
/* Driver macros. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
/* Alias for compatibility */
|
||||||
|
#define SystemUnlockReg() UNLOCKREG()
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* External declarations. */
|
/* External declarations. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
||||||
/* Various helpers.*/
|
/* Various helpers */
|
||||||
#include "nvic.h"
|
#include "NUC123.h"
|
||||||
#include "nuc123_isr.h"
|
#include "nuc123_isr.h"
|
||||||
//#include "nuc123_dma.h"
|
#include "nuc123_registry.h"
|
||||||
#include "hal_clks_lld.h"
|
#include "nvic.h"
|
||||||
#include "hal_pwm_lld.h"
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
|
@ -754,6 +299,6 @@ extern "C" {
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* HAL_LLD_H */
|
#endif /* _HAL_LLD_H_ */
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
|
@ -253,8 +253,12 @@
|
||||||
#define NUC123_HAS_CRC TRUE
|
#define NUC123_HAS_CRC TRUE
|
||||||
#define NUC123_CRC_PROGRAMMABLE FALSE
|
#define NUC123_CRC_PROGRAMMABLE FALSE
|
||||||
|
|
||||||
|
/*
|
||||||
|
This currently correspond to the header guards, and gets tripped on double inclusion.
|
||||||
|
This does not seem correct.
|
||||||
#else
|
#else
|
||||||
#error "NUC123SD4AN0 device not specified"
|
#error "NUC123SD4AN0 device not specified"
|
||||||
|
*/
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
|
|
|
@ -1,7 +1,5 @@
|
||||||
# Required platform files.
|
|
||||||
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
|
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
|
||||||
$(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123SD4AN0/hal_lld.c \
|
$(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123SD4AN0/hal_lld.c
|
||||||
$(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123SD4AN0/system_NUC123SD4AN0.c
|
|
||||||
|
|
||||||
# Required include directories.
|
# Required include directories.
|
||||||
PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
|
PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
|
||||||
|
@ -15,7 +13,10 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
|
||||||
endif
|
endif
|
||||||
|
|
||||||
# Drivers compatible with the platform.
|
# Drivers compatible with the platform.
|
||||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/CLKv1/driver.mk
|
|
||||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/driver.mk
|
include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/GPIOv1/driver.mk
|
||||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/TIMv1/driver.mk
|
include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/TIMv1/driver.mk
|
||||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/USBv1/driver.mk
|
include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/LLD/USBv1/driver.mk
|
||||||
|
|
||||||
|
# Shared variables
|
||||||
|
ALLCSRC += $(PLATFORMSRC)
|
||||||
|
ALLINC += $(PLATFORMINC)
|
|
@ -0,0 +1,205 @@
|
||||||
|
##############################################################################
|
||||||
|
# Build global options
|
||||||
|
# NOTE: Can be overridden externally.
|
||||||
|
#
|
||||||
|
|
||||||
|
# Compiler options here.
|
||||||
|
ifeq ($(USE_OPT),)
|
||||||
|
USE_OPT = -ggdb -g3 -gdwarf-3 -gstrict-dwarf -fomit-frame-pointer -falign-functions=16
|
||||||
|
endif
|
||||||
|
|
||||||
|
# C specific options here (added to USE_OPT).
|
||||||
|
ifeq ($(USE_COPT),)
|
||||||
|
USE_COPT =
|
||||||
|
endif
|
||||||
|
|
||||||
|
# C++ specific options here (added to USE_OPT).
|
||||||
|
ifeq ($(USE_CPPOPT),)
|
||||||
|
USE_CPPOPT = -fno-rtti
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Enable this if you want the linker to remove unused code and data.
|
||||||
|
ifeq ($(USE_LINK_GC),)
|
||||||
|
USE_LINK_GC = yes
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Linker extra options here.
|
||||||
|
ifeq ($(USE_LDOPT),)
|
||||||
|
USE_LDOPT =
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Enable this if you want link time optimizations (LTO).
|
||||||
|
ifeq ($(USE_LTO),)
|
||||||
|
USE_LTO = yes
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Enable this if you want to see the full log while compiling.
|
||||||
|
ifeq ($(USE_VERBOSE_COMPILE),)
|
||||||
|
USE_VERBOSE_COMPILE = no
|
||||||
|
endif
|
||||||
|
|
||||||
|
# If enabled, this option makes the build process faster by not compiling
|
||||||
|
# modules not used in the current configuration.
|
||||||
|
ifeq ($(USE_SMART_BUILD),)
|
||||||
|
USE_SMART_BUILD = yes
|
||||||
|
endif
|
||||||
|
|
||||||
|
#
|
||||||
|
# Build global options
|
||||||
|
##############################################################################
|
||||||
|
|
||||||
|
##############################################################################
|
||||||
|
# Architecture or project specific options
|
||||||
|
#
|
||||||
|
|
||||||
|
# Stack size to be allocated to the Cortex-M process stack. This stack is
|
||||||
|
# the stack used by the main() thread.
|
||||||
|
ifeq ($(USE_PROCESS_STACKSIZE),)
|
||||||
|
USE_PROCESS_STACKSIZE = 0x400
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
|
||||||
|
# stack is used for processing interrupts and exceptions.
|
||||||
|
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
|
||||||
|
USE_EXCEPTIONS_STACKSIZE = 0x400
|
||||||
|
endif
|
||||||
|
|
||||||
|
# Enables the use of FPU (no, softfp, hard).
|
||||||
|
ifeq ($(USE_FPU),)
|
||||||
|
USE_FPU = no
|
||||||
|
endif
|
||||||
|
|
||||||
|
# FPU-related options.
|
||||||
|
ifeq ($(USE_FPU_OPT),)
|
||||||
|
USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16
|
||||||
|
endif
|
||||||
|
|
||||||
|
#
|
||||||
|
# Architecture or project specific options
|
||||||
|
##############################################################################
|
||||||
|
|
||||||
|
##############################################################################
|
||||||
|
# Project, target, sources and paths
|
||||||
|
#
|
||||||
|
|
||||||
|
# Define project name here
|
||||||
|
PROJECT = ch
|
||||||
|
|
||||||
|
# Target settings.
|
||||||
|
MCU = cortex-m0
|
||||||
|
|
||||||
|
# Imported source files and paths.
|
||||||
|
BASE_PATH := ../../../../../../..
|
||||||
|
CHIBIOS := $(BASE_PATH)/ChibiOS/ChibiOS
|
||||||
|
CHIBIOS_CONTRIB := $(BASE_PATH)/ChibiOS/ChibiOS-Contrib
|
||||||
|
CONFDIR := ./cfg
|
||||||
|
BUILDDIR := ./build
|
||||||
|
DEPDIR := ./.dep
|
||||||
|
|
||||||
|
# Licensing files.
|
||||||
|
include $(CHIBIOS)/os/license/license.mk
|
||||||
|
# Startup files.
|
||||||
|
include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_NUC123SD4AN0.mk
|
||||||
|
# HAL-OSAL files (optional).
|
||||||
|
include $(CHIBIOS)/os/hal/hal.mk
|
||||||
|
include $(CHIBIOS_CONTRIB)/os/hal/ports/NUMICRO/NUC123SD4AN0/platform.mk
|
||||||
|
include $(CHIBIOS_CONTRIB)/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.mk
|
||||||
|
include $(CHIBIOS)/os/hal/osal/os-less/ARMCMx/osal.mk
|
||||||
|
# RTOS files (optional).
|
||||||
|
#include $(CHIBIOS)/os/rt/rt.mk
|
||||||
|
#include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk
|
||||||
|
# Auto-build files in ./source recursively.
|
||||||
|
include $(CHIBIOS)/tools/mk/autobuild.mk
|
||||||
|
# Other files (optional).
|
||||||
|
#include $(CHIBIOS)/test/lib/test.mk
|
||||||
|
#include $(CHIBIOS)/test/rt/rt_test.mk
|
||||||
|
#include $(CHIBIOS)/test/oslib/oslib_test.mk
|
||||||
|
|
||||||
|
# C sources that can be compiled in ARM or THUMB mode depending on the global
|
||||||
|
# setting.
|
||||||
|
CSRC = $(ALLCSRC) \
|
||||||
|
$(TESTSRC) \
|
||||||
|
main.c
|
||||||
|
|
||||||
|
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
|
||||||
|
# setting.
|
||||||
|
CPPSRC = $(ALLCPPSRC)
|
||||||
|
|
||||||
|
# List ASM source files here.
|
||||||
|
ASMSRC = $(ALLASMSRC)
|
||||||
|
|
||||||
|
# List ASM with preprocessor source files here.
|
||||||
|
ASMXSRC = $(ALLXASMSRC)
|
||||||
|
|
||||||
|
# Inclusion directories.
|
||||||
|
INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC)
|
||||||
|
|
||||||
|
# Define C warning options here.
|
||||||
|
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
|
||||||
|
|
||||||
|
# Define C++ warning options here.
|
||||||
|
CPPWARN = -Wall -Wextra -Wundef
|
||||||
|
|
||||||
|
#
|
||||||
|
# Project, target, sources and paths
|
||||||
|
##############################################################################
|
||||||
|
|
||||||
|
##############################################################################
|
||||||
|
# Start of user section
|
||||||
|
#
|
||||||
|
|
||||||
|
# List all user C define here, like -D_DEBUG=1
|
||||||
|
UDEFS =
|
||||||
|
|
||||||
|
# Define ASM defines here
|
||||||
|
UADEFS =
|
||||||
|
|
||||||
|
# List all user directories here
|
||||||
|
UINCDIR =
|
||||||
|
|
||||||
|
# List the user directory to look for the libraries here
|
||||||
|
ULIBDIR =
|
||||||
|
|
||||||
|
# List all user libraries here
|
||||||
|
ULIBS =
|
||||||
|
|
||||||
|
#
|
||||||
|
# End of user section
|
||||||
|
##############################################################################
|
||||||
|
|
||||||
|
##############################################################################
|
||||||
|
# Common rules
|
||||||
|
#
|
||||||
|
|
||||||
|
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
|
||||||
|
include $(RULESPATH)/arm-none-eabi.mk
|
||||||
|
include $(RULESPATH)/rules.mk
|
||||||
|
|
||||||
|
#
|
||||||
|
# Common rules
|
||||||
|
##############################################################################
|
||||||
|
|
||||||
|
##############################################################################
|
||||||
|
# Custom rules
|
||||||
|
#
|
||||||
|
|
||||||
|
|
||||||
|
OPENOCD:=$(shell readlink -f `which openocd`)
|
||||||
|
OPENOCDPATH:=$(shell dirname $(OPENOCD))/../share/openocd
|
||||||
|
|
||||||
|
install-openocd-config:
|
||||||
|
rm $(OPENOCDPATH)/scripts/target/numicroM0.cfg && cp $(CHIBIOS_CONTRIB)/ext/numicroM0.cfg $(OPENOCDPATH)/scripts/target/
|
||||||
|
|
||||||
|
connect:
|
||||||
|
openocd -f ../scripts/interface/nulink.cfg -f ../scripts/target/numicroM0.cfg
|
||||||
|
|
||||||
|
flash: $(BUILDDIR)/$(PROJECT).elf
|
||||||
|
openocd -f ../scripts/interface/nulink.cfg -f ../scripts/target/numicroM0.cfg -c "program $< verify reset exit"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#
|
||||||
|
# Custom rules
|
||||||
|
##############################################################################
|
||||||
|
|
|
@ -0,0 +1,531 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2020 Alex Lewontin
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file templates/halconf.h
|
||||||
|
* @brief HAL configuration header.
|
||||||
|
* @details HAL configuration file, this file allows to enable or disable the
|
||||||
|
* various device drivers from your application. You may also use
|
||||||
|
* this file in order to override the device drivers default settings.
|
||||||
|
*
|
||||||
|
* @addtogroup HAL_CONF
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef HALCONF_H
|
||||||
|
#define HALCONF_H
|
||||||
|
|
||||||
|
#define _CHIBIOS_HAL_CONF_
|
||||||
|
#define _CHIBIOS_HAL_CONF_VER_7_1_
|
||||||
|
|
||||||
|
#include "mcuconf.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the PAL subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_PAL TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the ADC subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_ADC FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the CAN subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_CAN FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the cryptographic subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_CRY FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the DAC subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_DAC FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the EFlash subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_EFL FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the GPT subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_GPT FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the I2C subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_I2C FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the I2S subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_I2S FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the ICU subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_ICU FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the MAC subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_MAC FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the MMC_SPI subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_MMC_SPI FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the PWM subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_PWM FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the RTC subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_RTC FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the SDC subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_SDC FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the SERIAL subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_SERIAL FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the SERIAL over USB subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_SERIAL_USB FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the SIO subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_SIO FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the SPI subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_SPI FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the TRNG subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_TRNG FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the UART subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_UART FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the USB subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_USB FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the WDG subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_WDG FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the WSPI subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_WSPI FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* PAL driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables synchronous APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
|
||||||
|
#define PAL_USE_CALLBACKS FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables synchronous APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
|
||||||
|
#define PAL_USE_WAIT FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* ADC driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables synchronous APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
|
||||||
|
#define ADC_USE_WAIT TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||||
|
#define ADC_USE_MUTUAL_EXCLUSION TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* CAN driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sleep mode related APIs inclusion switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
|
||||||
|
#define CAN_USE_SLEEP_MODE TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
|
||||||
|
*/
|
||||||
|
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
|
||||||
|
#define CAN_ENFORCE_USE_CALLBACKS FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* CRY driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the SW fall-back of the cryptographic driver.
|
||||||
|
* @details When enabled, this option, activates a fall-back software
|
||||||
|
* implementation for algorithms not supported by the underlying
|
||||||
|
* hardware.
|
||||||
|
* @note Fall-back implementations may not be present for all algorithms.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_CRY_USE_FALLBACK FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Makes the driver forcibly use the fall-back implementations.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_CRY_ENFORCE_FALLBACK FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* DAC driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables synchronous APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
|
||||||
|
#define DAC_USE_WAIT TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||||
|
#define DAC_USE_MUTUAL_EXCLUSION TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* I2C driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the mutual exclusion APIs on the I2C bus.
|
||||||
|
*/
|
||||||
|
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||||
|
#define I2C_USE_MUTUAL_EXCLUSION TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* MAC driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the zero-copy API.
|
||||||
|
*/
|
||||||
|
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
|
||||||
|
#define MAC_USE_ZERO_COPY FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables an event sources for incoming packets.
|
||||||
|
*/
|
||||||
|
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
|
||||||
|
#define MAC_USE_EVENTS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* MMC_SPI driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Delays insertions.
|
||||||
|
* @details If enabled this options inserts delays into the MMC waiting
|
||||||
|
* routines releasing some extra CPU time for the threads with
|
||||||
|
* lower priority, this may slow down the driver a bit however.
|
||||||
|
* This option is recommended also if the SPI driver does not
|
||||||
|
* use a DMA channel and heavily loads the CPU.
|
||||||
|
*/
|
||||||
|
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||||
|
#define MMC_NICE_WAITING TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* SDC driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of initialization attempts before rejecting the card.
|
||||||
|
* @note Attempts are performed at 10mS intervals.
|
||||||
|
*/
|
||||||
|
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
|
||||||
|
#define SDC_INIT_RETRY 100
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Include support for MMC cards.
|
||||||
|
* @note MMC support is not yet implemented so this option must be kept
|
||||||
|
* at @p FALSE.
|
||||||
|
*/
|
||||||
|
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
|
||||||
|
#define SDC_MMC_SUPPORT FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Delays insertions.
|
||||||
|
* @details If enabled this options inserts delays into the MMC waiting
|
||||||
|
* routines releasing some extra CPU time for the threads with
|
||||||
|
* lower priority, this may slow down the driver a bit however.
|
||||||
|
*/
|
||||||
|
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||||
|
#define SDC_NICE_WAITING TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief OCR initialization constant for V20 cards.
|
||||||
|
*/
|
||||||
|
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
|
||||||
|
#define SDC_INIT_OCR_V20 0x50FF8000U
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief OCR initialization constant for non-V20 cards.
|
||||||
|
*/
|
||||||
|
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
|
||||||
|
#define SDC_INIT_OCR 0x80100000U
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* SERIAL driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Default bit rate.
|
||||||
|
* @details Configuration parameter, this is the baud rate selected for the
|
||||||
|
* default configuration.
|
||||||
|
*/
|
||||||
|
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
|
||||||
|
#define SERIAL_DEFAULT_BITRATE 38400
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Serial buffers size.
|
||||||
|
* @details Configuration parameter, you can change the depth of the queue
|
||||||
|
* buffers depending on the requirements of your application.
|
||||||
|
* @note The default is 16 bytes for both the transmission and receive
|
||||||
|
* buffers.
|
||||||
|
*/
|
||||||
|
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||||
|
#define SERIAL_BUFFERS_SIZE 32
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* SERIAL_USB driver related setting. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Serial over USB buffers size.
|
||||||
|
* @details Configuration parameter, the buffer size must be a multiple of
|
||||||
|
* the USB data endpoint maximum packet size.
|
||||||
|
* @note The default is 256 bytes for both the transmission and receive
|
||||||
|
* buffers.
|
||||||
|
*/
|
||||||
|
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||||
|
#define SERIAL_USB_BUFFERS_SIZE 256
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Serial over USB number of buffers.
|
||||||
|
* @note The default is 2 buffers.
|
||||||
|
*/
|
||||||
|
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
|
||||||
|
#define SERIAL_USB_BUFFERS_NUMBER 2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* SPI driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables synchronous APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
|
||||||
|
#define SPI_USE_WAIT TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables circular transfers APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
|
||||||
|
#define SPI_USE_CIRCULAR FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||||
|
#define SPI_USE_MUTUAL_EXCLUSION TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Handling method for SPI CS line.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
|
||||||
|
#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* UART driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables synchronous APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
|
||||||
|
#define UART_USE_WAIT FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||||
|
#define UART_USE_MUTUAL_EXCLUSION FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* USB driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables synchronous APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
|
||||||
|
#define USB_USE_WAIT FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* WSPI driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables synchronous APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
|
||||||
|
#define WSPI_USE_WAIT TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||||
|
#define WSPI_USE_MUTUAL_EXCLUSION TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* HALCONF_H */
|
||||||
|
|
||||||
|
/** @} */
|
|
@ -0,0 +1,34 @@
|
||||||
|
/*
|
||||||
|
Copyright (C) 2016 Stephane D'Alu
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _MCUCONF_H_
|
||||||
|
#define _MCUCONF_H_
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Board setting
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* HAL driver system settings.
|
||||||
|
*/
|
||||||
|
#define NUC123_HSE_ENABLED TRUE
|
||||||
|
#define NUC123_PLL_ENABLED TRUE
|
||||||
|
#define NUC123_PLLSRC NUC123_PLLSRC_HSE
|
||||||
|
#define NUC123_HCLKSRC NUC123_HCLKSRC_PLL
|
||||||
|
|
||||||
|
#define NUC123SD4AN0_MCUCONF
|
||||||
|
|
||||||
|
#endif /* _MCUCONF_H_ */
|
|
@ -0,0 +1,67 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file templates/halconf.h
|
||||||
|
* @brief Bare-metal OSAL configuration header.
|
||||||
|
*
|
||||||
|
* @addtogroup OSAL_CONF
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef OSALCONF_H
|
||||||
|
#define OSALCONF_H
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Frequency in Hertz of the system tick.
|
||||||
|
*/
|
||||||
|
#if !defined(OSAL_ST_FREQUENCY) || defined(__DOXYGEN__)
|
||||||
|
#define OSAL_ST_FREQUENCY 10000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables OSAL assertions.
|
||||||
|
*/
|
||||||
|
#if !defined(OSAL_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
|
||||||
|
#define OSAL_DBG_ENABLE_ASSERTS FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables OSAL functions parameters checks.
|
||||||
|
*/
|
||||||
|
#if !defined(OSAL_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
|
||||||
|
#define OSAL_DBG_ENABLE_CHECKS FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief OSAL initialization hook.
|
||||||
|
*/
|
||||||
|
#if !defined(OSAL_INIT_HOOK) || defined(__DOXYGEN__)
|
||||||
|
#define OSAL_INIT_HOOK() { \
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Idle loop hook macro.
|
||||||
|
*/
|
||||||
|
#if !defined(OSAL_IDLE_HOOK) || defined(__DOXYGEN__)
|
||||||
|
#define OSAL_IDLE_HOOK() { \
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* OSALCONF_H */
|
||||||
|
|
||||||
|
/** @} */
|
|
@ -0,0 +1,46 @@
|
||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2020 Alex Lewontin
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "hal.h"
|
||||||
|
|
||||||
|
uint8_t buf;
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Application entry point.
|
||||||
|
*/
|
||||||
|
int main(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
/*
|
||||||
|
* System initializations.
|
||||||
|
* - HAL initialization, this also initializes the configured device drivers
|
||||||
|
* and performs the board-specific initializations.
|
||||||
|
*/
|
||||||
|
|
||||||
|
halInit();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Enabling interrupts, initialization done.
|
||||||
|
*/
|
||||||
|
osalSysEnable();
|
||||||
|
|
||||||
|
|
||||||
|
while (true) {
|
||||||
|
OnboardLED_Toggle();
|
||||||
|
osalThreadSleepMilliseconds(1000);
|
||||||
|
}
|
||||||
|
}
|
|
@ -0,0 +1,23 @@
|
||||||
|
*****************************************************************************
|
||||||
|
** ChibiOS/HAL - USB driver demo for NUC123. **
|
||||||
|
*****************************************************************************
|
||||||
|
|
||||||
|
** TARGET **
|
||||||
|
|
||||||
|
The demo runs on a NUTINY-SDK-NUC123-V2.0 board with a NUC123SD4AN0 MCU.
|
||||||
|
|
||||||
|
** The Demo **
|
||||||
|
|
||||||
|
The application demonstrates the use of the NUC123 platform driver, and a little
|
||||||
|
bit of the PAL. A successful run of the test involves the on-board LED blinking at .5 Hz
|
||||||
|
(on for 1 second, then off for one second).
|
||||||
|
|
||||||
|
|
||||||
|
** Board Setup **
|
||||||
|
|
||||||
|
- None
|
||||||
|
|
||||||
|
** Build Procedure **
|
||||||
|
|
||||||
|
The demo has been tested using gcc version 9.3.1 (GNU Arm Embedded Toolchain 9-2020-q2-update).
|
||||||
|
Just modify the TRGT line in the makefile in order to use different GCC ports.
|
Loading…
Reference in New Issue