Rename otg -> usbfs
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3a51ec0bf3
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9dace8a9ce
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@ -26,7 +26,7 @@
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#define GD32_USBFS_H
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/**
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* @brief OTG_FS FIFO memory size in words.
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* @brief USBFS FIFO memory size in words.
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*/
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#define GD32_USBFS_FIFO_MEM_SIZE 320
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@ -45,7 +45,7 @@ typedef struct {
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volatile uint32_t resvd14;
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volatile uint32_t resvd18;
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volatile uint32_t resvd1c;
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} gd32_otg_host_chn_t;
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} gd32_usbfs_host_chn_t;
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/**
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* @brief Device input endpoint registers group.
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@ -63,7 +63,7 @@ typedef struct {
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volatile uint32_t DTXFSTS; /**< @brief Device IN endpoint transmit FIFO
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status register. */
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volatile uint32_t resvd1C;
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} gd32_otg_in_ep_t;
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} gd32_usbfs_in_ep_t;
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/**
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* @brief Device output endpoint registers group.
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@ -80,7 +80,7 @@ typedef struct {
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volatile uint32_t resvd14;
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volatile uint32_t resvd18;
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volatile uint32_t resvd1C;
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} gd32_otg_out_ep_t;
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} gd32_usbfs_out_ep_t;
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/**
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* @brief USB registers memory map.
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@ -127,7 +127,7 @@ typedef struct {
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volatile uint32_t HPRT; /**< @brief Host port control and status
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register. */
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volatile uint32_t resvd444[47];
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gd32_otg_host_chn_t hc[16]; /**< @brief Host channels array. */
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gd32_usbfs_host_chn_t hc[16]; /**< @brief Host channels array. */
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volatile uint32_t resvd700[64];
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volatile uint32_t DCFG; /**< @brief Device configuration register. */
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volatile uint32_t DCTL; /**< @brief Device control register. */
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@ -155,14 +155,14 @@ typedef struct {
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volatile uint32_t resvd840[16];
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volatile uint32_t resvd880[16];
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volatile uint32_t resvd8C0[16];
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gd32_otg_in_ep_t ie[16]; /**< @brief Input endpoints. */
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gd32_otg_out_ep_t oe[16]; /**< @brief Output endpoints. */
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gd32_usbfs_in_ep_t ie[16]; /**< @brief Input endpoints. */
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gd32_usbfs_out_ep_t oe[16]; /**< @brief Output endpoints. */
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volatile uint32_t resvdD00[64];
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volatile uint32_t PCGCCTL; /**< @brief Power and clock gating control
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register. */
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volatile uint32_t resvdE04[127];
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volatile uint32_t FIFO[16][1024];
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} gd32_otg_t;
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} gd32_usbfs_t;
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/**
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* @name GOTGCS register bit definitions
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@ -892,12 +892,12 @@ typedef struct {
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#define PCGCCTL_STPPCLK (1U<<0) /**< Stop PCLK. */
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/** @} */
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#define OTG_FS_ADDR 0x50000000
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#define USBFS_ADDR 0x50000000
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/**
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* @brief Accesses to the OTG_FS registers block.
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* @brief Accesses to the USBFS registers block.
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*/
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#define OTG_FS ((gd32_otg_t *)OTG_FS_ADDR)
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#define USBFS ((gd32_usbfs_t *)USBFS_ADDR)
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#endif /* GD32_USBFS_H */
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@ -39,7 +39,7 @@
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#define EP0_MAX_OUTSIZE 64
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#if GD32_USBFS_STEPPING == 1
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#if defined(BOARD_OTG_NOVBUSSENS)
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#if defined(BOARD_USBFS_NOVBUSSENS)
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#define GCCFG_INIT_VALUE (GCCFG_NOVBUSSENS | GCCFG_VBUSASEN | \
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GCCFG_VBUSBSEN | GCCFG_PWRDWN)
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#else
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@ -48,7 +48,7 @@
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#endif
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#elif GD32_USBFS_STEPPING == 2
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#if defined(BOARD_OTG_NOVBUSSENS)
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#if defined(BOARD_USBFS_NOVBUSSENS)
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#define GCCFG_INIT_VALUE GCCFG_PWRDWN
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#else
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#define GCCFG_INIT_VALUE (GCCFG_VBDEN | GCCFG_PWRDWN)
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@ -60,7 +60,7 @@
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief OTG_FS driver identifier.*/
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/** @brief USBFS driver identifier.*/
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#if GD32_USB_USE_USBFS || defined(__DOXYGEN__)
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USBDriver USBD1;
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#endif
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@ -107,7 +107,7 @@ static const USBEndpointConfig ep0config = {
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};
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#if GD32_USB_USE_USBFS
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static const gd32_otg_params_t fsparams = {
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static const gd32_usbfs_params_t fsparams = {
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GD32_USB_USBFS_RX_FIFO_SIZE / 4,
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GD32_USBFS_FIFO_MEM_SIZE,
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GD32_USBFS_ENDPOINTS
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@ -119,7 +119,7 @@ static const gd32_otg_params_t fsparams = {
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/*===========================================================================*/
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static void otg_core_reset(USBDriver *usbp) {
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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/* Wait AHB idle condition.*/
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while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0)
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@ -139,7 +139,7 @@ static void otg_core_reset(USBDriver *usbp) {
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}
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static void otg_disable_ep(USBDriver *usbp) {
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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unsigned i;
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for (i = 0; i <= usbp->otgparams->num_endpoints; i++) {
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@ -159,7 +159,7 @@ static void otg_disable_ep(USBDriver *usbp) {
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}
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static void otg_rxfifo_flush(USBDriver *usbp) {
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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otgp->GRSTCTL = GRSTCTL_RXFFLSH;
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while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0)
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@ -169,7 +169,7 @@ static void otg_rxfifo_flush(USBDriver *usbp) {
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}
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static void otg_txfifo_flush(USBDriver *usbp, uint32_t fifo) {
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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otgp->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH;
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while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0)
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@ -204,7 +204,7 @@ static uint32_t otg_ram_alloc(USBDriver *usbp, size_t size) {
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next = usbp->pmnext;
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usbp->pmnext += size;
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osalDbgAssert(usbp->pmnext <= usbp->otgparams->otg_ram_size,
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"OTG FIFO memory overflow");
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"USBFS FIFO memory overflow");
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return next;
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}
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@ -337,9 +337,9 @@ static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
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return false;
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// TODO Enable again or keep brute force?
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/*#if GD32_USB_OTGFIFO_FILL_BASEPRI
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/*#if GD32_USB_USBFSFIFO_FILL_BASEPRI
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uint8_t threshold_old = eclic_get_mth();
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eclic_set_mth(GD32_USB_OTGFIFO_FILL_BASEPRI);
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eclic_set_mth(GD32_USB_USBFSFIFO_FILL_BASEPRI);
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#endif*/
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osalSysLockFromISR();
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otg_fifo_write_from_buffer(usbp->otg->FIFO[ep],
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@ -348,7 +348,7 @@ static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
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usbp->epc[ep]->in_state->txbuf += n;
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usbp->epc[ep]->in_state->txcnt += n;
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osalSysUnlockFromISR();
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/*#if GD32_USB_OTGFIFO_FILL_BASEPRI
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/*#if GD32_USB_USBFSFIFO_FILL_BASEPRI
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eclic_set_mth(threshold_old);
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#endif*/
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}
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@ -363,7 +363,7 @@ static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
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* @notapi
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*/
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static void otg_epin_handler(USBDriver *usbp, usbep_t ep) {
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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uint32_t epint = otgp->ie[ep].DIEPINT;
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otgp->ie[ep].DIEPINT = epint;
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@ -406,7 +406,7 @@ static void otg_epin_handler(USBDriver *usbp, usbep_t ep) {
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* @notapi
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*/
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static void otg_epout_handler(USBDriver *usbp, usbep_t ep) {
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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uint32_t epint = otgp->oe[ep].DOEPINT;
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/* Resets all EP IRQ sources.*/
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@ -464,7 +464,7 @@ static void otg_epout_handler(USBDriver *usbp, usbep_t ep) {
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*/
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static void otg_isoc_in_failed_handler(USBDriver *usbp) {
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usbep_t ep;
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
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if (((otgp->ie[ep].DIEPCTL & DIEPCTL_EPTYP_MASK) == DIEPCTL_EPTYP_ISO) &&
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@ -496,7 +496,7 @@ static void otg_isoc_in_failed_handler(USBDriver *usbp) {
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*/
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static void otg_isoc_out_failed_handler(USBDriver *usbp) {
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usbep_t ep;
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) {
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if (((otgp->oe[ep].DOEPCTL & DOEPCTL_EPTYP_MASK) == DOEPCTL_EPTYP_ISO) &&
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@ -514,14 +514,14 @@ static void otg_isoc_out_failed_handler(USBDriver *usbp) {
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}
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/**
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* @brief OTG shared ISR.
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* @brief USBFS shared ISR.
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*
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* @param[in] usbp pointer to the @p USBDriver object
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*
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* @notapi
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*/
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static void usb_lld_serve_interrupt(USBDriver *usbp) {
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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uint32_t sts, src;
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sts = otgp->GINTF;
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@ -652,13 +652,13 @@ void usb_lld_init(void) {
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/* Driver initialization.*/
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usbObjectInit(&USBD1);
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USBD1.otg = OTG_FS;
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USBD1.otg = USBFS;
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USBD1.otgparams = &fsparams;
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}
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/**
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* @brief Configures and activates the USB peripheral.
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* @note Starting the OTG cell can be a slow operation carried out with
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* @note Starting the USBFS cell can be a slow operation carried out with
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* interrupts disabled, perform it before starting time-critical
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* operations.
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*
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@ -667,15 +667,15 @@ void usb_lld_init(void) {
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* @notapi
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*/
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void usb_lld_start(USBDriver *usbp) {
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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if (usbp->state == USB_STOP) {
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/* Clock activation.*/
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if (&USBD1 == usbp) {
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/* OTG FS clock enable and reset.*/
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rccEnableOTG_FS(true);
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rccResetOTG_FS();
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/* USBFS clock enable and reset.*/
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rccEnableUSBFS(true);
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rccResetUSBFS();
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/* Enables IRQ vector.*/
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eclicEnableVector(GD32_USBFS_NUMBER, GD32_USB_USBFS_IRQ_PRIORITY, GD32_USB_USBFS_IRQ_TRIGGER);
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@ -737,7 +737,7 @@ void usb_lld_start(USBDriver *usbp) {
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* @notapi
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*/
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void usb_lld_stop(USBDriver *usbp) {
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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/* If in ready state then disables the USB clock.*/
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if (usbp->state != USB_STOP) {
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@ -752,7 +752,7 @@ void usb_lld_stop(USBDriver *usbp) {
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if (&USBD1 == usbp) {
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eclicDisableVector(GD32_USBFS_NUMBER);
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rccDisableOTG_FS();
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rccDisableUSBFS();
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}
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}
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}
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@ -766,7 +766,7 @@ void usb_lld_stop(USBDriver *usbp) {
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*/
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void usb_lld_reset(USBDriver *usbp) {
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unsigned i;
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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/* Flush the Tx FIFO.*/
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otg_txfifo_flush(usbp, 0);
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@ -819,7 +819,7 @@ void usb_lld_reset(USBDriver *usbp) {
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* @notapi
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*/
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void usb_lld_set_address(USBDriver *usbp) {
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(usbp->address);
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}
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@ -834,7 +834,7 @@ void usb_lld_set_address(USBDriver *usbp) {
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*/
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void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
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uint32_t ctl, fsize;
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gd32_otg_t *otgp = usbp->otg;
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gd32_usbfs_t *otgp = usbp->otg;
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/* IN and OUT common parameters.*/
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switch (usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) {
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@ -54,7 +54,7 @@
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/**
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* @brief USBFS driver enable switch.
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* @details If set to @p TRUE the support for OTG_FS is included.
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* @details If set to @p TRUE the support for USBFS is included.
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* @note The default is @p FALSE
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*/
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#if !defined(GD32_USB_USE_USBFS) || defined(__DOXYGEN__)
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* @brief Exception priority level during TXFIFOs operations.
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* @note Because an undocumented silicon behavior the operation of
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* copying a packet into a TXFIFO must not be interrupted by
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* any other operation on the OTG peripheral.
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* any other operation on the USBFS peripheral.
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* This parameter represents the priority mask during copy
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* operations. The default value only allows to call USB
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* functions from callbacks invoked from USB ISR handlers.
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* functions is only safe from thread level or from USB
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* callbacks.
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*/
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#if !defined(GD32_USB_OTGFIFO_FILL_BASEPRI) || defined(__DOXYGEN__)
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#define GD32_USB_OTGFIFO_FILL_BASEPRI 0
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#if !defined(GD32_USB_USBFSFIFO_FILL_BASEPRI) || defined(__DOXYGEN__)
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#define GD32_USB_USBFSFIFO_FILL_BASEPRI 0
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#endif
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/**
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@ -175,7 +175,7 @@ typedef struct {
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uint32_t rx_fifo_size;
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uint32_t otg_ram_size;
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uint32_t num_endpoints;
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} gd32_otg_params_t;
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} gd32_usbfs_params_t;
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/**
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* @brief Type of an IN endpoint state structure.
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@ -408,13 +408,13 @@ struct USBDriver {
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#endif
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/* End of the mandatory fields.*/
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/**
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* @brief Pointer to the OTG peripheral associated to this driver.
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* @brief Pointer to the USBFS peripheral associated to this driver.
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*/
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gd32_otg_t *otg;
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gd32_usbfs_t *otg;
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/**
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* @brief Peripheral-specific parameters.
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*/
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const gd32_otg_params_t *otgparams;
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const gd32_usbfs_params_t *otgparams;
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/**
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* @brief Pointer to the next address in the packet memory.
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*/
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@ -495,27 +495,27 @@
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* @{
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*/
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/**
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* @brief Enables the OTG_FS peripheral clock.
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* @brief Enables the USBFS peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableOTG_FS(lp) rccEnableAHB(RCC_AHBENR_OTGFSEN, lp)
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#define rccEnableUSBFS(lp) rccEnableAHB(RCC_AHBENR_OTGFSEN, lp)
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/**
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* @brief Disables the OTG_FS peripheral clock.
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* @brief Disables the USBFS peripheral clock.
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*
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* @api
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*/
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#define rccDisableOTG_FS() rccDisableAHB(RCC_AHBENR_OTGFSEN)
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#define rccDisableUSBFS() rccDisableAHB(RCC_AHBENR_OTGFSEN)
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/**
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* @brief Resets the OTG_FS peripheral.
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* @brief Resets the USBFS peripheral.
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*
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* @api
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*/
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#define rccResetOTG_FS() rccResetAHB(RCC_AHBRSTR_OTGFSRST)
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#define rccResetUSBFS() rccResetAHB(RCC_AHBRSTR_OTGFSRST)
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/** @} */
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/**
|
||||
|
|
|
@ -762,7 +762,7 @@ typedef struct
|
|||
|
||||
|
||||
/*!< USB registers base address */
|
||||
#define USB_OTG_FS_PERIPH_BASE 0x50000000U
|
||||
#define USB_USBFS_PERIPH_BASE 0x50000000U
|
||||
|
||||
#define USB_OTG_GLOBAL_BASE 0x00000000U
|
||||
#define USB_OTG_DEVICE_BASE 0x00000800U
|
||||
|
@ -842,7 +842,7 @@ typedef struct
|
|||
#define OB ((OB_TypeDef *)OB_BASE)
|
||||
#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
|
||||
|
||||
#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *)USB_OTG_FS_PERIPH_BASE)
|
||||
#define USB_USBFS ((USB_OTG_GlobalTypeDef *)USB_USBFS_PERIPH_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
@ -14211,7 +14211,7 @@ typedef struct
|
|||
|
||||
|
||||
/****************************** USB Instances ********************************/
|
||||
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
|
||||
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_USBFS)
|
||||
|
||||
|
||||
#define RCC_HSE_MIN 3000000U
|
||||
|
@ -14237,8 +14237,8 @@ typedef struct
|
|||
#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
|
||||
#define USB_HP_IRQn CAN1_TX_IRQn
|
||||
#define DMA1_Channel3_5_IRQn DMA1_Channel3_IRQn
|
||||
#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
|
||||
#define CEC_IRQn OTG_FS_WKUP_IRQn
|
||||
#define USBWakeUp_IRQn USBFS_WKUP_IRQn
|
||||
#define CEC_IRQn USBFS_WKUP_IRQn
|
||||
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
|
||||
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
|
||||
#define TIM9_IRQn TIM1_BRK_IRQn
|
||||
|
@ -14258,8 +14258,8 @@ typedef struct
|
|||
#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
|
||||
#define USB_HP_IRQHandler CAN1_TX_IRQHandler
|
||||
#define DMA1_Channel3_5_IRQHandler DMA1_Channel3_IRQHandler
|
||||
#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
|
||||
#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
|
||||
#define USBWakeUp_IRQHandler USBFS_WKUP_IRQHandler
|
||||
#define CEC_IRQHandler USBFS_WKUP_IRQHandler
|
||||
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
|
||||
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
|
||||
|
|
Loading…
Reference in New Issue