Updated i2c_lld to use TivaWare.
This commit is contained in:
parent
f66996bd7d
commit
9fd36443b4
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@ -109,6 +109,7 @@ typedef int IRQn_Type;
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#include "inc/hw_gpio.h"
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#include "inc/hw_gpio.h"
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#include "inc/hw_uart.h"
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#include "inc/hw_uart.h"
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#include "inc/hw_timer.h"
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#include "inc/hw_timer.h"
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#include "inc/hw_i2c.h"
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#if CORTEX_NUM_VECTORS != ((((NUM_INTERRUPTS - 16) + 7) / 8) * 8)
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#if CORTEX_NUM_VECTORS != ((((NUM_INTERRUPTS - 16) + 7) / 8) * 8)
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#error "TivaWare NUM_INTERRUPTS mismatch"
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#error "TivaWare NUM_INTERRUPTS mismatch"
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@ -94,6 +94,7 @@ typedef int IRQn_Type;
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#include "inc/hw_uart.h"
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#include "inc/hw_uart.h"
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#include "inc/hw_timer.h"
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#include "inc/hw_timer.h"
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#include "inc/hw_emac.h"
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#include "inc/hw_emac.h"
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#include "inc/hw_i2c.h"
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#if CORTEX_NUM_VECTORS != ((((NUM_INTERRUPTS - 16) + 7) / 8) * 8)
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#if CORTEX_NUM_VECTORS != ((((NUM_INTERRUPTS - 16) + 7) / 8) * 8)
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#error "TivaWare NUM_INTERRUPTS mismatch"
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#error "TivaWare NUM_INTERRUPTS mismatch"
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@ -125,14 +125,14 @@ I2CDriver I2CD10;
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*/
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*/
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static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
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static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
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{
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{
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I2C_TypeDef *dp = i2cp->i2c;
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uint32_t i2c = i2cp->i2c;
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uint32_t status;
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uint32_t status;
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// clear MIS bit in MICR by writing 1
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// clear MIS bit in MICR by writing 1
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dp->MICR = 1;
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HWREG(i2c + I2C_O_MICR) = 1;
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// read interrupt status
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// read interrupt status
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status = dp->MCS;
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status = HWREG(i2c + I2C_O_MCS);
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if (status & TIVA_MCS_ERROR) {
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if (status & TIVA_MCS_ERROR) {
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i2cp->errors |= I2C_BUS_ERROR;
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i2cp->errors |= I2C_BUS_ERROR;
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@ -152,11 +152,11 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
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if (i2cp->txbytes == 1) {
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if (i2cp->txbytes == 1) {
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i2cp->intstate = STATE_WRITE_FINAL;
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i2cp->intstate = STATE_WRITE_FINAL;
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}
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}
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dp->MDR = *(i2cp->txbuf);
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HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf);
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i2cp->txbuf++;
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i2cp->txbuf++;
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i2cp->txbytes--;
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i2cp->txbytes--;
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// start transmission
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// start transmission
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dp->MCS = TIVA_I2C_BURST_SEND_CONTINUE;
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HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_CONTINUE;
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break;
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break;
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}
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}
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case STATE_WRITE_FINAL: {
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case STATE_WRITE_FINAL: {
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@ -169,12 +169,12 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
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else {
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else {
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i2cp->intstate = STATE_READ_FIRST;
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i2cp->intstate = STATE_READ_FIRST;
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}
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}
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dp->MDR = *(i2cp->txbuf);
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HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf);
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i2cp->txbuf++;
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i2cp->txbuf++;
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// txbytes - 1
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// txbytes - 1
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i2cp->txbytes--;
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i2cp->txbytes--;
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// start transmission
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// start transmission
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dp->MCS = TIVA_I2C_BURST_SEND_FINISH;
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HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_FINISH;
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break;
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break;
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}
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}
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case STATE_WAIT_ACK: {
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case STATE_WAIT_ACK: {
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@ -189,10 +189,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
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i2cp->addr |= 1;
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i2cp->addr |= 1;
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// set slave address
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// set slave address
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dp->MSA = i2cp->addr;
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HWREG(i2c + I2C_O_MSA) = i2cp->addr;
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i2cp->rxbytes--;
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i2cp->rxbytes--;
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//start receiving
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//start receiving
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dp->MCS = TIVA_I2C_SINGLE_RECEIVE;
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HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SINGLE_RECEIVE;
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break;
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break;
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}
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}
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@ -208,10 +208,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
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i2cp->addr |= 1;
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i2cp->addr |= 1;
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// set slave address
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// set slave address
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dp->MSA = i2cp->addr;
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HWREG(i2c + I2C_O_MSA) = i2cp->addr;
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i2cp->rxbytes--;
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i2cp->rxbytes--;
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//start receiving
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//start receiving
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dp->MCS = TIVA_I2C_BURST_RECEIVE_START;
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HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_START;
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break;
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break;
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}
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}
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@ -219,27 +219,27 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
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if(i2cp->rxbytes == 2) {
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if(i2cp->rxbytes == 2) {
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i2cp->intstate = STATE_READ_FINAL;
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i2cp->intstate = STATE_READ_FINAL;
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}
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}
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*(i2cp->rxbuf) = dp->MDR;
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*(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR);
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i2cp->rxbuf++;
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i2cp->rxbuf++;
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i2cp->rxbytes--;
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i2cp->rxbytes--;
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//start receiving
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//start receiving
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dp->MCS = TIVA_I2C_BURST_RECEIVE_CONTINUE;
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HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_CONTINUE;
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break;
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break;
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}
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}
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case STATE_READ_FINAL: {
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case STATE_READ_FINAL: {
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i2cp->intstate = STATE_READ_WAIT;
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i2cp->intstate = STATE_READ_WAIT;
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*(i2cp->rxbuf) = dp->MDR;
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*(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR);
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i2cp->rxbuf++;
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i2cp->rxbuf++;
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i2cp->rxbytes--;
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i2cp->rxbytes--;
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//start receiving
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//start receiving
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dp->MCS = TIVA_I2C_BURST_RECEIVE_FINISH;
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HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_FINISH;
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break;
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break;
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}
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}
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case STATE_READ_WAIT: {
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case STATE_READ_WAIT: {
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i2cp->intstate = STATE_IDLE;
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i2cp->intstate = STATE_IDLE;
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*(i2cp->rxbuf) = dp->MDR;
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*(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR);
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i2cp->rxbuf++;
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i2cp->rxbuf++;
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_i2c_wakeup_isr(i2cp);
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_i2c_wakeup_isr(i2cp);
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break;
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break;
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@ -430,61 +430,61 @@ void i2c_lld_init(void) {
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#if TIVA_I2C_USE_I2C0
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#if TIVA_I2C_USE_I2C0
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i2cObjectInit(&I2CD1);
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i2cObjectInit(&I2CD1);
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I2CD1.thread = NULL;
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I2CD1.thread = NULL;
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I2CD1.i2c = I2C0;
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I2CD1.i2c = I2C0_BASE;
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#endif /* TIVA_I2C_USE_I2C0 */
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#endif /* TIVA_I2C_USE_I2C0 */
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#if TIVA_I2C_USE_I2C1
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#if TIVA_I2C_USE_I2C1
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i2cObjectInit(&I2CD2);
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i2cObjectInit(&I2CD2);
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I2CD2.thread = NULL;
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I2CD2.thread = NULL;
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I2CD2.i2c = I2C1;
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I2CD2.i2c = I2C1_BASE;
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#endif /* TIVA_I2C_USE_I2C1 */
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#endif /* TIVA_I2C_USE_I2C1 */
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#if TIVA_I2C_USE_I2C2
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#if TIVA_I2C_USE_I2C2
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i2cObjectInit(&I2CD3);
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i2cObjectInit(&I2CD3);
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I2CD3.thread = NULL;
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I2CD3.thread = NULL;
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I2CD3.i2c = I2C2;
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I2CD3.i2c = I2C2_BASE;
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#endif /* TIVA_I2C_USE_I2C2 */
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#endif /* TIVA_I2C_USE_I2C2 */
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#if TIVA_I2C_USE_I2C3
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#if TIVA_I2C_USE_I2C3
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i2cObjectInit(&I2CD4);
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i2cObjectInit(&I2CD4);
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I2CD4.thread = NULL;
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I2CD4.thread = NULL;
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I2CD4.i2c = I2C3;
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I2CD4.i2c = I2C3_BASE;
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#endif /* TIVA_I2C_USE_I2C3 */
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#endif /* TIVA_I2C_USE_I2C3 */
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#if TIVA_I2C_USE_I2C4
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#if TIVA_I2C_USE_I2C4
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i2cObjectInit(&I2CD5);
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i2cObjectInit(&I2CD5);
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I2CD5.thread = NULL;
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I2CD5.thread = NULL;
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I2CD5.i2c = I2C4;
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I2CD5.i2c = I2C4_BASE;
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#endif /* TIVA_I2C_USE_I2C4 */
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#endif /* TIVA_I2C_USE_I2C4 */
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#if TIVA_I2C_USE_I2C5
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#if TIVA_I2C_USE_I2C5
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i2cObjectInit(&I2CD6);
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i2cObjectInit(&I2CD6);
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I2CD6.thread = NULL;
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I2CD6.thread = NULL;
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I2CD6.i2c = I2C5;
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I2CD6.i2c = I2C5_BASE;
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#endif /* TIVA_I2C_USE_I2C5 */
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#endif /* TIVA_I2C_USE_I2C5 */
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#if TIVA_I2C_USE_I2C6
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#if TIVA_I2C_USE_I2C6
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i2cObjectInit(&I2CD7);
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i2cObjectInit(&I2CD7);
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I2CD7.thread = NULL;
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I2CD7.thread = NULL;
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I2CD7.i2c = I2C6;
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I2CD7.i2c = I2C6_BASE;
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#endif /* TIVA_I2C_USE_I2C6 */
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#endif /* TIVA_I2C_USE_I2C6 */
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#if TIVA_I2C_USE_I2C7
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#if TIVA_I2C_USE_I2C7
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i2cObjectInit(&I2CD8);
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i2cObjectInit(&I2CD8);
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I2CD8.thread = NULL;
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I2CD8.thread = NULL;
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I2CD8.i2c = I2C7;
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I2CD8.i2c = I2C7_BASE;
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#endif /* TIVA_I2C_USE_I2C7 */
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#endif /* TIVA_I2C_USE_I2C7 */
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#if TIVA_I2C_USE_I2C8
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#if TIVA_I2C_USE_I2C8
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i2cObjectInit(&I2CD9);
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i2cObjectInit(&I2CD9);
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I2CD9.thread = NULL;
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I2CD9.thread = NULL;
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I2CD9.i2c = I2C8;
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I2CD9.i2c = I2C8_BASE;
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#endif /* TIVA_I2C_USE_I2C8 */
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#endif /* TIVA_I2C_USE_I2C8 */
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#if TIVA_I2C_USE_I2C9
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#if TIVA_I2C_USE_I2C9
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i2cObjectInit(&I2CD10);
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i2cObjectInit(&I2CD10);
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I2CD10.thread = NULL;
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I2CD10.thread = NULL;
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I2CD10.i2c = I2C9;
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I2CD10.i2c = I2C9_BASE;
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#endif /* TIVA_I2C_USE_I2C9 */
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#endif /* TIVA_I2C_USE_I2C9 */
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}
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}
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@ -497,15 +497,15 @@ void i2c_lld_init(void) {
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*/
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*/
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void i2c_lld_start(I2CDriver *i2cp)
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void i2c_lld_start(I2CDriver *i2cp)
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{
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{
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I2C_TypeDef *dp = i2cp->i2c;
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uint32_t i2c = i2cp->i2c;
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/* If in stopped state then enables the I2C clocks.*/
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/* If in stopped state then enables the I2C clocks.*/
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if (i2cp->state == I2C_STOP) {
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if (i2cp->state == I2C_STOP) {
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#if TIVA_I2C_USE_I2C0
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#if TIVA_I2C_USE_I2C0
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if (&I2CD1 == i2cp) {
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if (&I2CD1 == i2cp) {
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SYSCTL->RCGCI2C |= (1 << 0);
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HWREG(SYSCTL_RCGCI2C) |= (1 << 0);
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while (!(SYSCTL->PRI2C & (1 << 0)))
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while (!(HWREG(SYSCTL_PRI2C) & (1 << 0)))
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;
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;
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nvicEnableVector(TIVA_I2C0_NUMBER, TIVA_I2C_I2C0_IRQ_PRIORITY);
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nvicEnableVector(TIVA_I2C0_NUMBER, TIVA_I2C_I2C0_IRQ_PRIORITY);
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@ -514,9 +514,9 @@ void i2c_lld_start(I2CDriver *i2cp)
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#if TIVA_I2C_USE_I2C1
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#if TIVA_I2C_USE_I2C1
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if (&I2CD2 == i2cp) {
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if (&I2CD2 == i2cp) {
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SYSCTL->RCGCI2C |= (1 << 1);
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HWREG(SYSCTL_RCGCI2C) |= (1 << 1);
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while (!(SYSCTL->PRI2C & (1 << 1)))
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while (!(HWREG(SYSCTL_PRI2C) & (1 << 1)))
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;
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;
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nvicEnableVector(TIVA_I2C1_NUMBER, TIVA_I2C_I2C1_IRQ_PRIORITY);
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nvicEnableVector(TIVA_I2C1_NUMBER, TIVA_I2C_I2C1_IRQ_PRIORITY);
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@ -525,9 +525,9 @@ void i2c_lld_start(I2CDriver *i2cp)
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#if TIVA_I2C_USE_I2C2
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#if TIVA_I2C_USE_I2C2
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if (&I2CD3 == i2cp) {
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if (&I2CD3 == i2cp) {
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SYSCTL->RCGCI2C |= (1 << 2);
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HWREG(SYSCTL_RCGCI2C) |= (1 << 2);
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while (!(SYSCTL->PRI2C & (1 << 2)))
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while (!(HWREG(SYSCTL_PRI2C) & (1 << 2)))
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;
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;
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nvicEnableVector(TIVA_I2C2_NUMBER, TIVA_I2C_I2C2_IRQ_PRIORITY);
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nvicEnableVector(TIVA_I2C2_NUMBER, TIVA_I2C_I2C2_IRQ_PRIORITY);
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@ -536,9 +536,9 @@ void i2c_lld_start(I2CDriver *i2cp)
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#if TIVA_I2C_USE_I2C3
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#if TIVA_I2C_USE_I2C3
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if (&I2CD4 == i2cp) {
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if (&I2CD4 == i2cp) {
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SYSCTL->RCGCI2C |= (1 << 3);
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HWREG(SYSCTL_RCGCI2C) |= (1 << 3);
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while (!(SYSCTL->PRI2C & (1 << 3)))
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while (!(HWREG(SYSCTL_PRI2C) & (1 << 3)))
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;
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;
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nvicEnableVector(TIVA_I2C3_NUMBER, TIVA_I2C_I2C3_IRQ_PRIORITY);
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nvicEnableVector(TIVA_I2C3_NUMBER, TIVA_I2C_I2C3_IRQ_PRIORITY);
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@ -547,9 +547,9 @@ void i2c_lld_start(I2CDriver *i2cp)
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#if TIVA_I2C_USE_I2C4
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#if TIVA_I2C_USE_I2C4
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if (&I2CD5 == i2cp) {
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if (&I2CD5 == i2cp) {
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SYSCTL->RCGCI2C |= (1 << 4);
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HWREG(SYSCTL_RCGCI2C) |= (1 << 4);
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while (!(SYSCTL->PRI2C & (1 << 4)))
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while (!(HWREG(SYSCTL_PRI2C) & (1 << 4)))
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;
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;
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nvicEnableVector(TIVA_I2C4_NUMBER, TIVA_I2C_I2C4_IRQ_PRIORITY);
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nvicEnableVector(TIVA_I2C4_NUMBER, TIVA_I2C_I2C4_IRQ_PRIORITY);
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@ -558,9 +558,9 @@ void i2c_lld_start(I2CDriver *i2cp)
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#if TIVA_I2C_USE_I2C5
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#if TIVA_I2C_USE_I2C5
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if (&I2CD6 == i2cp) {
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if (&I2CD6 == i2cp) {
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SYSCTL->RCGCI2C |= (1 << 5);
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HWREG(SYSCTL_RCGCI2C) |= (1 << 5);
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while (!(SYSCTL->PRI2C & (1 << 5)))
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while (!(HWREG(SYSCTL_PRI2C) & (1 << 5)))
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;
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;
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nvicEnableVector(TIVA_I2C5_NUMBER, TIVA_I2C_I2C5_IRQ_PRIORITY);
|
nvicEnableVector(TIVA_I2C5_NUMBER, TIVA_I2C_I2C5_IRQ_PRIORITY);
|
||||||
|
@ -569,9 +569,9 @@ void i2c_lld_start(I2CDriver *i2cp)
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C6
|
#if TIVA_I2C_USE_I2C6
|
||||||
if (&I2CD7 == i2cp) {
|
if (&I2CD7 == i2cp) {
|
||||||
SYSCTL->RCGCI2C |= (1 << 6);
|
HWREG(SYSCTL_RCGCI2C) |= (1 << 6);
|
||||||
|
|
||||||
while (!(SYSCTL->PRI2C & (1 << 6)))
|
while (!(HWREG(SYSCTL_PRI2C) & (1 << 6)))
|
||||||
;
|
;
|
||||||
|
|
||||||
nvicEnableVector(TIVA_I2C6_NUMBER, TIVA_I2C_I2C6_IRQ_PRIORITY);
|
nvicEnableVector(TIVA_I2C6_NUMBER, TIVA_I2C_I2C6_IRQ_PRIORITY);
|
||||||
|
@ -580,9 +580,9 @@ void i2c_lld_start(I2CDriver *i2cp)
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C7
|
#if TIVA_I2C_USE_I2C7
|
||||||
if (&I2CD8 == i2cp) {
|
if (&I2CD8 == i2cp) {
|
||||||
SYSCTL->RCGCI2C |= (1 << 7);
|
HWREG(SYSCTL_RCGCI2C) |= (1 << 7);
|
||||||
|
|
||||||
while (!(SYSCTL->PRI2C & (1 << 7)))
|
while (!(HWREG(SYSCTL_PRI2C) & (1 << 7)))
|
||||||
;
|
;
|
||||||
|
|
||||||
nvicEnableVector(TIVA_I2C7_NUMBER, TIVA_I2C_I2C7_IRQ_PRIORITY);
|
nvicEnableVector(TIVA_I2C7_NUMBER, TIVA_I2C_I2C7_IRQ_PRIORITY);
|
||||||
|
@ -591,9 +591,9 @@ void i2c_lld_start(I2CDriver *i2cp)
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C8
|
#if TIVA_I2C_USE_I2C8
|
||||||
if (&I2CD9 == i2cp) {
|
if (&I2CD9 == i2cp) {
|
||||||
SYSCTL->RCGCI2C |= (1 << 8);
|
HWREG(SYSCTL_RCGCI2C) |= (1 << 8);
|
||||||
|
|
||||||
while (!(SYSCTL->PRI2C & (1 << 8)))
|
while (!(HWREG(SYSCTL_PRI2C) & (1 << 8)))
|
||||||
;
|
;
|
||||||
|
|
||||||
nvicEnableVector(TIVA_I2C8_NUMBER, TIVA_I2C_I2C8_IRQ_PRIORITY);
|
nvicEnableVector(TIVA_I2C8_NUMBER, TIVA_I2C_I2C8_IRQ_PRIORITY);
|
||||||
|
@ -602,9 +602,9 @@ void i2c_lld_start(I2CDriver *i2cp)
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C9
|
#if TIVA_I2C_USE_I2C9
|
||||||
if (&I2CD10 == i2cp) {
|
if (&I2CD10 == i2cp) {
|
||||||
SYSCTL->RCGCI2C |= (1 << 9);
|
HWREG(SYSCTL_RCGCI2C) |= (1 << 9);
|
||||||
|
|
||||||
while (!(SYSCTL->PRI2C & (1 << 9)))
|
while (!(HWREG(SYSCTL_PRI2C) & (1 << 9)))
|
||||||
;
|
;
|
||||||
|
|
||||||
nvicEnableVector(TIVA_I2C9_NUMBER, TIVA_I2C_I2C9_IRQ_PRIORITY);
|
nvicEnableVector(TIVA_I2C9_NUMBER, TIVA_I2C_I2C9_IRQ_PRIORITY);
|
||||||
|
@ -612,8 +612,8 @@ void i2c_lld_start(I2CDriver *i2cp)
|
||||||
#endif /* TIVA_I2C_USE_I2C7 */
|
#endif /* TIVA_I2C_USE_I2C7 */
|
||||||
}
|
}
|
||||||
|
|
||||||
dp->MCR = 0x10;
|
HWREG(i2c + I2C_O_MCR) = 0x10;
|
||||||
dp->MTPR = MTPR_VALUE;
|
HWREG(i2c + I2C_O_MTPR) = MTPR_VALUE;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -625,7 +625,8 @@ void i2c_lld_start(I2CDriver *i2cp)
|
||||||
*/
|
*/
|
||||||
void i2c_lld_stop(I2CDriver *i2cp)
|
void i2c_lld_stop(I2CDriver *i2cp)
|
||||||
{
|
{
|
||||||
I2C_TypeDef *dp = i2cp->i2c;
|
uint32_t i2c = i2cp->i2c;
|
||||||
|
|
||||||
/* If not in stopped state then disables the I2C clock.*/
|
/* If not in stopped state then disables the I2C clock.*/
|
||||||
if (i2cp->state != I2C_STOP) {
|
if (i2cp->state != I2C_STOP) {
|
||||||
|
|
||||||
|
@ -635,76 +636,76 @@ void i2c_lld_stop(I2CDriver *i2cp)
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C0
|
#if TIVA_I2C_USE_I2C0
|
||||||
if (&I2CD1 == i2cp) {
|
if (&I2CD1 == i2cp) {
|
||||||
SYSCTL->RCGCI2C &= ~(1 << 0);
|
HWREG(SYSCTL_RCGCI2C) &= ~(1 << 0);
|
||||||
nvicDisableVector(TIVA_I2C0_NUMBER);
|
nvicDisableVector(TIVA_I2C0_NUMBER);
|
||||||
}
|
}
|
||||||
#endif /* TIVA_I2C_USE_I2C0 */
|
#endif /* TIVA_I2C_USE_I2C0 */
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C1
|
#if TIVA_I2C_USE_I2C1
|
||||||
if (&I2CD2 == i2cp) {
|
if (&I2CD2 == i2cp) {
|
||||||
SYSCTL->RCGCI2C &= ~(1 << 1);
|
HWREG(SYSCTL_RCGCI2C) &= ~(1 << 1);
|
||||||
nvicDisableVector(TIVA_I2C1_NUMBER);
|
nvicDisableVector(TIVA_I2C1_NUMBER);
|
||||||
}
|
}
|
||||||
#endif /* TIVA_I2C_USE_I2C1 */
|
#endif /* TIVA_I2C_USE_I2C1 */
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C2
|
#if TIVA_I2C_USE_I2C2
|
||||||
if (&I2CD3 == i2cp) {
|
if (&I2CD3 == i2cp) {
|
||||||
SYSCTL->RCGCI2C &= ~(1 << 2);
|
HWREG(SYSCTL_RCGCI2C) &= ~(1 << 2);
|
||||||
nvicDisableVector(TIVA_I2C2_NUMBER);
|
nvicDisableVector(TIVA_I2C2_NUMBER);
|
||||||
}
|
}
|
||||||
#endif /* TIVA_I2C_USE_I2C2 */
|
#endif /* TIVA_I2C_USE_I2C2 */
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C3
|
#if TIVA_I2C_USE_I2C3
|
||||||
if (&I2CD4 == i2cp) {
|
if (&I2CD4 == i2cp) {
|
||||||
SYSCTL->RCGCI2C &= ~(1 << 3);
|
HWREG(SYSCTL_RCGCI2C) &= ~(1 << 3);
|
||||||
nvicDisableVector(TIVA_I2C3_NUMBER);
|
nvicDisableVector(TIVA_I2C3_NUMBER);
|
||||||
}
|
}
|
||||||
#endif /* TIVA_I2C_USE_I2C3 */
|
#endif /* TIVA_I2C_USE_I2C3 */
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C4
|
#if TIVA_I2C_USE_I2C4
|
||||||
if (&I2CD5 == i2cp) {
|
if (&I2CD5 == i2cp) {
|
||||||
SYSCTL->RCGCI2C &= ~(1 << 4);
|
HWREG(SYSCTL_RCGCI2C) &= ~(1 << 4);
|
||||||
nvicDisableVector(TIVA_I2C4_NUMBER);
|
nvicDisableVector(TIVA_I2C4_NUMBER);
|
||||||
}
|
}
|
||||||
#endif /* TIVA_I2C_USE_I2C4 */
|
#endif /* TIVA_I2C_USE_I2C4 */
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C5
|
#if TIVA_I2C_USE_I2C5
|
||||||
if (&I2CD6 == i2cp) {
|
if (&I2CD6 == i2cp) {
|
||||||
SYSCTL->RCGCI2C &= ~(1 << 5);
|
HWREG(SYSCTL_RCGCI2C) &= ~(1 << 5);
|
||||||
nvicDisableVector(TIVA_I2C5_NUMBER);
|
nvicDisableVector(TIVA_I2C5_NUMBER);
|
||||||
}
|
}
|
||||||
#endif /* TIVA_I2C_USE_I2C5 */
|
#endif /* TIVA_I2C_USE_I2C5 */
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C6
|
#if TIVA_I2C_USE_I2C6
|
||||||
if (&I2CD7 == i2cp) {
|
if (&I2CD7 == i2cp) {
|
||||||
SYSCTL->RCGCI2C &= ~(1 << 6);
|
HWREG(SYSCTL_RCGCI2C) &= ~(1 << 6);
|
||||||
nvicDisableVector(TIVA_I2C6_NUMBER);
|
nvicDisableVector(TIVA_I2C6_NUMBER);
|
||||||
}
|
}
|
||||||
#endif /* TIVA_I2C_USE_I2C6 */
|
#endif /* TIVA_I2C_USE_I2C6 */
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C7
|
#if TIVA_I2C_USE_I2C7
|
||||||
if (&I2CD8 == i2cp) {
|
if (&I2CD8 == i2cp) {
|
||||||
SYSCTL->RCGCI2C &= ~(1 << 7);
|
HWREG(SYSCTL_RCGCI2C) &= ~(1 << 7);
|
||||||
nvicDisableVector(TIVA_I2C7_NUMBER);
|
nvicDisableVector(TIVA_I2C7_NUMBER);
|
||||||
}
|
}
|
||||||
#endif /* TIVA_I2C_USE_I2C7 */
|
#endif /* TIVA_I2C_USE_I2C7 */
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C8
|
#if TIVA_I2C_USE_I2C8
|
||||||
if (&I2CD9 == i2cp) {
|
if (&I2CD9 == i2cp) {
|
||||||
SYSCTL->RCGCI2C &= ~(1 << 8);
|
HWREG(SYSCTL_RCGCI2C) &= ~(1 << 8);
|
||||||
nvicDisableVector(TIVA_I2C8_NUMBER);
|
nvicDisableVector(TIVA_I2C8_NUMBER);
|
||||||
}
|
}
|
||||||
#endif /* TIVA_I2C_USE_I2C8 */
|
#endif /* TIVA_I2C_USE_I2C8 */
|
||||||
|
|
||||||
#if TIVA_I2C_USE_I2C9
|
#if TIVA_I2C_USE_I2C9
|
||||||
if (&I2CD10 == i2cp) {
|
if (&I2CD10 == i2cp) {
|
||||||
SYSCTL->RCGCI2C &= ~(1 << 9);
|
HWREG(SYSCTL_RCGCI2C) &= ~(1 << 9);
|
||||||
nvicDisableVector(TIVA_I2C9_NUMBER);
|
nvicDisableVector(TIVA_I2C9_NUMBER);
|
||||||
}
|
}
|
||||||
#endif /* TIVA_I2C_USE_I2C9 */
|
#endif /* TIVA_I2C_USE_I2C9 */
|
||||||
|
|
||||||
dp->MCR = 0;
|
HWREG(i2c + I2C_O_MCR) = 0;
|
||||||
dp->MTPR = 0;
|
HWREG(i2c + I2C_O_MTPR) = 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -733,7 +734,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
||||||
uint8_t *rxbuf, size_t rxbytes,
|
uint8_t *rxbuf, size_t rxbytes,
|
||||||
systime_t timeout)
|
systime_t timeout)
|
||||||
{
|
{
|
||||||
I2C_TypeDef *dp = i2cp->i2c;
|
uint32_t i2c = i2cp->i2c;
|
||||||
systime_t start, end;
|
systime_t start, end;
|
||||||
|
|
||||||
i2cp->rxbuf = rxbuf;
|
i2cp->rxbuf = rxbuf;
|
||||||
|
@ -759,7 +760,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
||||||
|
|
||||||
/* If the bus is not busy then the operation can continue, note, the
|
/* If the bus is not busy then the operation can continue, note, the
|
||||||
loop is exited in the locked state.*/
|
loop is exited in the locked state.*/
|
||||||
if ((dp->MCS & TIVA_MCS_BUSY) == 0)
|
if ((HWREG(i2c + I2C_O_MCS) & TIVA_MCS_BUSY) == 0)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
/* If the system time went outside the allowed window then a timeout
|
/* If the system time went outside the allowed window then a timeout
|
||||||
|
@ -771,10 +772,10 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
||||||
}
|
}
|
||||||
|
|
||||||
/* set slave address */
|
/* set slave address */
|
||||||
dp->MSA = addr;
|
HWREG(i2c + I2C_O_MSA) = addr;
|
||||||
|
|
||||||
/* Starts the operation.*/
|
/* Starts the operation.*/
|
||||||
dp->MCS = TIVA_I2C_SINGLE_RECEIVE;
|
HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SINGLE_RECEIVE;
|
||||||
|
|
||||||
/* Waits for the operation completion or a timeout.*/
|
/* Waits for the operation completion or a timeout.*/
|
||||||
return osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
|
return osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
|
||||||
|
@ -808,7 +809,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
||||||
uint8_t *rxbuf, size_t rxbytes,
|
uint8_t *rxbuf, size_t rxbytes,
|
||||||
systime_t timeout)
|
systime_t timeout)
|
||||||
{
|
{
|
||||||
I2C_TypeDef *dp = i2cp->i2c;
|
uint32_t i2c = i2cp->i2c;
|
||||||
systime_t start, end;
|
systime_t start, end;
|
||||||
|
|
||||||
i2cp->rxbuf = rxbuf;
|
i2cp->rxbuf = rxbuf;
|
||||||
|
@ -833,7 +834,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
||||||
|
|
||||||
/* If the bus is not busy then the operation can continue, note, the
|
/* If the bus is not busy then the operation can continue, note, the
|
||||||
loop is exited in the locked state.*/
|
loop is exited in the locked state.*/
|
||||||
if ((dp->MCS & TIVA_MCS_BUSY) == 0)
|
if ((HWREG(i2c + I2C_O_MCS) & TIVA_MCS_BUSY) == 0)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
/* If the system time went outside the allowed window then a timeout
|
/* If the system time went outside the allowed window then a timeout
|
||||||
|
@ -848,13 +849,13 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
||||||
i2cp->addr = addr << 1 | 0;
|
i2cp->addr = addr << 1 | 0;
|
||||||
|
|
||||||
/* set slave address */
|
/* set slave address */
|
||||||
dp->MSA = i2cp->addr;
|
HWREG(i2c + I2C_O_MSA) = i2cp->addr;
|
||||||
|
|
||||||
/* enable interrupts */
|
/* enable interrupts */
|
||||||
dp->MIMR = TIVA_MIMR_IM;
|
HWREG(i2c + I2C_O_MIMR) = TIVA_MIMR_IM;
|
||||||
|
|
||||||
/* put data in register */
|
/* put data in register */
|
||||||
dp->MDR = *(i2cp->txbuf);
|
HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf);
|
||||||
|
|
||||||
/* check if 1 or more bytes */
|
/* check if 1 or more bytes */
|
||||||
if (i2cp->txbytes == 1) {
|
if (i2cp->txbytes == 1) {
|
||||||
|
@ -867,7 +868,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
||||||
i2cp->intstate = STATE_READ_FIRST;
|
i2cp->intstate = STATE_READ_FIRST;
|
||||||
}
|
}
|
||||||
// single byte send
|
// single byte send
|
||||||
dp->MCS = TIVA_I2C_SIGNLE_SEND;
|
HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SIGNLE_SEND;
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
if (i2cp->txbytes == 2) {
|
if (i2cp->txbytes == 2) {
|
||||||
|
@ -879,7 +880,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
||||||
i2cp->intstate = STATE_WRITE_NEXT;
|
i2cp->intstate = STATE_WRITE_NEXT;
|
||||||
}
|
}
|
||||||
// multiple bytes start send
|
// multiple bytes start send
|
||||||
dp->MCS = TIVA_I2C_BURST_SEND_START;
|
HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_START;
|
||||||
}
|
}
|
||||||
|
|
||||||
i2cp->txbuf++;
|
i2cp->txbuf++;
|
||||||
|
|
|
@ -440,7 +440,7 @@ struct I2CDriver {
|
||||||
/**
|
/**
|
||||||
* @brief Pointer to the I2Cx registers block.
|
* @brief Pointer to the I2Cx registers block.
|
||||||
*/
|
*/
|
||||||
I2C_TypeDef *i2c;
|
uint32_t i2c;
|
||||||
};
|
};
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
|
Loading…
Reference in New Issue