diff --git a/os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.c b/os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.c
index 43489f26..b7e425fa 100644
--- a/os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.c
+++ b/os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.c
@@ -49,13 +49,13 @@ SerialDriver SD2;
 SerialDriver SD3;
 #endif
 
-/** @brief UART4 serial driver identifier.*/
-#if GD32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+/** @brief UART3 serial driver identifier.*/
+#if GD32_SERIAL_USE_UART3 || defined(__DOXYGEN__)
 SerialDriver SD4;
 #endif
 
-/** @brief UART5 serial driver identifier.*/
-#if GD32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+/** @brief UART4 serial driver identifier.*/
+#if GD32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
 SerialDriver SD5;
 #endif
 
@@ -231,19 +231,19 @@ static void notify3(io_queue_t *qp) {
 }
 #endif
 
-#if GD32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+#if GD32_SERIAL_USE_UART3 || defined(__DOXYGEN__)
 static void notify4(io_queue_t *qp) {
 
   (void)qp;
-  UART4->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
+  UART3->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
 }
 #endif
 
-#if GD32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+#if GD32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
 static void notify5(io_queue_t *qp) {
 
   (void)qp;
-  UART5->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
+  UART4->CTL0 |= USART_CTL0_TBEIE | USART_CTL0_TCIE;
 }
 #endif
 
@@ -308,6 +308,25 @@ OSAL_IRQ_HANDLER(GD32_USART2_HANDLER) {
 }
 #endif
 
+#if GD32_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+#if !defined(GD32_UART3_HANDLER)
+#error "GD32_UART3_HANDLER not defined"
+#endif
+/**
+ * @brief   UART3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_UART3_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
 #if GD32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
 #if !defined(GD32_UART4_HANDLER)
 #error "GD32_UART4_HANDLER not defined"
@@ -321,25 +340,6 @@ OSAL_IRQ_HANDLER(GD32_UART4_HANDLER) {
 
   OSAL_IRQ_PROLOGUE();
 
-  serve_interrupt(&SD4);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if GD32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
-#if !defined(GD32_UART5_HANDLER)
-#error "GD32_UART5_HANDLER not defined"
-#endif
-/**
- * @brief   UART5 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(GD32_UART5_HANDLER) {
-
-  OSAL_IRQ_PROLOGUE();
-
   serve_interrupt(&SD5);
 
   OSAL_IRQ_EPILOGUE();
@@ -372,14 +372,14 @@ void sd_lld_init(void) {
   SD3.usart = USART2;
 #endif
 
-#if GD32_SERIAL_USE_UART4
+#if GD32_SERIAL_USE_UART3
   sdObjectInit(&SD4, NULL, notify4);
-  SD4.usart = UART4;
+  SD4.usart = UART3;
 #endif
 
-#if GD32_SERIAL_USE_UART5
+#if GD32_SERIAL_USE_UART4
   sdObjectInit(&SD5, NULL, notify5);
-  SD5.usart = UART5;
+  SD5.usart = UART4;
 #endif
 }
 
@@ -417,16 +417,16 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
       eclicEnableVector(GD32_USART2_NUMBER, GD32_SERIAL_USART2_PRIORITY, GD32_SERIAL_USART2_TRIGGER);
     }
 #endif
-#if GD32_SERIAL_USE_UART4
+#if GD32_SERIAL_USE_UART3
     if (&SD4 == sdp) {
-      rccEnableUART4(true);
-      eclicEnableVector(GD32_UART4_NUMBER, GD32_SERIAL_UART4_PRIORITY, GD32_SERIAL_UART4_TRIGGER);
+      rccEnableUART3(true);
+      eclicEnableVector(GD32_UART3_NUMBER, GD32_SERIAL_UART3_PRIORITY, GD32_SERIAL_UART3_TRIGGER);
     }
 #endif
-#if GD32_SERIAL_USE_UART5
+#if GD32_SERIAL_USE_UART4
     if (&SD5 == sdp) {
-      rccEnableUART5(true);
-      eclicEnableVector(GD32_UART5_NUMBER, GD32_SERIAL_UART5_PRIORITY, GD32_SERIAL_UART5_TRIGGER);
+      rccEnableUART4(true);
+      eclicEnableVector(GD32_UART4_NUMBER, GD32_SERIAL_UART4_PRIORITY, GD32_SERIAL_UART4_TRIGGER);
     }
 #endif
   }
@@ -467,17 +467,17 @@ void sd_lld_stop(SerialDriver *sdp) {
       return;
     }
 #endif
-#if GD32_SERIAL_USE_UART4
+#if GD32_SERIAL_USE_UART3
     if (&SD4 == sdp) {
-      rccDisableUART4();
-      eclicDisableVector(GD32_UART4_NUMBER);
+      rccDisableUART3();
+      eclicDisableVector(GD32_UART3_NUMBER);
       return;
     }
 #endif
-#if GD32_SERIAL_USE_UART5
+#if GD32_SERIAL_USE_UART4
     if (&SD5 == sdp) {
-      rccDisableUART5();
-      eclicDisableVector(GD32_UART5_NUMBER);
+      rccDisableUART4();
+      eclicDisableVector(GD32_UART4_NUMBER);
       return;
     }
 #endif
diff --git a/os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.h b/os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.h
index 6a1413b4..ff1d3826 100644
--- a/os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.h
+++ b/os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.h
@@ -66,6 +66,15 @@
 #define GD32_SERIAL_USE_USART2             FALSE
 #endif
 
+/**
+ * @brief   UART3 driver enable switch.
+ * @details If set to @p TRUE the support for UART3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(GD32_SERIAL_USE_UART3) || defined(__DOXYGEN__)
+#define GD32_SERIAL_USE_UART3              FALSE
+#endif
+
 /**
  * @brief   UART4 driver enable switch.
  * @details If set to @p TRUE the support for UART4 is included.
@@ -75,15 +84,6 @@
 #define GD32_SERIAL_USE_UART4              FALSE
 #endif
 
-/**
- * @brief   UART5 driver enable switch.
- * @details If set to @p TRUE the support for UART5 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(GD32_SERIAL_USE_UART5) || defined(__DOXYGEN__)
-#define GD32_SERIAL_USE_UART5              FALSE
-#endif
-
 /**
  * @brief   USART0 interrupt priority level setting.
  */
@@ -105,19 +105,19 @@
 #define GD32_SERIAL_USART2_PRIORITY        12
 #endif
 
+/**
+ * @brief   UART3 interrupt priority level setting.
+ */
+#if !defined(GD32_SERIAL_UART3_PRIORITY) || defined(__DOXYGEN__)
+#define GD32_SERIAL_UART3_PRIORITY         12
+#endif
+
 /**
  * @brief   UART4 interrupt priority level setting.
  */
 #if !defined(GD32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
 #define GD32_SERIAL_UART4_PRIORITY         12
 #endif
-
-/**
- * @brief   UART5 interrupt priority level setting.
- */
-#if !defined(GD32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
-#define GD32_SERIAL_UART5_PRIORITY         12
-#endif
 /** @} */
 
 /*===========================================================================*/
@@ -136,17 +136,17 @@
 #error "USART2 not present in the selected device"
 #endif
 
+#if GD32_SERIAL_USE_UART3 && !GD32_HAS_UART3
+#error "UART3 not present in the selected device"
+#endif
+
 #if GD32_SERIAL_USE_UART4 && !GD32_HAS_UART4
 #error "UART4 not present in the selected device"
 #endif
 
-#if GD32_SERIAL_USE_UART5 && !GD32_HAS_UART5
-#error "UART5 not present in the selected device"
-#endif
-
 #if !GD32_SERIAL_USE_USART0 && !GD32_SERIAL_USE_USART1 &&                 \
-    !GD32_SERIAL_USE_USART2 && !GD32_SERIAL_USE_UART4  &&                 \
-    !GD32_SERIAL_USE_UART5
+    !GD32_SERIAL_USE_USART2 && !GD32_SERIAL_USE_UART3  &&                 \
+    !GD32_SERIAL_USE_UART4
 #error "SERIAL driver activated but no USART/UART peripheral assigned"
 #endif
 
@@ -165,16 +165,16 @@
 #error "Invalid IRQ priority assigned to USART2"
 #endif
 
+#if GD32_SERIAL_USE_UART3 &&                                               \
+    !OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_UART3_PRIORITY)
+#error "Invalid IRQ priority assigned to UART3"
+#endif
+
 #if GD32_SERIAL_USE_UART4 &&                                               \
     !OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_UART4_PRIORITY)
 #error "Invalid IRQ priority assigned to UART4"
 #endif
 
-#if GD32_SERIAL_USE_UART5 &&                                               \
-    !OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_UART5_PRIORITY)
-#error "Invalid IRQ priority assigned to UART5"
-#endif
-
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
@@ -253,10 +253,10 @@ extern SerialDriver SD2;
 #if GD32_SERIAL_USE_USART2 && !defined(__DOXYGEN__)
 extern SerialDriver SD3;
 #endif
-#if GD32_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
+#if GD32_SERIAL_USE_UART3 && !defined(__DOXYGEN__)
 extern SerialDriver SD4;
 #endif
-#if GD32_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
+#if GD32_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
 extern SerialDriver SD5;
 #endif
 
diff --git a/os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.c b/os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.c
index 7a521999..07626667 100644
--- a/os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.c
+++ b/os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.c
@@ -54,6 +54,14 @@
   GD32_DMA_GETCHANNEL(GD32_UART_USART2_TX_DMA_STREAM,                     \
                        GD32_USART2_TX_DMA_CHN)
 
+#define UART3_RX_DMA_CHANNEL                                                \
+  GD32_DMA_GETCHANNEL(GD32_UART_UART3_RX_DMA_STREAM,                      \
+                       GD32_UART3_RX_DMA_CHN)
+
+#define UART3_TX_DMA_CHANNEL                                                \
+  GD32_DMA_GETCHANNEL(GD32_UART_UART3_TX_DMA_STREAM,                      \
+                       GD32_UART3_TX_DMA_CHN)
+
 #define UART4_RX_DMA_CHANNEL                                                \
   GD32_DMA_GETCHANNEL(GD32_UART_UART4_RX_DMA_STREAM,                      \
                        GD32_UART4_RX_DMA_CHN)
@@ -62,19 +70,11 @@
   GD32_DMA_GETCHANNEL(GD32_UART_UART4_TX_DMA_STREAM,                      \
                        GD32_UART4_TX_DMA_CHN)
 
-#define UART5_RX_DMA_CHANNEL                                                \
-  GD32_DMA_GETCHANNEL(GD32_UART_UART5_RX_DMA_STREAM,                      \
-                       GD32_UART5_RX_DMA_CHN)
-
-#define UART5_TX_DMA_CHANNEL                                                \
-  GD32_DMA_GETCHANNEL(GD32_UART_UART5_TX_DMA_STREAM,                      \
-                       GD32_UART5_TX_DMA_CHN)
-
-#define GD32_UART45_CR2_CHECK_MASK                                         \
+#define GD32_UART34_CR2_CHECK_MASK                                         \
   (USART_CTL1_STB_0 | USART_CTL1_CKEN | USART_CTL1_CPL | USART_CTL1_CPH |   \
    USART_CTL1_CLEN)
 
-#define GD32_UART45_CR3_CHECK_MASK                                         \
+#define GD32_UART35_CR3_CHECK_MASK                                         \
   (USART_CTL2_CTSIE | USART_CTL2_CTSEN | USART_CTL2_RTSEN | USART_CTL2_SCEN |     \
    USART_CTL2_NKEN)
 
@@ -97,13 +97,13 @@ UARTDriver UARTD2;
 UARTDriver UARTD3;
 #endif
 
-/** @brief UART4 UART driver identifier.*/
-#if GD32_UART_USE_UART4 || defined(__DOXYGEN__)
+/** @brief UART3 UART driver identifier.*/
+#if GD32_UART_USE_UART3 || defined(__DOXYGEN__)
 UARTDriver UARTD4;
 #endif
 
-/** @brief UART5 UART driver identifier.*/
-#if GD32_UART_USE_UART5 || defined(__DOXYGEN__)
+/** @brief UART4 UART driver identifier.*/
+#if GD32_UART_USE_UART4 || defined(__DOXYGEN__)
 UARTDriver UARTD5;
 #endif
 
@@ -366,6 +366,25 @@ OSAL_IRQ_HANDLER(GD32_USART2_HANDLER) {
 }
 #endif /* GD32_UART_USE_USART2 */
 
+#if GD32_UART_USE_UART3 || defined(__DOXYGEN__)
+#if !defined(GD32_UART3_HANDLER)
+#error "GD32_UART3_HANDLER not defined"
+#endif
+/**
+ * @brief   UART3 IRQ handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_UART3_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  serve_usart_irq(&UARTD4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* GD32_UART_USE_UART3 */
+
 #if GD32_UART_USE_UART4 || defined(__DOXYGEN__)
 #if !defined(GD32_UART4_HANDLER)
 #error "GD32_UART4_HANDLER not defined"
@@ -379,30 +398,11 @@ OSAL_IRQ_HANDLER(GD32_UART4_HANDLER) {
 
   OSAL_IRQ_PROLOGUE();
 
-  serve_usart_irq(&UARTD4);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif /* GD32_UART_USE_UART4 */
-
-#if GD32_UART_USE_UART5 || defined(__DOXYGEN__)
-#if !defined(GD32_UART5_HANDLER)
-#error "GD32_UART5_HANDLER not defined"
-#endif
-/**
- * @brief   UART5 IRQ handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(GD32_UART5_HANDLER) {
-
-  OSAL_IRQ_PROLOGUE();
-
   serve_usart_irq(&UARTD5);
 
   OSAL_IRQ_EPILOGUE();
 }
-#endif /* GD32_UART_USE_UART5 */
+#endif /* GD32_UART_USE_UART4 */
 
 /*===========================================================================*/
 /* Driver exported functions.                                                */
@@ -442,18 +442,18 @@ void uart_lld_init(void) {
   UARTD3.dmatx   = NULL;
 #endif
 
-#if GD32_UART_USE_UART4
+#if GD32_UART_USE_UART3
   uartObjectInit(&UARTD4);
-  UARTD4.usart   = UART4;
+  UARTD4.usart   = UART3;
   UARTD4.dmarxmode = GD32_DMA_CTL_ERRIE;
   UARTD4.dmatxmode = GD32_DMA_CTL_ERRIE;
   UARTD4.dmarx   = NULL;
   UARTD4.dmatx   = NULL;
 #endif
 
-#if GD32_UART_USE_UART5
+#if GD32_UART_USE_UART4
   uartObjectInit(&UARTD5);
-  UARTD5.usart   = UART5;
+  UARTD5.usart   = UART4;
   UARTD5.dmarxmode = GD32_DMA_CTL_ERRIE;
   UARTD5.dmatxmode = GD32_DMA_CTL_ERRIE;
   UARTD5.dmarx   = NULL;
@@ -537,12 +537,40 @@ void uart_lld_start(UARTDriver *uartp) {
     }
 #endif
 
-#if GD32_UART_USE_UART4
+#if GD32_UART_USE_UART3
     if (&UARTD4 == uartp) {
 
-      osalDbgAssert((uartp->config->ctl1 & GD32_UART45_CR2_CHECK_MASK) == 0,
+      osalDbgAssert((uartp->config->ctl1 & GD32_UART34_CR2_CHECK_MASK) == 0,
+                    "specified invalid bits in UART3 CR2 register settings");
+      osalDbgAssert((uartp->config->ctl2 & GD32_UART35_CR3_CHECK_MASK) == 0,
+                    "specified invalid bits in UART3 CR3 register settings");
+
+      uartp->dmarx = dmaStreamAllocI(GD32_UART_UART3_RX_DMA_STREAM,
+                                     GD32_UART_UART3_IRQ_PRIORITY,
+                                     (gd32_dmaisr_t)uart_lld_serve_rx_end_irq,
+                                     (void *)uartp);
+      osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
+      uartp->dmatx = dmaStreamAllocI(GD32_UART_UART3_TX_DMA_STREAM,
+                                     GD32_UART_UART3_IRQ_PRIORITY,
+                                     (gd32_dmaisr_t)uart_lld_serve_tx_end_irq,
+                                     (void *)uartp);
+      osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
+
+      rccEnableUART3(true);
+      eclicEnableVector(GD32_UART3_NUMBER, GD32_UART_UART3_IRQ_PRIORITY, GD32_UART_UART3_IRQ_TRIGGER);
+      uartp->dmarxmode |= GD32_DMA_CTL_CHSEL(UART3_RX_DMA_CHANNEL) |
+                          GD32_DMA_CTL_PRIO(GD32_UART_UART3_DMA_PRIORITY);
+      uartp->dmatxmode |= GD32_DMA_CTL_CHSEL(UART3_TX_DMA_CHANNEL) |
+                          GD32_DMA_CTL_PRIO(GD32_UART_UART3_DMA_PRIORITY);
+    }
+#endif
+
+#if GD32_UART_USE_UART4
+    if (&UARTD5 == uartp) {
+
+      osalDbgAssert((uartp->config->ctl1 & GD32_UART34_CR2_CHECK_MASK) == 0,
                     "specified invalid bits in UART4 CR2 register settings");
-      osalDbgAssert((uartp->config->ctl2 & GD32_UART45_CR3_CHECK_MASK) == 0,
+      osalDbgAssert((uartp->config->ctl2 & GD32_UART35_CR3_CHECK_MASK) == 0,
                     "specified invalid bits in UART4 CR3 register settings");
 
       uartp->dmarx = dmaStreamAllocI(GD32_UART_UART4_RX_DMA_STREAM,
@@ -565,34 +593,6 @@ void uart_lld_start(UARTDriver *uartp) {
     }
 #endif
 
-#if GD32_UART_USE_UART5
-    if (&UARTD5 == uartp) {
-
-      osalDbgAssert((uartp->config->ctl1 & GD32_UART45_CR2_CHECK_MASK) == 0,
-                    "specified invalid bits in UART5 CR2 register settings");
-      osalDbgAssert((uartp->config->ctl2 & GD32_UART45_CR3_CHECK_MASK) == 0,
-                    "specified invalid bits in UART5 CR3 register settings");
-
-      uartp->dmarx = dmaStreamAllocI(GD32_UART_UART5_RX_DMA_STREAM,
-                                     GD32_UART_UART5_IRQ_PRIORITY,
-                                     (gd32_dmaisr_t)uart_lld_serve_rx_end_irq,
-                                     (void *)uartp);
-      osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
-      uartp->dmatx = dmaStreamAllocI(GD32_UART_UART5_TX_DMA_STREAM,
-                                     GD32_UART_UART5_IRQ_PRIORITY,
-                                     (gd32_dmaisr_t)uart_lld_serve_tx_end_irq,
-                                     (void *)uartp);
-      osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
-
-      rccEnableUART5(true);
-      eclicEnableVector(GD32_UART5_NUMBER, GD32_UART_UART5_IRQ_PRIORITY, GD32_UART_UART5_IRQ_TRIGGER);
-      uartp->dmarxmode |= GD32_DMA_CTL_CHSEL(UART5_RX_DMA_CHANNEL) |
-                          GD32_DMA_CTL_PRIO(GD32_UART_UART5_DMA_PRIORITY);
-      uartp->dmatxmode |= GD32_DMA_CTL_CHSEL(UART5_TX_DMA_CHANNEL) |
-                          GD32_DMA_CTL_PRIO(GD32_UART_UART5_DMA_PRIORITY);
-    }
-#endif
-
     /* Static DMA setup, the transfer size depends on the USART settings,
        it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
     if ((uartp->config->ctl0 & (USART_CTL0_WL | USART_CTL0_PCEN)) == USART_CTL0_WL) {
@@ -649,18 +649,18 @@ void uart_lld_stop(UARTDriver *uartp) {
     }
 #endif
 
-#if GD32_UART_USE_UART4
+#if GD32_UART_USE_UART3
     if (&UARTD4 == uartp) {
-      eclicDisableVector(GD32_UART4_NUMBER);
-      rccDisableUART4();
+      eclicDisableVector(GD32_UART3_NUMBER);
+      rccDisableUART3();
       return;
     }
 #endif
 
-#if GD32_UART_USE_UART5
+#if GD32_UART_USE_UART4
     if (&UARTD5 == uartp) {
-      eclicDisableVector(GD32_UART5_NUMBER);
-      rccDisableUART5();
+      eclicDisableVector(GD32_UART4_NUMBER);
+      rccDisableUART4();
       return;
     }
 #endif
diff --git a/os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.h b/os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.h
index 06dca55c..7a43545a 100644
--- a/os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.h
+++ b/os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.h
@@ -66,6 +66,15 @@
 #define GD32_UART_USE_USART2               FALSE
 #endif
 
+/**
+ * @brief   UART driver on UART3 enable switch.
+ * @details If set to @p TRUE the support for UART3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(GD32_UART_USE_UART3) || defined(__DOXYGEN__)
+#define GD32_UART_USE_UART3                FALSE
+#endif
+
 /**
  * @brief   UART driver on UART4 enable switch.
  * @details If set to @p TRUE the support for UART4 is included.
@@ -75,15 +84,6 @@
 #define GD32_UART_USE_UART4                FALSE
 #endif
 
-/**
- * @brief   UART driver on UART5 enable switch.
- * @details If set to @p TRUE the support for UART5 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(GD32_UART_USE_UART5) || defined(__DOXYGEN__)
-#define GD32_UART_USE_UART5                FALSE
-#endif
-
 /**
  * @brief   USART0 interrupt priority level setting.
  */
@@ -105,6 +105,13 @@
 #define GD32_UART_USART2_IRQ_PRIORITY      12
 #endif
 
+/**
+ * @brief   UART3 interrupt priority level setting.
+ */
+#if !defined(GD32_UART_UART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define GD32_UART_UART3_IRQ_PRIORITY       12
+#endif
+
 /**
  * @brief   UART4 interrupt priority level setting.
  */
@@ -112,13 +119,6 @@
 #define GD32_UART_UART4_IRQ_PRIORITY       12
 #endif
 
-/**
- * @brief   UART5 interrupt priority level setting.
- */
-#if !defined(GD32_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define GD32_UART_UART5_IRQ_PRIORITY       12
-#endif
-
 /**
  * @brief   USART0 DMA priority (0..3|lowest..highest).
  * @note    The priority level is used for both the TX and RX DMA channels but
@@ -149,6 +149,16 @@
 #define GD32_UART_USART2_DMA_PRIORITY      0
 #endif
 
+/**
+ * @brief   UART3 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is used for both the TX and RX DMA channels but
+ *          because of the channels ordering the RX channel has always priority
+ *          over the TX channel.
+ */
+#if !defined(GD32_UART_UART3_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define GD32_UART_UART3_DMA_PRIORITY       0
+#endif
+
 /**
  * @brief   UART4 DMA priority (0..3|lowest..highest).
  * @note    The priority level is used for both the TX and RX DMA channels but
@@ -159,16 +169,6 @@
 #define GD32_UART_UART4_DMA_PRIORITY       0
 #endif
 
-/**
- * @brief   UART5 DMA priority (0..3|lowest..highest).
- * @note    The priority level is used for both the TX and RX DMA channels but
- *          because of the channels ordering the RX channel has always priority
- *          over the TX channel.
- */
-#if !defined(GD32_UART_UART5_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define GD32_UART_UART5_DMA_PRIORITY       0
-#endif
-
 /**
  * @brief   USART DMA error hook.
  * @note    The default action for DMA errors is a system halt because DMA
@@ -195,17 +195,17 @@
 #error "USART2 not present in the selected device"
 #endif
 
+#if GD32_UART_USE_UART3 && !GD32_HAS_UART3
+#error "UART3 not present in the selected device"
+#endif
+
 #if GD32_UART_USE_UART4 && !GD32_HAS_UART4
 #error "UART4 not present in the selected device"
 #endif
 
-#if GD32_UART_USE_UART5 && !GD32_HAS_UART5
-#error "UART5 not present in the selected device"
-#endif
-
 #if !GD32_UART_USE_USART0 && !GD32_UART_USE_USART1 &&                     \
-    !GD32_UART_USE_USART2 && !GD32_UART_USE_UART4 &&                      \
-    !GD32_UART_USE_UART5  
+    !GD32_UART_USE_USART2 && !GD32_UART_USE_UART3 &&                      \
+    !GD32_UART_USE_UART4  
 #error "UART driver activated but no USART/UART peripheral assigned"
 #endif
 
@@ -224,16 +224,16 @@
 #error "Invalid IRQ priority assigned to USART2"
 #endif
 
+#if GD32_UART_USE_UART3 &&                                                 \
+    !OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_UART3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART3"
+#endif
+
 #if GD32_UART_USE_UART4 &&                                                 \
     !OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_UART4_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to UART4"
 #endif
 
-#if GD32_UART_USE_UART5 &&                                                 \
-    !OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_UART5_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to UART5"
-#endif
-
 #if GD32_UART_USE_USART0 &&                                                \
     !GD32_DMA_IS_VALID_PRIORITY(GD32_UART_USART0_DMA_PRIORITY)
 #error "Invalid DMA priority assigned to USART0"
@@ -249,16 +249,16 @@
 #error "Invalid DMA priority assigned to USART2"
 #endif
 
+#if GD32_UART_USE_UART3 &&                                                 \
+    !GD32_DMA_IS_VALID_PRIORITY(GD32_UART_UART3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to UART3"
+#endif
+
 #if GD32_UART_USE_UART4 &&                                                 \
     !GD32_DMA_IS_VALID_PRIORITY(GD32_UART_UART4_DMA_PRIORITY)
 #error "Invalid DMA priority assigned to UART4"
 #endif
 
-#if GD32_UART_USE_UART5 &&                                                 \
-    !GD32_DMA_IS_VALID_PRIORITY(GD32_UART_UART5_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to UART5"
-#endif
-
 #if !defined(GD32_DMA_REQUIRED)
 #define GD32_DMA_REQUIRED
 #endif
@@ -440,11 +440,11 @@ extern UARTDriver UARTD2;
 extern UARTDriver UARTD3;
 #endif
 
-#if GD32_UART_USE_UART4 && !defined(__DOXYGEN__)
+#if GD32_UART_USE_UART3 && !defined(__DOXYGEN__)
 extern UARTDriver UARTD4;
 #endif
 
-#if GD32_UART_USE_UART5 && !defined(__DOXYGEN__)
+#if GD32_UART_USE_UART4 && !defined(__DOXYGEN__)
 extern UARTDriver UARTD5;
 #endif
 
diff --git a/os/hal/ports/GD/GD32VF103/gd32_isr.h b/os/hal/ports/GD/GD32VF103/gd32_isr.h
index 4cbd18d7..36c094f1 100644
--- a/os/hal/ports/GD/GD32VF103/gd32_isr.h
+++ b/os/hal/ports/GD/GD32VF103/gd32_isr.h
@@ -94,14 +94,14 @@
 #define GD32_USART0_HANDLER        vector56
 #define GD32_USART1_HANDLER        vector57
 #define GD32_USART2_HANDLER        vector58
-#define GD32_UART4_HANDLER         vector71
-#define GD32_UART5_HANDLER         vector72
+#define GD32_UART3_HANDLER         vector71
+#define GD32_UART4_HANDLER         vector72
 
 #define GD32_USART0_NUMBER         56
 #define GD32_USART1_NUMBER         57
 #define GD32_USART2_NUMBER         58
-#define GD32_UART4_NUMBER          71
-#define GD32_UART5_NUMBER          72
+#define GD32_UART3_NUMBER          71
+#define GD32_UART4_NUMBER          72
 
 /*
  * OTG units.
@@ -270,8 +270,8 @@
 #define GD32_PWM_TIM8_IRQ_TRIGGER        ECLIC_TRIGGER_DEFAULT
 #define GD32_RTC_IRQ_TRIGGER             ECLIC_TRIGGER_DEFAULT
 #define GD32_SDC_SDIO_IRQ_TRIGGER        ECLIC_TRIGGER_DEFAULT
+#define GD32_SERIAL_UART3_TRIGGER        ECLIC_TRIGGER_DEFAULT
 #define GD32_SERIAL_UART4_TRIGGER        ECLIC_TRIGGER_DEFAULT
-#define GD32_SERIAL_UART5_TRIGGER        ECLIC_TRIGGER_DEFAULT
 #define GD32_SERIAL_UART7_TRIGGER        ECLIC_TRIGGER_DEFAULT
 #define GD32_SERIAL_UART8_TRIGGER        ECLIC_TRIGGER_DEFAULT
 #define GD32_SERIAL_USART0_TRIGGER       ECLIC_TRIGGER_DEFAULT
@@ -279,8 +279,8 @@
 #define GD32_SERIAL_USART2_TRIGGER       ECLIC_TRIGGER_DEFAULT
 #define GD32_SERIAL_USART6_TRIGGER       ECLIC_TRIGGER_DEFAULT
 #define GD32_ST_IRQ_TRIGGER              ECLIC_TRIGGER_DEFAULT
+#define GD32_UART_UART3_IRQ_TRIGGER      ECLIC_TRIGGER_DEFAULT
 #define GD32_UART_UART4_IRQ_TRIGGER      ECLIC_TRIGGER_DEFAULT
-#define GD32_UART_UART5_IRQ_TRIGGER      ECLIC_TRIGGER_DEFAULT
 #define GD32_UART_UART7_IRQ_TRIGGER      ECLIC_TRIGGER_DEFAULT
 #define GD32_UART_UART8_IRQ_TRIGGER      ECLIC_TRIGGER_DEFAULT
 #define GD32_UART_USART0_IRQ_TRIGGER     ECLIC_TRIGGER_DEFAULT
diff --git a/os/hal/ports/GD/GD32VF103/gd32_rcc.h b/os/hal/ports/GD/GD32VF103/gd32_rcc.h
index 581650c2..900bf495 100644
--- a/os/hal/ports/GD/GD32VF103/gd32_rcc.h
+++ b/os/hal/ports/GD/GD32VF103/gd32_rcc.h
@@ -1115,6 +1115,30 @@
  */
 #define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
 
+/**
+ * @brief   Enables the UART3 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART3(lp) rccEnableAPB1(RCC_APB1ENR_UART3EN, lp)
+
+/**
+ * @brief   Disables the UART3 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUART3() rccDisableAPB1(RCC_APB1ENR_UART3EN)
+
+/**
+ * @brief   Resets the UART3 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART3() rccResetAPB1(RCC_APB1RSTR_UART3RST)
+
 /**
  * @brief   Enables the UART4 peripheral clock.
  * @note    The @p lp parameter is ignored in this family.
@@ -1138,30 +1162,6 @@
  * @api
  */
 #define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
-
-/**
- * @brief   Enables the UART5 peripheral clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
-
-/**
- * @brief   Disables the UART5 peripheral clock.
- *
- * @api
- */
-#define rccDisableUART5() rccDisableAPB1(RCC_APB1ENR_UART5EN)
-
-/**
- * @brief   Resets the UART5 peripheral.
- *
- * @api
- */
-#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
 /** @} */
 
 /**
diff --git a/os/hal/ports/GD/GD32VF103/gd32_registry.h b/os/hal/ports/GD/GD32VF103/gd32_registry.h
index a2e4a2c3..a220383e 100644
--- a/os/hal/ports/GD/GD32VF103/gd32_registry.h
+++ b/os/hal/ports/GD/GD32VF103/gd32_registry.h
@@ -289,13 +289,13 @@
 #endif
 
 #if GD32_HAS_USART_01234
+    #define GD32_HAS_UART3                     TRUE
+    #define GD32_UART_UART3_RX_DMA_STREAM      GD32_DMA_STREAM_ID(1, 2)
+    #define GD32_UART_UART3_TX_DMA_STREAM      GD32_DMA_STREAM_ID(1, 4)
     #define GD32_HAS_UART4                     TRUE
-    #define GD32_UART_UART4_RX_DMA_STREAM      GD32_DMA_STREAM_ID(1, 2)
-    #define GD32_UART_UART4_TX_DMA_STREAM      GD32_DMA_STREAM_ID(1, 4)
-    #define GD32_HAS_UART5                     TRUE
 #else
+    #define GD32_HAS_UART3                     FALSE
     #define GD32_HAS_UART4                     FALSE
-    #define GD32_HAS_UART5                     FALSE
 #endif
 
 /* USB attributes.*/
diff --git a/os/hal/ports/GD/GD32VF103/stm32_registry.h b/os/hal/ports/GD/GD32VF103/stm32_registry.h
index d71a0322..64786275 100644
--- a/os/hal/ports/GD/GD32VF103/stm32_registry.h
+++ b/os/hal/ports/GD/GD32VF103/stm32_registry.h
@@ -240,8 +240,8 @@
 #define GD32_UART_USART2_RX_DMA_STREAM     GD32_DMA_STREAM_ID(1, 3)
 #define GD32_UART_USART2_TX_DMA_STREAM     GD32_DMA_STREAM_ID(1, 2)
 
+#define GD32_HAS_UART3                     FALSE
 #define GD32_HAS_UART4                     FALSE
-#define GD32_HAS_UART5                     FALSE
 #define GD32_HAS_USART6                    FALSE
 #define GD32_HAS_UART7                     FALSE
 #define GD32_HAS_UART8                     FALSE
@@ -425,8 +425,8 @@
 #define GD32_UART_USART1_TX_DMA_STREAM     GD32_DMA_STREAM_ID(1, 7)
 
 #define GD32_HAS_USART2                    FALSE
+#define GD32_HAS_UART3                     FALSE
 #define GD32_HAS_UART4                     FALSE
-#define GD32_HAS_UART5                     FALSE
 #define GD32_HAS_USART6                    FALSE
 #define GD32_HAS_UART7                     FALSE
 #define GD32_HAS_UART8                     FALSE
@@ -623,8 +623,8 @@
 #define GD32_UART_USART2_RX_DMA_STREAM     GD32_DMA_STREAM_ID(1, 3)
 #define GD32_UART_USART2_TX_DMA_STREAM     GD32_DMA_STREAM_ID(1, 2)
 
+#define GD32_HAS_UART3                     FALSE
 #define GD32_HAS_UART4                     FALSE
-#define GD32_HAS_UART5                     FALSE
 #define GD32_HAS_USART6                    FALSE
 #define GD32_HAS_UART7                     FALSE
 #define GD32_HAS_UART8                     FALSE
@@ -860,11 +860,11 @@
 #define GD32_UART_USART2_RX_DMA_STREAM     GD32_DMA_STREAM_ID(1, 3)
 #define GD32_UART_USART2_TX_DMA_STREAM     GD32_DMA_STREAM_ID(1, 2)
 
-#define GD32_HAS_UART4                     TRUE
-#define GD32_UART_UART4_RX_DMA_STREAM      GD32_DMA_STREAM_ID(2, 3)
-#define GD32_UART_UART4_TX_DMA_STREAM      GD32_DMA_STREAM_ID(2, 5)
+#define GD32_HAS_UART3                     TRUE
+#define GD32_UART_UART3_RX_DMA_STREAM      GD32_DMA_STREAM_ID(2, 3)
+#define GD32_UART_UART3_TX_DMA_STREAM      GD32_DMA_STREAM_ID(2, 5)
 
-#define GD32_HAS_UART5                     FALSE
+#define GD32_HAS_UART4                     FALSE
 #define GD32_HAS_USART6                    FALSE
 #define GD32_HAS_UART7                     FALSE
 #define GD32_HAS_UART8                     FALSE
@@ -1118,11 +1118,11 @@
 #define GD32_UART_USART2_RX_DMA_STREAM     GD32_DMA_STREAM_ID(1, 3)
 #define GD32_UART_USART2_TX_DMA_STREAM     GD32_DMA_STREAM_ID(1, 2)
 
-#define GD32_HAS_UART4                     TRUE
-#define GD32_UART_UART4_RX_DMA_STREAM      GD32_DMA_STREAM_ID(2, 3)
-#define GD32_UART_UART4_TX_DMA_STREAM      GD32_DMA_STREAM_ID(2, 5)
+#define GD32_HAS_UART3                     TRUE
+#define GD32_UART_UART3_RX_DMA_STREAM      GD32_DMA_STREAM_ID(2, 3)
+#define GD32_UART_UART3_TX_DMA_STREAM      GD32_DMA_STREAM_ID(2, 5)
 
-#define GD32_HAS_UART5                     FALSE
+#define GD32_HAS_UART4                     FALSE
 #define GD32_HAS_USART6                    FALSE
 #define GD32_HAS_UART7                     FALSE
 #define GD32_HAS_UART8                     FALSE
@@ -1356,11 +1356,11 @@
 #define GD32_UART_USART2_RX_DMA_STREAM     GD32_DMA_STREAM_ID(1, 3)
 #define GD32_UART_USART2_TX_DMA_STREAM     GD32_DMA_STREAM_ID(1, 2)
 
-#define GD32_HAS_UART4                     TRUE
-#define GD32_UART_UART4_RX_DMA_STREAM      GD32_DMA_STREAM_ID(2, 3)
-#define GD32_UART_UART4_TX_DMA_STREAM      GD32_DMA_STREAM_ID(2, 5)
+#define GD32_HAS_UART3                     TRUE
+#define GD32_UART_UART3_RX_DMA_STREAM      GD32_DMA_STREAM_ID(2, 3)
+#define GD32_UART_UART3_TX_DMA_STREAM      GD32_DMA_STREAM_ID(2, 5)
 
-#define GD32_HAS_UART5                     TRUE
+#define GD32_HAS_UART4                     TRUE
 
 #define GD32_HAS_USART6                    FALSE
 #define GD32_HAS_UART7                     FALSE
diff --git a/os/hal/ports/GD/GD32VF103/stm32f105xc.h b/os/hal/ports/GD/GD32VF103/stm32f105xc.h
index 34cc2be0..264b0aac 100644
--- a/os/hal/ports/GD/GD32VF103/stm32f105xc.h
+++ b/os/hal/ports/GD/GD32VF103/stm32f105xc.h
@@ -712,8 +712,8 @@ typedef struct
 #define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00U)
 #define USART1_BASE           (APB1PERIPH_BASE + 0x00004400U)
 #define USART2_BASE           (APB1PERIPH_BASE + 0x00004800U)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00U)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000U)
+#define UART3_BASE            (APB1PERIPH_BASE + 0x00004C00U)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x00005000U)
 #define I2C0_BASE             (APB1PERIPH_BASE + 0x00005400U)
 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5800)
 #define CAN1_BASE             (APB1PERIPH_BASE + 0x00006400U)
@@ -800,8 +800,8 @@ typedef struct
 #define SPI3                ((SPI_TypeDef *)SPI3_BASE)
 #define USART1              ((USART_TypeDef *)USART1_BASE)
 #define USART2              ((USART_TypeDef *)USART2_BASE)
+#define UART3               ((USART_TypeDef *)UART3_BASE)
 #define UART4               ((USART_TypeDef *)UART4_BASE)
-#define UART5               ((USART_TypeDef *)UART5_BASE)
 #define I2C0                ((I2C_TypeDef *)I2C0_BASE)
 #define I2C1                ((I2C_TypeDef *)I2C1_BASE)
 #define CAN1                ((CAN_TypeDef *)CAN1_BASE)
@@ -1600,12 +1600,12 @@ typedef struct
 #define RCC_APB1RSTR_SPI3RST_Pos             (15U)                             
 #define RCC_APB1RSTR_SPI3RST_Msk             (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
 #define RCC_APB1RSTR_SPI3RST                 RCC_APB1RSTR_SPI3RST_Msk          /*!< SPI 3 reset */
-#define RCC_APB1RSTR_UART4RST_Pos            (19U)                             
-#define RCC_APB1RSTR_UART4RST_Msk            (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_UART4RST                RCC_APB1RSTR_UART4RST_Msk         /*!< UART 4 reset */
-#define RCC_APB1RSTR_UART5RST_Pos            (20U)                             
-#define RCC_APB1RSTR_UART5RST_Msk            (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
-#define RCC_APB1RSTR_UART5RST                RCC_APB1RSTR_UART5RST_Msk         /*!< UART 5 reset */
+#define RCC_APB1RSTR_UART3RST_Pos            (19U)                             
+#define RCC_APB1RSTR_UART3RST_Msk            (0x1U << RCC_APB1RSTR_UART3RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART3RST                RCC_APB1RSTR_UART3RST_Msk         /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART4RST_Pos            (20U)                             
+#define RCC_APB1RSTR_UART4RST_Msk            (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART4RST                RCC_APB1RSTR_UART4RST_Msk         /*!< UART 5 reset */
 
 
 
@@ -1736,12 +1736,12 @@ typedef struct
 #define RCC_APB1ENR_SPI3EN_Pos               (15U)                             
 #define RCC_APB1ENR_SPI3EN_Msk               (0x1U << RCC_APB1ENR_SPI3EN_Pos)  /*!< 0x00008000 */
 #define RCC_APB1ENR_SPI3EN                   RCC_APB1ENR_SPI3EN_Msk            /*!< SPI 3 clock enable */
-#define RCC_APB1ENR_UART4EN_Pos              (19U)                             
-#define RCC_APB1ENR_UART4EN_Msk              (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
-#define RCC_APB1ENR_UART4EN                  RCC_APB1ENR_UART4EN_Msk           /*!< UART 4 clock enable */
-#define RCC_APB1ENR_UART5EN_Pos              (20U)                             
-#define RCC_APB1ENR_UART5EN_Msk              (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
-#define RCC_APB1ENR_UART5EN                  RCC_APB1ENR_UART5EN_Msk           /*!< UART 5 clock enable */
+#define RCC_APB1ENR_UART3EN_Pos              (19U)                             
+#define RCC_APB1ENR_UART3EN_Msk              (0x1U << RCC_APB1ENR_UART3EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART3EN                  RCC_APB1ENR_UART3EN_Msk           /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART4EN_Pos              (20U)                             
+#define RCC_APB1ENR_UART4EN_Msk              (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART4EN                  RCC_APB1ENR_UART4EN_Msk           /*!< UART 5 clock enable */
 
 
 
@@ -12863,22 +12863,22 @@ typedef struct
 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
                                     ((INSTANCE) == USART1) || \
                                     ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
+                                    ((INSTANCE) == UART3)  || \
+                                    ((INSTANCE) == UART4))
 
 /******************** UART Instances : Half-Duplex mode **********************/
 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
                                                ((INSTANCE) == USART1) || \
                                                ((INSTANCE) == USART2) || \
-                                               ((INSTANCE) == UART4)  || \
-                                               ((INSTANCE) == UART5))
+                                               ((INSTANCE) == UART3)  || \
+                                               ((INSTANCE) == UART4))
 
 /******************** UART Instances : LIN mode **********************/
 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
                                         ((INSTANCE) == USART1) || \
                                         ((INSTANCE) == USART2) || \
-                                        ((INSTANCE) == UART4)  || \
-                                        ((INSTANCE) == UART5))
+                                        ((INSTANCE) == UART3)  || \
+                                        ((INSTANCE) == UART4))
 
 /****************** UART Instances : Hardware Flow control ********************/                                    
 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
@@ -12894,21 +12894,21 @@ typedef struct
 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
                                     ((INSTANCE) == USART1) || \
                                     ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
+                                    ((INSTANCE) == UART3)  || \
+                                    ((INSTANCE) == UART4))
 
 /***************** UART Instances : Multi-Processor mode **********************/
 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
                                                    ((INSTANCE) == USART1) || \
                                                    ((INSTANCE) == USART2) || \
-                                                   ((INSTANCE) == UART4)  || \
-                                                   ((INSTANCE) == UART5))
+                                                   ((INSTANCE) == UART3)  || \
+                                                   ((INSTANCE) == UART4))
 
 /***************** UART Instances : DMA mode available **********************/
 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
                                         ((INSTANCE) == USART1) || \
                                         ((INSTANCE) == USART2) || \
-                                        ((INSTANCE) == UART4))
+                                        ((INSTANCE) == UART3))
 
 /****************************** RTC Instances *********************************/
 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)