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Replace STM32_ with GD32_

This commit is contained in:
Stefan Kerkmann 2021-03-20 19:47:59 +01:00
parent 3467aa8ffe
commit a9a4e46916
68 changed files with 6655 additions and 6654 deletions
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128
os/hal/ports/GD/GD32VF103/CAN/hal_can_lld.c
View File

@ -33,7 +33,7 @@
/*
* Addressing differences in the headers, they seem unable to agree on names.
*/
#if STM32_CAN_USE_CAN1
#if GD32_CAN_USE_CAN1
#if !defined(CAN1)
#define CAN1 CAN
#endif
@ -44,17 +44,17 @@
/*===========================================================================*/
/** @brief CAN1 driver identifier.*/
#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__)
#if GD32_CAN_USE_CAN1 || defined(__DOXYGEN__)
CANDriver CAND1;
#endif
/** @brief CAN2 driver identifier.*/
#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__)
#if GD32_CAN_USE_CAN2 || defined(__DOXYGEN__)
CANDriver CAND2;
#endif
/** @brief CAN3 driver identifier.*/
#if STM32_CAN_USE_CAN3 || defined(__DOXYGEN__)
#if GD32_CAN_USE_CAN3 || defined(__DOXYGEN__)
CANDriver CAND3;
#endif
@ -82,7 +82,7 @@ static void can_lld_set_filters(CANDriver* canp,
uint32_t num,
const CANFilter *cfp) {
#if STM32_CAN_USE_CAN2
#if GD32_CAN_USE_CAN2
if (canp == &CAND2) {
/* Set handle to CAN1, because CAN1 manages the filters of CAN2.*/
canp = &CAND1;
@ -90,7 +90,7 @@ static void can_lld_set_filters(CANDriver* canp,
#endif
/* Temporarily enabling CAN clock.*/
#if STM32_CAN_USE_CAN1
#if GD32_CAN_USE_CAN1
if (canp == &CAND1) {
rccEnableCAN1(true);
/* Filters initialization.*/
@ -99,7 +99,7 @@ static void can_lld_set_filters(CANDriver* canp,
}
#endif
#if STM32_CAN_USE_CAN3
#if GD32_CAN_USE_CAN3
if (canp == &CAND3) {
rccEnableCAN3(true);
/* Filters initialization.*/
@ -116,18 +116,18 @@ static void can_lld_set_filters(CANDriver* canp,
canp->can->FS1R = 0;
canp->can->FFA1R = 0;
#if STM32_CAN_USE_CAN1
#if GD32_CAN_USE_CAN1
if (canp == &CAND1) {
for (i = 0; i < STM32_CAN_MAX_FILTERS; i++) {
for (i = 0; i < GD32_CAN_MAX_FILTERS; i++) {
canp->can->sFilterRegister[i].FR1 = 0;
canp->can->sFilterRegister[i].FR2 = 0;
}
}
#endif
#if STM32_CAN_USE_CAN3
#if GD32_CAN_USE_CAN3
if (canp == &CAND3) {
for (i = 0; i < STM32_CAN3_MAX_FILTERS; i++) {
for (i = 0; i < GD32_CAN3_MAX_FILTERS; i++) {
canp->can->sFilterRegister[i].FR1 = 0;
canp->can->sFilterRegister[i].FR2 = 0;
}
@ -154,7 +154,7 @@ static void can_lld_set_filters(CANDriver* canp,
CANs.*/
canp->can->sFilterRegister[0].FR1 = 0;
canp->can->sFilterRegister[0].FR2 = 0;
#if STM32_CAN_USE_CAN2
#if GD32_CAN_USE_CAN2
if (canp == &CAND1) {
canp->can->sFilterRegister[can2sb].FR1 = 0;
canp->can->sFilterRegister[can2sb].FR2 = 0;
@ -164,7 +164,7 @@ static void can_lld_set_filters(CANDriver* canp,
canp->can->FFA1R = 0;
canp->can->FS1R = 1;
canp->can->FA1R = 1;
#if STM32_CAN_USE_CAN2
#if GD32_CAN_USE_CAN2
if (canp == &CAND1) {
canp->can->FS1R |= 1 << can2sb;
canp->can->FA1R |= 1 << can2sb;
@ -175,12 +175,12 @@ static void can_lld_set_filters(CANDriver* canp,
/* Clock disabled, it will be enabled again in can_lld_start().*/
/* Temporarily enabling CAN clock.*/
#if STM32_CAN_USE_CAN1
#if GD32_CAN_USE_CAN1
if (canp == &CAND1) {
rccDisableCAN1();
}
#endif
#if STM32_CAN_USE_CAN3
#if GD32_CAN_USE_CAN3
if (canp == &CAND3) {
rccDisableCAN3();
}
@ -312,7 +312,7 @@ static void can_lld_sce_handler(CANDriver *canp) {
eventflags_t flags;
uint32_t esr = canp->can->ESR;
#if STM32_CAN_REPORT_ALL_ERRORS
#if GD32_CAN_REPORT_ALL_ERRORS
flags = (eventflags_t)(esr & 7);
if ((esr & CAN_ESR_LEC) > 0)
flags |= CAN_FRAMING_ERROR;
@ -330,7 +330,7 @@ static void can_lld_sce_handler(CANDriver *canp) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__)
#if GD32_CAN_USE_CAN1 || defined(__DOXYGEN__)
#if defined(GD32_CAN0_UNIFIED_HANDLER)
/**
* @brief CAN1 unified interrupt handler.
@ -419,9 +419,9 @@ OSAL_IRQ_HANDLER(GD32_CAN0_EWMC_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(GD32_CAN0_UNIFIED_HANDLER) */
#endif /* STM32_CAN_USE_CAN1 */
#endif /* GD32_CAN_USE_CAN1 */
#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__)
#if GD32_CAN_USE_CAN2 || defined(__DOXYGEN__)
#if defined(GD32_CAN1_UNIFIED_HANDLER)
/**
* @brief CAN1 unified interrupt handler.
@ -510,9 +510,9 @@ OSAL_IRQ_HANDLER(GD32_CAN1_EWMC_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(GD32_CAN1_UNIFIED_HANDLER) */
#endif /* STM32_CAN_USE_CAN2 */
#endif /* GD32_CAN_USE_CAN2 */
#if STM32_CAN_USE_CAN3 || defined(__DOXYGEN__)
#if GD32_CAN_USE_CAN3 || defined(__DOXYGEN__)
#if defined(GD32_CAN3_UNIFIED_HANDLER)
/**
* @brief CAN1 unified interrupt handler.
@ -601,7 +601,7 @@ OSAL_IRQ_HANDLER(GD32_CAN3_EWMC_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(GD32_CAN0_UNIFIED_HANDLER) */
#endif /* STM32_CAN_USE_CAN1 */
#endif /* GD32_CAN_USE_CAN1 */
/*===========================================================================*/
/* Driver exported functions. */
@ -614,60 +614,60 @@ OSAL_IRQ_HANDLER(GD32_CAN3_EWMC_HANDLER) {
*/
void can_lld_init(void) {
#if STM32_CAN_USE_CAN1
#if GD32_CAN_USE_CAN1
/* Driver initialization.*/
canObjectInit(&CAND1);
CAND1.can = CAN1;
#if defined(GD32_CAN0_UNIFIED_NUMBER)
eclicEnableVector(GD32_CAN0_UNIFIED_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY, STM32_CAN_CAN1_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN0_UNIFIED_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
#else
eclicEnableVector(GD32_CAN0_TX_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY, STM32_CAN_CAN1_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN0_RX0_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY, STM32_CAN_CAN1_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN0_RX1_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY, STM32_CAN_CAN1_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN0_EWMC_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY, STM32_CAN_CAN1_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN0_TX_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN0_RX0_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN0_RX1_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN0_EWMC_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
#endif
#endif
#if STM32_CAN_USE_CAN2
#if GD32_CAN_USE_CAN2
/* Driver initialization.*/
canObjectInit(&CAND2);
CAND2.can = CAN2;
#if defined(GD32_CAN1_UNIFIED_NUMBER)
eclicEnableVector(GD32_CAN1_UNIFIED_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY, STM32_CAN_CAN2_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN1_UNIFIED_NUMBER, GD32_CAN_CAN2_IRQ_PRIORITY, GD32_CAN_CAN2_IRQ_TRIGGER);
#else
eclicEnableVector(GD32_CAN1_TX_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY, STM32_CAN_CAN2_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN1_RX0_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY, STM32_CAN_CAN2_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN1_RX1_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY, STM32_CAN_CAN2_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN1_EWMC_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY, STM32_CAN_CAN2_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN1_TX_NUMBER, GD32_CAN_CAN2_IRQ_PRIORITY, GD32_CAN_CAN2_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN1_RX0_NUMBER, GD32_CAN_CAN2_IRQ_PRIORITY, GD32_CAN_CAN2_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN1_RX1_NUMBER, GD32_CAN_CAN2_IRQ_PRIORITY, GD32_CAN_CAN2_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN1_EWMC_NUMBER, GD32_CAN_CAN2_IRQ_PRIORITY, GD32_CAN_CAN2_IRQ_TRIGGER);
#endif
#endif
#if STM32_CAN_USE_CAN3
#if GD32_CAN_USE_CAN3
/* Driver initialization.*/
canObjectInit(&CAND3);
CAND3.can = CAN3;
#if defined(GD32_CAN3_UNIFIED_NUMBER)
eclicEnableVector(GD32_CAN3_UNIFIED_NUMBER, STM32_CAN_CAN3_IRQ_PRIORITY, STM32_CAN_CAN3_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN3_UNIFIED_NUMBER, GD32_CAN_CAN3_IRQ_PRIORITY, GD32_CAN_CAN3_IRQ_TRIGGER);
#else
eclicEnableVector(GD32_CAN3_TX_NUMBER, STM32_CAN_CAN3_IRQ_PRIORITY, STM32_CAN_CAN3_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN3_RX0_NUMBER, STM32_CAN_CAN3_IRQ_PRIORITY, STM32_CAN_CAN3_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN3_RX1_NUMBER, STM32_CAN_CAN3_IRQ_PRIORITY, STM32_CAN_CAN3_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN3_EWMC_NUMBER, STM32_CAN_CAN3_IRQ_PRIORITY, STM32_CAN_CAN3_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN3_TX_NUMBER, GD32_CAN_CAN3_IRQ_PRIORITY, GD32_CAN_CAN3_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN3_RX0_NUMBER, GD32_CAN_CAN3_IRQ_PRIORITY, GD32_CAN_CAN3_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN3_RX1_NUMBER, GD32_CAN_CAN3_IRQ_PRIORITY, GD32_CAN_CAN3_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN3_EWMC_NUMBER, GD32_CAN_CAN3_IRQ_PRIORITY, GD32_CAN_CAN3_IRQ_TRIGGER);
#endif
#endif
/* Filters initialization.*/
#if STM32_CAN_USE_CAN1
#if STM32_HAS_CAN2
can_lld_set_filters(&CAND1, STM32_CAN_MAX_FILTERS / 2, 0, NULL);
#if GD32_CAN_USE_CAN1
#if GD32_HAS_CAN2
can_lld_set_filters(&CAND1, GD32_CAN_MAX_FILTERS / 2, 0, NULL);
#else
can_lld_set_filters(&CAND1, STM32_CAN_MAX_FILTERS, 0, NULL);
can_lld_set_filters(&CAND1, GD32_CAN_MAX_FILTERS, 0, NULL);
#endif
#endif
#if STM32_HAS_CAN3
#if STM32_CAN_USE_CAN3
can_lld_set_filters(&CAND3, STM32_CAN3_MAX_FILTERS, 0, NULL);
#if GD32_HAS_CAN3
#if GD32_CAN_USE_CAN3
can_lld_set_filters(&CAND3, GD32_CAN3_MAX_FILTERS, 0, NULL);
#endif
#endif
}
@ -682,20 +682,20 @@ void can_lld_init(void) {
void can_lld_start(CANDriver *canp) {
/* Clock activation.*/
#if STM32_CAN_USE_CAN1
#if GD32_CAN_USE_CAN1
if (&CAND1 == canp) {
rccEnableCAN1(true);
}
#endif
#if STM32_CAN_USE_CAN2
#if GD32_CAN_USE_CAN2
if (&CAND2 == canp) {
rccEnableCAN1(true); /* CAN 2 requires CAN1, so enabling it first.*/
rccEnableCAN2(true);
}
#endif
#if STM32_CAN_USE_CAN3
#if GD32_CAN_USE_CAN3
if (&CAND3 == canp) {
rccEnableCAN3(true);
}
@ -709,7 +709,7 @@ void can_lld_start(CANDriver *canp) {
canp->can->MCR = canp->config->mcr;
/* Interrupt sources initialization.*/
#if STM32_CAN_REPORT_ALL_ERRORS
#if GD32_CAN_REPORT_ALL_ERRORS
canp->can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 |
CAN_IER_WKUIE | CAN_IER_ERRIE | CAN_IER_LECIE |
CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE |
@ -733,11 +733,11 @@ void can_lld_stop(CANDriver *canp) {
/* If in ready state then disables the CAN peripheral.*/
if (canp->state == CAN_READY) {
#if STM32_CAN_USE_CAN1
#if GD32_CAN_USE_CAN1
if (&CAND1 == canp) {
CAN1->MCR = 0x00010002; /* Register reset value. */
CAN1->IER = 0x00000000; /* All sources disabled. */
#if STM32_CAN_USE_CAN2
#if GD32_CAN_USE_CAN2
/* If CAND2 is stopped then CAN1 clock is stopped here.*/
if (CAND2.state == CAN_STOP)
#endif
@ -747,11 +747,11 @@ void can_lld_stop(CANDriver *canp) {
}
#endif
#if STM32_CAN_USE_CAN2
#if GD32_CAN_USE_CAN2
if (&CAND2 == canp) {
CAN2->MCR = 0x00010002; /* Register reset value. */
CAN2->IER = 0x00000000; /* All sources disabled. */
#if STM32_CAN_USE_CAN1
#if GD32_CAN_USE_CAN1
/* If CAND1 is stopped then CAN1 clock is stopped here.*/
if (CAND1.state == CAN_STOP)
#endif
@ -762,7 +762,7 @@ void can_lld_stop(CANDriver *canp) {
}
#endif
#if STM32_CAN_USE_CAN3
#if GD32_CAN_USE_CAN3
if (&CAND3 == canp) {
CAN3->MCR = 0x00010002; /* Register reset value. */
CAN3->IER = 0x00000000; /* All sources disabled. */
@ -1000,27 +1000,27 @@ void can_lld_wakeup(CANDriver *canp) {
void canSTM32SetFilters(CANDriver *canp, uint32_t can2sb,
uint32_t num, const CANFilter *cfp) {
#if STM32_CAN_USE_CAN2
osalDbgCheck((can2sb <= STM32_CAN_MAX_FILTERS) &&
(num <= STM32_CAN_MAX_FILTERS));
#if GD32_CAN_USE_CAN2
osalDbgCheck((can2sb <= GD32_CAN_MAX_FILTERS) &&
(num <= GD32_CAN_MAX_FILTERS));
#endif
#if STM32_CAN_USE_CAN1
#if GD32_CAN_USE_CAN1
osalDbgAssert(CAND1.state == CAN_STOP, "invalid state");
#endif
#if STM32_CAN_USE_CAN2
#if GD32_CAN_USE_CAN2
osalDbgAssert(CAND2.state == CAN_STOP, "invalid state");
#endif
#if STM32_CAN_USE_CAN3
#if GD32_CAN_USE_CAN3
osalDbgAssert(CAND3.state == CAN_STOP, "invalid state");
#endif
#if STM32_CAN_USE_CAN1
#if GD32_CAN_USE_CAN1
if (canp == &CAND1) {
can_lld_set_filters(canp, can2sb, num, cfp);
}
#endif
#if STM32_CAN_USE_CAN3
#if GD32_CAN_USE_CAN3
if (canp == &CAND3) {
can_lld_set_filters(canp, can2sb, num, cfp);
}

64
os/hal/ports/GD/GD32VF103/CAN/hal_can_lld.h
View File

@ -84,55 +84,55 @@
* @brief CAN pedantic errors report.
* @details Use of this option is IRQ-intensive.
*/
#if !defined(STM32_CAN_REPORT_ALL_ERRORS) || defined(__DOXYGEN__)
#define STM32_CAN_REPORT_ALL_ERRORS FALSE
#if !defined(GD32_CAN_REPORT_ALL_ERRORS) || defined(__DOXYGEN__)
#define GD32_CAN_REPORT_ALL_ERRORS FALSE
#endif
/**
* @brief CAN1 driver enable switch.
* @details If set to @p TRUE the support for CAN1 is included.
*/
#if !defined(STM32_CAN_USE_CAN1) || defined(__DOXYGEN__)
#define STM32_CAN_USE_CAN1 FALSE
#if !defined(GD32_CAN_USE_CAN1) || defined(__DOXYGEN__)
#define GD32_CAN_USE_CAN1 FALSE
#endif
/**
* @brief CAN2 driver enable switch.
* @details If set to @p TRUE the support for CAN2 is included.
*/
#if !defined(STM32_CAN_USE_CAN2) || defined(__DOXYGEN__)
#define STM32_CAN_USE_CAN2 FALSE
#if !defined(GD32_CAN_USE_CAN2) || defined(__DOXYGEN__)
#define GD32_CAN_USE_CAN2 FALSE
#endif
/**
* @brief CAN3 driver enable switch.
* @details If set to @p TRUE the support for CAN3 is included.
*/
#if !defined(STM32_CAN_USE_CAN3) || defined(__DOXYGEN__)
#define STM32_CAN_USE_CAN3 FALSE
#if !defined(GD32_CAN_USE_CAN3) || defined(__DOXYGEN__)
#define GD32_CAN_USE_CAN3 FALSE
#endif
/**
* @brief CAN1 interrupt priority level setting.
*/
#if !defined(STM32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#if !defined(GD32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_CAN_CAN1_IRQ_PRIORITY 11
#endif
/** @} */
/**
* @brief CAN2 interrupt priority level setting.
*/
#if !defined(STM32_CAN_CAN2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
#if !defined(GD32_CAN_CAN2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_CAN_CAN2_IRQ_PRIORITY 11
#endif
/** @} */
/**
* @brief CAN3 interrupt priority level setting.
*/
#if !defined(STM32_CAN_CAN3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_CAN_CAN3_IRQ_PRIORITY 11
#if !defined(GD32_CAN_CAN3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_CAN_CAN3_IRQ_PRIORITY 11
#endif
/** @} */
@ -140,43 +140,43 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !defined(STM32_HAS_CAN1)
#error "STM32_HAS_CAN1 not defined in registry"
#if !defined(GD32_HAS_CAN1)
#error "GD32_HAS_CAN1 not defined in registry"
#endif
#if !defined(STM32_HAS_CAN2)
#error "STM32_HAS_CAN2 not defined in registry"
#if !defined(GD32_HAS_CAN2)
#error "GD32_HAS_CAN2 not defined in registry"
#endif
#if !defined(STM32_HAS_CAN3)
#error "STM32_HAS_CAN3 not defined in registry"
#if !defined(GD32_HAS_CAN3)
#error "GD32_HAS_CAN3 not defined in registry"
#endif
#if (STM32_HAS_CAN1 | STM32_HAS_CAN2) && !defined(STM32_CAN_MAX_FILTERS)
#error "STM32_CAN_MAX_FILTERS not defined in registry"
#if (GD32_HAS_CAN1 | GD32_HAS_CAN2) && !defined(GD32_CAN_MAX_FILTERS)
#error "GD32_CAN_MAX_FILTERS not defined in registry"
#endif
#if STM32_HAS_CAN3 && !defined(STM32_CAN3_MAX_FILTERS)
#error "STM32_CAN3_MAX_FILTERS not defined in registry"
#if GD32_HAS_CAN3 && !defined(GD32_CAN3_MAX_FILTERS)
#error "GD32_CAN3_MAX_FILTERS not defined in registry"
#endif
#if STM32_CAN_USE_CAN1 && !STM32_HAS_CAN1
#if GD32_CAN_USE_CAN1 && !GD32_HAS_CAN1
#error "CAN1 not present in the selected device"
#endif
#if STM32_CAN_USE_CAN2 && !STM32_HAS_CAN2
#if GD32_CAN_USE_CAN2 && !GD32_HAS_CAN2
#error "CAN2 not present in the selected device"
#endif
#if STM32_CAN_USE_CAN3 && !STM32_HAS_CAN3
#if GD32_CAN_USE_CAN3 && !GD32_HAS_CAN3
#error "CAN2 not present in the selected device"
#endif
#if !STM32_CAN_USE_CAN1 && !STM32_CAN_USE_CAN2 && !STM32_CAN_USE_CAN3
#if !GD32_CAN_USE_CAN1 && !GD32_CAN_USE_CAN2 && !GD32_CAN_USE_CAN3
#error "CAN driver activated but no CAN peripheral assigned"
#endif
#if !STM32_CAN_USE_CAN1 && STM32_CAN_USE_CAN2
#if !GD32_CAN_USE_CAN1 && GD32_CAN_USE_CAN2
#error "CAN2 requires CAN1, it cannot operate independently"
#endif
@ -426,15 +426,15 @@ struct CANDriver {
/* External declarations. */
/*===========================================================================*/
#if STM32_CAN_USE_CAN1 && !defined(__DOXYGEN__)
#if GD32_CAN_USE_CAN1 && !defined(__DOXYGEN__)
extern CANDriver CAND1;
#endif
#if STM32_CAN_USE_CAN2 && !defined(__DOXYGEN__)
#if GD32_CAN_USE_CAN2 && !defined(__DOXYGEN__)
extern CANDriver CAND2;
#endif
#if STM32_CAN_USE_CAN3 && !defined(__DOXYGEN__)
#if GD32_CAN_USE_CAN3 && !defined(__DOXYGEN__)
extern CANDriver CAND3;
#endif

312
os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.c
View File

@ -36,36 +36,36 @@
#endif
#define DAC1_CH1_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH1_DMA_STREAM, \
STM32_DAC1_CH1_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_DAC_DAC1_CH1_DMA_STREAM, \
GD32_DAC1_CH1_DMA_CHN)
#define DAC1_CH2_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH2_DMA_STREAM, \
STM32_DAC1_CH2_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_DAC_DAC1_CH2_DMA_STREAM, \
GD32_DAC1_CH2_DMA_CHN)
#define DAC2_CH1_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH1_DMA_STREAM, \
STM32_DAC2_CH1_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_DAC_DAC2_CH1_DMA_STREAM, \
GD32_DAC2_CH1_DMA_CHN)
#define DAC2_CH2_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH2_DMA_STREAM, \
STM32_DAC2_CH2_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_DAC_DAC2_CH2_DMA_STREAM, \
GD32_DAC2_CH2_DMA_CHN)
#define DAC3_CH1_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC_DAC3_CH1_DMA_STREAM, \
STM32_DAC3_CH1_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_DAC_DAC3_CH1_DMA_STREAM, \
GD32_DAC3_CH1_DMA_CHN)
#define DAC3_CH2_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC_DAC3_CH2_DMA_STREAM, \
STM32_DAC3_CH2_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_DAC_DAC3_CH2_DMA_STREAM, \
GD32_DAC3_CH2_DMA_CHN)
#define DAC4_CH1_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC_DAC4_CH1_DMA_STREAM, \
STM32_DAC4_CH1_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_DAC_DAC4_CH1_DMA_STREAM, \
GD32_DAC4_CH1_DMA_CHN)
#define DAC4_CH2_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_DAC_DAC4_CH2_DMA_STREAM, \
STM32_DAC4_CH2_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_DAC_DAC4_CH2_DMA_STREAM, \
GD32_DAC4_CH2_DMA_CHN)
#define CHANNEL_DATA_OFFSET 3U
@ -74,42 +74,42 @@
/*===========================================================================*/
/** @brief DAC1 CH1 driver identifier.*/
#if STM32_DAC_USE_DAC1_CH1 || defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC1_CH1 || defined(__DOXYGEN__)
DACDriver DACD1;
#endif
/** @brief DAC1 CH2 driver identifier.*/
#if (STM32_DAC_USE_DAC1_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
#if (GD32_DAC_USE_DAC1_CH2 && !GD32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
DACDriver DACD2;
#endif
/** @brief DAC2 CH1 driver identifier.*/
#if STM32_DAC_USE_DAC2_CH1 || defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC2_CH1 || defined(__DOXYGEN__)
DACDriver DACD3;
#endif
/** @brief DAC2 CH2 driver identifier.*/
#if (STM32_DAC_USE_DAC2_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
#if (GD32_DAC_USE_DAC2_CH2 && !GD32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
DACDriver DACD4;
#endif
/** @brief DAC3 CH1 driver identifier.*/
#if STM32_DAC_USE_DAC3_CH1 || defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC3_CH1 || defined(__DOXYGEN__)
DACDriver DACD5;
#endif
/** @brief DAC3 CH2 driver identifier.*/
#if (STM32_DAC_USE_DAC3_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
#if (GD32_DAC_USE_DAC3_CH2 && !GD32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
DACDriver DACD6;
#endif
/** @brief DAC4 CH1 driver identifier.*/
#if STM32_DAC_USE_DAC4_CH1 || defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC4_CH1 || defined(__DOXYGEN__)
DACDriver DACD7;
#endif
/** @brief DAC4 CH2 driver identifier.*/
#if (STM32_DAC_USE_DAC4_CH2 && !STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
#if (GD32_DAC_USE_DAC4_CH2 && !GD32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
DACDriver DACD8;
#endif
@ -117,155 +117,155 @@ DACDriver DACD8;
/* Driver local variables. */
/*===========================================================================*/
#if STM32_DAC_USE_DAC1_CH1 == TRUE
#if GD32_DAC_USE_DAC1_CH1 == TRUE
static const dacparams_t dac1_ch1_params = {
.dac = DAC1,
.dataoffset = 0U,
.regshift = 0U,
.regmask = 0xFFFF0000U,
.dmastream = STM32_DAC_DAC1_CH1_DMA_STREAM,
#if STM32_DMA_SUPPORTS_DMAMUX
.peripheral = STM32_DMAMUX1_DAC1_CH1,
.dmastream = GD32_DAC_DAC1_CH1_DMA_STREAM,
#if GD32_DMA_SUPPORTS_DMAMUX
.peripheral = GD32_DMAMUX1_DAC1_CH1,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
.dmairqprio = STM32_DAC_DAC1_CH1_IRQ_PRIORITY
.dmamode = GD32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_DAC_DAC1_CH1_DMA_PRIORITY) |
GD32_DMA_CR_MINC | GD32_DMA_CR_CIRC | GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE | GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE,
.dmairqprio = GD32_DAC_DAC1_CH1_IRQ_PRIORITY
};
#endif
#if STM32_DAC_USE_DAC1_CH2 == TRUE
#if GD32_DAC_USE_DAC1_CH2 == TRUE
static const dacparams_t dac1_ch2_params = {
.dac = DAC1,
.dataoffset = CHANNEL_DATA_OFFSET,
.regshift = 16U,
.regmask = 0x0000FFFFU,
.dmastream = STM32_DAC_DAC1_CH2_DMA_STREAM,
#if STM32_DMA_SUPPORTS_DMAMUX
.peripheral = STM32_DMAMUX1_DAC1_CH2,
.dmastream = GD32_DAC_DAC1_CH2_DMA_STREAM,
#if GD32_DMA_SUPPORTS_DMAMUX
.peripheral = GD32_DMAMUX1_DAC1_CH2,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC1_CH2_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
.dmairqprio = STM32_DAC_DAC1_CH2_IRQ_PRIORITY
.dmamode = GD32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_DAC_DAC1_CH2_DMA_PRIORITY) |
GD32_DMA_CR_MINC | GD32_DMA_CR_CIRC | GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE | GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE,
.dmairqprio = GD32_DAC_DAC1_CH2_IRQ_PRIORITY
};
#endif
#if STM32_DAC_USE_DAC2_CH1 == TRUE
#if GD32_DAC_USE_DAC2_CH1 == TRUE
static const dacparams_t dac2_ch1_params = {
.dac = DAC2,
.dataoffset = 0U,
.regshift = 0U,
.regmask = 0xFFFF0000U,
.dmastream = STM32_DAC_DAC2_CH1_DMA_STREAM,
#if STM32_DMA_SUPPORTS_DMAMUX
.peripheral = STM32_DMAMUX1_DAC2_CH1,
.dmastream = GD32_DAC_DAC2_CH1_DMA_STREAM,
#if GD32_DMA_SUPPORTS_DMAMUX
.peripheral = GD32_DMAMUX1_DAC2_CH1,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC2_CH1_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
.dmairqprio = STM32_DAC_DAC2_CH1_IRQ_PRIORITY
.dmamode = GD32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_DAC_DAC2_CH1_DMA_PRIORITY) |
GD32_DMA_CR_MINC | GD32_DMA_CR_CIRC | GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE | GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE,
.dmairqprio = GD32_DAC_DAC2_CH1_IRQ_PRIORITY
};
#endif
#if STM32_DAC_USE_DAC2_CH2 == TRUE
#if GD32_DAC_USE_DAC2_CH2 == TRUE
static const dacparams_t dac2_ch2_params = {
.dac = DAC2,
.dataoffset = CHANNEL_DATA_OFFSET,
.regshift = 16U,
.regmask = 0x0000FFFFU,
.dmastream = STM32_DAC_DAC2_CH2_DMA_STREAM,
#if STM32_DMA_SUPPORTS_DMAMUX
.peripheral = STM32_DMAMUX1_DAC2_CH2,
.dmastream = GD32_DAC_DAC2_CH2_DMA_STREAM,
#if GD32_DMA_SUPPORTS_DMAMUX
.peripheral = GD32_DMAMUX1_DAC2_CH2,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC2_CH2_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
.dmairqprio = STM32_DAC_DAC2_CH2_IRQ_PRIORITY
.dmamode = GD32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_DAC_DAC2_CH2_DMA_PRIORITY) |
GD32_DMA_CR_MINC | GD32_DMA_CR_CIRC | GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE | GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE,
.dmairqprio = GD32_DAC_DAC2_CH2_IRQ_PRIORITY
};
#endif
#if STM32_DAC_USE_DAC3_CH1 == TRUE
#if GD32_DAC_USE_DAC3_CH1 == TRUE
static const dacparams_t dac3_ch1_params = {
.dac = DAC3,
.dataoffset = 0U,
.regshift = 0U,
.regmask = 0xFFFF0000U,
.dmastream = STM32_DAC_DAC3_CH1_DMA_STREAM,
#if STM32_DMA_SUPPORTS_DMAMUX
.peripheral = STM32_DMAMUX1_DAC3_CH1,
.dmastream = GD32_DAC_DAC3_CH1_DMA_STREAM,
#if GD32_DMA_SUPPORTS_DMAMUX
.peripheral = GD32_DMAMUX1_DAC3_CH1,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC3_CH1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC3_CH1_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
.dmairqprio = STM32_DAC_DAC3_CH1_IRQ_PRIORITY
.dmamode = GD32_DMA_CR_CHSEL(DAC3_CH1_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_DAC_DAC3_CH1_DMA_PRIORITY) |
GD32_DMA_CR_MINC | GD32_DMA_CR_CIRC | GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE | GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE,
.dmairqprio = GD32_DAC_DAC3_CH1_IRQ_PRIORITY
};
#endif
#if STM32_DAC_USE_DAC3_CH2 == TRUE
#if GD32_DAC_USE_DAC3_CH2 == TRUE
static const dacparams_t dac3_ch2_params = {
.dac = DAC3,
.dataoffset = CHANNEL_DATA_OFFSET,
.regshift = 16U,
.regmask = 0x0000FFFFU,
.dmastream = STM32_DAC_DAC3_CH2_DMA_STREAM,
#if STM32_DMA_SUPPORTS_DMAMUX
.peripheral = STM32_DMAMUX1_DAC3_CH2,
.dmastream = GD32_DAC_DAC3_CH2_DMA_STREAM,
#if GD32_DMA_SUPPORTS_DMAMUX
.peripheral = GD32_DMAMUX1_DAC3_CH2,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC3_CH2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC3_CH2_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
.dmairqprio = STM32_DAC_DAC3_CH2_IRQ_PRIORITY
.dmamode = GD32_DMA_CR_CHSEL(DAC3_CH2_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_DAC_DAC3_CH2_DMA_PRIORITY) |
GD32_DMA_CR_MINC | GD32_DMA_CR_CIRC | GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE | GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE,
.dmairqprio = GD32_DAC_DAC3_CH2_IRQ_PRIORITY
};
#endif
#if STM32_DAC_USE_DAC4_CH1 == TRUE
#if GD32_DAC_USE_DAC4_CH1 == TRUE
static const dacparams_t dac4_ch1_params = {
.dac = DAC4,
.dataoffset = 0U,
.regshift = 0U,
.regmask = 0xFFFF0000U,
.dmastream = STM32_DAC_DAC4_CH1_DMA_STREAM,
#if STM32_DMA_SUPPORTS_DMAMUX
.peripheral = STM32_DMAMUX1_DAC4_CH1,
.dmastream = GD32_DAC_DAC4_CH1_DMA_STREAM,
#if GD32_DMA_SUPPORTS_DMAMUX
.peripheral = GD32_DMAMUX1_DAC4_CH1,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC4_CH1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC4_CH1_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
.dmairqprio = STM32_DAC_DAC4_CH1_IRQ_PRIORITY
.dmamode = GD32_DMA_CR_CHSEL(DAC4_CH1_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_DAC_DAC4_CH1_DMA_PRIORITY) |
GD32_DMA_CR_MINC | GD32_DMA_CR_CIRC | GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE | GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE,
.dmairqprio = GD32_DAC_DAC4_CH1_IRQ_PRIORITY
};
#endif
#if STM32_DAC_USE_DAC4_CH2 == TRUE
#if GD32_DAC_USE_DAC4_CH2 == TRUE
static const dacparams_t dac4_ch2_params = {
.dac = DAC4,
.dataoffset = CHANNEL_DATA_OFFSET,
.regshift = 16U,
.regmask = 0x0000FFFFU,
.dmastream = STM32_DAC_DAC4_CH2_DMA_STREAM,
#if STM32_DMA_SUPPORTS_DMAMUX
.peripheral = STM32_DMAMUX1_DAC4_CH2,
.dmastream = GD32_DAC_DAC4_CH2_DMA_STREAM,
#if GD32_DMA_SUPPORTS_DMAMUX
.peripheral = GD32_DMAMUX1_DAC4_CH2,
#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC4_CH2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC4_CH2_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
.dmairqprio = STM32_DAC_DAC4_CH2_IRQ_PRIORITY
.dmamode = GD32_DMA_CR_CHSEL(DAC4_CH2_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_DAC_DAC4_CH2_DMA_PRIORITY) |
GD32_DMA_CR_MINC | GD32_DMA_CR_CIRC | GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE | GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE,
.dmairqprio = GD32_DAC_DAC4_CH2_IRQ_PRIORITY
};
#endif
@ -281,17 +281,17 @@ static const dacparams_t dac4_ch2_params = {
*/
static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
if ((flags & (GD32_DMA_ISR_TEIF | GD32_DMA_ISR_DMEIF)) != 0) {
/* DMA errors handling.*/
dac_lld_stop_conversion(dacp);
_dac_isr_error_code(dacp, DAC_ERR_DMAFAILURE);
}
else {
if ((flags & STM32_DMA_ISR_HTIF) != 0) {
if ((flags & GD32_DMA_ISR_HTIF) != 0) {
/* Half transfer processing.*/
_dac_isr_half_code(dacp);
}
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
if ((flags & GD32_DMA_ISR_TCIF) != 0) {
/* Transfer complete processing.*/
_dac_isr_full_code(dacp);
}
@ -313,49 +313,49 @@ static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
*/
void dac_lld_init(void) {
#if STM32_DAC_USE_DAC1_CH1
#if GD32_DAC_USE_DAC1_CH1
dacObjectInit(&DACD1);
DACD1.params = &dac1_ch1_params;
DACD1.dma = NULL;
#endif
#if STM32_DAC_USE_DAC1_CH2
#if GD32_DAC_USE_DAC1_CH2
dacObjectInit(&DACD2);
DACD2.params = &dac1_ch2_params;
DACD2.dma = NULL;
#endif
#if STM32_DAC_USE_DAC2_CH1
#if GD32_DAC_USE_DAC2_CH1
dacObjectInit(&DACD3);
DACD3.params = &dac2_ch1_params;
DACD3.dma = NULL;
#endif
#if STM32_DAC_USE_DAC2_CH2
#if GD32_DAC_USE_DAC2_CH2
dacObjectInit(&DACD4);
DACD4.params = &dac2_ch2_params;
DACD4.dma = NULL;
#endif
#if STM32_DAC_USE_DAC3_CH1
#if GD32_DAC_USE_DAC3_CH1
dacObjectInit(&DACD5);
DACD5.params = &dac3_ch1_params;
DACD5.dma = NULL;
#endif
#if STM32_DAC_USE_DAC3_CH2
#if GD32_DAC_USE_DAC3_CH2
dacObjectInit(&DACD6);
DACD6.params = &dac3_ch2_params;
DACD6.dma = NULL;
#endif
#if STM32_DAC_USE_DAC4_CH1
#if GD32_DAC_USE_DAC4_CH1
dacObjectInit(&DACD7);
DACD7.params = &dac4_ch1_params;
DACD7.dma = NULL;
#endif
#if STM32_DAC_USE_DAC4_CH2
#if GD32_DAC_USE_DAC4_CH2
dacObjectInit(&DACD8);
DACD8.params = &dac4_ch2_params;
DACD8.dma = NULL;
@ -377,52 +377,52 @@ void dac_lld_start(DACDriver *dacp) {
dacchannel_t channel = 0;
/* Enabling the clock source.*/
#if STM32_DAC_USE_DAC1_CH1
#if GD32_DAC_USE_DAC1_CH1
if (&DACD1 == dacp) {
rccEnableDAC1(true);
}
#endif
#if STM32_DAC_USE_DAC1_CH2
#if GD32_DAC_USE_DAC1_CH2
if (&DACD2 == dacp) {
rccEnableDAC1(true);
channel = 1;
}
#endif
#if STM32_DAC_USE_DAC2_CH1
#if GD32_DAC_USE_DAC2_CH1
if (&DACD3 == dacp) {
rccEnableDAC2(true);
}
#endif
#if STM32_DAC_USE_DAC2_CH2
#if GD32_DAC_USE_DAC2_CH2
if (&DACD4 == dacp) {
rccEnableDAC2(true);
channel = 1;
}
#endif
#if STM32_DAC_USE_DAC3_CH1
#if GD32_DAC_USE_DAC3_CH1
if (&DACD5 == dacp) {
rccEnableDAC3(true);
}
#endif
#if STM32_DAC_USE_DAC3_CH2
#if GD32_DAC_USE_DAC3_CH2
if (&DACD6 == dacp) {
rccEnableDAC3(true);
channel = 1;
}
#endif
#if STM32_DAC_USE_DAC4_CH1
#if GD32_DAC_USE_DAC4_CH1
if (&DACD7 == dacp) {
rccEnableDAC4(true);
}
#endif
#if STM32_DAC_USE_DAC4_CH2
#if GD32_DAC_USE_DAC4_CH2
if (&DACD8 == dacp) {
rccEnableDAC4(true);
channel = 1;
@ -431,7 +431,7 @@ void dac_lld_start(DACDriver *dacp) {
/* Enabling DAC in SW triggering mode initially, initializing data to
zero.*/
#if STM32_DAC_DUAL_MODE == FALSE
#if GD32_DAC_DUAL_MODE == FALSE
{
uint32_t cr;
@ -471,7 +471,7 @@ void dac_lld_stop(DACDriver *dacp) {
/* Disabling DAC.*/
dacp->params->dac->CR &= dacp->params->regmask;
#if STM32_DAC_USE_DAC1_CH1
#if GD32_DAC_USE_DAC1_CH1
if (&DACD1 == dacp) {
if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
rccDisableDAC1();
@ -479,7 +479,7 @@ void dac_lld_stop(DACDriver *dacp) {
}
#endif
#if STM32_DAC_USE_DAC1_CH2
#if GD32_DAC_USE_DAC1_CH2
if (&DACD2 == dacp) {
if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
rccDisableDAC1();
@ -487,7 +487,7 @@ void dac_lld_stop(DACDriver *dacp) {
}
#endif
#if STM32_DAC_USE_DAC2_CH1
#if GD32_DAC_USE_DAC2_CH1
if (&DACD3 == dacp) {
if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
rccDisableDAC2();
@ -495,7 +495,7 @@ void dac_lld_stop(DACDriver *dacp) {
}
#endif
#if STM32_DAC_USE_DAC2_CH2
#if GD32_DAC_USE_DAC2_CH2
if (&DACD4 == dacp) {
if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
rccDisableDAC2();
@ -503,7 +503,7 @@ void dac_lld_stop(DACDriver *dacp) {
}
#endif
#if STM32_DAC_USE_DAC3_CH1
#if GD32_DAC_USE_DAC3_CH1
if (&DACD5 == dacp) {
if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
rccDisableDAC3();
@ -511,7 +511,7 @@ void dac_lld_stop(DACDriver *dacp) {
}
#endif
#if STM32_DAC_USE_DAC3_CH2
#if GD32_DAC_USE_DAC3_CH2
if (&DACD6 == dacp) {
if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
rccDisableDAC3();
@ -519,7 +519,7 @@ void dac_lld_stop(DACDriver *dacp) {
}
#endif
#if STM32_DAC_USE_DAC4_CH1
#if GD32_DAC_USE_DAC4_CH1
if (&DACD7 == dacp) {
if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
rccDisableDAC4();
@ -527,7 +527,7 @@ void dac_lld_stop(DACDriver *dacp) {
}
#endif
#if STM32_DAC_USE_DAC4_CH2
#if GD32_DAC_USE_DAC4_CH2
if (&DACD8 == dacp) {
if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
rccDisableDAC4();
@ -552,54 +552,54 @@ void dac_lld_put_channel(DACDriver *dacp,
switch (dacp->config->datamode) {
case DAC_DHRM_12BIT_RIGHT:
#if STM32_DAC_DUAL_MODE
#if GD32_DAC_DUAL_MODE
case DAC_DHRM_12BIT_RIGHT_DUAL:
#endif
if (channel == 0U) {
#if STM32_DAC_DUAL_MODE
#if GD32_DAC_DUAL_MODE
dacp->params->dac->DHR12R1 = (uint32_t)sample;
#else
*(&dacp->params->dac->DHR12R1 + dacp->params->dataoffset) = (uint32_t)sample;
#endif
}
#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2 || \
STM32_HAS_DAC3_CH2 || STM32_HAS_DAC4_CH2)
#if (GD32_HAS_DAC1_CH2 || GD32_HAS_DAC2_CH2 || \
GD32_HAS_DAC3_CH2 || GD32_HAS_DAC4_CH2)
else {
dacp->params->dac->DHR12R2 = (uint32_t)sample;
}
#endif
break;
case DAC_DHRM_12BIT_LEFT:
#if STM32_DAC_DUAL_MODE
#if GD32_DAC_DUAL_MODE
case DAC_DHRM_12BIT_LEFT_DUAL:
#endif
if (channel == 0U) {
#if STM32_DAC_DUAL_MODE
#if GD32_DAC_DUAL_MODE
dacp->params->dac->DHR12L1 = (uint32_t)sample;
#else
*(&dacp->params->dac->DHR12L1 + dacp->params->dataoffset) = (uint32_t)sample;
#endif
}
#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2 || \
STM32_HAS_DAC3_CH2 || STM32_HAS_DAC4_CH2)
#if (GD32_HAS_DAC1_CH2 || GD32_HAS_DAC2_CH2 || \
GD32_HAS_DAC3_CH2 || GD32_HAS_DAC4_CH2)
else {
dacp->params->dac->DHR12L2 = (uint32_t)sample;
}
#endif
break;
case DAC_DHRM_8BIT_RIGHT:
#if STM32_DAC_DUAL_MODE
#if GD32_DAC_DUAL_MODE
case DAC_DHRM_8BIT_RIGHT_DUAL:
#endif
if (channel == 0U) {
#if STM32_DAC_DUAL_MODE
#if GD32_DAC_DUAL_MODE
dacp->params->dac->DHR8R1 = (uint32_t)sample;
#else
*(&dacp->params->dac->DHR8R1 + dacp->params->dataoffset) = (uint32_t)sample;
#endif
}
#if (STM32_HAS_DAC1_CH2 || STM32_HAS_DAC2_CH2 || \
STM32_HAS_DAC3_CH2 || STM32_HAS_DAC4_CH2)
#if (GD32_HAS_DAC1_CH2 || GD32_HAS_DAC2_CH2 || \
GD32_HAS_DAC3_CH2 || GD32_HAS_DAC4_CH2)
else {
dacp->params->dac->DHR8R2 = (uint32_t)sample;
}
@ -639,7 +639,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
(void *)dacp);
osalDbgAssert(dacp->dma != NULL, "unable to allocate stream");
#if STM32_DMA_SUPPORTS_DMAMUX
#if GD32_DMA_SUPPORTS_DMAMUX
dmaSetRequestSource(dacp->dma, dacp->params->peripheral);
#endif
@ -652,7 +652,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12R1 +
dacp->params->dataoffset);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
GD32_DMA_CR_PSIZE_HWORD | GD32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_12BIT_LEFT:
osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
@ -660,7 +660,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12L1 +
dacp->params->dataoffset);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
GD32_DMA_CR_PSIZE_HWORD | GD32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_8BIT_RIGHT:
osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
@ -668,19 +668,19 @@ void dac_lld_start_conversion(DACDriver *dacp) {
dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8R1 +
dacp->params->dataoffset);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
GD32_DMA_CR_PSIZE_BYTE | GD32_DMA_CR_MSIZE_BYTE;
/* In this mode the size of the buffer is halved because two samples
packed in a single dacsample_t element.*/
n = (n + 1) / 2;
break;
#if STM32_DAC_DUAL_MODE == TRUE
#if GD32_DAC_DUAL_MODE == TRUE
case DAC_DHRM_12BIT_RIGHT_DUAL:
osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12RD);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
GD32_DMA_CR_PSIZE_WORD | GD32_DMA_CR_MSIZE_WORD;
n /= 2;
break;
case DAC_DHRM_12BIT_LEFT_DUAL:
@ -688,7 +688,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12LD);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;
GD32_DMA_CR_PSIZE_WORD | GD32_DMA_CR_MSIZE_WORD;
n /= 2;
break;
case DAC_DHRM_8BIT_RIGHT_DUAL:
@ -696,7 +696,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8RD);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
GD32_DMA_CR_PSIZE_HWORD | GD32_DMA_CR_MSIZE_HWORD;
n /= 2;
break;
#endif
@ -708,14 +708,14 @@ void dac_lld_start_conversion(DACDriver *dacp) {
dmaStreamSetMemory0(dacp->dma, dacp->samples);
dmaStreamSetTransactionSize(dacp->dma, n);
dmaStreamSetMode(dacp->dma, dmamode |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_HTIE | STM32_DMA_CR_TCIE);
GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE |
GD32_DMA_CR_HTIE | GD32_DMA_CR_TCIE);
dmaStreamEnable(dacp->dma);
/* DAC configuration.*/
cr = dacp->params->dac->CR;
#if STM32_DAC_DUAL_MODE == FALSE
#if GD32_DAC_DUAL_MODE == FALSE
cr &= dacp->params->regmask;
cr |= (DAC_CR_DMAEN1 | (dacp->grpp->trigger << DAC_CR_TSEL1_Pos) | DAC_CR_TEN1 | DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift;
#else
@ -746,7 +746,7 @@ void dac_lld_stop_conversion(DACDriver *dacp) {
cr = dacp->params->dac->CR;
#if STM32_DAC_DUAL_MODE == FALSE
#if GD32_DAC_DUAL_MODE == FALSE
cr &= dacp->params->regmask;
cr |= (DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift;
#else

308
os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.h
View File

@ -51,8 +51,8 @@
* @brief Enables the DAC dual mode.
* @note In dual mode DAC second channels cannot be accessed individually.
*/
#if !defined(STM32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
#define STM32_DAC_DUAL_MODE FALSE
#if !defined(GD32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
#define GD32_DAC_DUAL_MODE FALSE
#endif
/**
@ -60,8 +60,8 @@
* @details If set to @p TRUE the support for DAC1 channel 1 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_DAC_USE_DAC1_CH1) || defined(__DOXYGEN__)
#define STM32_DAC_USE_DAC1_CH1 FALSE
#if !defined(GD32_DAC_USE_DAC1_CH1) || defined(__DOXYGEN__)
#define GD32_DAC_USE_DAC1_CH1 FALSE
#endif
/**
@ -69,8 +69,8 @@
* @details If set to @p TRUE the support for DAC1 channel 2 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_DAC_USE_DAC1_CH2) || defined(__DOXYGEN__)
#define STM32_DAC_USE_DAC1_CH2 FALSE
#if !defined(GD32_DAC_USE_DAC1_CH2) || defined(__DOXYGEN__)
#define GD32_DAC_USE_DAC1_CH2 FALSE
#endif
/**
@ -78,8 +78,8 @@
* @details If set to @p TRUE the support for DAC2 channel 1 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_DAC_USE_DAC2_CH1) || defined(__DOXYGEN__)
#define STM32_DAC_USE_DAC2_CH1 FALSE
#if !defined(GD32_DAC_USE_DAC2_CH1) || defined(__DOXYGEN__)
#define GD32_DAC_USE_DAC2_CH1 FALSE
#endif
/**
@ -87,8 +87,8 @@
* @details If set to @p TRUE the support for DAC2 channel 2 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_DAC_USE_DAC2_CH2) || defined(__DOXYGEN__)
#define STM32_DAC_USE_DAC2_CH2 FALSE
#if !defined(GD32_DAC_USE_DAC2_CH2) || defined(__DOXYGEN__)
#define GD32_DAC_USE_DAC2_CH2 FALSE
#endif
/**
@ -96,8 +96,8 @@
* @details If set to @p TRUE the support for DAC3 channel 1 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_DAC_USE_DAC3_CH1) || defined(__DOXYGEN__)
#define STM32_DAC_USE_DAC3_CH1 FALSE
#if !defined(GD32_DAC_USE_DAC3_CH1) || defined(__DOXYGEN__)
#define GD32_DAC_USE_DAC3_CH1 FALSE
#endif
/**
@ -105,8 +105,8 @@
* @details If set to @p TRUE the support for DAC3 channel 2 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_DAC_USE_DAC3_CH2) || defined(__DOXYGEN__)
#define STM32_DAC_USE_DAC3_CH2 FALSE
#if !defined(GD32_DAC_USE_DAC3_CH2) || defined(__DOXYGEN__)
#define GD32_DAC_USE_DAC3_CH2 FALSE
#endif
/**
@ -114,8 +114,8 @@
* @details If set to @p TRUE the support for DAC4 channel 1 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_DAC_USE_DAC4_CH1) || defined(__DOXYGEN__)
#define STM32_DAC_USE_DAC4_CH1 FALSE
#if !defined(GD32_DAC_USE_DAC4_CH1) || defined(__DOXYGEN__)
#define GD32_DAC_USE_DAC4_CH1 FALSE
#endif
/**
@ -123,120 +123,120 @@
* @details If set to @p TRUE the support for DAC4 channel 2 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_DAC_USE_DAC4_CH2) || defined(__DOXYGEN__)
#define STM32_DAC_USE_DAC4_CH2 FALSE
#if !defined(GD32_DAC_USE_DAC4_CH2) || defined(__DOXYGEN__)
#define GD32_DAC_USE_DAC4_CH2 FALSE
#endif
/**
* @brief DAC1 CH1 interrupt priority level setting.
*/
#if !defined(STM32_DAC_DAC1_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#if !defined(GD32_DAC_DAC1_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#endif
/**
* @brief DAC1 CH2 interrupt priority level setting.
*/
#if !defined(STM32_DAC_DAC1_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#if !defined(GD32_DAC_DAC1_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#endif
/**
* @brief DAC2 CH1 interrupt priority level setting.
*/
#if !defined(STM32_DAC_DAC2_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC2_CH1_IRQ_PRIORITY 10
#if !defined(GD32_DAC_DAC2_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC2_CH1_IRQ_PRIORITY 10
#endif
/**
* @brief DAC2 CH2 interrupt priority level setting.
*/
#if !defined(STM32_DAC_DAC2_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC2_CH2_IRQ_PRIORITY 10
#if !defined(GD32_DAC_DAC2_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC2_CH2_IRQ_PRIORITY 10
#endif
/**
* @brief DAC3 CH1 interrupt priority level setting.
*/
#if !defined(STM32_DAC_DAC3_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC3_CH1_IRQ_PRIORITY 10
#if !defined(GD32_DAC_DAC3_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC3_CH1_IRQ_PRIORITY 10
#endif
/**
* @brief DAC3 CH2 interrupt priority level setting.
*/
#if !defined(STM32_DAC_DAC3_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC3_CH2_IRQ_PRIORITY 10
#if !defined(GD32_DAC_DAC3_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC3_CH2_IRQ_PRIORITY 10
#endif
/**
* @brief DAC4 CH1 interrupt priority level setting.
*/
#if !defined(STM32_DAC_DAC4_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC4_CH1_IRQ_PRIORITY 10
#if !defined(GD32_DAC_DAC4_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC4_CH1_IRQ_PRIORITY 10
#endif
/**
* @brief DAC4 CH2 interrupt priority level setting.
*/
#if !defined(STM32_DAC_DAC4_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC4_CH2_IRQ_PRIORITY 10
#if !defined(GD32_DAC_DAC4_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC4_CH2_IRQ_PRIORITY 10
#endif
/**
* @brief DAC1 CH1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC_DAC1_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#if !defined(GD32_DAC_DAC1_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC1_CH1_DMA_PRIORITY 2
#endif
/**
* @brief DAC1 CH2 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC_DAC1_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#if !defined(GD32_DAC_DAC1_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC1_CH2_DMA_PRIORITY 2
#endif
/**
* @brief DAC2 CH1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC_DAC2_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC2_CH1_DMA_PRIORITY 2
#if !defined(GD32_DAC_DAC2_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC2_CH1_DMA_PRIORITY 2
#endif
/**
* @brief DAC2 CH2 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC_DAC2_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC2_CH2_DMA_PRIORITY 2
#if !defined(GD32_DAC_DAC2_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC2_CH2_DMA_PRIORITY 2
#endif
/**
* @brief DAC3 CH1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC_DAC3_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC3_CH1_DMA_PRIORITY 2
#if !defined(GD32_DAC_DAC3_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC3_CH1_DMA_PRIORITY 2
#endif
/**
* @brief DAC3 CH2 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC_DAC3_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC3_CH2_DMA_PRIORITY 2
#if !defined(GD32_DAC_DAC3_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC3_CH2_DMA_PRIORITY 2
#endif
/**
* @brief DAC4 CH1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC_DAC4_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC4_CH1_DMA_PRIORITY 2
#if !defined(GD32_DAC_DAC4_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC4_CH1_DMA_PRIORITY 2
#endif
/**
* @brief DAC4 CH2 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_DAC_DAC4_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_DAC_DAC4_CH2_DMA_PRIORITY 2
#if !defined(GD32_DAC_DAC4_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC4_CH2_DMA_PRIORITY 2
#endif
/** @} */
@ -245,249 +245,249 @@
/*===========================================================================*/
/* Handling missing registry keys.*/
#if !defined(STM32_HAS_DAC1_CH1)
#define STM32_HAS_DAC1_CH1 FALSE
#if !defined(GD32_HAS_DAC1_CH1)
#define GD32_HAS_DAC1_CH1 FALSE
#endif
#if !defined(STM32_HAS_DAC1_CH2)
#define STM32_HAS_DAC1_CH2 FALSE
#if !defined(GD32_HAS_DAC1_CH2)
#define GD32_HAS_DAC1_CH2 FALSE
#endif
#if !defined(STM32_HAS_DAC2_CH1)
#define STM32_HAS_DAC2_CH1 FALSE
#if !defined(GD32_HAS_DAC2_CH1)
#define GD32_HAS_DAC2_CH1 FALSE
#endif
#if !defined(STM32_HAS_DAC2_CH2)
#define STM32_HAS_DAC2_CH2 FALSE
#if !defined(GD32_HAS_DAC2_CH2)
#define GD32_HAS_DAC2_CH2 FALSE
#endif
#if !defined(STM32_HAS_DAC3_CH1)
#define STM32_HAS_DAC3_CH1 FALSE
#if !defined(GD32_HAS_DAC3_CH1)
#define GD32_HAS_DAC3_CH1 FALSE
#endif
#if !defined(STM32_HAS_DAC3_CH2)
#define STM32_HAS_DAC3_CH2 FALSE
#if !defined(GD32_HAS_DAC3_CH2)
#define GD32_HAS_DAC3_CH2 FALSE
#endif
#if !defined(STM32_HAS_DAC4_CH1)
#define STM32_HAS_DAC4_CH1 FALSE
#if !defined(GD32_HAS_DAC4_CH1)
#define GD32_HAS_DAC4_CH1 FALSE
#endif
#if !defined(STM32_HAS_DAC4_CH2)
#define STM32_HAS_DAC4_CH2 FALSE
#if !defined(GD32_HAS_DAC4_CH2)
#define GD32_HAS_DAC4_CH2 FALSE
#endif
#if STM32_DAC_USE_DAC1_CH1 && !STM32_HAS_DAC1_CH1
#if GD32_DAC_USE_DAC1_CH1 && !GD32_HAS_DAC1_CH1
#error "DAC1 CH1 not present in the selected device"
#endif
#if STM32_DAC_USE_DAC1_CH2 && !STM32_HAS_DAC1_CH2
#if GD32_DAC_USE_DAC1_CH2 && !GD32_HAS_DAC1_CH2
#error "DAC1 CH2 not present in the selected device"
#endif
#if STM32_DAC_USE_DAC2_CH1 && !STM32_HAS_DAC2_CH1
#if GD32_DAC_USE_DAC2_CH1 && !GD32_HAS_DAC2_CH1
#error "DAC2 CH1 not present in the selected device"
#endif
#if STM32_DAC_USE_DAC2_CH2 && !STM32_HAS_DAC2_CH2
#if GD32_DAC_USE_DAC2_CH2 && !GD32_HAS_DAC2_CH2
#error "DAC2 CH2 not present in the selected device"
#endif
#if STM32_DAC_USE_DAC3_CH1 && !STM32_HAS_DAC3_CH1
#if GD32_DAC_USE_DAC3_CH1 && !GD32_HAS_DAC3_CH1
#error "DAC3 CH1 not present in the selected device"
#endif
#if STM32_DAC_USE_DAC3_CH2 && !STM32_HAS_DAC3_CH2
#if GD32_DAC_USE_DAC3_CH2 && !GD32_HAS_DAC3_CH2
#error "DAC3 CH2 not present in the selected device"
#endif
#if STM32_DAC_USE_DAC4_CH1 && !STM32_HAS_DAC4_CH1
#if GD32_DAC_USE_DAC4_CH1 && !GD32_HAS_DAC4_CH1
#error "DAC4 CH1 not present in the selected device"
#endif
#if STM32_DAC_USE_DAC4_CH2 && !STM32_HAS_DAC4_CH2
#if GD32_DAC_USE_DAC4_CH2 && !GD32_HAS_DAC4_CH2
#error "DAC4 CH2 not present in the selected device"
#endif
#if (STM32_DAC_USE_DAC1_CH2 || STM32_DAC_USE_DAC2_CH2 || \
STM32_DAC_USE_DAC3_CH2 || STM32_DAC_USE_DAC4_CH2) && STM32_DAC_DUAL_MODE
#if (GD32_DAC_USE_DAC1_CH2 || GD32_DAC_USE_DAC2_CH2 || \
GD32_DAC_USE_DAC3_CH2 || GD32_DAC_USE_DAC4_CH2) && GD32_DAC_DUAL_MODE
#error "DACx CH2 cannot be used independently in dual mode"
#endif
#if !STM32_DAC_USE_DAC1_CH1 && !STM32_DAC_USE_DAC1_CH2 && \
!STM32_DAC_USE_DAC2_CH1 && !STM32_DAC_USE_DAC2_CH2 && \
!STM32_DAC_USE_DAC3_CH1 && !STM32_DAC_USE_DAC3_CH2 && \
!STM32_DAC_USE_DAC4_CH1 && !STM32_DAC_USE_DAC4_CH2
#if !GD32_DAC_USE_DAC1_CH1 && !GD32_DAC_USE_DAC1_CH2 && \
!GD32_DAC_USE_DAC2_CH1 && !GD32_DAC_USE_DAC2_CH2 && \
!GD32_DAC_USE_DAC3_CH1 && !GD32_DAC_USE_DAC3_CH2 && \
!GD32_DAC_USE_DAC4_CH1 && !GD32_DAC_USE_DAC4_CH2
#error "DAC driver activated but no DAC peripheral assigned"
#endif
#if STM32_DAC_USE_DAC1_CH1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC1_CH1_IRQ_PRIORITY)
#if GD32_DAC_USE_DAC1_CH1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC1_CH1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC1 CH1"
#endif
#if STM32_DAC_USE_DAC1_CH2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC1_CH2_IRQ_PRIORITY)
#if GD32_DAC_USE_DAC1_CH2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC1_CH2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC1 CH2"
#endif
#if STM32_DAC_USE_DAC2_CH1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC2_CH1_IRQ_PRIORITY)
#if GD32_DAC_USE_DAC2_CH1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC2_CH1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC2 CH1"
#endif
#if STM32_DAC_USE_DAC2_CH2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC2_CH2_IRQ_PRIORITY)
#if GD32_DAC_USE_DAC2_CH2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC2_CH2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC2 CH2"
#endif
#if STM32_DAC_USE_DAC3_CH1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC3_CH1_IRQ_PRIORITY)
#if GD32_DAC_USE_DAC3_CH1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC3_CH1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC3 CH1"
#endif
#if STM32_DAC_USE_DAC3_CH2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC3_CH2_IRQ_PRIORITY)
#if GD32_DAC_USE_DAC3_CH2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC3_CH2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC3 CH2"
#endif
#if STM32_DAC_USE_DAC4_CH1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC4_CH1_IRQ_PRIORITY)
#if GD32_DAC_USE_DAC4_CH1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC4_CH1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC4 CH1"
#endif
#if STM32_DAC_USE_DAC4_CH2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_DAC_DAC4_CH2_IRQ_PRIORITY)
#if GD32_DAC_USE_DAC4_CH2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC4_CH2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC4 CH2"
#endif
/* The following checks are only required when there is a DMA able to
reassign streams to different channels.*/
#if STM32_ADVANCED_DMA
#if GD32_ADVANCED_DMA
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC_DAC1_CH1_DMA_STREAM)
#if GD32_DAC_USE_DAC1_CH1 && !defined(GD32_DAC_DAC1_CH1_DMA_STREAM)
#error "DAC1 CH1 DMA stream not defined"
#endif
#if STM32_DAC_USE_DAC1_CH2 && !defined(STM32_DAC_DAC1_CH2_DMA_STREAM)
#if GD32_DAC_USE_DAC1_CH2 && !defined(GD32_DAC_DAC1_CH2_DMA_STREAM)
#error "DAC1 CH2 DMA stream not defined"
#endif
#if STM32_DAC_USE_DAC2_CH1 && !defined(STM32_DAC_DAC2_CH1_DMA_STREAM)
#if GD32_DAC_USE_DAC2_CH1 && !defined(GD32_DAC_DAC2_CH1_DMA_STREAM)
#error "DAC2 CH1 DMA stream not defined"
#endif
#if STM32_DAC_USE_DAC2_CH2 && !defined(STM32_DAC_DAC2_CH2_DMA_STREAM)
#if GD32_DAC_USE_DAC2_CH2 && !defined(GD32_DAC_DAC2_CH2_DMA_STREAM)
#error "DAC2 CH2 DMA stream not defined"
#endif
#if STM32_DAC_USE_DAC3_CH1 && !defined(STM32_DAC_DAC3_CH1_DMA_STREAM)
#if GD32_DAC_USE_DAC3_CH1 && !defined(GD32_DAC_DAC3_CH1_DMA_STREAM)
#error "DAC3 CH1 DMA stream not defined"
#endif
#if STM32_DAC_USE_DAC3_CH2 && !defined(STM32_DAC_DAC3_CH2_DMA_STREAM)
#if GD32_DAC_USE_DAC3_CH2 && !defined(GD32_DAC_DAC3_CH2_DMA_STREAM)
#error "DAC3 CH2 DMA stream not defined"
#endif
#if STM32_DAC_USE_DAC4_CH1 && !defined(STM32_DAC_DAC4_CH1_DMA_STREAM)
#if GD32_DAC_USE_DAC4_CH1 && !defined(GD32_DAC_DAC4_CH1_DMA_STREAM)
#error "DAC4 CH1 DMA stream not defined"
#endif
#if STM32_DAC_USE_DAC4_CH2 && !defined(STM32_DAC_DAC4_CH2_DMA_STREAM)
#if GD32_DAC_USE_DAC4_CH2 && !defined(GD32_DAC_DAC4_CH2_DMA_STREAM)
#error "DAC4 CH2 DMA stream not defined"
#endif
#if STM32_DMA_SUPPORTS_DMAMUX
#if GD32_DMA_SUPPORTS_DMAMUX
#else /* !STM32_DMA_SUPPORTS_DMAMUX */
#else /* !GD32_DMA_SUPPORTS_DMAMUX */
/* Check on the validity of the assigned DMA streams.*/
#if STM32_DAC_USE_DAC1_CH1 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC1_CH1_DMA_STREAM, STM32_DAC1_CH1_DMA_MSK)
#if GD32_DAC_USE_DAC1_CH1 && \
!GD32_DMA_IS_VALID_ID(GD32_DAC_DAC1_CH1_DMA_STREAM, GD32_DAC1_CH1_DMA_MSK)
#error "invalid DMA stream associated to DAC1 CH1"
#endif
#if STM32_DAC_USE_DAC1_CH2 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC1_CH2_DMA_STREAM, STM32_DAC1_CH2_DMA_MSK)
#if GD32_DAC_USE_DAC1_CH2 && \
!GD32_DMA_IS_VALID_ID(GD32_DAC_DAC1_CH2_DMA_STREAM, GD32_DAC1_CH2_DMA_MSK)
#error "invalid DMA stream associated to DAC1 CH2"
#endif
#if STM32_DAC_USE_DAC2_CH1 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC2_CH1_DMA_STREAM, STM32_DAC2_CH1_DMA_MSK)
#if GD32_DAC_USE_DAC2_CH1 && \
!GD32_DMA_IS_VALID_ID(GD32_DAC_DAC2_CH1_DMA_STREAM, GD32_DAC2_CH1_DMA_MSK)
#error "invalid DMA stream associated to DAC2 CH1"
#endif
#if STM32_DAC_USE_DAC2_CH2 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC2_CH2_DMA_STREAM, STM32_DAC2_CH2_DMA_MSK)
#if GD32_DAC_USE_DAC2_CH2 && \
!GD32_DMA_IS_VALID_ID(GD32_DAC_DAC2_CH2_DMA_STREAM, GD32_DAC2_CH2_DMA_MSK)
#error "invalid DMA stream associated to DAC2 CH2"
#endif
#if STM32_DAC_USE_DAC3_CH1 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC3_CH1_DMA_STREAM, STM32_DAC3_CH1_DMA_MSK)
#if GD32_DAC_USE_DAC3_CH1 && \
!GD32_DMA_IS_VALID_ID(GD32_DAC_DAC3_CH1_DMA_STREAM, GD32_DAC3_CH1_DMA_MSK)
#error "invalid DMA stream associated to DAC1 CH1"
#endif
#if STM32_DAC_USE_DAC3_CH2 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC3_CH2_DMA_STREAM, STM32_DAC3_CH2_DMA_MSK)
#if GD32_DAC_USE_DAC3_CH2 && \
!GD32_DMA_IS_VALID_ID(GD32_DAC_DAC3_CH2_DMA_STREAM, GD32_DAC3_CH2_DMA_MSK)
#error "invalid DMA stream associated to DAC1 CH2"
#endif
#if STM32_DAC_USE_DAC4_CH1 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC4_CH1_DMA_STREAM, STM32_DAC4_CH1_DMA_MSK)
#if GD32_DAC_USE_DAC4_CH1 && \
!GD32_DMA_IS_VALID_ID(GD32_DAC_DAC4_CH1_DMA_STREAM, GD32_DAC4_CH1_DMA_MSK)
#error "invalid DMA stream associated to DAC2 CH1"
#endif
#if STM32_DAC_USE_DAC4_CH2 && \
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC4_CH2_DMA_STREAM, STM32_DAC4_CH2_DMA_MSK)
#if GD32_DAC_USE_DAC4_CH2 && \
!GD32_DMA_IS_VALID_ID(GD32_DAC_DAC4_CH2_DMA_STREAM, GD32_DAC4_CH2_DMA_MSK)
#error "invalid DMA stream associated to DAC2 CH2"
#endif
#endif /* !STM32_DMA_SUPPORTS_DMAMUX */
#endif /* !GD32_DMA_SUPPORTS_DMAMUX */
#endif /* STM32_ADVANCED_DMA */
#endif /* GD32_ADVANCED_DMA */
#if STM32_DAC_USE_DAC1_CH1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC1_CH1_DMA_PRIORITY)
#if GD32_DAC_USE_DAC1_CH1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC1_CH1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC1 CH1"
#endif
#if STM32_DAC_USE_DAC1_CH2 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC1_CH2_DMA_PRIORITY)
#if GD32_DAC_USE_DAC1_CH2 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC1_CH2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC1 CH2"
#endif
#if STM32_DAC_USE_DAC2_CH1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC2_CH1_DMA_PRIORITY)
#if GD32_DAC_USE_DAC2_CH1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC2_CH1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC2 CH1"
#endif
#if STM32_DAC_USE_DAC2_CH2 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC2_CH2_DMA_PRIORITY)
#if GD32_DAC_USE_DAC2_CH2 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC2_CH2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC2 CH2"
#endif
#if STM32_DAC_USE_DAC3_CH1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC3_CH1_DMA_PRIORITY)
#if GD32_DAC_USE_DAC3_CH1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC3_CH1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC3 CH1"
#endif
#if STM32_DAC_USE_DAC3_CH2 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC3_CH2_DMA_PRIORITY)
#if GD32_DAC_USE_DAC3_CH2 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC3_CH2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC3 CH2"
#endif
#if STM32_DAC_USE_DAC4_CH1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC4_CH1_DMA_PRIORITY)
#if GD32_DAC_USE_DAC4_CH1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC4_CH1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC4 CH1"
#endif
#if STM32_DAC_USE_DAC4_CH2 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC4_CH2_DMA_PRIORITY)
#if GD32_DAC_USE_DAC4_CH2 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC4_CH2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC4 CH2"
#endif
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#if !defined(GD32_DMA_REQUIRED)
#define GD32_DMA_REQUIRED
#endif
/**
* @brief Max DAC channels.
*/
#if STM32_DAC_DUAL_MODE == FALSE
#if GD32_DAC_DUAL_MODE == FALSE
#define DAC_MAX_CHANNELS 2
#else
#define DAC_MAX_CHANNELS 1
@ -539,7 +539,7 @@ typedef struct {
* @brief DMA channel IRQ priority.
*/
uint32_t dmairqprio;
#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__)
#if (GD32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__)
/**
* @brief DMAMUX peripheral selector.
*/
@ -564,7 +564,7 @@ typedef enum {
DAC_DHRM_12BIT_RIGHT = 0,
DAC_DHRM_12BIT_LEFT = 1,
DAC_DHRM_8BIT_RIGHT = 2,
#if STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
#if GD32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
DAC_DHRM_12BIT_RIGHT_DUAL = 3,
DAC_DHRM_12BIT_LEFT_DUAL = 4,
DAC_DHRM_8BIT_RIGHT_DUAL = 5
@ -608,35 +608,35 @@ typedef enum {
/* External declarations. */
/*===========================================================================*/
#if STM32_DAC_USE_DAC1_CH1 && !defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC1_CH1 && !defined(__DOXYGEN__)
extern DACDriver DACD1;
#endif
#if STM32_DAC_USE_DAC1_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC1_CH2 && !GD32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
extern DACDriver DACD2;
#endif
#if STM32_DAC_USE_DAC2_CH1 && !defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC2_CH1 && !defined(__DOXYGEN__)
extern DACDriver DACD3;
#endif
#if STM32_DAC_USE_DAC2_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC2_CH2 && !GD32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
extern DACDriver DACD4;
#endif
#if STM32_DAC_USE_DAC3_CH1 && !defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC3_CH1 && !defined(__DOXYGEN__)
extern DACDriver DACD5;
#endif
#if STM32_DAC_USE_DAC3_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC3_CH2 && !GD32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
extern DACDriver DACD6;
#endif
#if STM32_DAC_USE_DAC4_CH1 && !defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC4_CH1 && !defined(__DOXYGEN__)
extern DACDriver DACD7;
#endif
#if STM32_DAC_USE_DAC4_CH2 && !STM32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC4_CH2 && !GD32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
extern DACDriver DACD8;
#endif

8
os/hal/ports/GD/GD32VF103/DMA/notes.txt
View File

@ -14,13 +14,13 @@ Driver capability:
The file registry must export:
STM32_ADVANCED_DMA - TRUE not used by the DMA drivers but other
GD32_ADVANCED_DMA - TRUE not used by the DMA drivers but other
drivers use it to enable checks on DMA
channels. Probably will be removed in the
future.
STM32_DMA_SUPPORTS_CSELR - TRUE if the DMA have a CSELR register.
STM32_DMA_SUPPORTS_DMAMUX - TRUE if the DMA is riven by a DMAMUX.
STM32_DMAn_NUM_CHANNELS - Number of channels in DMAs "n" (1..2).
GD32_DMA_SUPPORTS_CSELR - TRUE if the DMA have a CSELR register.
GD32_DMA_SUPPORTS_DMAMUX - TRUE if the DMA is riven by a DMAMUX.
GD32_DMAn_NUM_CHANNELS - Number of channels in DMAs "n" (1..2).
GD32_DMAn_CHx_HANDLER - Vector name for IRQ "x" (1..7). If the macro
is not exported then the ISR is not declared.
GD32_DMAn_CHx_NUMBER - Vector number for IRQ "x" (1..7).

164
os/hal/ports/GD/GD32VF103/DMA/stm32_dma.c
View File

@ -18,7 +18,7 @@
* @file DMA/stm32_dma.c
* @brief DMA helper driver code.
*
* @addtogroup STM32_DMA
* @addtogroup GD32_DMA
* @details DMA sharing helper driver. In the STM32 the DMA streams are a
* shared resource, this driver allows to allocate and free DMA
* streams at runtime in order to allow all the other device
@ -33,7 +33,7 @@
/* The following macro is only defined if some driver requiring DMA services
has been enabled.*/
#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
#if defined(GD32_DMA_REQUIRED) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
@ -42,13 +42,13 @@
/**
* @brief Mask of the DMA1 streams in @p dma_streams_mask.
*/
#define STM32_DMA1_STREAMS_MASK ((1U << STM32_DMA1_NUM_CHANNELS) - 1U)
#define GD32_DMA1_STREAMS_MASK ((1U << GD32_DMA1_NUM_CHANNELS) - 1U)
/**
* @brief Mask of the DMA2 streams in @p dma_streams_mask.
*/
#define STM32_DMA2_STREAMS_MASK (((1U << STM32_DMA2_NUM_CHANNELS) - \
1U) << STM32_DMA1_NUM_CHANNELS)
#define GD32_DMA2_STREAMS_MASK (((1U << GD32_DMA2_NUM_CHANNELS) - \
1U) << GD32_DMA1_NUM_CHANNELS)
#define DMA1_CH1_VARIANT 0
#define DMA1_CH2_VARIANT 0
@ -68,52 +68,52 @@
/*
* Default ISR collision masks.
*/
#if !defined(STM32_DMA1_CH1_CMASK)
#define STM32_DMA1_CH1_CMASK (1U << 0U)
#if !defined(GD32_DMA1_CH1_CMASK)
#define GD32_DMA1_CH1_CMASK (1U << 0U)
#endif
#if !defined(STM32_DMA1_CH2_CMASK)
#define STM32_DMA1_CH2_CMASK (1U << 1U)
#if !defined(GD32_DMA1_CH2_CMASK)
#define GD32_DMA1_CH2_CMASK (1U << 1U)
#endif
#if !defined(STM32_DMA1_CH3_CMASK)
#define STM32_DMA1_CH3_CMASK (1U << 2U)
#if !defined(GD32_DMA1_CH3_CMASK)
#define GD32_DMA1_CH3_CMASK (1U << 2U)
#endif
#if !defined(STM32_DMA1_CH4_CMASK)
#define STM32_DMA1_CH4_CMASK (1U << 3U)
#if !defined(GD32_DMA1_CH4_CMASK)
#define GD32_DMA1_CH4_CMASK (1U << 3U)
#endif
#if !defined(STM32_DMA1_CH5_CMASK)
#define STM32_DMA1_CH5_CMASK (1U << 4U)
#if !defined(GD32_DMA1_CH5_CMASK)
#define GD32_DMA1_CH5_CMASK (1U << 4U)
#endif
#if !defined(STM32_DMA1_CH6_CMASK)
#define STM32_DMA1_CH6_CMASK (1U << 5U)
#if !defined(GD32_DMA1_CH6_CMASK)
#define GD32_DMA1_CH6_CMASK (1U << 5U)
#endif
#if !defined(STM32_DMA1_CH7_CMASK)
#define STM32_DMA1_CH7_CMASK (1U << 6U)
#if !defined(GD32_DMA1_CH7_CMASK)
#define GD32_DMA1_CH7_CMASK (1U << 6U)
#endif
#if !defined(STM32_DMA2_CH1_CMASK)
#define STM32_DMA2_CH1_CMASK (1U << (STM32_DMA1_NUM_CHANNELS + 0U))
#if !defined(GD32_DMA2_CH1_CMASK)
#define GD32_DMA2_CH1_CMASK (1U << (GD32_DMA1_NUM_CHANNELS + 0U))
#endif
#if !defined(STM32_DMA2_CH2_CMASK)
#define STM32_DMA2_CH2_CMASK (1U << (STM32_DMA1_NUM_CHANNELS + 1U))
#if !defined(GD32_DMA2_CH2_CMASK)
#define GD32_DMA2_CH2_CMASK (1U << (GD32_DMA1_NUM_CHANNELS + 1U))
#endif
#if !defined(STM32_DMA2_CH3_CMASK)
#define STM32_DMA2_CH3_CMASK (1U << (STM32_DMA1_NUM_CHANNELS + 2U))
#if !defined(GD32_DMA2_CH3_CMASK)
#define GD32_DMA2_CH3_CMASK (1U << (GD32_DMA1_NUM_CHANNELS + 2U))
#endif
#if !defined(STM32_DMA2_CH4_CMASK)
#define STM32_DMA2_CH4_CMASK (1U << (STM32_DMA1_NUM_CHANNELS + 3U))
#if !defined(GD32_DMA2_CH4_CMASK)
#define GD32_DMA2_CH4_CMASK (1U << (GD32_DMA1_NUM_CHANNELS + 3U))
#endif
#if !defined(STM32_DMA2_CH5_CMASK)
#define STM32_DMA2_CH5_CMASK (1U << (STM32_DMA1_NUM_CHANNELS + 4U))
#if !defined(GD32_DMA2_CH5_CMASK)
#define GD32_DMA2_CH5_CMASK (1U << (GD32_DMA1_NUM_CHANNELS + 4U))
#endif
/*===========================================================================*/
@ -125,21 +125,21 @@
* @details This table keeps the association between an unique stream
* identifier and the involved physical registers.
* @note Don't use this array directly, use the appropriate wrapper macros
* instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
* instead: @p GD32_DMA1_STREAM1, @p GD32_DMA1_STREAM2 etc.
*/
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
{DMA1, DMA1_Channel1, STM32_DMA1_CH1_CMASK, DMA1_CH1_VARIANT, 0, 0, GD32_DMA1_CH1_NUMBER},
{DMA1, DMA1_Channel2, STM32_DMA1_CH2_CMASK, DMA1_CH2_VARIANT, 4, 1, GD32_DMA1_CH2_NUMBER},
{DMA1, DMA1_Channel3, STM32_DMA1_CH3_CMASK, DMA1_CH3_VARIANT, 8, 2, GD32_DMA1_CH3_NUMBER},
{DMA1, DMA1_Channel4, STM32_DMA1_CH4_CMASK, DMA1_CH4_VARIANT, 12, 3, GD32_DMA1_CH4_NUMBER},
{DMA1, DMA1_Channel5, STM32_DMA1_CH5_CMASK, DMA1_CH5_VARIANT, 16, 4, GD32_DMA1_CH5_NUMBER},
{DMA1, DMA1_Channel6, STM32_DMA1_CH6_CMASK, DMA1_CH6_VARIANT, 20, 5, GD32_DMA1_CH6_NUMBER},
{DMA1, DMA1_Channel7, STM32_DMA1_CH7_CMASK, DMA1_CH7_VARIANT, 24, 6, GD32_DMA1_CH7_NUMBER},
{DMA2, DMA2_Channel1, STM32_DMA2_CH1_CMASK, DMA2_CH1_VARIANT, 0, 0 + STM32_DMA1_NUM_CHANNELS, GD32_DMA2_CH1_NUMBER},
{DMA2, DMA2_Channel2, STM32_DMA2_CH2_CMASK, DMA2_CH2_VARIANT, 4, 1 + STM32_DMA1_NUM_CHANNELS, GD32_DMA2_CH2_NUMBER},
{DMA2, DMA2_Channel3, STM32_DMA2_CH3_CMASK, DMA2_CH3_VARIANT, 8, 2 + STM32_DMA1_NUM_CHANNELS, GD32_DMA2_CH3_NUMBER},
{DMA2, DMA2_Channel4, STM32_DMA2_CH4_CMASK, DMA2_CH4_VARIANT, 12, 3 + STM32_DMA1_NUM_CHANNELS, GD32_DMA2_CH4_NUMBER},
{DMA2, DMA2_Channel5, STM32_DMA2_CH5_CMASK, DMA2_CH5_VARIANT, 16, 4 + STM32_DMA1_NUM_CHANNELS, GD32_DMA2_CH5_NUMBER},
const stm32_dma_stream_t _stm32_dma_streams[GD32_DMA_STREAMS] = {
{DMA1, DMA1_Channel1, GD32_DMA1_CH1_CMASK, DMA1_CH1_VARIANT, 0, 0, GD32_DMA1_CH1_NUMBER},
{DMA1, DMA1_Channel2, GD32_DMA1_CH2_CMASK, DMA1_CH2_VARIANT, 4, 1, GD32_DMA1_CH2_NUMBER},
{DMA1, DMA1_Channel3, GD32_DMA1_CH3_CMASK, DMA1_CH3_VARIANT, 8, 2, GD32_DMA1_CH3_NUMBER},
{DMA1, DMA1_Channel4, GD32_DMA1_CH4_CMASK, DMA1_CH4_VARIANT, 12, 3, GD32_DMA1_CH4_NUMBER},
{DMA1, DMA1_Channel5, GD32_DMA1_CH5_CMASK, DMA1_CH5_VARIANT, 16, 4, GD32_DMA1_CH5_NUMBER},
{DMA1, DMA1_Channel6, GD32_DMA1_CH6_CMASK, DMA1_CH6_VARIANT, 20, 5, GD32_DMA1_CH6_NUMBER},
{DMA1, DMA1_Channel7, GD32_DMA1_CH7_CMASK, DMA1_CH7_VARIANT, 24, 6, GD32_DMA1_CH7_NUMBER},
{DMA2, DMA2_Channel1, GD32_DMA2_CH1_CMASK, DMA2_CH1_VARIANT, 0, 0 + GD32_DMA1_NUM_CHANNELS, GD32_DMA2_CH1_NUMBER},
{DMA2, DMA2_Channel2, GD32_DMA2_CH2_CMASK, DMA2_CH2_VARIANT, 4, 1 + GD32_DMA1_NUM_CHANNELS, GD32_DMA2_CH2_NUMBER},
{DMA2, DMA2_Channel3, GD32_DMA2_CH3_CMASK, DMA2_CH3_VARIANT, 8, 2 + GD32_DMA1_NUM_CHANNELS, GD32_DMA2_CH3_NUMBER},
{DMA2, DMA2_Channel4, GD32_DMA2_CH4_CMASK, DMA2_CH4_VARIANT, 12, 3 + GD32_DMA1_NUM_CHANNELS, GD32_DMA2_CH4_NUMBER},
{DMA2, DMA2_Channel5, GD32_DMA2_CH5_CMASK, DMA2_CH5_VARIANT, 16, 4 + GD32_DMA1_NUM_CHANNELS, GD32_DMA2_CH5_NUMBER},
};
/*===========================================================================*/
@ -170,7 +170,7 @@ static struct {
* @brief DMA callback parameter.
*/
void *param;
} streams[STM32_DMA_STREAMS];
} streams[GD32_DMA_STREAMS];
} dma;
/*===========================================================================*/
@ -191,7 +191,7 @@ OSAL_IRQ_HANDLER(GD32_DMA1_CH1_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(STM32_DMA1_STREAM1);
dmaServeInterrupt(GD32_DMA1_STREAM1);
OSAL_IRQ_EPILOGUE();
}
@ -207,7 +207,7 @@ OSAL_IRQ_HANDLER(GD32_DMA1_CH2_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(STM32_DMA1_STREAM2);
dmaServeInterrupt(GD32_DMA1_STREAM2);
OSAL_IRQ_EPILOGUE();
}
@ -223,7 +223,7 @@ OSAL_IRQ_HANDLER(GD32_DMA1_CH3_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(STM32_DMA1_STREAM3);
dmaServeInterrupt(GD32_DMA1_STREAM3);
OSAL_IRQ_EPILOGUE();
}
@ -239,7 +239,7 @@ OSAL_IRQ_HANDLER(GD32_DMA1_CH4_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(STM32_DMA1_STREAM4);
dmaServeInterrupt(GD32_DMA1_STREAM4);
OSAL_IRQ_EPILOGUE();
}
@ -255,7 +255,7 @@ OSAL_IRQ_HANDLER(GD32_DMA1_CH5_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(STM32_DMA1_STREAM5);
dmaServeInterrupt(GD32_DMA1_STREAM5);
OSAL_IRQ_EPILOGUE();
}
@ -271,7 +271,7 @@ OSAL_IRQ_HANDLER(GD32_DMA1_CH6_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(STM32_DMA1_STREAM6);
dmaServeInterrupt(GD32_DMA1_STREAM6);
OSAL_IRQ_EPILOGUE();
}
@ -287,7 +287,7 @@ OSAL_IRQ_HANDLER(GD32_DMA1_CH7_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(STM32_DMA1_STREAM7);
dmaServeInterrupt(GD32_DMA1_STREAM7);
OSAL_IRQ_EPILOGUE();
}
@ -303,7 +303,7 @@ OSAL_IRQ_HANDLER(GD32_DMA2_CH1_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(STM32_DMA2_STREAM1);
dmaServeInterrupt(GD32_DMA2_STREAM1);
OSAL_IRQ_EPILOGUE();
}
@ -319,7 +319,7 @@ OSAL_IRQ_HANDLER(GD32_DMA2_CH2_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(STM32_DMA2_STREAM2);
dmaServeInterrupt(GD32_DMA2_STREAM2);
OSAL_IRQ_EPILOGUE();
}
@ -335,7 +335,7 @@ OSAL_IRQ_HANDLER(GD32_DMA2_CH3_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(STM32_DMA2_STREAM3);
dmaServeInterrupt(GD32_DMA2_STREAM3);
OSAL_IRQ_EPILOGUE();
}
@ -351,7 +351,7 @@ OSAL_IRQ_HANDLER(GD32_DMA2_CH4_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(STM32_DMA2_STREAM4);
dmaServeInterrupt(GD32_DMA2_STREAM4);
OSAL_IRQ_EPILOGUE();
}
@ -367,7 +367,7 @@ OSAL_IRQ_HANDLER(GD32_DMA2_CH5_HANDLER) {
OSAL_IRQ_PROLOGUE();
dmaServeInterrupt(STM32_DMA2_STREAM5);
dmaServeInterrupt(GD32_DMA2_STREAM5);
OSAL_IRQ_EPILOGUE();
}
@ -388,8 +388,8 @@ void dmaInit(void) {
dma.allocated_mask = 0U;
dma.isr_mask = 0U;
for (i = 0; i < STM32_DMA_STREAMS; i++) {
_stm32_dma_streams[i].channel->CCR = STM32_DMA_CCR_RESET_VALUE;
for (i = 0; i < GD32_DMA_STREAMS; i++) {
_stm32_dma_streams[i].channel->CCR = GD32_DMA_CCR_RESET_VALUE;
dma.streams[i].func = NULL;
}
DMA1->IFCR = 0xFFFFFFFFU;
@ -403,10 +403,10 @@ void dmaInit(void) {
* and initializes its priority.
*
* @param[in] id numeric identifiers of a specific stream or:
* - @p STM32_DMA_STREAM_ID_ANY for any stream.
* - @p STM32_DMA_STREAM_ID_ANY_DMA1 for any stream
* - @p GD32_DMA_STREAM_ID_ANY for any stream.
* - @p GD32_DMA_STREAM_ID_ANY_DMA1 for any stream
* on DMA1.
* - @p STM32_DMA_STREAM_ID_ANY_DMA2 for any stream
* - @p GD32_DMA_STREAM_ID_ANY_DMA2 for any stream
* on DMA2.
* .
* @param[in] priority IRQ priority for the DMA stream
@ -426,23 +426,23 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id,
osalDbgCheckClassI();
if (id < STM32_DMA_STREAMS) {
if (id < GD32_DMA_STREAMS) {
startid = id;
endid = id;
}
#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
else if (id == STM32_DMA_STREAM_ID_ANY) {
#if GD32_DMA_SUPPORTS_DMAMUX == TRUE
else if (id == GD32_DMA_STREAM_ID_ANY) {
startid = 0U;
endid = STM32_DMA_STREAMS - 1U;
endid = GD32_DMA_STREAMS - 1U;
}
else if (id == STM32_DMA_STREAM_ID_ANY_DMA1) {
else if (id == GD32_DMA_STREAM_ID_ANY_DMA1) {
startid = 0U;
endid = STM32_DMA1_NUM_CHANNELS - 1U;
endid = GD32_DMA1_NUM_CHANNELS - 1U;
}
#if STM32_DMA2_NUM_CHANNELS > 0
else if (id == STM32_DMA_STREAM_ID_ANY_DMA2) {
startid = STM32_DMA1_NUM_CHANNELS;
endid = STM32_DMA_STREAMS - 1U;
#if GD32_DMA2_NUM_CHANNELS > 0
else if (id == GD32_DMA_STREAM_ID_ANY_DMA2) {
startid = GD32_DMA1_NUM_CHANNELS;
endid = GD32_DMA_STREAMS - 1U;
}
#endif
#endif
@ -454,7 +454,7 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id,
for (i = startid; i <= endid; i++) {
uint32_t mask = (1U << i);
if ((dma.allocated_mask & mask) == 0U) {
const stm32_dma_stream_t *dmastp = STM32_DMA_STREAM(i);
const stm32_dma_stream_t *dmastp = GD32_DMA_STREAM(i);
/* Installs the DMA handler.*/
dma.streams[i].func = func;
@ -462,11 +462,11 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id,
dma.allocated_mask |= mask;
/* Enabling DMA clocks required by the current streams set.*/
if ((STM32_DMA1_STREAMS_MASK & mask) != 0U) {
if ((GD32_DMA1_STREAMS_MASK & mask) != 0U) {
rccEnableDMA1(true);
}
if ((STM32_DMA2_STREAMS_MASK & mask) != 0U) {
if ((GD32_DMA2_STREAMS_MASK & mask) != 0U) {
rccEnableDMA2(true);
}
@ -481,7 +481,7 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id,
/* Putting the stream in a known state.*/
dmaStreamDisable(dmastp);
dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
dmastp->channel->CCR = GD32_DMA_CCR_RESET_VALUE;
return dmastp;
}
@ -497,10 +497,10 @@ const stm32_dma_stream_t *dmaStreamAllocI(uint32_t id,
* and initializes its priority.
*
* @param[in] id numeric identifiers of a specific stream or:
* - @p STM32_DMA_STREAM_ID_ANY for any stream.
* - @p STM32_DMA_STREAM_ID_ANY_DMA1 for any stream
* - @p GD32_DMA_STREAM_ID_ANY for any stream.
* - @p GD32_DMA_STREAM_ID_ANY_DMA1 for any stream
* on DMA1.
* - @p STM32_DMA_STREAM_ID_ANY_DMA2 for any stream
* - @p GD32_DMA_STREAM_ID_ANY_DMA2 for any stream
* on DMA2.
* .
* @param[in] priority IRQ priority for the DMA stream
@ -558,10 +558,10 @@ void dmaStreamFreeI(const stm32_dma_stream_t *dmastp) {
dma.streams[selfindex].param = NULL;
/* Shutting down clocks that are no more required, if any.*/
if ((dma.allocated_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
if ((dma.allocated_mask & GD32_DMA1_STREAMS_MASK) == 0U) {
rccDisableDMA1();
}
if ((dma.allocated_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
if ((dma.allocated_mask & GD32_DMA2_STREAMS_MASK) == 0U) {
rccDisableDMA2();
}
}
@ -594,7 +594,7 @@ void dmaServeInterrupt(const stm32_dma_stream_t *dmastp) {
uint32_t flags;
uint32_t selfindex = (uint32_t)dmastp->selfindex;
flags = (dmastp->dma->ISR >> dmastp->shift) & STM32_DMA_ISR_MASK;
flags = (dmastp->dma->ISR >> dmastp->shift) & GD32_DMA_ISR_MASK;
if (flags & dmastp->channel->CCR) {
dmastp->dma->IFCR = flags << dmastp->shift;
if (dma.streams[selfindex].func) {
@ -603,6 +603,6 @@ void dmaServeInterrupt(const stm32_dma_stream_t *dmastp) {
}
}
#endif /* STM32_DMA_REQUIRED */
#endif /* GD32_DMA_REQUIRED */
/** @} */

196
os/hal/ports/GD/GD32VF103/DMA/stm32_dma.h
View File

@ -20,12 +20,12 @@
* @note This driver uses the new naming convention used for the STM32F2xx
* so the "DMA channels" are referred as "DMA streams".
*
* @addtogroup STM32_DMA
* @addtogroup GD32_DMA
* @{
*/
#ifndef STM32_DMA_H
#define STM32_DMA_H
#ifndef GD32_DMA_H
#define GD32_DMA_H
/*===========================================================================*/
/* Driver constants. */
@ -36,19 +36,19 @@
* @details if @p TRUE then the DMA is able of burst transfers, FIFOs,
* scatter gather and other advanced features.
*/
#define STM32_DMA_ADVANCED FALSE
#define GD32_DMA_ADVANCED FALSE
/**
* @brief Total number of DMA streams.
* @details This is the total number of streams among all the DMA units.
*/
#define STM32_DMA_STREAMS (STM32_DMA1_NUM_CHANNELS + \
STM32_DMA2_NUM_CHANNELS)
#define GD32_DMA_STREAMS (GD32_DMA1_NUM_CHANNELS + \
GD32_DMA2_NUM_CHANNELS)
/**
* @brief Mask of the ISR bits passed to the DMA callback functions.
*/
#define STM32_DMA_ISR_MASK 0x0E
#define GD32_DMA_ISR_MASK 0x0E
/**
* @brief Returns the request line associated to the specified stream.
@ -60,8 +60,8 @@
* nibble
* @return Returns the request associated to the stream.
*/
#define STM32_DMA_GETCHANNEL(id, c) \
(((uint32_t)(c) >> (((uint32_t)(id) % (uint32_t)STM32_DMA1_NUM_CHANNELS) * 4U)) & 15U)
#define GD32_DMA_GETCHANNEL(id, c) \
(((uint32_t)(c) >> (((uint32_t)(id) % (uint32_t)GD32_DMA1_NUM_CHANNELS) * 4U)) & 15U)
/**
* @brief Checks if a DMA priority is within the valid range.
@ -71,9 +71,9 @@
* @retval false invalid DMA priority.
* @retval true correct DMA priority.
*/
#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
#define GD32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
#if (STM32_DMA_SUPPORTS_DMAMUX == FALSE) || defined(_DOXYGEN__)
#if (GD32_DMA_SUPPORTS_DMAMUX == FALSE) || defined(_DOXYGEN__)
/**
* @brief Checks if a DMA stream id is within the valid range.
*
@ -82,17 +82,17 @@
* @retval false invalid DMA channel.
* @retval true correct DMA channel.
*/
#define STM32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
((id) < STM32_DMA_STREAMS))
#else /* STM32_DMA_SUPPORTS_DMAMUX == FALSE */
#if STM32_DMA2_NUM_CHANNELS > 0
#define STM32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
((id) <= (STM32_DMA_STREAMS + 2)))
#define GD32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
((id) < GD32_DMA_STREAMS))
#else /* GD32_DMA_SUPPORTS_DMAMUX == FALSE */
#if GD32_DMA2_NUM_CHANNELS > 0
#define GD32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
((id) <= (GD32_DMA_STREAMS + 2)))
#else
#define STM32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
((id) <= (STM32_DMA_STREAMS + 1)))
#define GD32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \
((id) <= (GD32_DMA_STREAMS + 1)))
#endif
#endif /* STM32_DMA_SUPPORTS_DMAMUX == FALSE */
#endif /* GD32_DMA_SUPPORTS_DMAMUX == FALSE */
/**
* @brief Returns an unique numeric identifier for a DMA stream.
@ -101,8 +101,8 @@
* @param[in] stream the stream number
* @return An unique numeric stream identifier.
*/
#define STM32_DMA_STREAM_ID(dma, stream) \
((((dma) - 1) * STM32_DMA1_NUM_CHANNELS) + ((stream) - 1))
#define GD32_DMA_STREAM_ID(dma, stream) \
((((dma) - 1) * GD32_DMA1_NUM_CHANNELS) + ((stream) - 1))
/**
* @brief Returns a DMA stream identifier mask.
@ -112,8 +112,8 @@
* @param[in] stream the stream number
* @return A DMA stream identifier mask.
*/
#define STM32_DMA_STREAM_ID_MSK(dma, stream) \
(1U << STM32_DMA_STREAM_ID(dma, stream))
#define GD32_DMA_STREAM_ID_MSK(dma, stream) \
(1U << GD32_DMA_STREAM_ID(dma, stream))
/**
* @brief Checks if a DMA stream unique identifier belongs to a mask.
@ -125,17 +125,17 @@
* @retval false id does not belong to the mask.
* @retval true id belongs to the mask.
*/
#define STM32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask)))
#define GD32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask)))
#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(_DOXYGEN__)
#if (GD32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(_DOXYGEN__)
/**
* @name Special stream identifiers
* @{
*/
#define STM32_DMA_STREAM_ID_ANY STM32_DMA_STREAMS
#define STM32_DMA_STREAM_ID_ANY_DMA1 (STM32_DMA_STREAM_ID_ANY + 1)
#if STM32_DMA2_NUM_CHANNELS > 0
#define STM32_DMA_STREAM_ID_ANY_DMA2 (STM32_DMA_STREAM_ID_ANY_DMA1 + 1)
#define GD32_DMA_STREAM_ID_ANY GD32_DMA_STREAMS
#define GD32_DMA_STREAM_ID_ANY_DMA1 (GD32_DMA_STREAM_ID_ANY + 1)
#if GD32_DMA2_NUM_CHANNELS > 0
#define GD32_DMA_STREAM_ID_ANY_DMA2 (GD32_DMA_STREAM_ID_ANY_DMA1 + 1)
#endif
/** @} */
#endif
@ -151,62 +151,62 @@
* @return A pointer to the stm32_dma_stream_t constant structure
* associated to the DMA stream.
*/
#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id])
#define GD32_DMA_STREAM(id) (&_stm32_dma_streams[id])
#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0)
#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1)
#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2)
#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3)
#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4)
#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5)
#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6)
#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(STM32_DMA1_NUM_CHANNELS + 0)
#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(STM32_DMA1_NUM_CHANNELS + 1)
#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(STM32_DMA1_NUM_CHANNELS + 2)
#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(STM32_DMA1_NUM_CHANNELS + 3)
#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(STM32_DMA1_NUM_CHANNELS + 4)
#define GD32_DMA1_STREAM1 GD32_DMA_STREAM(0)
#define GD32_DMA1_STREAM2 GD32_DMA_STREAM(1)
#define GD32_DMA1_STREAM3 GD32_DMA_STREAM(2)
#define GD32_DMA1_STREAM4 GD32_DMA_STREAM(3)
#define GD32_DMA1_STREAM5 GD32_DMA_STREAM(4)
#define GD32_DMA1_STREAM6 GD32_DMA_STREAM(5)
#define GD32_DMA1_STREAM7 GD32_DMA_STREAM(6)
#define GD32_DMA2_STREAM1 GD32_DMA_STREAM(GD32_DMA1_NUM_CHANNELS + 0)
#define GD32_DMA2_STREAM2 GD32_DMA_STREAM(GD32_DMA1_NUM_CHANNELS + 1)
#define GD32_DMA2_STREAM3 GD32_DMA_STREAM(GD32_DMA1_NUM_CHANNELS + 2)
#define GD32_DMA2_STREAM4 GD32_DMA_STREAM(GD32_DMA1_NUM_CHANNELS + 3)
#define GD32_DMA2_STREAM5 GD32_DMA_STREAM(GD32_DMA1_NUM_CHANNELS + 4)
/** @} */
/**
* @name CR register constants common to all DMA types
* @{
*/
#define STM32_DMA_CCR_RESET_VALUE 0x00000000U
#define STM32_DMA_CR_EN DMA_CCR_EN
#define STM32_DMA_CR_TEIE DMA_CCR_TEIE
#define STM32_DMA_CR_HTIE DMA_CCR_HTIE
#define STM32_DMA_CR_TCIE DMA_CCR_TCIE
#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
#define STM32_DMA_CR_DIR_P2M 0U
#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR
#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM
#define STM32_DMA_CR_CIRC DMA_CCR_CIRC
#define STM32_DMA_CR_PINC DMA_CCR_PINC
#define STM32_DMA_CR_MINC DMA_CCR_MINC
#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE
#define STM32_DMA_CR_PSIZE_BYTE 0U
#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0
#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1
#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE
#define STM32_DMA_CR_MSIZE_BYTE 0U
#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0
#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1
#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \
STM32_DMA_CR_MSIZE_MASK)
#define STM32_DMA_CR_PL_MASK DMA_CCR_PL
#define STM32_DMA_CR_PL(n) ((n) << 12U)
#define GD32_DMA_CCR_RESET_VALUE 0x00000000U
#define GD32_DMA_CR_EN DMA_CCR_EN
#define GD32_DMA_CR_TEIE DMA_CCR_TEIE
#define GD32_DMA_CR_HTIE DMA_CCR_HTIE
#define GD32_DMA_CR_TCIE DMA_CCR_TCIE
#define GD32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
#define GD32_DMA_CR_DIR_P2M 0U
#define GD32_DMA_CR_DIR_M2P DMA_CCR_DIR
#define GD32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM
#define GD32_DMA_CR_CIRC DMA_CCR_CIRC
#define GD32_DMA_CR_PINC DMA_CCR_PINC
#define GD32_DMA_CR_MINC DMA_CCR_MINC
#define GD32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE
#define GD32_DMA_CR_PSIZE_BYTE 0U
#define GD32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0
#define GD32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1
#define GD32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE
#define GD32_DMA_CR_MSIZE_BYTE 0U
#define GD32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0
#define GD32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1
#define GD32_DMA_CR_SIZE_MASK (GD32_DMA_CR_PSIZE_MASK | \
GD32_DMA_CR_MSIZE_MASK)
#define GD32_DMA_CR_PL_MASK DMA_CCR_PL
#define GD32_DMA_CR_PL(n) ((n) << 12U)
/** @} */
/**
* @name Request line selector macro
* @{
*/
#if STM32_DMA_SUPPORTS_CSELR || defined(__DOXYGEN__)
#define STM32_DMA_CR_CHSEL_MASK (15U << 16U)
#define STM32_DMA_CR_CHSEL(n) ((n) << 16U)
#if GD32_DMA_SUPPORTS_CSELR || defined(__DOXYGEN__)
#define GD32_DMA_CR_CHSEL_MASK (15U << 16U)
#define GD32_DMA_CR_CHSEL(n) ((n) << 16U)
#else
#define STM32_DMA_CR_CHSEL_MASK 0U
#define STM32_DMA_CR_CHSEL(n) 0U
#define GD32_DMA_CR_CHSEL_MASK 0U
#define GD32_DMA_CR_CHSEL(n) 0U
#endif
/** @} */
@ -214,18 +214,18 @@
* @name CR register constants only found in enhanced DMA
* @{
*/
#define STM32_DMA_CR_DMEIE 0U /**< @brief Ignored by normal DMA. */
#define GD32_DMA_CR_DMEIE 0U /**< @brief Ignored by normal DMA. */
/** @} */
/**
* @name Status flags passed to the ISR callbacks
* @{
*/
#define STM32_DMA_ISR_FEIF 0U
#define STM32_DMA_ISR_DMEIF 0U
#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1
#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1
#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1
#define GD32_DMA_ISR_FEIF 0U
#define GD32_DMA_ISR_DMEIF 0U
#define GD32_DMA_ISR_TEIF DMA_ISR_TEIF1
#define GD32_DMA_ISR_HTIF DMA_ISR_HTIF1
#define GD32_DMA_ISR_TCIF DMA_ISR_TCIF1
/** @} */
/*===========================================================================*/
@ -236,19 +236,19 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !defined(STM32_DMA1_NUM_CHANNELS)
#error "STM32_DMA1_NUM_CHANNELS not defined in registry"
#if !defined(GD32_DMA1_NUM_CHANNELS)
#error "GD32_DMA1_NUM_CHANNELS not defined in registry"
#endif
#if !defined(STM32_DMA2_NUM_CHANNELS)
#error "STM32_DMA2_NUM_CHANNELS not defined in registry"
#if !defined(GD32_DMA2_NUM_CHANNELS)
#error "GD32_DMA2_NUM_CHANNELS not defined in registry"
#endif
#if (STM32_DMA1_NUM_CHANNELS < 0) || (STM32_DMA1_NUM_CHANNELS > 7)
#if (GD32_DMA1_NUM_CHANNELS < 0) || (GD32_DMA1_NUM_CHANNELS > 7)
#error "unsupported channels configuration"
#endif
#if (STM32_DMA2_NUM_CHANNELS < 0) || (STM32_DMA2_NUM_CHANNELS > 5)
#if (GD32_DMA2_NUM_CHANNELS < 0) || (GD32_DMA2_NUM_CHANNELS > 5)
#error "unsupported channels configuration"
#endif
@ -357,7 +357,7 @@ typedef struct {
*
* @special
*/
#if STM32_DMA_SUPPORTS_CSELR || defined(__DOXYGEN__)
#if GD32_DMA_SUPPORTS_CSELR || defined(__DOXYGEN__)
#define dmaStreamSetMode(dmastp, mode) { \
uint32_t cselr = *(dmastp)->cselr; \
cselr &= ~(0x0000000FU << (dmastp)->shift); \
@ -382,7 +382,7 @@ typedef struct {
* @special
*/
#define dmaStreamEnable(dmastp) { \
(dmastp)->channel->CCR |= STM32_DMA_CR_EN; \
(dmastp)->channel->CCR |= GD32_DMA_CR_EN; \
}
/**
@ -400,8 +400,8 @@ typedef struct {
* @special
*/
#define dmaStreamDisable(dmastp) { \
(dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \
(dmastp)->channel->CCR &= ~(GD32_DMA_CR_TCIE | GD32_DMA_CR_HTIE | \
GD32_DMA_CR_TEIE | GD32_DMA_CR_EN); \
dmaStreamClearInterrupt(dmastp); \
}
@ -416,7 +416,7 @@ typedef struct {
* @special
*/
#define dmaStreamClearInterrupt(dmastp) { \
(dmastp)->dma->IFCR = STM32_DMA_ISR_MASK << (dmastp)->shift; \
(dmastp)->dma->IFCR = GD32_DMA_ISR_MASK << (dmastp)->shift; \
}
/**
@ -429,10 +429,10 @@ typedef struct {
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] mode value to be written in the CCR register, this value
* is implicitly ORed with:
* - @p STM32_DMA_CR_MINC
* - @p STM32_DMA_CR_PINC
* - @p STM32_DMA_CR_DIR_M2M
* - @p STM32_DMA_CR_EN
* - @p GD32_DMA_CR_MINC
* - @p GD32_DMA_CR_PINC
* - @p GD32_DMA_CR_DIR_M2M
* - @p GD32_DMA_CR_EN
* .
* @param[in] src source address
* @param[in] dst destination address
@ -443,8 +443,8 @@ typedef struct {
dmaStreamSetMemory0(dmastp, dst); \
dmaStreamSetTransactionSize(dmastp, n); \
dmaStreamSetMode(dmastp, (mode) | \
STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \
GD32_DMA_CR_MINC | GD32_DMA_CR_PINC | \
GD32_DMA_CR_DIR_M2M | GD32_DMA_CR_EN); \
}
/**
@ -466,7 +466,7 @@ typedef struct {
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
extern const stm32_dma_stream_t _stm32_dma_streams[GD32_DMA_STREAMS];
#endif
#ifdef __cplusplus
@ -484,13 +484,13 @@ extern "C" {
void dmaStreamFreeI(const stm32_dma_stream_t *dmastp);
void dmaStreamFree(const stm32_dma_stream_t *dmastp);
void dmaServeInterrupt(const stm32_dma_stream_t *dmastp);
#if STM32_DMA_SUPPORTS_DMAMUX == TRUE
#if GD32_DMA_SUPPORTS_DMAMUX == TRUE
void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per);
#endif
#ifdef __cplusplus
}
#endif
#endif /* STM32_DMA_H */
#endif /* GD32_DMA_H */
/** @} */

6
os/hal/ports/GD/GD32VF103/DMA/stm32_dma1_ch23.inc
View File

@ -51,7 +51,7 @@
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
#if defined(GD32_DMA_REQUIRED) || defined(__DOXYGEN__)
/**
* @brief DMA1 streams 2 and 3 shared ISR.
*
@ -62,10 +62,10 @@ OSAL_IRQ_HANDLER(GD32_DMA1_CH23_HANDLER) {
OSAL_IRQ_PROLOGUE();
/* Check on channel 2.*/
dmaServeInterrupt(STM32_DMA1_STREAM2);
dmaServeInterrupt(GD32_DMA1_STREAM2);
/* Check on channel 3.*/
dmaServeInterrupt(STM32_DMA1_STREAM3);
dmaServeInterrupt(GD32_DMA1_STREAM3);
OSAL_IRQ_EPILOGUE();
}

10
os/hal/ports/GD/GD32VF103/DMA/stm32_dma1_ch4567.inc
View File

@ -51,7 +51,7 @@
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
#if defined(GD32_DMA_REQUIRED) || defined(__DOXYGEN__)
/**
* @brief DMA1 streams 4, 5, 6 and 7 shared ISR.
*
@ -62,16 +62,16 @@ OSAL_IRQ_HANDLER(GD32_DMA1_CH4567_HANDLER) {
OSAL_IRQ_PROLOGUE();
/* Check on channel 4.*/
dmaServeInterrupt(STM32_DMA1_STREAM4);
dmaServeInterrupt(GD32_DMA1_STREAM4);
/* Check on channel 5.*/
dmaServeInterrupt(STM32_DMA1_STREAM5);
dmaServeInterrupt(GD32_DMA1_STREAM5);
/* Check on channel 6.*/
dmaServeInterrupt(STM32_DMA1_STREAM6);
dmaServeInterrupt(GD32_DMA1_STREAM6);
/* Check on channel 7.*/
dmaServeInterrupt(STM32_DMA1_STREAM7);
dmaServeInterrupt(GD32_DMA1_STREAM7);
OSAL_IRQ_EPILOGUE();
}

14
os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c
View File

@ -30,12 +30,12 @@
/* Driver local definitions. */
/*===========================================================================*/
#if STM32_HAS_GPIOG
#if GD32_HAS_GPIOG
#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \
RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN)
#elif STM32_HAS_GPIOE
#elif GD32_HAS_GPIOE
#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN)
@ -110,15 +110,15 @@ void _pal_lld_init(const PALConfig *config) {
GPIOD->ODR = config->PDData.odr;
GPIOD->CRH = config->PDData.crh;
GPIOD->CRL = config->PDData.crl;
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
#if GD32_HAS_GPIOE || defined(__DOXYGEN__)
GPIOE->ODR = config->PEData.odr;
GPIOE->CRH = config->PEData.crh;
GPIOE->CRL = config->PEData.crl;
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
#if GD32_HAS_GPIOF || defined(__DOXYGEN__)
GPIOF->ODR = config->PFData.odr;
GPIOF->CRH = config->PFData.crh;
GPIOF->CRL = config->PFData.crl;
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
#if GD32_HAS_GPIOG || defined(__DOXYGEN__)
GPIOG->ODR = config->PGData.odr;
GPIOG->CRH = config->PGData.crh;
GPIOG->CRL = config->PGData.crl;
@ -162,8 +162,8 @@ void _pal_lld_setgroupmode(ioportid_t port,
8, /* Reserved.*/
8, /* Reserved.*/
8, /* Reserved.*/
0xB, /* PAL_MODE_STM32_ALTERNATE_PUSHPULL, 50MHz.*/
0xF, /* PAL_MODE_STM32_ALTERNATE_OPENDRAIN, 50MHz.*/
0xB, /* PAL_MODE_GD32_ALTERNATE_PUSHPULL, 50MHz.*/
0xF, /* PAL_MODE_GD32_ALTERNATE_OPENDRAIN, 50MHz.*/
};
uint32_t mh, ml, crh, crl, cfg;
unsigned i;

24
os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.h
View File

@ -38,12 +38,12 @@
/**
* @brief STM32 specific alternate push-pull output mode.
*/
#define PAL_MODE_STM32_ALTERNATE_PUSHPULL 16
#define PAL_MODE_GD32_ALTERNATE_PUSHPULL 16
/**
* @brief STM32 specific alternate open-drain output mode.
*/
#define PAL_MODE_STM32_ALTERNATE_OPENDRAIN 17
#define PAL_MODE_GD32_ALTERNATE_OPENDRAIN 17
/** @} */
/*===========================================================================*/
@ -126,13 +126,13 @@ typedef struct {
stm32_gpio_setup_t PCData;
/** @brief Port D setup data.*/
stm32_gpio_setup_t PDData;
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
#if GD32_HAS_GPIOE || defined(__DOXYGEN__)
/** @brief Port E setup data.*/
stm32_gpio_setup_t PEData;
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
#if GD32_HAS_GPIOF || defined(__DOXYGEN__)
/** @brief Port F setup data.*/
stm32_gpio_setup_t PFData;
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
#if GD32_HAS_GPIOG || defined(__DOXYGEN__)
/** @brief Port G setup data.*/
stm32_gpio_setup_t PGData;
#endif
@ -182,49 +182,49 @@ typedef uint32_t iopadid_t;
/**
* @brief GPIO port A identifier.
*/
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
#if GD32_HAS_GPIOA || defined(__DOXYGEN__)
#define IOPORT1 GPIOA
#endif
/**
* @brief GPIO port B identifier.
*/
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
#if GD32_HAS_GPIOB || defined(__DOXYGEN__)
#define IOPORT2 GPIOB
#endif
/**
* @brief GPIO port C identifier.
*/
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
#if GD32_HAS_GPIOC || defined(__DOXYGEN__)
#define IOPORT3 GPIOC
#endif
/**
* @brief GPIO port D identifier.
*/
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
#if GD32_HAS_GPIOD || defined(__DOXYGEN__)
#define IOPORT4 GPIOD
#endif
/**
* @brief GPIO port E identifier.
*/
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
#if GD32_HAS_GPIOE || defined(__DOXYGEN__)
#define IOPORT5 GPIOE
#endif
/**
* @brief GPIO port F identifier.
*/
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
#if GD32_HAS_GPIOF || defined(__DOXYGEN__)
#define IOPORT6 GPIOF
#endif
/**
* @brief GPIO port G identifier.
*/
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
#if GD32_HAS_GPIOG || defined(__DOXYGEN__)
#define IOPORT7 GPIOG
#endif

152
os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.c
View File

@ -35,28 +35,28 @@
/*===========================================================================*/
#define I2C1_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \
STM32_I2C1_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_I2C_I2C1_RX_DMA_STREAM, \
GD32_I2C1_RX_DMA_CHN)
#define I2C1_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \
STM32_I2C1_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_I2C_I2C1_TX_DMA_STREAM, \
GD32_I2C1_TX_DMA_CHN)
#define I2C2_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \
STM32_I2C2_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_I2C_I2C2_RX_DMA_STREAM, \
GD32_I2C2_RX_DMA_CHN)
#define I2C2_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \
STM32_I2C2_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_I2C_I2C2_TX_DMA_STREAM, \
GD32_I2C2_TX_DMA_CHN)
#define I2C3_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_RX_DMA_STREAM, \
STM32_I2C3_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_I2C_I2C3_RX_DMA_STREAM, \
GD32_I2C3_RX_DMA_CHN)
#define I2C3_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM, \
STM32_I2C3_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_I2C_I2C3_TX_DMA_STREAM, \
GD32_I2C3_TX_DMA_CHN)
/*===========================================================================*/
/* Driver constants. */
@ -93,17 +93,17 @@
/*===========================================================================*/
/** @brief I2C1 driver identifier.*/
#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
#if GD32_I2C_USE_I2C1 || defined(__DOXYGEN__)
I2CDriver I2CD1;
#endif
/** @brief I2C2 driver identifier.*/
#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
#if GD32_I2C_USE_I2C2 || defined(__DOXYGEN__)
I2CDriver I2CD2;
#endif
/** @brief I2C3 driver identifier.*/
#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__)
#if GD32_I2C_USE_I2C3 || defined(__DOXYGEN__)
I2CDriver I2CD3;
#endif
@ -166,9 +166,9 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
osalDbgAssert(duty == STD_DUTY_CYCLE, "invalid standard mode duty cycle");
/* Standard mode clock_div calculate: Tlow/Thigh = 1/1.*/
osalDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0,
osalDbgAssert((GD32_PCLK1 % (clock_speed * 2)) == 0,
"PCLK1 must be divisible without remainder");
clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2));
clock_div = (uint16_t)(GD32_PCLK1 / (clock_speed * 2));
osalDbgAssert(clock_div >= 0x04,
"clock divider less then 0x04 not allowed");
@ -185,15 +185,15 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
if (duty == FAST_DUTY_CYCLE_2) {
/* Fast mode clock_div calculate: Tlow/Thigh = 2/1.*/
osalDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0,
osalDbgAssert((GD32_PCLK1 % (clock_speed * 3)) == 0,
"PCLK1 must be divided without remainder");
clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3));
clock_div = (uint16_t)(GD32_PCLK1 / (clock_speed * 3));
}
else if (duty == FAST_DUTY_CYCLE_16_9) {
/* Fast mode clock_div calculate: Tlow/Thigh = 16/9.*/
osalDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0,
osalDbgAssert((GD32_PCLK1 % (clock_speed * 25)) == 0,
"PCLK1 must be divided without remainder");
clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25));
clock_div = (uint16_t)(GD32_PCLK1 / (clock_speed * 25));
regCCR |= I2C_CCR_DUTY;
}
@ -328,9 +328,9 @@ static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) {
I2C_TypeDef *dp = i2cp->i2c;
/* DMA errors handling.*/
#if defined(STM32_I2C_DMA_ERROR_HOOK)
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
STM32_I2C_DMA_ERROR_HOOK(i2cp);
#if defined(GD32_I2C_DMA_ERROR_HOOK)
if ((flags & (GD32_DMA_ISR_TEIF | GD32_DMA_ISR_DMEIF)) != 0) {
GD32_I2C_DMA_ERROR_HOOK(i2cp);
}
#else
(void)flags;
@ -355,9 +355,9 @@ static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) {
I2C_TypeDef *dp = i2cp->i2c;
/* DMA errors handling.*/
#if defined(STM32_I2C_DMA_ERROR_HOOK)
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
STM32_I2C_DMA_ERROR_HOOK(i2cp);
#if defined(GD32_I2C_DMA_ERROR_HOOK)
if ((flags & (GD32_DMA_ISR_TEIF | GD32_DMA_ISR_DMEIF)) != 0) {
GD32_I2C_DMA_ERROR_HOOK(i2cp);
}
#else
(void)flags;
@ -423,7 +423,7 @@ static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
#if GD32_I2C_USE_I2C1 || defined(__DOXYGEN__)
/**
* @brief I2C1 event interrupt handler.
*
@ -451,9 +451,9 @@ OSAL_IRQ_HANDLER(GD32_I2C1_ERROR_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_I2C_USE_I2C1 */
#endif /* GD32_I2C_USE_I2C1 */
#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
#if GD32_I2C_USE_I2C2 || defined(__DOXYGEN__)
/**
* @brief I2C2 event interrupt handler.
*
@ -483,9 +483,9 @@ OSAL_IRQ_HANDLER(GD32_I2C2_ERROR_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_I2C_USE_I2C2 */
#endif /* GD32_I2C_USE_I2C2 */
#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__)
#if GD32_I2C_USE_I2C3 || defined(__DOXYGEN__)
/**
* @brief I2C3 event interrupt handler.
*
@ -515,7 +515,7 @@ OSAL_IRQ_HANDLER(GD32_I2C3_ERROR_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_I2C_USE_I2C3 */
#endif /* GD32_I2C_USE_I2C3 */
/*===========================================================================*/
/* Driver exported functions. */
@ -528,29 +528,29 @@ OSAL_IRQ_HANDLER(GD32_I2C3_ERROR_HANDLER) {
*/
void i2c_lld_init(void) {
#if STM32_I2C_USE_I2C1
#if GD32_I2C_USE_I2C1
i2cObjectInit(&I2CD1);
I2CD1.thread = NULL;
I2CD1.i2c = I2C1;
I2CD1.dmarx = NULL;
I2CD1.dmatx = NULL;
#endif /* STM32_I2C_USE_I2C1 */
#endif /* GD32_I2C_USE_I2C1 */
#if STM32_I2C_USE_I2C2
#if GD32_I2C_USE_I2C2
i2cObjectInit(&I2CD2);
I2CD2.thread = NULL;
I2CD2.i2c = I2C2;
I2CD2.dmarx = NULL;
I2CD2.dmatx = NULL;
#endif /* STM32_I2C_USE_I2C2 */
#endif /* GD32_I2C_USE_I2C2 */
#if STM32_I2C_USE_I2C3
#if GD32_I2C_USE_I2C3
i2cObjectInit(&I2CD3);
I2CD3.thread = NULL;
I2CD3.i2c = I2C3;
I2CD3.dmarx = NULL;
I2CD3.dmatx = NULL;
#endif /* STM32_I2C_USE_I2C3 */
#endif /* GD32_I2C_USE_I2C3 */
}
/**
@ -566,66 +566,66 @@ void i2c_lld_start(I2CDriver *i2cp) {
/* If in stopped state then enables the I2C and DMA clocks.*/
if (i2cp->state == I2C_STOP) {
i2cp->txdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DIR_M2P;
i2cp->rxdmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DIR_P2M;
i2cp->txdmamode = GD32_DMA_CR_PSIZE_BYTE | GD32_DMA_CR_MSIZE_BYTE |
GD32_DMA_CR_MINC | GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE | GD32_DMA_CR_TCIE |
GD32_DMA_CR_DIR_M2P;
i2cp->rxdmamode = GD32_DMA_CR_PSIZE_BYTE | GD32_DMA_CR_MSIZE_BYTE |
GD32_DMA_CR_MINC | GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE | GD32_DMA_CR_TCIE |
GD32_DMA_CR_DIR_P2M;
#if STM32_I2C_USE_I2C1
#if GD32_I2C_USE_I2C1
if (&I2CD1 == i2cp) {
rccResetI2C1();
i2cp->dmarx = dmaStreamAllocI(STM32_I2C_I2C1_RX_DMA_STREAM,
STM32_I2C_I2C1_IRQ_PRIORITY,
i2cp->dmarx = dmaStreamAllocI(GD32_I2C_I2C1_RX_DMA_STREAM,
GD32_I2C_I2C1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
(void *)i2cp);
osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream");
i2cp->dmatx = dmaStreamAllocI(STM32_I2C_I2C1_TX_DMA_STREAM,
STM32_I2C_I2C1_IRQ_PRIORITY,
i2cp->dmatx = dmaStreamAllocI(GD32_I2C_I2C1_TX_DMA_STREAM,
GD32_I2C_I2C1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
(void *)i2cp);
osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream");
rccEnableI2C1(true);
eclicEnableVector(I2C0_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY, STM32_I2C_I2C1_IRQ_TRIGGER);
eclicEnableVector(I2C0_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY, STM32_I2C_I2C1_IRQ_TRIGGER);
eclicEnableVector(I2C0_EV_IRQn, GD32_I2C_I2C1_IRQ_PRIORITY, GD32_I2C_I2C1_IRQ_TRIGGER);
eclicEnableVector(I2C0_ER_IRQn, GD32_I2C_I2C1_IRQ_PRIORITY, GD32_I2C_I2C1_IRQ_TRIGGER);
i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
i2cp->rxdmamode |= GD32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_I2C_I2C1_DMA_PRIORITY);
i2cp->txdmamode |= GD32_DMA_CR_CHSEL(I2C1_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_I2C_I2C1_DMA_PRIORITY);
}
#endif /* STM32_I2C_USE_I2C1 */
#endif /* GD32_I2C_USE_I2C1 */
#if STM32_I2C_USE_I2C2
#if GD32_I2C_USE_I2C2
if (&I2CD2 == i2cp) {
rccResetI2C2();
i2cp->dmarx = dmaStreamAllocI(STM32_I2C_I2C2_RX_DMA_STREAM,
STM32_I2C_I2C2_IRQ_PRIORITY,
i2cp->dmarx = dmaStreamAllocI(GD32_I2C_I2C2_RX_DMA_STREAM,
GD32_I2C_I2C2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
(void *)i2cp);
osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream");
i2cp->dmatx = dmaStreamAllocI(STM32_I2C_I2C2_TX_DMA_STREAM,
STM32_I2C_I2C2_IRQ_PRIORITY,
i2cp->dmatx = dmaStreamAllocI(GD32_I2C_I2C2_TX_DMA_STREAM,
GD32_I2C_I2C2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
(void *)i2cp);
osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream");
rccEnableI2C2(true);
eclicEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY, STM32_I2C_I2C2_IRQ_TRIGGER);
eclicEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY, STM32_I2C_I2C2_IRQ_TRIGGER);
eclicEnableVector(I2C1_EV_IRQn, GD32_I2C_I2C2_IRQ_PRIORITY, GD32_I2C_I2C2_IRQ_TRIGGER);
eclicEnableVector(I2C1_ER_IRQn, GD32_I2C_I2C2_IRQ_PRIORITY, GD32_I2C_I2C2_IRQ_TRIGGER);
i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
i2cp->txdmamode |= STM32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
i2cp->rxdmamode |= GD32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_I2C_I2C2_DMA_PRIORITY);
i2cp->txdmamode |= GD32_DMA_CR_CHSEL(I2C2_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_I2C_I2C2_DMA_PRIORITY);
}
#endif /* STM32_I2C_USE_I2C2 */
#endif /* GD32_I2C_USE_I2C2 */
}
/* I2C registers pointed by the DMA.*/
@ -663,7 +663,7 @@ void i2c_lld_stop(I2CDriver *i2cp) {
i2cp->dmatx = NULL;
i2cp->dmarx = NULL;
#if STM32_I2C_USE_I2C1
#if GD32_I2C_USE_I2C1
if (&I2CD1 == i2cp) {
eclicDisableVector(I2C1_EV_IRQn);
eclicDisableVector(I2C1_ER_IRQn);
@ -671,7 +671,7 @@ void i2c_lld_stop(I2CDriver *i2cp) {
}
#endif
#if STM32_I2C_USE_I2C2
#if GD32_I2C_USE_I2C2
if (&I2CD2 == i2cp) {
eclicDisableVector(I2C2_EV_IRQn);
eclicDisableVector(I2C2_ER_IRQn);
@ -679,7 +679,7 @@ void i2c_lld_stop(I2CDriver *i2cp) {
}
#endif
#if STM32_I2C_USE_I2C3
#if GD32_I2C_USE_I2C3
if (&I2CD3 == i2cp) {
eclicDisableVector(I2C3_EV_IRQn);
eclicDisableVector(I2C3_ER_IRQn);
@ -739,7 +739,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
/* Calculating the time window for the timeout on the busy bus condition.*/
start = osalOsGetSystemTimeX();
end = osalTimeAddX(start, OSAL_MS2I(STM32_I2C_BUSY_TIMEOUT));
end = osalTimeAddX(start, OSAL_MS2I(GD32_I2C_BUSY_TIMEOUT));
/* Waits until BUSY flag is reset or, alternatively, for a timeout
condition.*/
@ -832,7 +832,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
/* Calculating the time window for the timeout on the busy bus condition.*/
start = osalOsGetSystemTimeX();
end = osalTimeAddX(start, OSAL_MS2I(STM32_I2C_BUSY_TIMEOUT));
end = osalTimeAddX(start, OSAL_MS2I(GD32_I2C_BUSY_TIMEOUT));
/* Waits until BUSY flag is reset or, alternatively, for a timeout
condition.*/

176
os/hal/ports/GD/GD32VF103/I2C/hal_i2c_lld.h
View File

@ -38,7 +38,7 @@
/**
* @brief Peripheral clock frequency.
*/
#define I2C_CLK_FREQ ((STM32_PCLK1) / 1000000)
#define I2C_CLK_FREQ ((GD32_PCLK1) / 1000000)
/*===========================================================================*/
/* Driver pre-compile time settings. */
@ -53,8 +53,8 @@
* @details If set to @p TRUE the support for I2C1 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
#define STM32_I2C_USE_I2C1 FALSE
#if !defined(GD32_I2C_USE_I2C1) || defined(__DOXYGEN__)
#define GD32_I2C_USE_I2C1 FALSE
#endif
/**
@ -62,8 +62,8 @@
* @details If set to @p TRUE the support for I2C2 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
#define STM32_I2C_USE_I2C2 FALSE
#if !defined(GD32_I2C_USE_I2C2) || defined(__DOXYGEN__)
#define GD32_I2C_USE_I2C2 FALSE
#endif
/**
@ -71,36 +71,36 @@
* @details If set to @p TRUE the support for I2C3 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__)
#define STM32_I2C_USE_I2C3 FALSE
#if !defined(GD32_I2C_USE_I2C3) || defined(__DOXYGEN__)
#define GD32_I2C_USE_I2C3 FALSE
#endif
/**
* @brief I2C timeout on busy condition in milliseconds.
*/
#if !defined(STM32_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__)
#define STM32_I2C_BUSY_TIMEOUT 50
#if !defined(GD32_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__)
#define GD32_I2C_BUSY_TIMEOUT 50
#endif
/**
* @brief I2C1 interrupt priority level setting.
*/
#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2C_I2C1_IRQ_PRIORITY 10
#if !defined(GD32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2C_I2C1_IRQ_PRIORITY 10
#endif
/**
* @brief I2C2 interrupt priority level setting.
*/
#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2C_I2C2_IRQ_PRIORITY 10
#if !defined(GD32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2C_I2C2_IRQ_PRIORITY 10
#endif
/**
* @brief I2C3 interrupt priority level setting.
*/
#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2C_I2C3_IRQ_PRIORITY 10
#if !defined(GD32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2C_I2C3_IRQ_PRIORITY 10
#endif
/**
@ -109,8 +109,8 @@
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2C_I2C1_DMA_PRIORITY 1
#if !defined(GD32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2C_I2C1_DMA_PRIORITY 1
#endif
/**
@ -119,8 +119,8 @@
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2C_I2C2_DMA_PRIORITY 1
#if !defined(GD32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2C_I2C2_DMA_PRIORITY 1
#endif
/**
@ -129,8 +129,8 @@
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(STM32_I2C_I2C3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2C_I2C3_DMA_PRIORITY 1
#if !defined(GD32_I2C_I2C3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2C_I2C3_DMA_PRIORITY 1
#endif
/**
@ -138,70 +138,70 @@
* @note The default action for DMA errors is a system halt because DMA
* error can only happen because programming errors.
*/
#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
#if !defined(GD32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define GD32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
#endif
#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
#if GD32_ADVANCED_DMA || defined(__DOXYGEN__)
/**
* @brief DMA stream used for I2C1 RX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_I2C_I2C1_RX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#if !defined(GD32_I2C_I2C1_RX_DMA_STREAM) || defined(__DOXYGEN__)
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 0)
#endif
/**
* @brief DMA stream used for I2C1 TX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_I2C_I2C1_TX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#if !defined(GD32_I2C_I2C1_TX_DMA_STREAM) || defined(__DOXYGEN__)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#endif
/**
* @brief DMA stream used for I2C2 RX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_I2C_I2C2_RX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#if !defined(GD32_I2C_I2C2_RX_DMA_STREAM) || defined(__DOXYGEN__)
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#endif
/**
* @brief DMA stream used for I2C2 TX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_I2C_I2C2_TX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#if !defined(GD32_I2C_I2C2_TX_DMA_STREAM) || defined(__DOXYGEN__)
#define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#endif
/**
* @brief DMA stream used for I2C3 RX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_I2C_I2C3_RX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#if !defined(GD32_I2C_I2C3_RX_DMA_STREAM) || defined(__DOXYGEN__)
#define GD32_I2C_I2C3_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#endif
/**
* @brief DMA stream used for I2C3 TX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_I2C_I2C3_TX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#if !defined(GD32_I2C_I2C3_TX_DMA_STREAM) || defined(__DOXYGEN__)
#define GD32_I2C_I2C3_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#endif
#else /* !STM32_ADVANCED_DMA */
#else /* !GD32_ADVANCED_DMA */
/* Fixed streams for platforms using the old DMA peripheral, the values are
valid for both STM32F1xx and STM32L1xx.*/
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#endif /* !STM32_ADVANCED_DMA*/
#endif /* !GD32_ADVANCED_DMA*/
/* Flag for the whole STM32F1XX family. */
#if defined(STM32F10X_LD_VL) || defined(GD32VF103_MD_VL) || \
@ -217,107 +217,107 @@
/*===========================================================================*/
/** @brief error checks */
#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1
#if GD32_I2C_USE_I2C1 && !GD32_HAS_I2C1
#error "I2C1 not present in the selected device"
#endif
#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2
#if GD32_I2C_USE_I2C2 && !GD32_HAS_I2C2
#error "I2C2 not present in the selected device"
#endif
#if STM32_I2C_USE_I2C3 && !STM32_HAS_I2C3
#if GD32_I2C_USE_I2C3 && !GD32_HAS_I2C3
#error "I2C3 not present in the selected device"
#endif
#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 && \
!STM32_I2C_USE_I2C3
#if !GD32_I2C_USE_I2C1 && !GD32_I2C_USE_I2C2 && \
!GD32_I2C_USE_I2C3
#error "I2C driver activated but no I2C peripheral assigned"
#endif
#if STM32_I2C_USE_I2C1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C1_IRQ_PRIORITY)
#if GD32_I2C_USE_I2C1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_I2C_I2C1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to I2C1"
#endif
#if STM32_I2C_USE_I2C2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C2_IRQ_PRIORITY)
#if GD32_I2C_USE_I2C2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_I2C_I2C2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to I2C2"
#endif
#if STM32_I2C_USE_I2C3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2C_I2C3_IRQ_PRIORITY)
#if GD32_I2C_USE_I2C3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_I2C_I2C3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to I2C3"
#endif
#if STM32_I2C_USE_I2C1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C1_DMA_PRIORITY)
#if GD32_I2C_USE_I2C1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_I2C_I2C1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to I2C1"
#endif
#if STM32_I2C_USE_I2C2 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C2_DMA_PRIORITY)
#if GD32_I2C_USE_I2C2 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_I2C_I2C2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to I2C2"
#endif
#if STM32_I2C_USE_I2C3 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C3_DMA_PRIORITY)
#if GD32_I2C_USE_I2C3 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_I2C_I2C3_DMA_PRIORITY)
#error "Invalid DMA priority assigned to I2C3"
#endif
/* The following checks are only required when there is a DMA able to
reassign streams to different channels.*/
#if STM32_ADVANCED_DMA
#if GD32_ADVANCED_DMA
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_I2C_USE_I2C1 && (!defined(STM32_I2C_I2C1_RX_DMA_STREAM) || \
!defined(STM32_I2C_I2C1_TX_DMA_STREAM))
#if GD32_I2C_USE_I2C1 && (!defined(GD32_I2C_I2C1_RX_DMA_STREAM) || \
!defined(GD32_I2C_I2C1_TX_DMA_STREAM))
#error "I2C1 DMA streams not defined"
#endif
#if STM32_I2C_USE_I2C2 && (!defined(STM32_I2C_I2C2_RX_DMA_STREAM) || \
!defined(STM32_I2C_I2C2_TX_DMA_STREAM))
#if GD32_I2C_USE_I2C2 && (!defined(GD32_I2C_I2C2_RX_DMA_STREAM) || \
!defined(GD32_I2C_I2C2_TX_DMA_STREAM))
#error "I2C2 DMA streams not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_I2C_USE_I2C1 && \
!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \
STM32_I2C1_RX_DMA_MSK)
#if GD32_I2C_USE_I2C1 && \
!GD32_DMA_IS_VALID_ID(GD32_I2C_I2C1_RX_DMA_STREAM, \
GD32_I2C1_RX_DMA_MSK)
#error "invalid DMA stream associated to I2C1 RX"
#endif
#if STM32_I2C_USE_I2C1 && \
!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \
STM32_I2C1_TX_DMA_MSK)
#if GD32_I2C_USE_I2C1 && \
!GD32_DMA_IS_VALID_ID(GD32_I2C_I2C1_TX_DMA_STREAM, \
GD32_I2C1_TX_DMA_MSK)
#error "invalid DMA stream associated to I2C1 TX"
#endif
#if STM32_I2C_USE_I2C2 && \
!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \
STM32_I2C2_RX_DMA_MSK)
#if GD32_I2C_USE_I2C2 && \
!GD32_DMA_IS_VALID_ID(GD32_I2C_I2C2_RX_DMA_STREAM, \
GD32_I2C2_RX_DMA_MSK)
#error "invalid DMA stream associated to I2C2 RX"
#endif
#if STM32_I2C_USE_I2C2 && \
!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \
STM32_I2C2_TX_DMA_MSK)
#if GD32_I2C_USE_I2C2 && \
!GD32_DMA_IS_VALID_ID(GD32_I2C_I2C2_TX_DMA_STREAM, \
GD32_I2C2_TX_DMA_MSK)
#error "invalid DMA stream associated to I2C2 TX"
#endif
#if STM32_I2C_USE_I2C3 && \
!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM, \
STM32_I2C3_RX_DMA_MSK)
#if GD32_I2C_USE_I2C3 && \
!GD32_DMA_IS_VALID_ID(GD32_I2C_I2C3_RX_DMA_STREAM, \
GD32_I2C3_RX_DMA_MSK)
#error "invalid DMA stream associated to I2C3 RX"
#endif
#if STM32_I2C_USE_I2C3 && \
!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM, \
STM32_I2C3_TX_DMA_MSK)
#if GD32_I2C_USE_I2C3 && \
!GD32_DMA_IS_VALID_ID(GD32_I2C_I2C3_TX_DMA_STREAM, \
GD32_I2C3_TX_DMA_MSK)
#error "invalid DMA stream associated to I2C3 TX"
#endif
#endif /* STM32_ADVANCED_DMA */
#endif /* GD32_ADVANCED_DMA */
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#if !defined(GD32_DMA_REQUIRED)
#define GD32_DMA_REQUIRED
#endif
/* Check clock range. */
@ -461,15 +461,15 @@ struct I2CDriver {
/*===========================================================================*/
#if !defined(__DOXYGEN__)
#if STM32_I2C_USE_I2C1
#if GD32_I2C_USE_I2C1
extern I2CDriver I2CD1;
#endif
#if STM32_I2C_USE_I2C2
#if GD32_I2C_USE_I2C2
extern I2CDriver I2CD2;
#endif
#if STM32_I2C_USE_I2C3
#if GD32_I2C_USE_I2C3
extern I2CDriver I2CD3;
#endif
#endif /* !defined(__DOXYGEN__) */

67
os/hal/ports/GD/GD32VF103/OTG/hal_usb_lld.c
View File

@ -38,7 +38,7 @@
#define EP0_MAX_INSIZE 64
#define EP0_MAX_OUTSIZE 64
#if STM32_OTG_STEPPING == 1
#if GD32_OTG_STEPPING == 1
#if defined(BOARD_OTG_NOVBUSSENS)
#define GCCFG_INIT_VALUE (GCCFG_NOVBUSSENS | GCCFG_VBUSASEN | \
GCCFG_VBUSBSEN | GCCFG_PWRDWN)
@ -47,7 +47,7 @@
GCCFG_PWRDWN)
#endif
#elif STM32_OTG_STEPPING == 2
#elif GD32_OTG_STEPPING == 2
#if defined(BOARD_OTG_NOVBUSSENS)
#define GCCFG_INIT_VALUE GCCFG_PWRDWN
#else
@ -61,12 +61,12 @@
/*===========================================================================*/
/** @brief OTG_FS driver identifier.*/
#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__)
#if GD32_USB_USE_OTG1 || defined(__DOXYGEN__)
USBDriver USBD1;
#endif
/** @brief OTG_HS driver identifier.*/
#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__)
#if GD32_USB_USE_OTG2 || defined(__DOXYGEN__)
USBDriver USBD2;
#endif
@ -111,19 +111,19 @@ static const USBEndpointConfig ep0config = {
ep0setup_buffer
};
#if STM32_USB_USE_OTG1
#if GD32_USB_USE_OTG1
static const stm32_otg_params_t fsparams = {
STM32_USB_OTG1_RX_FIFO_SIZE / 4,
STM32_OTG1_FIFO_MEM_SIZE,
STM32_OTG1_ENDPOINTS
GD32_USB_OTG1_RX_FIFO_SIZE / 4,
GD32_OTG1_FIFO_MEM_SIZE,
GD32_OTG1_ENDPOINTS
};
#endif
#if STM32_USB_USE_OTG2
#if GD32_USB_USE_OTG2
static const stm32_otg_params_t hsparams = {
STM32_USB_OTG2_RX_FIFO_SIZE / 4,
STM32_OTG2_FIFO_MEM_SIZE,
STM32_OTG2_ENDPOINTS
GD32_USB_OTG2_RX_FIFO_SIZE / 4,
GD32_OTG2_FIFO_MEM_SIZE,
GD32_OTG2_ENDPOINTS
};
#endif
@ -349,20 +349,21 @@ static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
if (((usbp->otg->ie[ep].DTXFSTS & DTXFSTS_INEPTFSAV_MASK) * 4) < n)
return false;
#if STM32_USB_OTGFIFO_FILL_BASEPRI
// TODO Enable again or keep brute force?
/*#if GD32_USB_OTGFIFO_FILL_BASEPRI
uint8_t threshold_old = eclic_get_mth();
eclic_set_mth(STM32_USB_OTGFIFO_FILL_BASEPRI);
#endif
osalSysLock();
eclic_set_mth(GD32_USB_OTGFIFO_FILL_BASEPRI);
#endif*/
osalSysLockFromISR();
otg_fifo_write_from_buffer(usbp->otg->FIFO[ep],
usbp->epc[ep]->in_state->txbuf,
n);
usbp->epc[ep]->in_state->txbuf += n;
usbp->epc[ep]->in_state->txcnt += n;
osalSysUnlock();
#if STM32_USB_OTGFIFO_FILL_BASEPRI
osalSysUnlockFromISR();
/*#if GD32_USB_OTGFIFO_FILL_BASEPRI
eclic_set_mth(threshold_old);
#endif
#endif*/
}
}
@ -439,7 +440,7 @@ static void otg_epout_handler(USBDriver *usbp, usbep_t ep) {
/* EP0 requires special handling.*/
if (ep == 0) {
#if defined(STM32_OTG_SEQUENCE_WORKAROUND)
#if defined(GD32_OTG_SEQUENCE_WORKAROUND)
/* If an OUT transaction end interrupt is processed while the state
machine is not in an OUT state then it is ignored, this is caused
on some devices (L4) apparently injecting spurious data complete
@ -675,7 +676,7 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__)
#if GD32_USB_USE_OTG1 || defined(__DOXYGEN__)
/**
* @brief OTG1 interrupt handler.
*
@ -691,7 +692,7 @@ OSAL_IRQ_HANDLER(GD32_OTG1_HANDLER) {
}
#endif
#if STM32_USB_USE_OTG2 || defined(__DOXYGEN__)
#if GD32_USB_USE_OTG2 || defined(__DOXYGEN__)
/**
* @brief OTG2 interrupt handler.
*
@ -719,14 +720,14 @@ OSAL_IRQ_HANDLER(GD32_OTG2_HANDLER) {
void usb_lld_init(void) {
/* Driver initialization.*/
#if STM32_USB_USE_OTG1
#if GD32_USB_USE_OTG1
usbObjectInit(&USBD1);
USBD1.otg = OTG_FS;
USBD1.otgparams = &fsparams;
#endif
#if STM32_USB_USE_OTG2
#if GD32_USB_USE_OTG2
usbObjectInit(&USBD2);
USBD2.otg = OTG_HS;
USBD2.otgparams = &hsparams;
@ -749,14 +750,14 @@ void usb_lld_start(USBDriver *usbp) {
if (usbp->state == USB_STOP) {
/* Clock activation.*/
#if STM32_USB_USE_OTG1
#if GD32_USB_USE_OTG1
if (&USBD1 == usbp) {
/* OTG FS clock enable and reset.*/
rccEnableOTG_FS(true);
rccResetOTG_FS();
/* Enables IRQ vector.*/
eclicEnableVector(GD32_OTG1_NUMBER, STM32_USB_OTG1_IRQ_PRIORITY, STM32_USB_OTG1_IRQ_TRIGGER);
eclicEnableVector(GD32_OTG1_NUMBER, GD32_USB_OTG1_IRQ_PRIORITY, GD32_USB_OTG1_IRQ_TRIGGER);
/* - Forced device mode.
- USB turn-around time = TRDT_VALUE_FS.
@ -769,7 +770,7 @@ void usb_lld_start(USBDriver *usbp) {
}
#endif
#if STM32_USB_USE_OTG2
#if GD32_USB_USE_OTG2
if (&USBD2 == usbp) {
/* OTG HS clock enable and reset.*/
rccEnableOTG_HS(true);
@ -786,7 +787,7 @@ void usb_lld_start(USBDriver *usbp) {
#endif
/* Enables IRQ vector.*/
eclicEnableVector(GD32_OTG2_NUMBER, STM32_USB_OTG2_IRQ_PRIORITY, STM32_USB_OTG2_IRQ_TRIGGER);
eclicEnableVector(GD32_OTG2_NUMBER, GD32_USB_OTG2_IRQ_PRIORITY, GD32_USB_OTG2_IRQ_TRIGGER);
/* - Forced device mode.
- USB turn-around time = TRDT_VALUE_HS or TRDT_VALUE_FS.*/
@ -800,7 +801,7 @@ void usb_lld_start(USBDriver *usbp) {
#endif
#if defined(BOARD_OTG2_USES_ULPI)
#if STM32_USE_USB_OTG2_HS
#if GD32_USE_USB_OTG2_HS
/* USB 2.0 High Speed PHY in HS mode.*/
otgp->DCFG = 0x02200000 | DCFG_DSPD_HS;
#else
@ -821,13 +822,13 @@ void usb_lld_start(USBDriver *usbp) {
otgp->GOTGCTL = GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
#if defined(BOARD_OTG2_USES_ULPI)
#if STM32_USB_USE_OTG1
#if GD32_USB_USE_OTG1
if (&USBD1 == usbp) {
otgp->GCCFG = GCCFG_INIT_VALUE;
}
#endif
#if STM32_USB_USE_OTG2
#if GD32_USB_USE_OTG2
if (&USBD2 == usbp) {
otgp->GCCFG = 0;
}
@ -889,14 +890,14 @@ void usb_lld_stop(USBDriver *usbp) {
otgp->GAHBCFG = 0;
otgp->GCCFG = 0;
#if STM32_USB_USE_OTG1
#if GD32_USB_USE_OTG1
if (&USBD1 == usbp) {
eclicDisableVector(GD32_OTG1_NUMBER);
rccDisableOTG_FS();
}
#endif
#if STM32_USB_USE_OTG2
#if GD32_USB_USE_OTG2
if (&USBD2 == usbp) {
eclicDisableVector(GD32_OTG2_NUMBER);
rccDisableOTG_HS();

126
os/hal/ports/GD/GD32VF103/OTG/hal_usb_lld.h
View File

@ -57,8 +57,8 @@
* @details If set to @p TRUE the support for OTG_FS is included.
* @note The default is @p FALSE
*/
#if !defined(STM32_USB_USE_OTG1) || defined(__DOXYGEN__)
#define STM32_USB_USE_OTG1 FALSE
#if !defined(GD32_USB_USE_OTG1) || defined(__DOXYGEN__)
#define GD32_USB_USE_OTG1 FALSE
#endif
/**
@ -66,38 +66,38 @@
* @details If set to @p TRUE the support for OTG_HS is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_USB_USE_OTG2) || defined(__DOXYGEN__)
#define STM32_USB_USE_OTG2 FALSE
#if !defined(GD32_USB_USE_OTG2) || defined(__DOXYGEN__)
#define GD32_USB_USE_OTG2 FALSE
#endif
/**
* @brief OTG1 interrupt priority level setting.
*/
#if !defined(STM32_USB_OTG1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_USB_OTG1_IRQ_PRIORITY 1
#if !defined(GD32_USB_OTG1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_USB_OTG1_IRQ_PRIORITY 1
#endif
/**
* @brief OTG2 interrupt priority level setting.
*/
#if !defined(STM32_USB_OTG2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_USB_OTG2_IRQ_PRIORITY 1
#if !defined(GD32_USB_OTG2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_USB_OTG2_IRQ_PRIORITY 1
#endif
/**
* @brief OTG1 RX shared FIFO size.
* @note Must be a multiple of 4.
*/
#if !defined(STM32_USB_OTG1_RX_FIFO_SIZE) || defined(__DOXYGEN__)
#define STM32_USB_OTG1_RX_FIFO_SIZE 128
#if !defined(GD32_USB_OTG1_RX_FIFO_SIZE) || defined(__DOXYGEN__)
#define GD32_USB_OTG1_RX_FIFO_SIZE 128
#endif
/**
* @brief OTG2 RX shared FIFO size.
* @note Must be a multiple of 4.
*/
#if !defined(STM32_USB_OTG2_RX_FIFO_SIZE) || defined(__DOXYGEN__)
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#if !defined(GD32_USB_OTG2_RX_FIFO_SIZE) || defined(__DOXYGEN__)
#define GD32_USB_OTG2_RX_FIFO_SIZE 1024
#endif
/**
@ -105,8 +105,8 @@
* @note The default is @p TRUE.
* @note Has effect only if @p BOARD_OTG2_USES_ULPI is defined.
*/
#if !defined(STM32_USE_USB_OTG2_HS) || defined(__DOXYGEN__)
#define STM32_USE_USB_OTG2_HS TRUE
#if !defined(GD32_USE_USB_OTG2_HS) || defined(__DOXYGEN__)
#define GD32_USE_USB_OTG2_HS TRUE
#endif
/**
@ -124,15 +124,15 @@
* functions is only safe from thread level or from USB
* callbacks.
*/
#if !defined(STM32_USB_OTGFIFO_FILL_BASEPRI) || defined(__DOXYGEN__)
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
#if !defined(GD32_USB_OTGFIFO_FILL_BASEPRI) || defined(__DOXYGEN__)
#define GD32_USB_OTGFIFO_FILL_BASEPRI 0
#endif
/**
* @brief Host wake-up procedure duration.
*/
#if !defined(STM32_USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)
#define STM32_USB_HOST_WAKEUP_DURATION 2
#if !defined(GD32_USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)
#define GD32_USB_HOST_WAKEUP_DURATION 2
#endif
/*===========================================================================*/
@ -140,96 +140,96 @@
/*===========================================================================*/
/* Registry checks.*/
#if !defined(STM32_OTG_STEPPING)
#error "STM32_OTG_STEPPING not defined in registry"
#if !defined(GD32_OTG_STEPPING)
#error "GD32_OTG_STEPPING not defined in registry"
#endif
#if (STM32_OTG_STEPPING < 1) || (STM32_OTG_STEPPING > 2)
#error "unsupported STM32_OTG_STEPPING"
#if (GD32_OTG_STEPPING < 1) || (GD32_OTG_STEPPING > 2)
#error "unsupported GD32_OTG_STEPPING"
#endif
#define STM32_HAS_OTG2 FALSE
#if !defined(STM32_HAS_OTG1) || !defined(STM32_HAS_OTG2)
#error "STM32_HAS_OTGx not defined in registry"
#define GD32_HAS_OTG2 FALSE
#if !defined(GD32_HAS_OTG1) || !defined(GD32_HAS_OTG2)
#error "GD32_HAS_OTGx not defined in registry"
#endif
#if STM32_HAS_OTG1 && !defined(STM32_OTG1_ENDPOINTS)
#error "STM32_OTG1_ENDPOINTS not defined in registry"
#if GD32_HAS_OTG1 && !defined(GD32_OTG1_ENDPOINTS)
#error "GD32_OTG1_ENDPOINTS not defined in registry"
#endif
#if STM32_HAS_OTG2 && !defined(STM32_OTG2_ENDPOINTS)
#error "STM32_OTG2_ENDPOINTS not defined in registry"
#if GD32_HAS_OTG2 && !defined(GD32_OTG2_ENDPOINTS)
#error "GD32_OTG2_ENDPOINTS not defined in registry"
#endif
#if STM32_HAS_OTG1 && !defined(STM32_OTG1_FIFO_MEM_SIZE)
#error "STM32_OTG1_FIFO_MEM_SIZE not defined in registry"
#if GD32_HAS_OTG1 && !defined(GD32_OTG1_FIFO_MEM_SIZE)
#error "GD32_OTG1_FIFO_MEM_SIZE not defined in registry"
#endif
#if STM32_HAS_OTG2 && !defined(STM32_OTG2_FIFO_MEM_SIZE)
#error "STM32_OTG2_FIFO_MEM_SIZE not defined in registry"
#if GD32_HAS_OTG2 && !defined(GD32_OTG2_FIFO_MEM_SIZE)
#error "GD32_OTG2_FIFO_MEM_SIZE not defined in registry"
#endif
#if (STM32_USB_USE_OTG1 && !defined(GD32_OTG1_HANDLER)) || \
(STM32_USB_USE_OTG2 && !defined(GD32_OTG2_HANDLER))
#if (GD32_USB_USE_OTG1 && !defined(GD32_OTG1_HANDLER)) || \
(GD32_USB_USE_OTG2 && !defined(GD32_OTG2_HANDLER))
#error "GD32_OTGx_HANDLER not defined in registry"
#endif
#if (STM32_USB_USE_OTG1 && !defined(GD32_OTG1_NUMBER)) || \
(STM32_USB_USE_OTG2 && !defined(GD32_OTG2_NUMBER))
#if (GD32_USB_USE_OTG1 && !defined(GD32_OTG1_NUMBER)) || \
(GD32_USB_USE_OTG2 && !defined(GD32_OTG2_NUMBER))
#error "GD32_OTGx_NUMBER not defined in registry"
#endif
/**
* @brief Maximum endpoint address.
*/
#if (STM32_HAS_OTG2 && STM32_USB_USE_OTG2) || defined(__DOXYGEN__)
#if (STM32_OTG1_ENDPOINTS < STM32_OTG2_ENDPOINTS) || defined(__DOXYGEN__)
#define USB_MAX_ENDPOINTS STM32_OTG2_ENDPOINTS
#if (GD32_HAS_OTG2 && GD32_USB_USE_OTG2) || defined(__DOXYGEN__)
#if (GD32_OTG1_ENDPOINTS < GD32_OTG2_ENDPOINTS) || defined(__DOXYGEN__)
#define USB_MAX_ENDPOINTS GD32_OTG2_ENDPOINTS
#else
#define USB_MAX_ENDPOINTS STM32_OTG1_ENDPOINTS
#define USB_MAX_ENDPOINTS GD32_OTG1_ENDPOINTS
#endif
#else
#define USB_MAX_ENDPOINTS STM32_OTG1_ENDPOINTS
#define USB_MAX_ENDPOINTS GD32_OTG1_ENDPOINTS
#endif
#if STM32_USB_USE_OTG1 && !STM32_HAS_OTG1
#if GD32_USB_USE_OTG1 && !GD32_HAS_OTG1
#error "OTG1 not present in the selected device"
#endif
#if STM32_USB_USE_OTG2 && !STM32_HAS_OTG2
#if GD32_USB_USE_OTG2 && !GD32_HAS_OTG2
#error "OTG2 not present in the selected device"
#endif
#if !STM32_USB_USE_OTG1 && !STM32_USB_USE_OTG2
#if !GD32_USB_USE_OTG1 && !GD32_USB_USE_OTG2
#error "USB driver activated but no USB peripheral assigned"
#endif
#if STM32_USB_USE_OTG1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_USB_OTG1_IRQ_PRIORITY)
#if GD32_USB_USE_OTG1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_USB_OTG1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to OTG1"
#endif
#if STM32_USB_USE_OTG2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_USB_OTG2_IRQ_PRIORITY)
#if GD32_USB_USE_OTG2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_USB_OTG2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to OTG2"
#endif
#if (STM32_USB_OTG1_RX_FIFO_SIZE & 3) != 0
#if (GD32_USB_OTG1_RX_FIFO_SIZE & 3) != 0
#error "OTG1 RX FIFO size must be a multiple of 4"
#endif
#if (STM32_USB_OTG2_RX_FIFO_SIZE & 3) != 0
#if (GD32_USB_OTG2_RX_FIFO_SIZE & 3) != 0
#error "OTG2 RX FIFO size must be a multiple of 4"
#endif
/*#if defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX)
#define STM32_USBCLK STM32_PLL48CLK*/
#define GD32_USBCLK GD32_PLL48CLK*/
#if defined(STM32F10X_CL) || defined (GD32VF103CB)
#define STM32_USBCLK STM32_OTGFSCLK
#define GD32_USBCLK GD32_OTGFSCLK
// #elif defined(STM32L4XX) || defined(STM32L4XXP)
// #define STM32_USBCLK STM32_48CLK
// #define GD32_USBCLK GD32_48CLK
// #elif defined(STM32H7XX)
// /* Defines directly STM32_USBCLK.*/
// /* Defines directly GD32_USBCLK.*/
// #define rccEnableOTG_FS rccEnableUSB2_OTG_HS
// #define rccDisableOTG_FS rccDisableUSB2_OTG_HS
// #define rccResetOTG_FS rccResetUSB2_OTG_HS
@ -243,12 +243,12 @@
#endif
/* Allowing for a small tolerance.*/
#if STM32_USBCLK < 47880000 || STM32_USBCLK > 48120000
#if GD32_USBCLK < 47880000 || GD32_USBCLK > 48120000
#error "the USB OTG driver requires a 48MHz clock"
#endif
#if (STM32_USB_HOST_WAKEUP_DURATION < 2) || (STM32_USB_HOST_WAKEUP_DURATION > 15)
#error "invalid STM32_USB_HOST_WAKEUP_DURATION setting, it must be between 2 and 15"
#if (GD32_USB_HOST_WAKEUP_DURATION < 2) || (GD32_USB_HOST_WAKEUP_DURATION > 15)
#error "invalid GD32_USB_HOST_WAKEUP_DURATION setting, it must be between 2 and 15"
#endif
/*===========================================================================*/
@ -534,7 +534,7 @@ struct USBDriver {
*
* @notapi
*/
#if (STM32_OTG_STEPPING == 1) || defined(__DOXYGEN__)
#if (GD32_OTG_STEPPING == 1) || defined(__DOXYGEN__)
#define usb_lld_connect_bus(usbp) ((usbp)->otg->GCCFG |= GCCFG_VBUSBSEN)
#else
#define usb_lld_connect_bus(usbp) ((usbp)->otg->DCTL &= ~DCTL_SDIS)
@ -545,7 +545,7 @@ struct USBDriver {
*
* @notapi
*/
#if (STM32_OTG_STEPPING == 1) || defined(__DOXYGEN__)
#if (GD32_OTG_STEPPING == 1) || defined(__DOXYGEN__)
#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->GCCFG &= ~GCCFG_VBUSBSEN)
#else
#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->DCTL |= DCTL_SDIS)
@ -559,7 +559,7 @@ struct USBDriver {
#define usb_lld_wakeup_host(usbp) \
do { \
(usbp)->otg->DCTL |= DCTL_RWUSIG; \
osalThreadSleepMilliseconds(STM32_USB_HOST_WAKEUP_DURATION); \
osalThreadSleepMilliseconds(GD32_USB_HOST_WAKEUP_DURATION); \
(usbp)->otg->DCTL &= ~DCTL_RWUSIG; \
} while (false)
@ -567,11 +567,11 @@ struct USBDriver {
/* External declarations. */
/*===========================================================================*/
#if STM32_USB_USE_OTG1 && !defined(__DOXYGEN__)
#if GD32_USB_USE_OTG1 && !defined(__DOXYGEN__)
extern USBDriver USBD1;
#endif
#if STM32_USB_USE_OTG2 && !defined(__DOXYGEN__)
#if GD32_USB_USE_OTG2 && !defined(__DOXYGEN__)
extern USBDriver USBD2;
#endif

10
os/hal/ports/GD/GD32VF103/OTG/stm32_otg.h
View File

@ -22,18 +22,18 @@
* @{
*/
#ifndef STM32_OTG_H
#define STM32_OTG_H
#ifndef GD32_OTG_H
#define GD32_OTG_H
/**
* @brief OTG_FS FIFO memory size in words.
*/
#define STM32_OTG1_FIFO_MEM_SIZE 320
#define GD32_OTG1_FIFO_MEM_SIZE 320
/**
* @brief OTG_HS FIFO memory size in words.
*/
#define STM32_OTG2_FIFO_MEM_SIZE 1024
#define GD32_OTG2_FIFO_MEM_SIZE 1024
/**
* @brief Host channel registers group.
@ -904,6 +904,6 @@ typedef struct {
*/
#define OTG_FS ((stm32_otg_t *)OTG_FS_ADDR)
#endif /* STM32_OTG_H */
#endif /* GD32_OTG_H */
/** @} */

8
os/hal/ports/GD/GD32VF103/RTC/hal_rtc_lld.c
View File

@ -200,8 +200,8 @@ void rtc_lld_set_prescaler(void) {
sts = osalSysGetStatusAndLockX();
rtc_acquire_access();
RTC->PRLH = (uint16_t)((STM32_RTCCLK - 1) >> 16) & 0x000F;
RTC->PRLL = (uint16_t)(((STM32_RTCCLK - 1)) & 0xFFFF);
RTC->PRLH = (uint16_t)((GD32_RTCCLK - 1) >> 16) & 0x000F;
RTC->PRLL = (uint16_t)(((GD32_RTCCLK - 1)) & 0xFFFF);
rtc_release_access();
/* Leaving a reentrant critical zone.*/
@ -236,7 +236,7 @@ void rtc_lld_init(void) {
RTCD1.callback = NULL;
/* IRQ vector permanently assigned to this driver.*/
eclicEnableVector(GD32_RTC1_NUMBER, STM32_RTC_IRQ_PRIORITY, STM32_RTC_IRQ_TRIGGER);
eclicEnableVector(GD32_RTC1_NUMBER, GD32_RTC_IRQ_PRIORITY, GD32_RTC_IRQ_TRIGGER);
}
/**
@ -413,7 +413,7 @@ void rtcSTM32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec) {
osalSysRestoreStatusX(sts);
if (NULL != tv_msec)
*tv_msec = (((uint32_t)STM32_RTCCLK - 1 - time_frac) * 1000) / STM32_RTCCLK;
*tv_msec = (((uint32_t)GD32_RTCCLK - 1 - time_frac) * 1000) / GD32_RTCCLK;
}
/**

6
os/hal/ports/GD/GD32VF103/RTC/hal_rtc_lld.h
View File

@ -65,18 +65,18 @@
/*
* RTC driver system settings.
*/
#define STM32_RTC_IRQ_PRIORITY 15
#define GD32_RTC_IRQ_PRIORITY 15
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if HAL_USE_RTC && !STM32_HAS_RTC
#if HAL_USE_RTC && !GD32_HAS_RTC
#error "RTC not present in the selected device"
#endif
#if STM32_RTCCLK == 0
#if GD32_RTCCLK == 0
#error "RTC clock not enabled"
#endif

332
os/hal/ports/GD/GD32VF103/SPI/hal_i2s_lld.c
View File

@ -31,105 +31,105 @@
/*===========================================================================*/
#define I2S1_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_RX_DMA_STREAM, \
STM32_SPI1_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_I2S_SPI1_RX_DMA_STREAM, \
GD32_SPI1_RX_DMA_CHN)
#define I2S1_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_TX_DMA_STREAM, \
STM32_SPI1_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_I2S_SPI1_TX_DMA_STREAM, \
GD32_SPI1_TX_DMA_CHN)
#define I2S2_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_RX_DMA_STREAM, \
STM32_SPI2_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_I2S_SPI2_RX_DMA_STREAM, \
GD32_SPI2_RX_DMA_CHN)
#define I2S2_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_TX_DMA_STREAM, \
STM32_SPI2_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_I2S_SPI2_TX_DMA_STREAM, \
GD32_SPI2_TX_DMA_CHN)
#define I2S3_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_RX_DMA_STREAM, \
STM32_SPI3_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_I2S_SPI3_RX_DMA_STREAM, \
GD32_SPI3_RX_DMA_CHN)
#define I2S3_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_TX_DMA_STREAM, \
STM32_SPI3_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_I2S_SPI3_TX_DMA_STREAM, \
GD32_SPI3_TX_DMA_CHN)
/*
* Static I2S settings for I2S1.
*/
#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE)
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
#define STM32_I2S1_CFGR_CFG 0
#if !GD32_I2S_IS_MASTER(GD32_I2S_SPI1_MODE)
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI1_MODE)
#define GD32_I2S1_CFGR_CFG 0
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI1_MODE)
#define GD32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
#endif
#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
#else /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI1_MODE) */
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI1_MODE)
#define GD32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
#define STM32_I2S1_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI1_MODE)
#define GD32_I2S1_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
SPI_I2SCFGR_I2SCFG_0)
#endif
#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */
#endif /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI1_MODE) */
/*
* Static I2S settings for I2S2.
*/
#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE)
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
#define STM32_I2S2_CFGR_CFG 0
#if !GD32_I2S_IS_MASTER(GD32_I2S_SPI2_MODE)
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE)
#define GD32_I2S2_CFGR_CFG 0
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE)
#define GD32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
#endif
#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
#define STM32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
#else /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI2_MODE) */
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE)
#define GD32_I2S2_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
#define STM32_I2S2_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE)
#define GD32_I2S2_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
SPI_I2SCFGR_I2SCFG_0)
#endif
#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI2_MODE) */
#endif /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI2_MODE) */
/*
* Static I2S settings for I2S3.
*/
#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE)
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
#define STM32_I2S3_CFGR_CFG 0
#if !GD32_I2S_IS_MASTER(GD32_I2S_SPI3_MODE)
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI3_MODE)
#define GD32_I2S3_CFGR_CFG 0
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI3_MODE)
#define GD32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_0
#endif
#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
#define STM32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
#else /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI3_MODE) */
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI3_MODE)
#define GD32_I2S3_CFGR_CFG SPI_I2SCFGR_I2SCFG_1
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
#define STM32_I2S3_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI3_MODE)
#define GD32_I2S3_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \
SPI_I2SCFGR_I2SCFG_0)
#endif
#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI3_MODE) */
#endif /* !GD32_I2S_IS_MASTER(GD32_I2S_SPI3_MODE) */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/** @brief I2S1 driver identifier.*/
#if STM32_I2S_USE_SPI1 || defined(__DOXYGEN__)
#if GD32_I2S_USE_SPI1 || defined(__DOXYGEN__)
I2SDriver I2SD1;
#endif
/** @brief I2S2 driver identifier.*/
#if STM32_I2S_USE_SPI2 || defined(__DOXYGEN__)
#if GD32_I2S_USE_SPI2 || defined(__DOXYGEN__)
I2SDriver I2SD2;
#endif
/** @brief I2S3 driver identifier.*/
#if STM32_I2S_USE_SPI3 || defined(__DOXYGEN__)
#if GD32_I2S_USE_SPI3 || defined(__DOXYGEN__)
I2SDriver I2SD3;
#endif
@ -141,9 +141,9 @@ I2SDriver I2SD3;
/* Driver local functions. */
/*===========================================================================*/
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) || \
STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) || \
STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI1_MODE) || \
GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE) || \
GD32_I2S_RX_ENABLED(GD32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
/**
* @brief Shared end-of-rx service routine.
*
@ -155,28 +155,28 @@ static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) {
(void)i2sp;
/* DMA errors handling.*/
#if defined(STM32_I2S_DMA_ERROR_HOOK)
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
STM32_I2S_DMA_ERROR_HOOK(i2sp);
#if defined(GD32_I2S_DMA_ERROR_HOOK)
if ((flags & (GD32_DMA_ISR_TEIF | GD32_DMA_ISR_DMEIF)) != 0) {
GD32_I2S_DMA_ERROR_HOOK(i2sp);
}
#endif
/* Callbacks handling, note it is portable code defined in the high
level driver.*/
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
if ((flags & GD32_DMA_ISR_TCIF) != 0) {
/* Transfer complete processing.*/
_i2s_isr_full_code(i2sp);
}
else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
else if ((flags & GD32_DMA_ISR_HTIF) != 0) {
/* Half transfer processing.*/
_i2s_isr_half_code(i2sp);
}
}
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) || \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) || \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI1_MODE) || \
GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE) || \
GD32_I2S_TX_ENABLED(GD32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
/**
* @brief Shared end-of-tx service routine.
*
@ -188,19 +188,19 @@ static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) {
(void)i2sp;
/* DMA errors handling.*/
#if defined(STM32_I2S_DMA_ERROR_HOOK)
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
STM32_I2S_DMA_ERROR_HOOK(i2sp);
#if defined(GD32_I2S_DMA_ERROR_HOOK)
if ((flags & (GD32_DMA_ISR_TEIF | GD32_DMA_ISR_DMEIF)) != 0) {
GD32_I2S_DMA_ERROR_HOOK(i2sp);
}
#endif
/* Callbacks handling, note it is portable code defined in the high
level driver.*/
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
if ((flags & GD32_DMA_ISR_TCIF) != 0) {
/* Transfer complete processing.*/
_i2s_isr_full_code(i2sp);
}
else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
else if ((flags & GD32_DMA_ISR_HTIF) != 0) {
/* Half transfer processing.*/
_i2s_isr_half_code(i2sp);
}
@ -222,115 +222,115 @@ static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) {
*/
void i2s_lld_init(void) {
#if STM32_I2S_USE_SPI1
#if GD32_I2S_USE_SPI1
i2sObjectInit(&I2SD1);
I2SD1.spi = SPI1;
I2SD1.cfg = STM32_I2S1_CFGR_CFG;
I2SD1.cfg = GD32_I2S1_CFGR_CFG;
I2SD1.dmarx = NULL;
I2SD1.dmatx = NULL;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
I2SD1.rxdmamode = STM32_DMA_CR_CHSEL(I2S1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI1_MODE)
I2SD1.rxdmamode = GD32_DMA_CR_CHSEL(I2S1_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_I2S_SPI1_DMA_PRIORITY) |
GD32_DMA_CR_PSIZE_HWORD |
GD32_DMA_CR_MSIZE_HWORD |
GD32_DMA_CR_DIR_P2M |
GD32_DMA_CR_MINC |
GD32_DMA_CR_CIRC |
GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
#else
I2SD1.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
I2SD1.txdmamode = STM32_DMA_CR_CHSEL(I2S1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI1_MODE)
I2SD1.txdmamode = GD32_DMA_CR_CHSEL(I2S1_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_I2S_SPI1_DMA_PRIORITY) |
GD32_DMA_CR_PSIZE_HWORD |
GD32_DMA_CR_MSIZE_HWORD |
GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_MINC |
GD32_DMA_CR_CIRC |
GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
#else
I2SD1.txdmamode = 0;
#endif
#endif
#if STM32_I2S_USE_SPI2
#if GD32_I2S_USE_SPI2
i2sObjectInit(&I2SD2);
I2SD2.spi = SPI2;
I2SD2.cfg = STM32_I2S2_CFGR_CFG;
I2SD2.cfg = GD32_I2S2_CFGR_CFG;
I2SD2.dmarx = NULL;
I2SD2.dmatx = NULL;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
I2SD2.rxdmamode = STM32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE)
I2SD2.rxdmamode = GD32_DMA_CR_CHSEL(I2S2_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_I2S_SPI2_DMA_PRIORITY) |
GD32_DMA_CR_PSIZE_HWORD |
GD32_DMA_CR_MSIZE_HWORD |
GD32_DMA_CR_DIR_P2M |
GD32_DMA_CR_MINC |
GD32_DMA_CR_CIRC |
GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
#else
I2SD2.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
I2SD2.txdmamode = STM32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE)
I2SD2.txdmamode = GD32_DMA_CR_CHSEL(I2S2_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_I2S_SPI2_DMA_PRIORITY) |
GD32_DMA_CR_PSIZE_HWORD |
GD32_DMA_CR_MSIZE_HWORD |
GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_MINC |
GD32_DMA_CR_CIRC |
GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
#else
I2SD2.txdmamode = 0;
#endif
#endif
#if STM32_I2S_USE_SPI3
#if GD32_I2S_USE_SPI3
i2sObjectInit(&I2SD3);
I2SD3.spi = SPI3;
I2SD3.cfg = STM32_I2S3_CFGR_CFG;
I2SD3.cfg = GD32_I2S3_CFGR_CFG;
I2SD3.dmarx = NULL;
I2SD3.dmatx = NULL;
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
I2SD3.rxdmamode = STM32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI3_MODE)
I2SD3.rxdmamode = GD32_DMA_CR_CHSEL(I2S3_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_I2S_SPI3_DMA_PRIORITY) |
GD32_DMA_CR_PSIZE_HWORD |
GD32_DMA_CR_MSIZE_HWORD |
GD32_DMA_CR_DIR_P2M |
GD32_DMA_CR_MINC |
GD32_DMA_CR_CIRC |
GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
#else
I2SD3.rxdmamode = 0;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
I2SD3.txdmamode = STM32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_I2S_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC |
STM32_DMA_CR_CIRC |
STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI3_MODE)
I2SD3.txdmamode = GD32_DMA_CR_CHSEL(I2S3_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_I2S_SPI3_DMA_PRIORITY) |
GD32_DMA_CR_PSIZE_HWORD |
GD32_DMA_CR_MSIZE_HWORD |
GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_MINC |
GD32_DMA_CR_CIRC |
GD32_DMA_CR_HTIE |
GD32_DMA_CR_TCIE |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
#else
I2SD3.txdmamode = 0;
#endif
@ -349,15 +349,15 @@ void i2s_lld_start(I2SDriver *i2sp) {
/* If in stopped state then enables the SPI and DMA clocks.*/
if (i2sp->state == I2S_STOP) {
#if STM32_I2S_USE_SPI1
#if GD32_I2S_USE_SPI1
if (&I2SD1 == i2sp) {
/* Enabling I2S unit clock.*/
rccEnableSPI1(true);
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE)
i2sp->dmarx = dmaStreamAllocI(STM32_I2S_SPI1_RX_DMA_STREAM,
STM32_I2S_SPI1_IRQ_PRIORITY,
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI1_MODE)
i2sp->dmarx = dmaStreamAllocI(GD32_I2S_SPI1_RX_DMA_STREAM,
GD32_I2S_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(i2sp->dmarx != NULL, "unable to allocate stream");
@ -367,9 +367,9 @@ void i2s_lld_start(I2SDriver *i2sp) {
i2sp->spi->CR1 = 0;
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
i2sp->dmatx = dmaStreamAllocI(STM32_I2S_SPI1_TX_DMA_STREAM,
STM32_I2S_SPI1_IRQ_PRIORITY,
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI1_MODE)
i2sp->dmatx = dmaStreamAllocI(GD32_I2S_SPI1_TX_DMA_STREAM,
GD32_I2S_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(i2sp->dmatx != NULL, "unable to allocate stream");
@ -382,15 +382,15 @@ void i2s_lld_start(I2SDriver *i2sp) {
}
#endif
#if STM32_I2S_USE_SPI2
#if GD32_I2S_USE_SPI2
if (&I2SD2 == i2sp) {
/* Enabling I2S unit clock.*/
rccEnableSPI2(true);
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE)
i2sp->dmarx = dmaStreamAllocI(STM32_I2S_SPI2_RX_DMA_STREAM,
STM32_I2S_SPI2_IRQ_PRIORITY,
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE)
i2sp->dmarx = dmaStreamAllocI(GD32_I2S_SPI2_RX_DMA_STREAM,
GD32_I2S_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(i2sp->dmarx != NULL, "unable to allocate stream");
@ -400,9 +400,9 @@ void i2s_lld_start(I2SDriver *i2sp) {
i2sp->spi->CR1 = 0;
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
i2sp->dmatx = dmaStreamAllocI(STM32_I2S_SPI2_TX_DMA_STREAM,
STM32_I2S_SPI2_IRQ_PRIORITY,
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE)
i2sp->dmatx = dmaStreamAllocI(GD32_I2S_SPI2_TX_DMA_STREAM,
GD32_I2S_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(i2sp->dmatx != NULL, "unable to allocate stream");
@ -415,15 +415,15 @@ void i2s_lld_start(I2SDriver *i2sp) {
}
#endif
#if STM32_I2S_USE_SPI3
#if GD32_I2S_USE_SPI3
if (&I2SD3 == i2sp) {
/* Enabling I2S unit clock.*/
rccEnableSPI3(true);
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE)
i2sp->dmarx = dmaStreamAllocI(STM32_I2S_SPI3_RX_DMA_STREAM,
STM32_I2S_SPI3_IRQ_PRIORITY,
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI3_MODE)
i2sp->dmarx = dmaStreamAllocI(GD32_I2S_SPI3_RX_DMA_STREAM,
GD32_I2S_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
(void *)i2sp);
osalDbgAssert(i2sp->dmarx != NULL, "unable to allocate stream");
@ -433,9 +433,9 @@ void i2s_lld_start(I2SDriver *i2sp) {
i2sp->spi->CR1 = 0;
i2sp->spi->CR2 = SPI_CR2_RXDMAEN;
#endif
#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
i2sp->dmatx = dmaStreamAllocI(STM32_I2S_SPI3_TX_DMA_STREAM,
STM32_I2S_SPI3_IRQ_PRIORITY,
#if GD32_I2S_TX_ENABLED(GD32_I2S_SPI3_MODE)
i2sp->dmatx = dmaStreamAllocI(GD32_I2S_SPI3_TX_DMA_STREAM,
GD32_I2S_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)i2s_lld_serve_tx_interrupt,
(void *)i2sp);
osalDbgAssert(i2sp->dmatx != NULL, "unable to allocate stream");
@ -477,17 +477,17 @@ void i2s_lld_stop(I2SDriver *i2sp) {
i2sp->dmatx = NULL;
}
#if STM32_I2S_USE_SPI1
#if GD32_I2S_USE_SPI1
if (&I2SD1 == i2sp)
rccDisableSPI1();
#endif
#if STM32_I2S_USE_SPI2
#if GD32_I2S_USE_SPI2
if (&I2SD2 == i2sp)
rccDisableSPI2();
#endif
#if STM32_I2S_USE_SPI3
#if GD32_I2S_USE_SPI3
if (&I2SD3 == i2sp)
rccDisableSPI3();
#endif

176
os/hal/ports/GD/GD32VF103/SPI/hal_i2s_lld.h
View File

@ -35,21 +35,21 @@
* @name Static I2S modes
* @{
*/
#define STM32_I2S_MODE_SLAVE 0
#define STM32_I2S_MODE_MASTER 1
#define STM32_I2S_MODE_RX 2
#define STM32_I2S_MODE_TX 4
#define STM32_I2S_MODE_RXTX (STM32_I2S_MODE_RX | \
STM32_I2S_MODE_TX)
#define GD32_I2S_MODE_SLAVE 0
#define GD32_I2S_MODE_MASTER 1
#define GD32_I2S_MODE_RX 2
#define GD32_I2S_MODE_TX 4
#define GD32_I2S_MODE_RXTX (GD32_I2S_MODE_RX | \
GD32_I2S_MODE_TX)
/** @} */
/**
* @name Mode checks
* @{
*/
#define STM32_I2S_IS_MASTER(mode) ((mode) & STM32_I2S_MODE_MASTER)
#define STM32_I2S_RX_ENABLED(mode) ((mode) & STM32_I2S_MODE_RX)
#define STM32_I2S_TX_ENABLED(mode) ((mode) & STM32_I2S_MODE_TX)
#define GD32_I2S_IS_MASTER(mode) ((mode) & GD32_I2S_MODE_MASTER)
#define GD32_I2S_RX_ENABLED(mode) ((mode) & GD32_I2S_MODE_RX)
#define GD32_I2S_TX_ENABLED(mode) ((mode) & GD32_I2S_MODE_TX)
/** @} */
/*===========================================================================*/
@ -65,8 +65,8 @@
* @details If set to @p TRUE the support for I2S1 is included.
* @note The default is @p TRUE.
*/
#if !defined(STM32_I2S_USE_SPI1) || defined(__DOXYGEN__)
#define STM32_I2S_USE_SPI1 FALSE
#if !defined(GD32_I2S_USE_SPI1) || defined(__DOXYGEN__)
#define GD32_I2S_USE_SPI1 FALSE
#endif
/**
@ -74,8 +74,8 @@
* @details If set to @p TRUE the support for I2S2 is included.
* @note The default is @p TRUE.
*/
#if !defined(STM32_I2S_USE_SPI2) || defined(__DOXYGEN__)
#define STM32_I2S_USE_SPI2 FALSE
#if !defined(GD32_I2S_USE_SPI2) || defined(__DOXYGEN__)
#define GD32_I2S_USE_SPI2 FALSE
#endif
/**
@ -83,81 +83,81 @@
* @details If set to @p TRUE the support for I2S3 is included.
* @note The default is @p TRUE.
*/
#if !defined(STM32_I2S_USE_SPI3) || defined(__DOXYGEN__)
#define STM32_I2S_USE_SPI3 FALSE
#if !defined(GD32_I2S_USE_SPI3) || defined(__DOXYGEN__)
#define GD32_I2S_USE_SPI3 FALSE
#endif
/**
* @brief I2S1 mode.
*/
#if !defined(STM32_I2S_SPI1_MODE) || defined(__DOXYGEN__)
#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
STM32_I2S_MODE_RX)
#if !defined(GD32_I2S_SPI1_MODE) || defined(__DOXYGEN__)
#define GD32_I2S_SPI1_MODE (GD32_I2S_MODE_MASTER | \
GD32_I2S_MODE_RX)
#endif
/**
* @brief I2S2 mode.
*/
#if !defined(STM32_I2S_SPI2_MODE) || defined(__DOXYGEN__)
#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
STM32_I2S_MODE_RX)
#if !defined(GD32_I2S_SPI2_MODE) || defined(__DOXYGEN__)
#define GD32_I2S_SPI2_MODE (GD32_I2S_MODE_MASTER | \
GD32_I2S_MODE_RX)
#endif
/**
* @brief I2S3 mode.
*/
#if !defined(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
#define STM32_I2S_SPI3_MODE (STM32_I2S_MODE_MASTER | \
STM32_I2S_MODE_RX)
#if !defined(GD32_I2S_SPI3_MODE) || defined(__DOXYGEN__)
#define GD32_I2S_SPI3_MODE (GD32_I2S_MODE_MASTER | \
GD32_I2S_MODE_RX)
#endif
/**
* @brief I2S1 interrupt priority level setting.
*/
#if !defined(STM32_I2S_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI1_IRQ_PRIORITY 10
#if !defined(GD32_I2S_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2S_SPI1_IRQ_PRIORITY 10
#endif
/**
* @brief I2S2 interrupt priority level setting.
*/
#if !defined(STM32_I2S_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI2_IRQ_PRIORITY 10
#if !defined(GD32_I2S_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2S_SPI2_IRQ_PRIORITY 10
#endif
/**
* @brief I2S3 interrupt priority level setting.
*/
#if !defined(STM32_I2S_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI3_IRQ_PRIORITY 10
#if !defined(GD32_I2S_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2S_SPI3_IRQ_PRIORITY 10
#endif
/**
* @brief I2S1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_I2S_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI1_DMA_PRIORITY 1
#if !defined(GD32_I2S_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2S_SPI1_DMA_PRIORITY 1
#endif
/**
* @brief I2S2 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_I2S_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#if !defined(GD32_I2S_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2S_SPI2_DMA_PRIORITY 1
#endif
/**
* @brief I2S3 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_I2S_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2S_SPI3_DMA_PRIORITY 1
#if !defined(GD32_I2S_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_I2S_SPI3_DMA_PRIORITY 1
#endif
/**
* @brief I2S DMA error hook.
*/
#if !defined(STM32_I2S_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
#if !defined(GD32_I2S_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define GD32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
#endif
/** @} */
@ -165,132 +165,132 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if STM32_I2S_USE_SPI1 && !STM32_SPI1_SUPPORTS_I2S
#if GD32_I2S_USE_SPI1 && !GD32_SPI1_SUPPORTS_I2S
#error "SPI1 does not support I2S mode"
#endif
#if STM32_I2S_USE_SPI2 && !STM32_SPI2_SUPPORTS_I2S
#if GD32_I2S_USE_SPI2 && !GD32_SPI2_SUPPORTS_I2S
#error "SPI2 does not support I2S mode"
#endif
#if STM32_I2S_USE_SPI3 && !STM32_SPI3_SUPPORTS_I2S
#if GD32_I2S_USE_SPI3 && !GD32_SPI3_SUPPORTS_I2S
#error "SPI3 does not support I2S mode"
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) && \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE)
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI1_MODE) && \
GD32_I2S_TX_ENABLED(GD32_I2S_SPI1_MODE)
#error "I2S1 RX and TX mode not supported in this driver implementation"
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) && \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE)
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI2_MODE) && \
GD32_I2S_TX_ENABLED(GD32_I2S_SPI2_MODE)
#error "I2S2 RX and TX mode not supported in this driver implementation"
#endif
#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) && \
STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE)
#if GD32_I2S_RX_ENABLED(GD32_I2S_SPI3_MODE) && \
GD32_I2S_TX_ENABLED(GD32_I2S_SPI3_MODE)
#error "I2S3 RX and TX mode not supported in this driver implementation"
#endif
#if STM32_I2S_USE_SPI1 && !STM32_HAS_SPI1
#if GD32_I2S_USE_SPI1 && !GD32_HAS_SPI1
#error "SPI1 not present in the selected device"
#endif
#if STM32_I2S_USE_SPI2 && !STM32_HAS_SPI2
#if GD32_I2S_USE_SPI2 && !GD32_HAS_SPI2
#error "SPI2 not present in the selected device"
#endif
#if STM32_I2S_USE_SPI3 && !STM32_HAS_SPI3
#if GD32_I2S_USE_SPI3 && !GD32_HAS_SPI3
#error "SPI3 not present in the selected device"
#endif
#if !STM32_I2S_USE_SPI1 && !STM32_I2S_USE_SPI2 && !STM32_I2S_USE_SPI3
#if !GD32_I2S_USE_SPI1 && !GD32_I2S_USE_SPI2 && !GD32_I2S_USE_SPI3
#error "I2S driver activated but no SPI peripheral assigned"
#endif
#if STM32_I2S_USE_SPI1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI1_IRQ_PRIORITY)
#if GD32_I2S_USE_SPI1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_I2S_SPI1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI1"
#endif
#if STM32_I2S_USE_SPI2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI2_IRQ_PRIORITY)
#if GD32_I2S_USE_SPI2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_I2S_SPI2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI2"
#endif
#if STM32_I2S_USE_SPI3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI3_IRQ_PRIORITY)
#if GD32_I2S_USE_SPI3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_I2S_SPI3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI3"
#endif
#if STM32_I2S_USE_SPI1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI1_DMA_PRIORITY)
#if GD32_I2S_USE_SPI1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_I2S_SPI1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI1"
#endif
#if STM32_I2S_USE_SPI2 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI2_DMA_PRIORITY)
#if GD32_I2S_USE_SPI2 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_I2S_SPI2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI2"
#endif
#if STM32_I2S_USE_SPI3 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI3_DMA_PRIORITY)
#if GD32_I2S_USE_SPI3 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_I2S_SPI3_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI3"
#endif
/* The following checks are only required when there is a DMA able to
reassign streams to different channels.*/
#if STM32_ADVANCED_DMA
#if GD32_ADVANCED_DMA
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_I2S_USE_SPI1 && (!defined(STM32_I2S_SPI1_RX_DMA_STREAM) || \
!defined(STM32_I2S_SPI1_TX_DMA_STREAM))
#if GD32_I2S_USE_SPI1 && (!defined(GD32_I2S_SPI1_RX_DMA_STREAM) || \
!defined(GD32_I2S_SPI1_TX_DMA_STREAM))
#error "SPI1 DMA streams not defined"
#endif
#if STM32_I2S_USE_SPI2 && (!defined(STM32_I2S_SPI2_RX_DMA_STREAM) || \
!defined(STM32_I2S_SPI2_TX_DMA_STREAM))
#if GD32_I2S_USE_SPI2 && (!defined(GD32_I2S_SPI2_RX_DMA_STREAM) || \
!defined(GD32_I2S_SPI2_TX_DMA_STREAM))
#error "SPI2 DMA streams not defined"
#endif
#if STM32_I2S_USE_SPI3 && (!defined(STM32_I2S_SPI3_RX_DMA_STREAM) || \
!defined(STM32_I2S_SPI3_TX_DMA_STREAM))
#if GD32_I2S_USE_SPI3 && (!defined(GD32_I2S_SPI3_RX_DMA_STREAM) || \
!defined(GD32_I2S_SPI3_TX_DMA_STREAM))
#error "SPI3 DMA streams not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_I2S_USE_SPI1 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
#if GD32_I2S_USE_SPI1 && \
!GD32_DMA_IS_VALID_ID(GD32_I2S_SPI1_RX_DMA_STREAM, GD32_SPI1_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI1 RX"
#endif
#if STM32_I2S_USE_SPI1 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
#if GD32_I2S_USE_SPI1 && \
!GD32_DMA_IS_VALID_ID(GD32_I2S_SPI1_TX_DMA_STREAM, GD32_SPI1_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI1 TX"
#endif
#if STM32_I2S_USE_SPI2 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
#if GD32_I2S_USE_SPI2 && \
!GD32_DMA_IS_VALID_ID(GD32_I2S_SPI2_RX_DMA_STREAM, GD32_SPI2_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI2 RX"
#endif
#if STM32_I2S_USE_SPI2 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
#if GD32_I2S_USE_SPI2 && \
!GD32_DMA_IS_VALID_ID(GD32_I2S_SPI2_TX_DMA_STREAM, GD32_SPI2_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI2 TX"
#endif
#if STM32_I2S_USE_SPI3 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
#if GD32_I2S_USE_SPI3 && \
!GD32_DMA_IS_VALID_ID(GD32_I2S_SPI3_RX_DMA_STREAM, GD32_SPI3_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI3 RX"
#endif
#if STM32_I2S_USE_SPI3 && \
!STM32_DMA_IS_VALID_ID(STM32_I2S_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
#if GD32_I2S_USE_SPI3 && \
!GD32_DMA_IS_VALID_ID(GD32_I2S_SPI3_TX_DMA_STREAM, GD32_SPI3_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI3 TX"
#endif
#endif /* STM32_ADVANCED_DMA */
#endif /* GD32_ADVANCED_DMA */
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#if !defined(GD32_DMA_REQUIRED)
#define GD32_DMA_REQUIRED
#endif
/*===========================================================================*/
@ -340,15 +340,15 @@
/* External declarations. */
/*===========================================================================*/
#if STM32_I2S_USE_SPI1 && !defined(__DOXYGEN__)
#if GD32_I2S_USE_SPI1 && !defined(__DOXYGEN__)
extern I2SDriver I2SD1;
#endif
#if STM32_I2S_USE_SPI2 && !defined(__DOXYGEN__)
#if GD32_I2S_USE_SPI2 && !defined(__DOXYGEN__)
extern I2SDriver I2SD2;
#endif
#if STM32_I2S_USE_SPI3 && !defined(__DOXYGEN__)
#if GD32_I2S_USE_SPI3 && !defined(__DOXYGEN__)
extern I2SDriver I2SD3;
#endif

324
os/hal/ports/GD/GD32VF103/SPI/hal_spi_lld.c
View File

@ -31,84 +31,84 @@
/*===========================================================================*/
#define SPI1_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM, \
STM32_SPI1_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_SPI_SPI1_RX_DMA_STREAM, \
GD32_SPI1_RX_DMA_CHN)
#define SPI1_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM, \
STM32_SPI1_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_SPI_SPI1_TX_DMA_STREAM, \
GD32_SPI1_TX_DMA_CHN)
#define SPI2_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM, \
STM32_SPI2_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_SPI_SPI2_RX_DMA_STREAM, \
GD32_SPI2_RX_DMA_CHN)
#define SPI2_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM, \
STM32_SPI2_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_SPI_SPI2_TX_DMA_STREAM, \
GD32_SPI2_TX_DMA_CHN)
#define SPI3_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM, \
STM32_SPI3_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_SPI_SPI3_RX_DMA_STREAM, \
GD32_SPI3_RX_DMA_CHN)
#define SPI3_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \
STM32_SPI3_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_SPI_SPI3_TX_DMA_STREAM, \
GD32_SPI3_TX_DMA_CHN)
#define SPI4_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_RX_DMA_STREAM, \
STM32_SPI4_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_SPI_SPI4_RX_DMA_STREAM, \
GD32_SPI4_RX_DMA_CHN)
#define SPI4_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_TX_DMA_STREAM, \
STM32_SPI4_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_SPI_SPI4_TX_DMA_STREAM, \
GD32_SPI4_TX_DMA_CHN)
#define SPI5_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_RX_DMA_STREAM, \
STM32_SPI5_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_SPI_SPI5_RX_DMA_STREAM, \
GD32_SPI5_RX_DMA_CHN)
#define SPI5_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_TX_DMA_STREAM, \
STM32_SPI5_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_SPI_SPI5_TX_DMA_STREAM, \
GD32_SPI5_TX_DMA_CHN)
#define SPI6_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_RX_DMA_STREAM, \
STM32_SPI6_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_SPI_SPI6_RX_DMA_STREAM, \
GD32_SPI6_RX_DMA_CHN)
#define SPI6_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_TX_DMA_STREAM, \
STM32_SPI6_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_SPI_SPI6_TX_DMA_STREAM, \
GD32_SPI6_TX_DMA_CHN)
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/** @brief SPI1 driver identifier.*/
#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI1 || defined(__DOXYGEN__)
SPIDriver SPID1;
#endif
/** @brief SPI2 driver identifier.*/
#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI2 || defined(__DOXYGEN__)
SPIDriver SPID2;
#endif
/** @brief SPI3 driver identifier.*/
#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI3 || defined(__DOXYGEN__)
SPIDriver SPID3;
#endif
/** @brief SPI4 driver identifier.*/
#if STM32_SPI_USE_SPI4 || defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI4 || defined(__DOXYGEN__)
SPIDriver SPID4;
#endif
/** @brief SPI5 driver identifier.*/
#if STM32_SPI_USE_SPI5 || defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI5 || defined(__DOXYGEN__)
SPIDriver SPID5;
#endif
/** @brief SPI6 driver identifier.*/
#if STM32_SPI_USE_SPI6 || defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI6 || defined(__DOXYGEN__)
SPIDriver SPID6;
#endif
@ -132,20 +132,20 @@ static uint16_t dummyrx;
static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
/* DMA errors handling.*/
#if defined(STM32_SPI_DMA_ERROR_HOOK)
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
STM32_SPI_DMA_ERROR_HOOK(spip);
#if defined(GD32_SPI_DMA_ERROR_HOOK)
if ((flags & (GD32_DMA_ISR_TEIF | GD32_DMA_ISR_DMEIF)) != 0) {
GD32_SPI_DMA_ERROR_HOOK(spip);
}
#else
(void)flags;
#endif
if (spip->config->circular) {
if ((flags & STM32_DMA_ISR_HTIF) != 0U) {
if ((flags & GD32_DMA_ISR_HTIF) != 0U) {
/* Half buffer interrupt.*/
_spi_isr_half_code(spip);
}
if ((flags & STM32_DMA_ISR_TCIF) != 0U) {
if ((flags & GD32_DMA_ISR_TCIF) != 0U) {
/* End buffer interrupt.*/
_spi_isr_full_code(spip);
}
@ -170,10 +170,10 @@ static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
/* DMA errors handling.*/
#if defined(STM32_SPI_DMA_ERROR_HOOK)
#if defined(GD32_SPI_DMA_ERROR_HOOK)
(void)spip;
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
STM32_SPI_DMA_ERROR_HOOK(spip);
if ((flags & (GD32_DMA_ISR_TEIF | GD32_DMA_ISR_DMEIF)) != 0) {
GD32_SPI_DMA_ERROR_HOOK(spip);
}
#else
(void)spip;
@ -196,112 +196,112 @@ static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
*/
void spi_lld_init(void) {
#if STM32_SPI_USE_SPI1
#if GD32_SPI_USE_SPI1
spiObjectInit(&SPID1);
SPID1.spi = SPI1;
SPID1.dmarx = NULL;
SPID1.dmatx = NULL;
SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID1.rxdmamode = GD32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_SPI_SPI1_DMA_PRIORITY) |
GD32_DMA_CR_DIR_P2M |
GD32_DMA_CR_TCIE |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
SPID1.txdmamode = GD32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_SPI_SPI1_DMA_PRIORITY) |
GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI2
#if GD32_SPI_USE_SPI2
spiObjectInit(&SPID2);
SPID2.spi = SPI2;
SPID2.dmarx = NULL;
SPID2.dmatx = NULL;
SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID2.rxdmamode = GD32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_SPI_SPI2_DMA_PRIORITY) |
GD32_DMA_CR_DIR_P2M |
GD32_DMA_CR_TCIE |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
SPID2.txdmamode = GD32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_SPI_SPI2_DMA_PRIORITY) |
GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI3
#if GD32_SPI_USE_SPI3
spiObjectInit(&SPID3);
SPID3.spi = SPI3;
SPID3.dmarx = NULL;
SPID3.dmatx = NULL;
SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID3.rxdmamode = GD32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_SPI_SPI3_DMA_PRIORITY) |
GD32_DMA_CR_DIR_P2M |
GD32_DMA_CR_TCIE |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
SPID3.txdmamode = GD32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_SPI_SPI3_DMA_PRIORITY) |
GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI4
#if GD32_SPI_USE_SPI4
spiObjectInit(&SPID4);
SPID4.spi = SPI4;
SPID4.dmarx = NULL;
SPID4.dmatx = NULL;
SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID4.rxdmamode = GD32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_SPI_SPI4_DMA_PRIORITY) |
GD32_DMA_CR_DIR_P2M |
GD32_DMA_CR_TCIE |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
SPID4.txdmamode = GD32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_SPI_SPI4_DMA_PRIORITY) |
GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI5
#if GD32_SPI_USE_SPI5
spiObjectInit(&SPID5);
SPID5.spi = SPI5;
SPID5.dmarx = NULL;
SPID5.dmatx = NULL;
SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID5.rxdmamode = GD32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_SPI_SPI5_DMA_PRIORITY) |
GD32_DMA_CR_DIR_P2M |
GD32_DMA_CR_TCIE |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
SPID5.txdmamode = GD32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_SPI_SPI5_DMA_PRIORITY) |
GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI6
#if GD32_SPI_USE_SPI6
spiObjectInit(&SPID6);
SPID6.spi = SPI6;
SPID6.dmarx = NULL;
SPID6.dmatx = NULL;
SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID6.rxdmamode = GD32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_SPI_SPI6_DMA_PRIORITY) |
GD32_DMA_CR_DIR_P2M |
GD32_DMA_CR_TCIE |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
SPID6.txdmamode = GD32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_SPI_SPI6_DMA_PRIORITY) |
GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_DMEIE |
GD32_DMA_CR_TEIE;
#endif
}
@ -316,90 +316,90 @@ void spi_lld_start(SPIDriver *spip) {
/* If in stopped state then enables the SPI and DMA clocks.*/
if (spip->state == SPI_STOP) {
#if STM32_SPI_USE_SPI1
#if GD32_SPI_USE_SPI1
if (&SPID1 == spip) {
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI1_RX_DMA_STREAM,
STM32_SPI_SPI1_IRQ_PRIORITY,
spip->dmarx = dmaStreamAllocI(GD32_SPI_SPI1_RX_DMA_STREAM,
GD32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI1_TX_DMA_STREAM,
STM32_SPI_SPI1_IRQ_PRIORITY,
spip->dmatx = dmaStreamAllocI(GD32_SPI_SPI1_TX_DMA_STREAM,
GD32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI1(true);
}
#endif
#if STM32_SPI_USE_SPI2
#if GD32_SPI_USE_SPI2
if (&SPID2 == spip) {
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI2_RX_DMA_STREAM,
STM32_SPI_SPI2_IRQ_PRIORITY,
spip->dmarx = dmaStreamAllocI(GD32_SPI_SPI2_RX_DMA_STREAM,
GD32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI2_TX_DMA_STREAM,
STM32_SPI_SPI2_IRQ_PRIORITY,
spip->dmatx = dmaStreamAllocI(GD32_SPI_SPI2_TX_DMA_STREAM,
GD32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI2(true);
}
#endif
#if STM32_SPI_USE_SPI3
#if GD32_SPI_USE_SPI3
if (&SPID3 == spip) {
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI3_RX_DMA_STREAM,
STM32_SPI_SPI3_IRQ_PRIORITY,
spip->dmarx = dmaStreamAllocI(GD32_SPI_SPI3_RX_DMA_STREAM,
GD32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI3_TX_DMA_STREAM,
STM32_SPI_SPI3_IRQ_PRIORITY,
spip->dmatx = dmaStreamAllocI(GD32_SPI_SPI3_TX_DMA_STREAM,
GD32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI3(true);
}
#endif
#if STM32_SPI_USE_SPI4
#if GD32_SPI_USE_SPI4
if (&SPID4 == spip) {
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI4_RX_DMA_STREAM,
STM32_SPI_SPI4_IRQ_PRIORITY,
spip->dmarx = dmaStreamAllocI(GD32_SPI_SPI4_RX_DMA_STREAM,
GD32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI4_TX_DMA_STREAM,
STM32_SPI_SPI4_IRQ_PRIORITY,
spip->dmatx = dmaStreamAllocI(GD32_SPI_SPI4_TX_DMA_STREAM,
GD32_SPI_SPI4_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI4(true);
}
#endif
#if STM32_SPI_USE_SPI5
#if GD32_SPI_USE_SPI5
if (&SPID5 == spip) {
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI5_RX_DMA_STREAM,
STM32_SPI_SPI5_IRQ_PRIORITY,
spip->dmarx = dmaStreamAllocI(GD32_SPI_SPI5_RX_DMA_STREAM,
GD32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI5_TX_DMA_STREAM,
STM32_SPI_SPI5_IRQ_PRIORITY,
spip->dmatx = dmaStreamAllocI(GD32_SPI_SPI5_TX_DMA_STREAM,
GD32_SPI_SPI5_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
rccEnableSPI5(true);
}
#endif
#if STM32_SPI_USE_SPI6
#if GD32_SPI_USE_SPI6
if (&SPID6 == spip) {
spip->dmarx = dmaStreamAllocI(STM32_SPI_SPI6_RX_DMA_STREAM,
STM32_SPI_SPI6_IRQ_PRIORITY,
spip->dmarx = dmaStreamAllocI(GD32_SPI_SPI6_RX_DMA_STREAM,
GD32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmarx != NULL, "unable to allocate stream");
spip->dmatx = dmaStreamAllocI(STM32_SPI_SPI6_TX_DMA_STREAM,
STM32_SPI_SPI6_IRQ_PRIORITY,
spip->dmatx = dmaStreamAllocI(GD32_SPI_SPI6_TX_DMA_STREAM,
GD32_SPI_SPI6_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
osalDbgAssert(spip->dmatx != NULL, "unable to allocate stream");
@ -415,26 +415,26 @@ void spi_lld_start(SPIDriver *spip) {
/* Configuration-specific DMA setup.*/
if ((spip->config->cr1 & SPI_CR1_DFF) == 0) {
/* Frame width is 8 bits or smaller.*/
spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
spip->rxdmamode = (spip->rxdmamode & ~GD32_DMA_CR_SIZE_MASK) |
GD32_DMA_CR_PSIZE_BYTE | GD32_DMA_CR_MSIZE_BYTE;
spip->txdmamode = (spip->txdmamode & ~GD32_DMA_CR_SIZE_MASK) |
GD32_DMA_CR_PSIZE_BYTE | GD32_DMA_CR_MSIZE_BYTE;
}
else {
/* Frame width is larger than 8 bits.*/
spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
spip->rxdmamode = (spip->rxdmamode & ~GD32_DMA_CR_SIZE_MASK) |
GD32_DMA_CR_PSIZE_HWORD | GD32_DMA_CR_MSIZE_HWORD;
spip->txdmamode = (spip->txdmamode & ~GD32_DMA_CR_SIZE_MASK) |
GD32_DMA_CR_PSIZE_HWORD | GD32_DMA_CR_MSIZE_HWORD;
}
if (spip->config->circular) {
spip->rxdmamode |= (STM32_DMA_CR_CIRC | STM32_DMA_CR_HTIE);
spip->txdmamode |= (STM32_DMA_CR_CIRC | STM32_DMA_CR_HTIE);
spip->rxdmamode |= (GD32_DMA_CR_CIRC | GD32_DMA_CR_HTIE);
spip->txdmamode |= (GD32_DMA_CR_CIRC | GD32_DMA_CR_HTIE);
}
else {
spip->rxdmamode &= ~(STM32_DMA_CR_CIRC | STM32_DMA_CR_HTIE);
spip->txdmamode &= ~(STM32_DMA_CR_CIRC | STM32_DMA_CR_HTIE);
spip->rxdmamode &= ~(GD32_DMA_CR_CIRC | GD32_DMA_CR_HTIE);
spip->txdmamode &= ~(GD32_DMA_CR_CIRC | GD32_DMA_CR_HTIE);
}
/* SPI setup and enable.*/
@ -467,27 +467,27 @@ void spi_lld_stop(SPIDriver *spip) {
spip->dmarx = NULL;
spip->dmatx = NULL;
#if STM32_SPI_USE_SPI1
#if GD32_SPI_USE_SPI1
if (&SPID1 == spip)
rccDisableSPI1();
#endif
#if STM32_SPI_USE_SPI2
#if GD32_SPI_USE_SPI2
if (&SPID2 == spip)
rccDisableSPI2();
#endif
#if STM32_SPI_USE_SPI3
#if GD32_SPI_USE_SPI3
if (&SPID3 == spip)
rccDisableSPI3();
#endif
#if STM32_SPI_USE_SPI4
#if GD32_SPI_USE_SPI4
if (&SPID4 == spip)
rccDisableSPI4();
#endif
#if STM32_SPI_USE_SPI5
#if GD32_SPI_USE_SPI5
if (&SPID5 == spip)
rccDisableSPI5();
#endif
#if STM32_SPI_USE_SPI6
#if GD32_SPI_USE_SPI6
if (&SPID6 == spip)
rccDisableSPI6();
#endif
@ -570,11 +570,11 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode| GD32_DMA_CR_MINC);
dmaStreamSetMemory0(spip->dmatx, txbuf);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | GD32_DMA_CR_MINC);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
@ -603,7 +603,7 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
dmaStreamSetMemory0(spip->dmatx, txbuf);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | GD32_DMA_CR_MINC);
dmaStreamEnable(spip->dmarx);
dmaStreamEnable(spip->dmatx);
@ -628,7 +628,7 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | GD32_DMA_CR_MINC);
dmaStreamSetMemory0(spip->dmatx, &dummytx);
dmaStreamSetTransactionSize(spip->dmatx, n);

232
os/hal/ports/GD/GD32VF103/SPI/hal_spi_lld.h
View File

@ -49,8 +49,8 @@
* @details If set to @p TRUE the support for SPI1 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__)
#define STM32_SPI_USE_SPI1 FALSE
#if !defined(GD32_SPI_USE_SPI1) || defined(__DOXYGEN__)
#define GD32_SPI_USE_SPI1 FALSE
#endif
/**
@ -58,8 +58,8 @@
* @details If set to @p TRUE the support for SPI2 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__)
#define STM32_SPI_USE_SPI2 FALSE
#if !defined(GD32_SPI_USE_SPI2) || defined(__DOXYGEN__)
#define GD32_SPI_USE_SPI2 FALSE
#endif
/**
@ -67,8 +67,8 @@
* @details If set to @p TRUE the support for SPI3 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__)
#define STM32_SPI_USE_SPI3 FALSE
#if !defined(GD32_SPI_USE_SPI3) || defined(__DOXYGEN__)
#define GD32_SPI_USE_SPI3 FALSE
#endif
/**
@ -76,8 +76,8 @@
* @details If set to @p TRUE the support for SPI4 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SPI_USE_SPI4) || defined(__DOXYGEN__)
#define STM32_SPI_USE_SPI4 FALSE
#if !defined(GD32_SPI_USE_SPI4) || defined(__DOXYGEN__)
#define GD32_SPI_USE_SPI4 FALSE
#endif
/**
@ -85,8 +85,8 @@
* @details If set to @p TRUE the support for SPI5 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SPI_USE_SPI5) || defined(__DOXYGEN__)
#define STM32_SPI_USE_SPI5 FALSE
#if !defined(GD32_SPI_USE_SPI5) || defined(__DOXYGEN__)
#define GD32_SPI_USE_SPI5 FALSE
#endif
/**
@ -94,50 +94,50 @@
* @details If set to @p TRUE the support for SPI6 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SPI_USE_SPI6) || defined(__DOXYGEN__)
#define STM32_SPI_USE_SPI6 FALSE
#if !defined(GD32_SPI_USE_SPI6) || defined(__DOXYGEN__)
#define GD32_SPI_USE_SPI6 FALSE
#endif
/**
* @brief SPI1 interrupt priority level setting.
*/
#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#if !defined(GD32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI1_IRQ_PRIORITY 10
#endif
/**
* @brief SPI2 interrupt priority level setting.
*/
#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#if !defined(GD32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI2_IRQ_PRIORITY 10
#endif
/**
* @brief SPI3 interrupt priority level setting.
*/
#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#if !defined(GD32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI3_IRQ_PRIORITY 10
#endif
/**
* @brief SPI4 interrupt priority level setting.
*/
#if !defined(STM32_SPI_SPI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
#if !defined(GD32_SPI_SPI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI4_IRQ_PRIORITY 10
#endif
/**
* @brief SPI5 interrupt priority level setting.
*/
#if !defined(STM32_SPI_SPI5_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
#if !defined(GD32_SPI_SPI5_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI5_IRQ_PRIORITY 10
#endif
/**
* @brief SPI6 interrupt priority level setting.
*/
#if !defined(STM32_SPI_SPI6_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#if !defined(GD32_SPI_SPI6_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI6_IRQ_PRIORITY 10
#endif
/**
@ -146,8 +146,8 @@
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#if !defined(GD32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI1_DMA_PRIORITY 1
#endif
/**
@ -156,8 +156,8 @@
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#if !defined(GD32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI2_DMA_PRIORITY 1
#endif
/**
@ -166,8 +166,8 @@
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#if !defined(GD32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI3_DMA_PRIORITY 1
#endif
/**
@ -176,8 +176,8 @@
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(STM32_SPI_SPI4_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#if !defined(GD32_SPI_SPI4_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI4_DMA_PRIORITY 1
#endif
/**
@ -186,8 +186,8 @@
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(STM32_SPI_SPI5_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI5_DMA_PRIORITY 1
#if !defined(GD32_SPI_SPI5_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI5_DMA_PRIORITY 1
#endif
/**
@ -196,15 +196,15 @@
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(STM32_SPI_SPI6_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI6_DMA_PRIORITY 1
#if !defined(GD32_SPI_SPI6_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SPI_SPI6_DMA_PRIORITY 1
#endif
/**
* @brief SPI DMA error hook.
*/
#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
#if !defined(GD32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define GD32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
#endif
/** @} */
@ -212,193 +212,193 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1
#if GD32_SPI_USE_SPI1 && !GD32_HAS_SPI1
#error "SPI1 not present in the selected device"
#endif
#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2
#if GD32_SPI_USE_SPI2 && !GD32_HAS_SPI2
#error "SPI2 not present in the selected device"
#endif
#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3
#if GD32_SPI_USE_SPI3 && !GD32_HAS_SPI3
#error "SPI3 not present in the selected device"
#endif
#if STM32_SPI_USE_SPI4 && !STM32_HAS_SPI4
#if GD32_SPI_USE_SPI4 && !GD32_HAS_SPI4
#error "SPI4 not present in the selected device"
#endif
#if STM32_SPI_USE_SPI5 && !STM32_HAS_SPI5
#if GD32_SPI_USE_SPI5 && !GD32_HAS_SPI5
#error "SPI5 not present in the selected device"
#endif
#if STM32_SPI_USE_SPI6 && !STM32_HAS_SPI6
#if GD32_SPI_USE_SPI6 && !GD32_HAS_SPI6
#error "SPI6 not present in the selected device"
#endif
#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 && \
!STM32_SPI_USE_SPI4 && !STM32_SPI_USE_SPI5 && !STM32_SPI_USE_SPI6
#if !GD32_SPI_USE_SPI1 && !GD32_SPI_USE_SPI2 && !GD32_SPI_USE_SPI3 && \
!GD32_SPI_USE_SPI4 && !GD32_SPI_USE_SPI5 && !GD32_SPI_USE_SPI6
#error "SPI driver activated but no SPI peripheral assigned"
#endif
#if STM32_SPI_USE_SPI1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
#if GD32_SPI_USE_SPI1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SPI_SPI1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI1"
#endif
#if STM32_SPI_USE_SPI2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
#if GD32_SPI_USE_SPI2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SPI_SPI2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI2"
#endif
#if STM32_SPI_USE_SPI3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
#if GD32_SPI_USE_SPI3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SPI_SPI3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI3"
#endif
#if STM32_SPI_USE_SPI4 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY)
#if GD32_SPI_USE_SPI4 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SPI_SPI4_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI4"
#endif
#if STM32_SPI_USE_SPI5 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY)
#if GD32_SPI_USE_SPI5 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SPI_SPI5_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI5"
#endif
#if STM32_SPI_USE_SPI6 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY)
#if GD32_SPI_USE_SPI6 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SPI_SPI6_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to SPI6"
#endif
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY)
#if GD32_SPI_USE_SPI1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_SPI_SPI1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI1"
#endif
#if STM32_SPI_USE_SPI2 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY)
#if GD32_SPI_USE_SPI2 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_SPI_SPI2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI2"
#endif
#if STM32_SPI_USE_SPI3 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY)
#if GD32_SPI_USE_SPI3 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_SPI_SPI3_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI3"
#endif
#if STM32_SPI_USE_SPI4 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI4_DMA_PRIORITY)
#if GD32_SPI_USE_SPI4 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_SPI_SPI4_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI4"
#endif
#if STM32_SPI_USE_SPI5 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI5_DMA_PRIORITY)
#if GD32_SPI_USE_SPI5 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_SPI_SPI5_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI5"
#endif
#if STM32_SPI_USE_SPI6 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI6_DMA_PRIORITY)
#if GD32_SPI_USE_SPI6 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_SPI_SPI6_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI6"
#endif
/* The following checks are only required when there is a DMA able to
reassign streams to different channels.*/
#if STM32_ADVANCED_DMA
#if GD32_ADVANCED_DMA
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) || \
!defined(STM32_SPI_SPI1_TX_DMA_STREAM))
#if GD32_SPI_USE_SPI1 && (!defined(GD32_SPI_SPI1_RX_DMA_STREAM) || \
!defined(GD32_SPI_SPI1_TX_DMA_STREAM))
#error "SPI1 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_STREAM) || \
!defined(STM32_SPI_SPI2_TX_DMA_STREAM))
#if GD32_SPI_USE_SPI2 && (!defined(GD32_SPI_SPI2_RX_DMA_STREAM) || \
!defined(GD32_SPI_SPI2_TX_DMA_STREAM))
#error "SPI2 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_STREAM) || \
!defined(STM32_SPI_SPI3_TX_DMA_STREAM))
#if GD32_SPI_USE_SPI3 && (!defined(GD32_SPI_SPI3_RX_DMA_STREAM) || \
!defined(GD32_SPI_SPI3_TX_DMA_STREAM))
#error "SPI3 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_STREAM) || \
!defined(STM32_SPI_SPI4_TX_DMA_STREAM))
#if GD32_SPI_USE_SPI4 && (!defined(GD32_SPI_SPI4_RX_DMA_STREAM) || \
!defined(GD32_SPI_SPI4_TX_DMA_STREAM))
#error "SPI4 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_STREAM) || \
!defined(STM32_SPI_SPI5_TX_DMA_STREAM))
#if GD32_SPI_USE_SPI5 && (!defined(GD32_SPI_SPI5_RX_DMA_STREAM) || \
!defined(GD32_SPI_SPI5_TX_DMA_STREAM))
#error "SPI5 DMA streams not defined"
#endif
#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_DMA_STREAM) || \
!defined(STM32_SPI_SPI6_TX_DMA_STREAM))
#if GD32_SPI_USE_SPI6 && (!defined(GD32_SPI_SPI6_RX_DMA_STREAM) || \
!defined(GD32_SPI_SPI6_TX_DMA_STREAM))
#error "SPI6 DMA streams not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
#if GD32_SPI_USE_SPI1 && \
!GD32_DMA_IS_VALID_ID(GD32_SPI_SPI1_RX_DMA_STREAM, GD32_SPI1_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI1 RX"
#endif
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
#if GD32_SPI_USE_SPI1 && \
!GD32_DMA_IS_VALID_ID(GD32_SPI_SPI1_TX_DMA_STREAM, GD32_SPI1_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI1 TX"
#endif
#if STM32_SPI_USE_SPI2 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
#if GD32_SPI_USE_SPI2 && \
!GD32_DMA_IS_VALID_ID(GD32_SPI_SPI2_RX_DMA_STREAM, GD32_SPI2_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI2 RX"
#endif
#if STM32_SPI_USE_SPI2 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
#if GD32_SPI_USE_SPI2 && \
!GD32_DMA_IS_VALID_ID(GD32_SPI_SPI2_TX_DMA_STREAM, GD32_SPI2_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI2 TX"
#endif
#if STM32_SPI_USE_SPI3 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
#if GD32_SPI_USE_SPI3 && \
!GD32_DMA_IS_VALID_ID(GD32_SPI_SPI3_RX_DMA_STREAM, GD32_SPI3_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI3 RX"
#endif
#if STM32_SPI_USE_SPI3 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
#if GD32_SPI_USE_SPI3 && \
!GD32_DMA_IS_VALID_ID(GD32_SPI_SPI3_TX_DMA_STREAM, GD32_SPI3_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI3 TX"
#endif
#if STM32_SPI_USE_SPI4 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_RX_DMA_STREAM, STM32_SPI4_RX_DMA_MSK)
#if GD32_SPI_USE_SPI4 && \
!GD32_DMA_IS_VALID_ID(GD32_SPI_SPI4_RX_DMA_STREAM, GD32_SPI4_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI4 RX"
#endif
#if STM32_SPI_USE_SPI4 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_TX_DMA_STREAM, STM32_SPI4_TX_DMA_MSK)
#if GD32_SPI_USE_SPI4 && \
!GD32_DMA_IS_VALID_ID(GD32_SPI_SPI4_TX_DMA_STREAM, GD32_SPI4_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI4 TX"
#endif
#if STM32_SPI_USE_SPI5 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_RX_DMA_STREAM, STM32_SPI5_RX_DMA_MSK)
#if GD32_SPI_USE_SPI5 && \
!GD32_DMA_IS_VALID_ID(GD32_SPI_SPI5_RX_DMA_STREAM, GD32_SPI5_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI5 RX"
#endif
#if STM32_SPI_USE_SPI5 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_TX_DMA_STREAM, STM32_SPI5_TX_DMA_MSK)
#if GD32_SPI_USE_SPI5 && \
!GD32_DMA_IS_VALID_ID(GD32_SPI_SPI5_TX_DMA_STREAM, GD32_SPI5_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI5 TX"
#endif
#if STM32_SPI_USE_SPI6 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_RX_DMA_STREAM, STM32_SPI6_RX_DMA_MSK)
#if GD32_SPI_USE_SPI6 && \
!GD32_DMA_IS_VALID_ID(GD32_SPI_SPI6_RX_DMA_STREAM, GD32_SPI6_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI6 RX"
#endif
#if STM32_SPI_USE_SPI6 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_TX_DMA_STREAM, STM32_SPI6_TX_DMA_MSK)
#if GD32_SPI_USE_SPI6 && \
!GD32_DMA_IS_VALID_ID(GD32_SPI_SPI6_TX_DMA_STREAM, GD32_SPI6_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI6 TX"
#endif
#endif /* STM32_ADVANCED_DMA */
#endif /* GD32_ADVANCED_DMA */
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#if !defined(GD32_DMA_REQUIRED)
#define GD32_DMA_REQUIRED
#endif
#if SPI_SELECT_MODE == SPI_SELECT_MODE_LLD
@ -441,27 +441,27 @@
/* External declarations. */
/*===========================================================================*/
#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
extern SPIDriver SPID1;
#endif
#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
extern SPIDriver SPID2;
#endif
#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI3 && !defined(__DOXYGEN__)
extern SPIDriver SPID3;
#endif
#if STM32_SPI_USE_SPI4 && !defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI4 && !defined(__DOXYGEN__)
extern SPIDriver SPID4;
#endif
#if STM32_SPI_USE_SPI5 && !defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI5 && !defined(__DOXYGEN__)
extern SPIDriver SPID5;
#endif
#if STM32_SPI_USE_SPI6 && !defined(__DOXYGEN__)
#if GD32_SPI_USE_SPI6 && !defined(__DOXYGEN__)
extern SPIDriver SPID6;
#endif

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os/hal/ports/GD/GD32VF103/TIM/hal_gpt_lld.c
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os/hal/ports/GD/GD32VF103/TIM/hal_gpt_lld.h
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os/hal/ports/GD/GD32VF103/TIM/hal_icu_lld.c
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434
os/hal/ports/GD/GD32VF103/TIM/hal_icu_lld.h
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@ -46,8 +46,8 @@
* @details If set to @p TRUE the support for ICUD1 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM1) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM1 FALSE
#if !defined(GD32_ICU_USE_TIM1) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM1 FALSE
#endif
/**
@ -55,8 +55,8 @@
* @details If set to @p TRUE the support for ICUD2 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM2) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM2 FALSE
#if !defined(GD32_ICU_USE_TIM2) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM2 FALSE
#endif
/**
@ -64,8 +64,8 @@
* @details If set to @p TRUE the support for ICUD3 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM3) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM3 FALSE
#if !defined(GD32_ICU_USE_TIM3) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM3 FALSE
#endif
/**
@ -73,8 +73,8 @@
* @details If set to @p TRUE the support for ICUD4 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM4) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM4 FALSE
#if !defined(GD32_ICU_USE_TIM4) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM4 FALSE
#endif
/**
@ -82,8 +82,8 @@
* @details If set to @p TRUE the support for ICUD5 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM5) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM5 FALSE
#if !defined(GD32_ICU_USE_TIM5) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM5 FALSE
#endif
/**
@ -91,8 +91,8 @@
* @details If set to @p TRUE the support for ICUD8 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM8) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM8 FALSE
#if !defined(GD32_ICU_USE_TIM8) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM8 FALSE
#endif
/**
@ -100,8 +100,8 @@
* @details If set to @p TRUE the support for ICUD9 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM9) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM9 FALSE
#if !defined(GD32_ICU_USE_TIM9) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM9 FALSE
#endif
/**
@ -109,8 +109,8 @@
* @details If set to @p TRUE the support for ICUD10 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM10) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM10 FALSE
#if !defined(GD32_ICU_USE_TIM10) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM10 FALSE
#endif
/**
@ -118,8 +118,8 @@
* @details If set to @p TRUE the support for ICUD11 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM11) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM11 FALSE
#if !defined(GD32_ICU_USE_TIM11) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM11 FALSE
#endif
/**
@ -127,8 +127,8 @@
* @details If set to @p TRUE the support for ICUD12 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM12) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM12 FALSE
#if !defined(GD32_ICU_USE_TIM12) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM12 FALSE
#endif
/**
@ -136,8 +136,8 @@
* @details If set to @p TRUE the support for ICUD13 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM13) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM13 FALSE
#if !defined(GD32_ICU_USE_TIM13) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM13 FALSE
#endif
/**
@ -145,8 +145,8 @@
* @details If set to @p TRUE the support for ICUD14 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM14) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM14 FALSE
#if !defined(GD32_ICU_USE_TIM14) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM14 FALSE
#endif
/**
@ -154,8 +154,8 @@
* @details If set to @p TRUE the support for ICUD15 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM15) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM15 FALSE
#if !defined(GD32_ICU_USE_TIM15) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM15 FALSE
#endif
/**
@ -163,8 +163,8 @@
* @details If set to @p TRUE the support for ICUD20 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM20) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM20 FALSE
#if !defined(GD32_ICU_USE_TIM20) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM20 FALSE
#endif
/**
@ -172,8 +172,8 @@
* @details If set to @p TRUE the support for ICUD21 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM21) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM21 FALSE
#if !defined(GD32_ICU_USE_TIM21) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM21 FALSE
#endif
/**
@ -181,120 +181,120 @@
* @details If set to @p TRUE the support for ICUD22 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ICU_USE_TIM22) || defined(__DOXYGEN__)
#define STM32_ICU_USE_TIM22 FALSE
#if !defined(GD32_ICU_USE_TIM22) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM22 FALSE
#endif
/**
* @brief ICUD1 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM1_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD2 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM2_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD3 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM3_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD4 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM4_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD5 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM5_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD8 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM8_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD9 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM9_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD10 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM10_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM10_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM10_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM10_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD11 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM11_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM11_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD12 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM12_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM12_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD13 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM13_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM13_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM13_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM13_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD14 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM14_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM14_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD15 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM15_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM15_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM15_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM15_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD20 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM20_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM20_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM20_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM20_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD21 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM21_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM21_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM21_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM21_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD22 interrupt priority level setting.
*/
#if !defined(STM32_ICU_TIM22_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM22_IRQ_PRIORITY 7
#if !defined(GD32_ICU_TIM22_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM22_IRQ_PRIORITY 7
#endif
/** @} */
@ -302,352 +302,352 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !defined(STM32_HAS_TIM1)
#define STM32_HAS_TIM1 FALSE
#if !defined(GD32_HAS_TIM1)
#define GD32_HAS_TIM1 FALSE
#endif
#if !defined(STM32_HAS_TIM2)
#define STM32_HAS_TIM2 FALSE
#if !defined(GD32_HAS_TIM2)
#define GD32_HAS_TIM2 FALSE
#endif
#if !defined(STM32_HAS_TIM3)
#define STM32_HAS_TIM3 FALSE
#if !defined(GD32_HAS_TIM3)
#define GD32_HAS_TIM3 FALSE
#endif
#if !defined(STM32_HAS_TIM4)
#define STM32_HAS_TIM4 FALSE
#if !defined(GD32_HAS_TIM4)
#define GD32_HAS_TIM4 FALSE
#endif
#if !defined(STM32_HAS_TIM5)
#define STM32_HAS_TIM5 FALSE
#if !defined(GD32_HAS_TIM5)
#define GD32_HAS_TIM5 FALSE
#endif
#if !defined(STM32_HAS_TIM8)
#define STM32_HAS_TIM8 FALSE
#if !defined(GD32_HAS_TIM8)
#define GD32_HAS_TIM8 FALSE
#endif
#if !defined(STM32_HAS_TIM9)
#define STM32_HAS_TIM9 FALSE
#if !defined(GD32_HAS_TIM9)
#define GD32_HAS_TIM9 FALSE
#endif
#if !defined(STM32_HAS_TIM10)
#define STM32_HAS_TIM10 FALSE
#if !defined(GD32_HAS_TIM10)
#define GD32_HAS_TIM10 FALSE
#endif
#if !defined(STM32_HAS_TIM11)
#define STM32_HAS_TIM11 FALSE
#if !defined(GD32_HAS_TIM11)
#define GD32_HAS_TIM11 FALSE
#endif
#if !defined(STM32_HAS_TIM12)
#define STM32_HAS_TIM12 FALSE
#if !defined(GD32_HAS_TIM12)
#define GD32_HAS_TIM12 FALSE
#endif
#if !defined(STM32_HAS_TIM13)
#define STM32_HAS_TIM13 FALSE
#if !defined(GD32_HAS_TIM13)
#define GD32_HAS_TIM13 FALSE
#endif
#if !defined(STM32_HAS_TIM14)
#define STM32_HAS_TIM14 FALSE
#if !defined(GD32_HAS_TIM14)
#define GD32_HAS_TIM14 FALSE
#endif
#if !defined(STM32_HAS_TIM15)
#define STM32_HAS_TIM15 FALSE
#if !defined(GD32_HAS_TIM15)
#define GD32_HAS_TIM15 FALSE
#endif
#if !defined(STM32_HAS_TIM20)
#define STM32_HAS_TIM20 FALSE
#if !defined(GD32_HAS_TIM20)
#define GD32_HAS_TIM20 FALSE
#endif
#if !defined(STM32_HAS_TIM21)
#define STM32_HAS_TIM21 FALSE
#if !defined(GD32_HAS_TIM21)
#define GD32_HAS_TIM21 FALSE
#endif
#if !defined(STM32_HAS_TIM22)
#define STM32_HAS_TIM22 FALSE
#if !defined(GD32_HAS_TIM22)
#define GD32_HAS_TIM22 FALSE
#endif
#if STM32_ICU_USE_TIM1 && !STM32_HAS_TIM1
#if GD32_ICU_USE_TIM1 && !GD32_HAS_TIM1
#error "TIM1 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM2 && !STM32_HAS_TIM2
#if GD32_ICU_USE_TIM2 && !GD32_HAS_TIM2
#error "TIM2 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM3 && !STM32_HAS_TIM3
#if GD32_ICU_USE_TIM3 && !GD32_HAS_TIM3
#error "TIM3 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM4 && !STM32_HAS_TIM4
#if GD32_ICU_USE_TIM4 && !GD32_HAS_TIM4
#error "TIM4 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM5 && !STM32_HAS_TIM5
#if GD32_ICU_USE_TIM5 && !GD32_HAS_TIM5
#error "TIM5 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM8 && !STM32_HAS_TIM8
#if GD32_ICU_USE_TIM8 && !GD32_HAS_TIM8
#error "TIM8 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM9 && !STM32_HAS_TIM9
#if GD32_ICU_USE_TIM9 && !GD32_HAS_TIM9
#error "TIM9 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM10 && !STM32_HAS_TIM10
#if GD32_ICU_USE_TIM10 && !GD32_HAS_TIM10
#error "TIM10 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM11 && !STM32_HAS_TIM11
#if GD32_ICU_USE_TIM11 && !GD32_HAS_TIM11
#error "TIM11 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM12 && !STM32_HAS_TIM12
#if GD32_ICU_USE_TIM12 && !GD32_HAS_TIM12
#error "TIM12 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM13 && !STM32_HAS_TIM13
#if GD32_ICU_USE_TIM13 && !GD32_HAS_TIM13
#error "TIM13 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM14 && !STM32_HAS_TIM14
#if GD32_ICU_USE_TIM14 && !GD32_HAS_TIM14
#error "TIM14 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM15 && !STM32_HAS_TIM15
#if GD32_ICU_USE_TIM15 && !GD32_HAS_TIM15
#error "TIM15 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM20 && !STM32_HAS_TIM20
#if GD32_ICU_USE_TIM20 && !GD32_HAS_TIM20
#error "TIM20 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM21 && !STM32_HAS_TIM21
#if GD32_ICU_USE_TIM21 && !GD32_HAS_TIM21
#error "TIM21 not present in the selected device"
#endif
#if STM32_ICU_USE_TIM22 && !STM32_HAS_TIM22
#if GD32_ICU_USE_TIM22 && !GD32_HAS_TIM22
#error "TIM22 not present in the selected device"
#endif
#if !STM32_ICU_USE_TIM1 && !STM32_ICU_USE_TIM2 && \
!STM32_ICU_USE_TIM3 && !STM32_ICU_USE_TIM4 && \
!STM32_ICU_USE_TIM5 && !STM32_ICU_USE_TIM8 && \
!STM32_ICU_USE_TIM9 && !STM32_ICU_USE_TIM10 && \
!STM32_ICU_USE_TIM11 && !STM32_ICU_USE_TIM12 && \
!STM32_ICU_USE_TIM13 && !STM32_ICU_USE_TIM14 && \
!STM32_ICU_USE_TIM15 && !STM32_ICU_USE_TIM20 && \
!STM32_ICU_USE_TIM21 && !STM32_ICU_USE_TIM22
#if !GD32_ICU_USE_TIM1 && !GD32_ICU_USE_TIM2 && \
!GD32_ICU_USE_TIM3 && !GD32_ICU_USE_TIM4 && \
!GD32_ICU_USE_TIM5 && !GD32_ICU_USE_TIM8 && \
!GD32_ICU_USE_TIM9 && !GD32_ICU_USE_TIM10 && \
!GD32_ICU_USE_TIM11 && !GD32_ICU_USE_TIM12 && \
!GD32_ICU_USE_TIM13 && !GD32_ICU_USE_TIM14 && \
!GD32_ICU_USE_TIM15 && !GD32_ICU_USE_TIM20 && \
!GD32_ICU_USE_TIM21 && !GD32_ICU_USE_TIM22
#error "ICU driver activated but no TIM peripheral assigned"
#endif
/* Checks on allocation of TIMx units.*/
#if STM32_ICU_USE_TIM1
#if defined(STM32_TIM1_IS_USED)
#if GD32_ICU_USE_TIM1
#if defined(GD32_TIM1_IS_USED)
#error "ICUD1 requires TIM1 but the timer is already used"
#else
#define STM32_TIM1_IS_USED
#define GD32_TIM1_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM2
#if defined(STM32_TIM2_IS_USED)
#if GD32_ICU_USE_TIM2
#if defined(GD32_TIM2_IS_USED)
#error "ICUD2 requires TIM2 but the timer is already used"
#else
#define STM32_TIM2_IS_USED
#define GD32_TIM2_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM3
#if defined(STM32_TIM3_IS_USED)
#if GD32_ICU_USE_TIM3
#if defined(GD32_TIM3_IS_USED)
#error "ICUD3 requires TIM3 but the timer is already used"
#else
#define STM32_TIM3_IS_USED
#define GD32_TIM3_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM4
#if defined(STM32_TIM4_IS_USED)
#if GD32_ICU_USE_TIM4
#if defined(GD32_TIM4_IS_USED)
#error "ICUD4 requires TIM4 but the timer is already used"
#else
#define STM32_TIM4_IS_USED
#define GD32_TIM4_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM5
#if defined(STM32_TIM5_IS_USED)
#if GD32_ICU_USE_TIM5
#if defined(GD32_TIM5_IS_USED)
#error "ICUD5 requires TIM5 but the timer is already used"
#else
#define STM32_TIM5_IS_USED
#define GD32_TIM5_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM8
#if defined(STM32_TIM8_IS_USED)
#if GD32_ICU_USE_TIM8
#if defined(GD32_TIM8_IS_USED)
#error "ICUD8 requires TIM8 but the timer is already used"
#else
#define STM32_TIM8_IS_USED
#define GD32_TIM8_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM9
#if defined(STM32_TIM9_IS_USED)
#if GD32_ICU_USE_TIM9
#if defined(GD32_TIM9_IS_USED)
#error "ICUD9 requires TIM9 but the timer is already used"
#else
#define STM32_TIM9_IS_USED
#define GD32_TIM9_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM10
#if defined(STM32_TIM10_IS_USED)
#if GD32_ICU_USE_TIM10
#if defined(GD32_TIM10_IS_USED)
#error "ICUD10 requires TIM10 but the timer is already used"
#else
#define STM32_TIM10_IS_USED
#define GD32_TIM10_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM11
#if defined(STM32_TIM11_IS_USED)
#if GD32_ICU_USE_TIM11
#if defined(GD32_TIM11_IS_USED)
#error "ICUD11 requires TIM11 but the timer is already used"
#else
#define STM32_TIM11_IS_USED
#define GD32_TIM11_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM12
#if defined(STM32_TIM12_IS_USED)
#if GD32_ICU_USE_TIM12
#if defined(GD32_TIM12_IS_USED)
#error "ICUD12 requires TIM12 but the timer is already used"
#else
#define STM32_TIM12_IS_USED
#define GD32_TIM12_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM13
#if defined(STM32_TIM13_IS_USED)
#if GD32_ICU_USE_TIM13
#if defined(GD32_TIM13_IS_USED)
#error "ICUD13 requires TIM13 but the timer is already used"
#else
#define STM32_TIM13_IS_USED
#define GD32_TIM13_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM14
#if defined(STM32_TIM14_IS_USED)
#if GD32_ICU_USE_TIM14
#if defined(GD32_TIM14_IS_USED)
#error "ICUD14 requires TIM14 but the timer is already used"
#else
#define STM32_TIM14_IS_USED
#define GD32_TIM14_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM15
#if defined(STM32_TIM15_IS_USED)
#if GD32_ICU_USE_TIM15
#if defined(GD32_TIM15_IS_USED)
#error "ICUD15 requires TIM15 but the timer is already used"
#else
#define STM32_TIM15_IS_USED
#define GD32_TIM15_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM20
#if defined(STM32_TIM20_IS_USED)
#if GD32_ICU_USE_TIM20
#if defined(GD32_TIM20_IS_USED)
#error "ICUD20 requires TIM20 but the timer is already used"
#else
#define STM32_TIM20_IS_USED
#define GD32_TIM20_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM21
#if defined(STM32_TIM21_IS_USED)
#if GD32_ICU_USE_TIM21
#if defined(GD32_TIM21_IS_USED)
#error "ICUD21 requires TIM21 but the timer is already used"
#else
#define STM32_TIM21_IS_USED
#define GD32_TIM21_IS_USED
#endif
#endif
#if STM32_ICU_USE_TIM22
#if defined(STM32_TIM22_IS_USED)
#if GD32_ICU_USE_TIM22
#if defined(GD32_TIM22_IS_USED)
#error "ICUD22 requires TIM22 but the timer is already used"
#else
#define STM32_TIM22_IS_USED
#define GD32_TIM22_IS_USED
#endif
#endif
/* IRQ priority checks.*/
#if STM32_ICU_USE_TIM1 && !defined(STM32_TIM1_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM1_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM1 && !defined(GD32_TIM1_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM1"
#endif
#if STM32_ICU_USE_TIM2 && !defined(STM32_TIM2_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM2_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM2 && !defined(GD32_TIM2_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM2"
#endif
#if STM32_ICU_USE_TIM3 && !defined(STM32_TIM3_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM3_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM3 && !defined(GD32_TIM3_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM3"
#endif
#if STM32_ICU_USE_TIM4 && !defined(STM32_TIM4_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM4_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM4 && !defined(GD32_TIM4_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM4_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM4"
#endif
#if STM32_ICU_USE_TIM5 && !defined(STM32_TIM5_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM5_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM5 && !defined(GD32_TIM5_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM5_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM5"
#endif
#if STM32_ICU_USE_TIM8 && !defined(STM32_TIM8_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM8_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM8 && !defined(GD32_TIM8_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM8_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM8"
#endif
#if STM32_ICU_USE_TIM9 && !defined(STM32_TIM9_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM9_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM9 && !defined(GD32_TIM9_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM9_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM9"
#endif
#if STM32_ICU_USE_TIM10 && !defined(STM32_TIM10_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM10_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM10 && !defined(GD32_TIM10_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM10_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM10"
#endif
#if STM32_ICU_USE_TIM11 && !defined(STM32_TIM11_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM11_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM11 && !defined(GD32_TIM11_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM11_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM11"
#endif
#if STM32_ICU_USE_TIM12 && !defined(STM32_TIM12_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM12_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM12 && !defined(GD32_TIM12_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM12_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM12"
#endif
#if STM32_ICU_USE_TIM13 && !defined(STM32_TIM13_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM13_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM13 && !defined(GD32_TIM13_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM13_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM13"
#endif
#if STM32_ICU_USE_TIM14 && !defined(STM32_TIM14_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM14_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM14 && !defined(GD32_TIM14_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM14_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM14"
#endif
#if STM32_ICU_USE_TIM15 && !defined(STM32_TIM15_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM15_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM15 && !defined(GD32_TIM15_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM15_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM15"
#endif
#if STM32_ICU_USE_TIM20 && !defined(STM32_TIM20_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM20_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM20 && !defined(GD32_TIM20_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM20_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM20"
#endif
#if STM32_ICU_USE_TIM21 && !defined(STM32_TIM21_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM21_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM21 && !defined(GD32_TIM21_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM21_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM21"
#endif
#if STM32_ICU_USE_TIM22 && !defined(STM32_TIM22_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM22_IRQ_PRIORITY)
#if GD32_ICU_USE_TIM22 && !defined(GD32_TIM22_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM22_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM22"
#endif
@ -800,73 +800,73 @@ struct ICUDriver {
* @notapi
*/
#define icu_lld_are_notifications_enabled(icup) \
(bool)(((icup)->tim->DIER & STM32_TIM_DIER_IRQ_MASK) != 0)
(bool)(((icup)->tim->DIER & GD32_TIM_DIER_IRQ_MASK) != 0)
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if STM32_ICU_USE_TIM1 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM1 && !defined(__DOXYGEN__)
extern ICUDriver ICUD1;
#endif
#if STM32_ICU_USE_TIM2 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM2 && !defined(__DOXYGEN__)
extern ICUDriver ICUD2;
#endif
#if STM32_ICU_USE_TIM3 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM3 && !defined(__DOXYGEN__)
extern ICUDriver ICUD3;
#endif
#if STM32_ICU_USE_TIM4 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM4 && !defined(__DOXYGEN__)
extern ICUDriver ICUD4;
#endif
#if STM32_ICU_USE_TIM5 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM5 && !defined(__DOXYGEN__)
extern ICUDriver ICUD5;
#endif
#if STM32_ICU_USE_TIM8 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM8 && !defined(__DOXYGEN__)
extern ICUDriver ICUD8;
#endif
#if STM32_ICU_USE_TIM9 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM9 && !defined(__DOXYGEN__)
extern ICUDriver ICUD9;
#endif
#if STM32_ICU_USE_TIM10 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM10 && !defined(__DOXYGEN__)
extern ICUDriver ICUD10;
#endif
#if STM32_ICU_USE_TIM11 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM11 && !defined(__DOXYGEN__)
extern ICUDriver ICUD11;
#endif
#if STM32_ICU_USE_TIM12 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM12 && !defined(__DOXYGEN__)
extern ICUDriver ICUD12;
#endif
#if STM32_ICU_USE_TIM13 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM13 && !defined(__DOXYGEN__)
extern ICUDriver ICUD13;
#endif
#if STM32_ICU_USE_TIM14 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM14 && !defined(__DOXYGEN__)
extern ICUDriver ICUD14;
#endif
#if STM32_ICU_USE_TIM15 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM15 && !defined(__DOXYGEN__)
extern ICUDriver ICUD15;
#endif
#if STM32_ICU_USE_TIM20 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM20 && !defined(__DOXYGEN__)
extern ICUDriver ICUD20;
#endif
#if STM32_ICU_USE_TIM21 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM21 && !defined(__DOXYGEN__)
extern ICUDriver ICUD21;
#endif
#if STM32_ICU_USE_TIM22 && !defined(__DOXYGEN__)
#if GD32_ICU_USE_TIM22 && !defined(__DOXYGEN__)
extern ICUDriver ICUD22;
#endif

618
os/hal/ports/GD/GD32VF103/TIM/hal_pwm_lld.c
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File diff suppressed because it is too large Load Diff

502
os/hal/ports/GD/GD32VF103/TIM/hal_pwm_lld.h
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File diff suppressed because it is too large Load Diff

138
os/hal/ports/GD/GD32VF103/TIM/hal_st_lld.c
View File

@ -38,19 +38,19 @@
#define ST_ARR_INIT 0x0000FFFFU
#endif
#if STM32_ST_USE_TIMER == 2
#if GD32_ST_USE_TIMER == 2
#if !STM32_HAS_TIM2
#if !GD32_HAS_TIM2
#error "TIM2 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM2_IS_32BITS
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM2_IS_32BITS
#error "TIM2 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM2_HANDLER
#define ST_NUMBER GD32_TIM2_NUMBER
#define ST_CLOCK_SRC STM32_TIMCLK1
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM2(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP
@ -64,19 +64,19 @@
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM2_STOP
#endif
#elif STM32_ST_USE_TIMER == 3
#elif GD32_ST_USE_TIMER == 3
#if !STM32_HAS_TIM3
#if !GD32_HAS_TIM3
#error "TIM3 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM3_IS_32BITS
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM3_IS_32BITS
#error "TIM3 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM3_HANDLER
#define ST_NUMBER GD32_TIM3_NUMBER
#define ST_CLOCK_SRC STM32_TIMCLK1
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM3(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM3_STOP
@ -90,19 +90,19 @@
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM3_STOP
#endif
#elif STM32_ST_USE_TIMER == 4
#elif GD32_ST_USE_TIMER == 4
#if !STM32_HAS_TIM4
#if !GD32_HAS_TIM4
#error "TIM4 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM4_IS_32BITS
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM4_IS_32BITS
#error "TIM4 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM4_HANDLER
#define ST_NUMBER GD32_TIM4_NUMBER
#define ST_CLOCK_SRC STM32_TIMCLK1
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM4(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM4_STOP
@ -114,19 +114,19 @@
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM4_STOP
#endif
#elif STM32_ST_USE_TIMER == 5
#elif GD32_ST_USE_TIMER == 5
#if !STM32_HAS_TIM5
#if !GD32_HAS_TIM5
#error "TIM5 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM5_IS_32BITS
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM5_IS_32BITS
#error "TIM5 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM5_HANDLER
#define ST_NUMBER GD32_TIM5_NUMBER
#define ST_CLOCK_SRC STM32_TIMCLK1
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM5(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM5_STOP
@ -138,19 +138,19 @@
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM5_STOP
#endif
#elif STM32_ST_USE_TIMER == 9
#elif GD32_ST_USE_TIMER == 9
#if !STM32_HAS_TIM9
#if !GD32_HAS_TIM9
#error "TIM9 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM9_IS_32BITS
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM9_IS_32BITS
#error "TIM9 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM9_HANDLER
#define ST_NUMBER GD32_TIM9_NUMBER
#define ST_CLOCK_SRC STM32_TIMCLK2
#define ST_CLOCK_SRC GD32_TIMCLK2
#define ST_ENABLE_CLOCK() rccEnableTIM9(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM9_STOP
@ -162,19 +162,19 @@
#define ST_ENABLE_STOP() DBGMCU->APB2FZ |= DBGMCU_APB2_FZ_DBG_TIM9_STOP
#endif
#elif STM32_ST_USE_TIMER == 10
#elif GD32_ST_USE_TIMER == 10
#if !STM32_HAS_TIM10
#if !GD32_HAS_TIM10
#error "TIM10 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM10_IS_32BITS
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM10_IS_32BITS
#error "TIM10 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM10_HANDLER
#define ST_NUMBER GD32_TIM10_NUMBER
#define ST_CLOCK_SRC STM32_TIMCLK2
#define ST_CLOCK_SRC GD32_TIMCLK2
#define ST_ENABLE_CLOCK() rccEnableTIM10(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM10_STOP
@ -186,19 +186,19 @@
#define ST_ENABLE_STOP() DBGMCU->APB2FZ |= DBGMCU_APB2_FZ_DBG_TIM10_STOP
#endif
#elif STM32_ST_USE_TIMER == 11
#elif GD32_ST_USE_TIMER == 11
#if !STM32_HAS_TIM11
#if !GD32_HAS_TIM11
#error "TIM11 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM11_IS_32BITS
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM11_IS_32BITS
#error "TIM11 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM11_HANDLER
#define ST_NUMBER GD32_TIM11_NUMBER
#define ST_CLOCK_SRC STM32_TIMCLK2
#define ST_CLOCK_SRC GD32_TIMCLK2
#define ST_ENABLE_CLOCK() rccEnableTIM11(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM11_STOP
@ -210,19 +210,19 @@
#define ST_ENABLE_STOP() DBGMCU->APB2FZ |= DBGMCU_APB2_FZ_DBG_TIM11_STOP
#endif
#elif STM32_ST_USE_TIMER == 12
#elif GD32_ST_USE_TIMER == 12
#if !STM32_HAS_TIM12
#if !GD32_HAS_TIM12
#error "TIM12 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM12_IS_32BITS
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM12_IS_32BITS
#error "TIM12 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM12_HANDLER
#define ST_NUMBER GD32_TIM12_NUMBER
#define ST_CLOCK_SRC STM32_TIMCLK1
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM12(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM12_STOP
@ -234,19 +234,19 @@
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM12_STOP
#endif
#elif STM32_ST_USE_TIMER == 13
#elif GD32_ST_USE_TIMER == 13
#if !STM32_HAS_TIM13
#if !GD32_HAS_TIM13
#error "TIM13 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM13_IS_32BITS
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM13_IS_32BITS
#error "TIM13 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM13_HANDLER
#define ST_NUMBER GD32_TIM13_NUMBER
#define ST_CLOCK_SRC STM32_TIMCLK1
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM13(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM13_STOP
@ -258,19 +258,19 @@
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM13_STOP
#endif
#elif STM32_ST_USE_TIMER == 14
#elif GD32_ST_USE_TIMER == 14
#if !STM32_HAS_TIM14
#if !GD32_HAS_TIM14
#error "TIM14 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM14_IS_32BITS
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM14_IS_32BITS
#error "TIM14 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM14_HANDLER
#define ST_NUMBER GD32_TIM14_NUMBER
#define ST_CLOCK_SRC STM32_TIMCLK1
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM14(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM14_STOP
@ -282,40 +282,40 @@
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM14_STOP
#endif
#elif STM32_ST_USE_TIMER == 21
#elif GD32_ST_USE_TIMER == 21
#if !STM32_HAS_TIM21
#if !GD32_HAS_TIM21
#error "TIM21 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM21_IS_32BITS
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM21_IS_32BITS
#error "TIM21 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM21_HANDLER
#define ST_NUMBER GD32_TIM21_NUMBER
#define ST_CLOCK_SRC STM32_TIMCLK2
#define ST_CLOCK_SRC GD32_TIMCLK2
#define ST_ENABLE_CLOCK() rccEnableTIM21(true)
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB2_FZ_DBG_TIM21_STOP
#elif STM32_ST_USE_TIMER == 22
#elif GD32_ST_USE_TIMER == 22
#if !STM32_HAS_TIM22
#if !GD32_HAS_TIM22
#error "TIM22 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM22_IS_32BITS
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM22_IS_32BITS
#error "TIM21 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM22_HANDLER
#define ST_NUMBER GD32_TIM22_NUMBER
#define ST_CLOCK_SRC STM32_TIMCLK2
#define ST_CLOCK_SRC GD32_TIMCLK2
#define ST_ENABLE_CLOCK() rccEnableTIM22(true)
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB2_FZ_DBG_TIM21_STOP
#else
#error "STM32_ST_USE_TIMER specifies an unsupported timer"
#error "GD32_ST_USE_TIMER specifies an unsupported timer"
#endif
#if ST_CLOCK_SRC % OSAL_ST_FREQUENCY != 0
@ -332,10 +332,10 @@
#define ST_HANDLER vector7
#if defined(STM32_CORE_CK)
#define SYSTICK_CK STM32_CORE_CK
#if defined(GD32_CORE_CK)
#define SYSTICK_CK GD32_CORE_CK
#else
#define SYSTICK_CK STM32_HCLK
#define SYSTICK_CK GD32_HCLK
#endif
#if SYSTICK_CK % OSAL_ST_FREQUENCY != 0
@ -368,7 +368,7 @@
/* Driver interrupt handlers. */
/*===========================================================================*/
#if !defined(STM32_SYSTICK_SUPPRESS_ISR)
#if !defined(GD32_SYSTICK_SUPPRESS_ISR)
/**
* @brief Interrupt handler.
*
@ -405,28 +405,28 @@ void st_lld_init(void) {
ST_ENABLE_STOP();
/* Initializing the counter in free running mode.*/
STM32_ST_TIM->PSC = (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1;
STM32_ST_TIM->ARR = ST_ARR_INIT;
STM32_ST_TIM->CCMR1 = 0;
STM32_ST_TIM->CCR[0] = 0;
GD32_ST_TIM->PSC = (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1;
GD32_ST_TIM->ARR = ST_ARR_INIT;
GD32_ST_TIM->CCMR1 = 0;
GD32_ST_TIM->CCR[0] = 0;
#if ST_LLD_NUM_ALARMS > 1
STM32_ST_TIM->CCR[1] = 0;
GD32_ST_TIM->CCR[1] = 0;
#endif
#if ST_LLD_NUM_ALARMS > 2
STM32_ST_TIM->CCR[2] = 0;
GD32_ST_TIM->CCR[2] = 0;
#endif
#if ST_LLD_NUM_ALARMS > 3
STM32_ST_TIM->CCR[3] = 0;
GD32_ST_TIM->CCR[3] = 0;
#endif
STM32_ST_TIM->DIER = 0;
STM32_ST_TIM->CR2 = 0;
STM32_ST_TIM->EGR = TIM_EGR_UG;
STM32_ST_TIM->CR1 = TIM_CR1_CEN;
GD32_ST_TIM->DIER = 0;
GD32_ST_TIM->CR2 = 0;
GD32_ST_TIM->EGR = TIM_EGR_UG;
GD32_ST_TIM->CR1 = TIM_CR1_CEN;
//TODO
#if !defined(STM32_SYSTICK_SUPPRESS_ISR)
#if !defined(GD32_SYSTICK_SUPPRESS_ISR)
/* IRQ enabled.*/
eclicEnableVector(ST_NUMBER, STM32_ST_IRQ_PRIORITY, STM32_ST_IRQ_TRIGGER);
eclicEnableVector(ST_NUMBER, GD32_ST_IRQ_PRIORITY, GD32_ST_IRQ_TRIGGER);
#endif
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
@ -443,7 +443,7 @@ void st_lld_init(void) {
SysTick_CTRL_TICKINT_Msk;
*/
/* IRQ enabled.*/
eclicEnableVector(HANDLER_SYSTICK, STM32_ST_IRQ_PRIORITY, STM32_ST_IRQ_TRIGGER);
eclicEnableVector(HANDLER_SYSTICK, GD32_ST_IRQ_PRIORITY, GD32_ST_IRQ_TRIGGER);
#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
}
@ -458,10 +458,10 @@ void st_lld_serve_interrupt(void) {
#endif
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
uint32_t sr;
stm32_tim_t *timp = STM32_ST_TIM;
stm32_tim_t *timp = GD32_ST_TIM;
sr = timp->SR;
sr &= timp->DIER & STM32_TIM_DIER_IRQ_MASK;
sr &= timp->DIER & GD32_TIM_DIER_IRQ_MASK;
timp->SR = ~sr;
if ((sr & TIM_SR_CC1IF) != 0U)

634
os/hal/ports/GD/GD32VF103/TIM/hal_st_lld.h
View File

@ -32,7 +32,7 @@
/*===========================================================================*/
/* Feature currently disabled.*/
#define STM32_ST_ENFORCE_ALARMS 1
#define GD32_ST_ENFORCE_ALARMS 1
/*===========================================================================*/
/* Driver pre-compile time settings. */
@ -45,8 +45,8 @@
/**
* @brief SysTick timer IRQ priority.
*/
#if !defined(STM32_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ST_IRQ_PRIORITY 8
#if !defined(GD32_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ST_IRQ_PRIORITY 8
#endif
/**
@ -55,8 +55,8 @@
* is required.
* @note Timers 2, 3, 4, 5, 21 and 22 are supported.
*/
#if !defined(STM32_ST_USE_TIMER) || defined(__DOXYGEN__)
#define STM32_ST_USE_TIMER 2
#if !defined(GD32_ST_USE_TIMER) || defined(__DOXYGEN__)
#define GD32_ST_USE_TIMER 2
#endif
/** @} */
@ -66,438 +66,438 @@
/* This has to go after transition to shared handlers is complete for all
platforms.*/
#if !defined(STM32_HAS_TIM2)
#define STM32_HAS_TIM2 FALSE
#if !defined(GD32_HAS_TIM2)
#define GD32_HAS_TIM2 FALSE
#endif
#if !defined(STM32_HAS_TIM3)
#define STM32_HAS_TIM3 FALSE
#if !defined(GD32_HAS_TIM3)
#define GD32_HAS_TIM3 FALSE
#endif
#if !defined(STM32_HAS_TIM4)
#define STM32_HAS_TIM4 FALSE
#if !defined(GD32_HAS_TIM4)
#define GD32_HAS_TIM4 FALSE
#endif
#if !defined(STM32_HAS_TIM5)
#define STM32_HAS_TIM5 FALSE
#if !defined(GD32_HAS_TIM5)
#define GD32_HAS_TIM5 FALSE
#endif
#if !defined(STM32_HAS_TIM9)
#define STM32_HAS_TIM9 FALSE
#if !defined(GD32_HAS_TIM9)
#define GD32_HAS_TIM9 FALSE
#endif
#if !defined(STM32_HAS_TIM10)
#define STM32_HAS_TIM10 FALSE
#if !defined(GD32_HAS_TIM10)
#define GD32_HAS_TIM10 FALSE
#endif
#if !defined(STM32_HAS_TIM11)
#define STM32_HAS_TIM11 FALSE
#if !defined(GD32_HAS_TIM11)
#define GD32_HAS_TIM11 FALSE
#endif
#if !defined(STM32_HAS_TIM12)
#define STM32_HAS_TIM12 FALSE
#if !defined(GD32_HAS_TIM12)
#define GD32_HAS_TIM12 FALSE
#endif
#if !defined(STM32_HAS_TIM13)
#define STM32_HAS_TIM13 FALSE
#if !defined(GD32_HAS_TIM13)
#define GD32_HAS_TIM13 FALSE
#endif
#if !defined(STM32_HAS_TIM14)
#define STM32_HAS_TIM14 FALSE
#if !defined(GD32_HAS_TIM14)
#define GD32_HAS_TIM14 FALSE
#endif
#if !defined(STM32_HAS_TIM21)
#define STM32_HAS_TIM21 FALSE
#if !defined(GD32_HAS_TIM21)
#define GD32_HAS_TIM21 FALSE
#endif
#if !defined(STM32_HAS_TIM22)
#define STM32_HAS_TIM22 FALSE
#if !defined(GD32_HAS_TIM22)
#define GD32_HAS_TIM22 FALSE
#endif
/**/
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
#if STM32_ST_USE_TIMER == 2
#if GD32_ST_USE_TIMER == 2
#if defined(STM32_TIM2_IS_USED)
#if defined(GD32_TIM2_IS_USED)
#error "ST requires TIM2 but the timer is already used"
#else
#define STM32_TIM2_IS_USED
#define GD32_TIM2_IS_USED
#endif
#if defined(STM32_TIM2_SUPPRESS_ISR)
#define STM32_SYSTICK_SUPPRESS_ISR
#if defined(GD32_TIM2_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define STM32_ST_TIM STM32_TIM2
#define ST_LLD_NUM_ALARMS STM32_TIM2_CHANNELS
#define STM32_ST_USE_SYSTICK FALSE
#define STM32_ST_USE_TIM2 TRUE
#define STM32_ST_USE_TIM3 FALSE
#define STM32_ST_USE_TIM4 FALSE
#define STM32_ST_USE_TIM5 FALSE
#define STM32_ST_USE_TIM9 FALSE
#define STM32_ST_USE_TIM10 FALSE
#define STM32_ST_USE_TIM11 FALSE
#define STM32_ST_USE_TIM12 FALSE
#define STM32_ST_USE_TIM13 FALSE
#define STM32_ST_USE_TIM14 FALSE
#define STM32_ST_USE_TIM21 FALSE
#define STM32_ST_USE_TIM22 FALSE
#define GD32_ST_TIM GD32_TIM2
#define ST_LLD_NUM_ALARMS GD32_TIM2_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 TRUE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif STM32_ST_USE_TIMER == 3
#elif GD32_ST_USE_TIMER == 3
#if defined(STM32_TIM3_IS_USED)
#if defined(GD32_TIM3_IS_USED)
#error "ST requires TIM3 but the timer is already used"
#else
#define STM32_TIM3_IS_USED
#define GD32_TIM3_IS_USED
#endif
#if defined(STM32_TIM3_SUPPRESS_ISR)
#define STM32_SYSTICK_SUPPRESS_ISR
#if defined(GD32_TIM3_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define STM32_ST_TIM STM32_TIM3
#define ST_LLD_NUM_ALARMS STM32_TIM3_CHANNELS
#define STM32_ST_USE_SYSTICK FALSE
#define STM32_ST_USE_TIM2 FALSE
#define STM32_ST_USE_TIM3 TRUE
#define STM32_ST_USE_TIM4 FALSE
#define STM32_ST_USE_TIM5 FALSE
#define STM32_ST_USE_TIM9 FALSE
#define STM32_ST_USE_TIM10 FALSE
#define STM32_ST_USE_TIM11 FALSE
#define STM32_ST_USE_TIM12 FALSE
#define STM32_ST_USE_TIM13 FALSE
#define STM32_ST_USE_TIM14 FALSE
#define STM32_ST_USE_TIM21 FALSE
#define STM32_ST_USE_TIM22 FALSE
#define GD32_ST_TIM GD32_TIM3
#define ST_LLD_NUM_ALARMS GD32_TIM3_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 TRUE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif STM32_ST_USE_TIMER == 4
#elif GD32_ST_USE_TIMER == 4
#if defined(STM32_TIM4_IS_USED)
#if defined(GD32_TIM4_IS_USED)
#error "ST requires TIM4 but the timer is already used"
#else
#define STM32_TIM4_IS_USED
#define GD32_TIM4_IS_USED
#endif
#if defined(STM32_TIM4_SUPPRESS_ISR)
#define STM32_SYSTICK_SUPPRESS_ISR
#if defined(GD32_TIM4_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define STM32_ST_TIM STM32_TIM4
#define ST_LLD_NUM_ALARMS STM32_TIM4_CHANNELS
#define STM32_ST_USE_SYSTICK FALSE
#define STM32_ST_USE_TIM2 FALSE
#define STM32_ST_USE_TIM3 FALSE
#define STM32_ST_USE_TIM4 TRUE
#define STM32_ST_USE_TIM5 FALSE
#define STM32_ST_USE_TIM9 FALSE
#define STM32_ST_USE_TIM10 FALSE
#define STM32_ST_USE_TIM11 FALSE
#define STM32_ST_USE_TIM12 FALSE
#define STM32_ST_USE_TIM13 FALSE
#define STM32_ST_USE_TIM14 FALSE
#define STM32_ST_USE_TIM21 FALSE
#define STM32_ST_USE_TIM22 FALSE
#define GD32_ST_TIM GD32_TIM4
#define ST_LLD_NUM_ALARMS GD32_TIM4_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 TRUE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif STM32_ST_USE_TIMER == 5
#elif GD32_ST_USE_TIMER == 5
#if defined(STM32_TIM5_IS_USED)
#if defined(GD32_TIM5_IS_USED)
#error "ST requires TIM5 but the timer is already used"
#else
#define STM32_TIM5_IS_USED
#define GD32_TIM5_IS_USED
#endif
#if defined(STM32_TIM5_SUPPRESS_ISR)
#define STM32_SYSTICK_SUPPRESS_ISR
#if defined(GD32_TIM5_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define STM32_ST_TIM STM32_TIM5
#define ST_LLD_NUM_ALARMS STM32_TIM5_CHANNELS
#define STM32_ST_USE_SYSTICK FALSE
#define STM32_ST_USE_TIM2 FALSE
#define STM32_ST_USE_TIM3 FALSE
#define STM32_ST_USE_TIM4 FALSE
#define STM32_ST_USE_TIM5 TRUE
#define STM32_ST_USE_TIM9 FALSE
#define STM32_ST_USE_TIM10 FALSE
#define STM32_ST_USE_TIM11 FALSE
#define STM32_ST_USE_TIM12 FALSE
#define STM32_ST_USE_TIM13 FALSE
#define STM32_ST_USE_TIM14 FALSE
#define STM32_ST_USE_TIM21 FALSE
#define STM32_ST_USE_TIM22 FALSE
#define GD32_ST_TIM GD32_TIM5
#define ST_LLD_NUM_ALARMS GD32_TIM5_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 TRUE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif STM32_ST_USE_TIMER == 9
#elif GD32_ST_USE_TIMER == 9
#if defined(STM32_TIM9_IS_USED)
#if defined(GD32_TIM9_IS_USED)
#error "ST requires TIM9 but the timer is already used"
#else
#define STM32_TIM9_IS_USED
#define GD32_TIM9_IS_USED
#endif
#if defined(STM32_TIM9_SUPPRESS_ISR)
#define STM32_SYSTICK_SUPPRESS_ISR
#if defined(GD32_TIM9_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define STM32_ST_TIM STM32_TIM9
#define ST_LLD_NUM_ALARMS STM32_TIM9_CHANNELS
#define STM32_ST_USE_SYSTICK FALSE
#define STM32_ST_USE_TIM2 FALSE
#define STM32_ST_USE_TIM3 FALSE
#define STM32_ST_USE_TIM4 FALSE
#define STM32_ST_USE_TIM5 FALSE
#define STM32_ST_USE_TIM9 TRUE
#define STM32_ST_USE_TIM10 FALSE
#define STM32_ST_USE_TIM11 FALSE
#define STM32_ST_USE_TIM12 FALSE
#define STM32_ST_USE_TIM13 FALSE
#define STM32_ST_USE_TIM14 FALSE
#define STM32_ST_USE_TIM21 FALSE
#define STM32_ST_USE_TIM22 FALSE
#define GD32_ST_TIM GD32_TIM9
#define ST_LLD_NUM_ALARMS GD32_TIM9_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 TRUE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif STM32_ST_USE_TIMER == 10
#elif GD32_ST_USE_TIMER == 10
#if defined(STM32_TIM10_IS_USED)
#if defined(GD32_TIM10_IS_USED)
#error "ST requires TIM10 but the timer is already used"
#else
#define STM32_TIM10_IS_USED
#define GD32_TIM10_IS_USED
#endif
#if defined(STM32_TIM10_SUPPRESS_ISR)
#define STM32_SYSTICK_SUPPRESS_ISR
#if defined(GD32_TIM10_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define STM32_ST_TIM STM32_TIM10
#define ST_LLD_NUM_ALARMS STM32_TIM10_CHANNELS
#define STM32_ST_USE_SYSTICK FALSE
#define STM32_ST_USE_TIM2 FALSE
#define STM32_ST_USE_TIM3 FALSE
#define STM32_ST_USE_TIM4 FALSE
#define STM32_ST_USE_TIM5 FALSE
#define STM32_ST_USE_TIM9 FALSE
#define STM32_ST_USE_TIM10 TRUE
#define STM32_ST_USE_TIM11 FALSE
#define STM32_ST_USE_TIM12 FALSE
#define STM32_ST_USE_TIM13 FALSE
#define STM32_ST_USE_TIM14 FALSE
#define STM32_ST_USE_TIM21 FALSE
#define STM32_ST_USE_TIM22 FALSE
#define GD32_ST_TIM GD32_TIM10
#define ST_LLD_NUM_ALARMS GD32_TIM10_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 TRUE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif STM32_ST_USE_TIMER == 11
#elif GD32_ST_USE_TIMER == 11
#if defined(STM32_TIM11_IS_USED)
#if defined(GD32_TIM11_IS_USED)
#error "ST requires TIM11 but the timer is already used"
#else
#define STM32_TIM11_IS_USED
#define GD32_TIM11_IS_USED
#endif
#if defined(STM32_TIM11_SUPPRESS_ISR)
#define STM32_SYSTICK_SUPPRESS_ISR
#if defined(GD32_TIM11_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define STM32_ST_TIM STM32_TIM11
#define ST_LLD_NUM_ALARMS STM32_TIM11_CHANNELS
#define STM32_ST_USE_SYSTICK FALSE
#define STM32_ST_USE_TIM2 FALSE
#define STM32_ST_USE_TIM3 FALSE
#define STM32_ST_USE_TIM4 FALSE
#define STM32_ST_USE_TIM5 FALSE
#define STM32_ST_USE_TIM9 FALSE
#define STM32_ST_USE_TIM10 FALSE
#define STM32_ST_USE_TIM11 TRUE
#define STM32_ST_USE_TIM12 FALSE
#define STM32_ST_USE_TIM13 FALSE
#define STM32_ST_USE_TIM14 FALSE
#define STM32_ST_USE_TIM21 FALSE
#define STM32_ST_USE_TIM22 FALSE
#define GD32_ST_TIM GD32_TIM11
#define ST_LLD_NUM_ALARMS GD32_TIM11_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 TRUE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif STM32_ST_USE_TIMER == 12
#elif GD32_ST_USE_TIMER == 12
#if defined(STM32_TIM12_IS_USED)
#if defined(GD32_TIM12_IS_USED)
#error "ST requires TIM12 but the timer is already used"
#else
#define STM32_TIM12_IS_USED
#define GD32_TIM12_IS_USED
#endif
#if defined(STM32_TIM12_SUPPRESS_ISR)
#define STM32_SYSTICK_SUPPRESS_ISR
#if defined(GD32_TIM12_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define STM32_ST_TIM STM32_TIM12
#define ST_LLD_NUM_ALARMS STM32_TIM12_CHANNELS
#define STM32_ST_USE_SYSTICK FALSE
#define STM32_ST_USE_TIM2 FALSE
#define STM32_ST_USE_TIM3 FALSE
#define STM32_ST_USE_TIM4 FALSE
#define STM32_ST_USE_TIM5 FALSE
#define STM32_ST_USE_TIM9 FALSE
#define STM32_ST_USE_TIM10 FALSE
#define STM32_ST_USE_TIM11 FALSE
#define STM32_ST_USE_TIM12 TRUE
#define STM32_ST_USE_TIM13 FALSE
#define STM32_ST_USE_TIM14 FALSE
#define STM32_ST_USE_TIM21 FALSE
#define STM32_ST_USE_TIM22 FALSE
#define GD32_ST_TIM GD32_TIM12
#define ST_LLD_NUM_ALARMS GD32_TIM12_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 TRUE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif STM32_ST_USE_TIMER == 13
#elif GD32_ST_USE_TIMER == 13
#if defined(STM32_TIM13_IS_USED)
#if defined(GD32_TIM13_IS_USED)
#error "ST requires TIM13 but the timer is already used"
#else
#define STM32_TIM13_IS_USED
#define GD32_TIM13_IS_USED
#endif
#if defined(STM32_TIM13_SUPPRESS_ISR)
#define STM32_SYSTICK_SUPPRESS_ISR
#if defined(GD32_TIM13_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define STM32_ST_TIM STM32_TIM13
#define ST_LLD_NUM_ALARMS STM32_TIM13_CHANNELS
#define STM32_ST_USE_SYSTICK FALSE
#define STM32_ST_USE_TIM2 FALSE
#define STM32_ST_USE_TIM3 FALSE
#define STM32_ST_USE_TIM4 FALSE
#define STM32_ST_USE_TIM5 FALSE
#define STM32_ST_USE_TIM9 FALSE
#define STM32_ST_USE_TIM10 FALSE
#define STM32_ST_USE_TIM11 FALSE
#define STM32_ST_USE_TIM12 FALSE
#define STM32_ST_USE_TIM13 TRUE
#define STM32_ST_USE_TIM14 FALSE
#define STM32_ST_USE_TIM21 FALSE
#define STM32_ST_USE_TIM22 FALSE
#define GD32_ST_TIM GD32_TIM13
#define ST_LLD_NUM_ALARMS GD32_TIM13_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 TRUE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif STM32_ST_USE_TIMER == 14
#elif GD32_ST_USE_TIMER == 14
#if defined(STM32_TIM14_IS_USED)
#if defined(GD32_TIM14_IS_USED)
#error "ST requires TIM14 but the timer is already used"
#else
#define STM32_TIM14_IS_USED
#define GD32_TIM14_IS_USED
#endif
#if defined(STM32_TIM14_SUPPRESS_ISR)
#define STM32_SYSTICK_SUPPRESS_ISR
#if defined(GD32_TIM14_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define STM32_ST_TIM STM32_TIM14
#define ST_LLD_NUM_ALARMS STM32_TIM14_CHANNELS
#define STM32_ST_USE_SYSTICK FALSE
#define STM32_ST_USE_TIM2 FALSE
#define STM32_ST_USE_TIM3 FALSE
#define STM32_ST_USE_TIM4 FALSE
#define STM32_ST_USE_TIM5 FALSE
#define STM32_ST_USE_TIM9 FALSE
#define STM32_ST_USE_TIM10 FALSE
#define STM32_ST_USE_TIM11 FALSE
#define STM32_ST_USE_TIM12 FALSE
#define STM32_ST_USE_TIM13 FALSE
#define STM32_ST_USE_TIM14 TRUE
#define STM32_ST_USE_TIM21 FALSE
#define STM32_ST_USE_TIM22 FALSE
#define GD32_ST_TIM GD32_TIM14
#define ST_LLD_NUM_ALARMS GD32_TIM14_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 TRUE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif STM32_ST_USE_TIMER == 21
#elif GD32_ST_USE_TIMER == 21
#if defined(STM32_TIM21_IS_USED)
#if defined(GD32_TIM21_IS_USED)
#error "ST requires TIM21 but the timer is already used"
#else
#define STM32_TIM21_IS_USED
#define GD32_TIM21_IS_USED
#endif
#if defined(STM32_TIM21_SUPPRESS_ISR)
#define STM32_SYSTICK_SUPPRESS_ISR
#if defined(GD32_TIM21_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define STM32_ST_TIM STM32_TIM21
#define ST_LLD_NUM_ALARMS STM32_TIM21_CHANNELS
#define STM32_ST_USE_SYSTICK FALSE
#define STM32_ST_USE_TIM2 FALSE
#define STM32_ST_USE_TIM3 FALSE
#define STM32_ST_USE_TIM4 FALSE
#define STM32_ST_USE_TIM5 FALSE
#define STM32_ST_USE_TIM9 FALSE
#define STM32_ST_USE_TIM10 FALSE
#define STM32_ST_USE_TIM11 FALSE
#define STM32_ST_USE_TIM12 FALSE
#define STM32_ST_USE_TIM13 FALSE
#define STM32_ST_USE_TIM14 FALSE
#define STM32_ST_USE_TIM21 TRUE
#define STM32_ST_USE_TIM22 FALSE
#define GD32_ST_TIM GD32_TIM21
#define ST_LLD_NUM_ALARMS GD32_TIM21_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 TRUE
#define GD32_ST_USE_TIM22 FALSE
#elif STM32_ST_USE_TIMER == 22
#elif GD32_ST_USE_TIMER == 22
#if defined(STM32_TIM22_IS_USED)
#if defined(GD32_TIM22_IS_USED)
#error "ST requires TIM22 but the timer is already used"
#else
#define STM32_TIM22_IS_USED
#define GD32_TIM22_IS_USED
#endif
#if defined(STM32_TIM22_SUPPRESS_ISR)
#define STM32_SYSTICK_SUPPRESS_ISR
#if defined(GD32_TIM22_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define STM32_ST_TIM STM32_TIM22
#define ST_LLD_NUM_ALARMS STM32_TIM22_CHANNELS
#define STM32_ST_USE_SYSTICK FALSE
#define STM32_ST_USE_TIM2 FALSE
#define STM32_ST_USE_TIM3 FALSE
#define STM32_ST_USE_TIM4 FALSE
#define STM32_ST_USE_TIM5 FALSE
#define STM32_ST_USE_TIM9 FALSE
#define STM32_ST_USE_TIM10 FALSE
#define STM32_ST_USE_TIM11 FALSE
#define STM32_ST_USE_TIM12 FALSE
#define STM32_ST_USE_TIM13 FALSE
#define STM32_ST_USE_TIM14 FALSE
#define STM32_ST_USE_TIM21 FALSE
#define STM32_ST_USE_TIM22 TRUE
#define GD32_ST_TIM GD32_TIM22
#define ST_LLD_NUM_ALARMS GD32_TIM22_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 TRUE
#else
#error "STM32_ST_USE_TIMER specifies an unsupported timer"
#error "GD32_ST_USE_TIMER specifies an unsupported timer"
#endif
#if defined(STM32_ST_ENFORCE_ALARMS)
#if defined(GD32_ST_ENFORCE_ALARMS)
#if (STM32_ST_ENFORCE_ALARMS < 1) || (STM32_ST_ENFORCE_ALARMS > ST_LLD_NUM_ALARMS)
#error "invalid STM32_ST_ENFORCE_ALARMS value"
#if (GD32_ST_ENFORCE_ALARMS < 1) || (GD32_ST_ENFORCE_ALARMS > ST_LLD_NUM_ALARMS)
#error "invalid GD32_ST_ENFORCE_ALARMS value"
#endif
#undef ST_LLD_NUM_ALARMS
#define ST_LLD_NUM_ALARMS STM32_ST_ENFORCE_ALARMS
#define ST_LLD_NUM_ALARMS GD32_ST_ENFORCE_ALARMS
#endif
#elif OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
#define STM32_ST_USE_SYSTICK TRUE
#define STM32_ST_USE_TIM2 FALSE
#define STM32_ST_USE_TIM3 FALSE
#define STM32_ST_USE_TIM4 FALSE
#define STM32_ST_USE_TIM5 FALSE
#define STM32_ST_USE_TIM9 FALSE
#define STM32_ST_USE_TIM10 FALSE
#define STM32_ST_USE_TIM11 FALSE
#define STM32_ST_USE_TIM12 FALSE
#define STM32_ST_USE_TIM13 FALSE
#define STM32_ST_USE_TIM14 FALSE
#define STM32_ST_USE_TIM21 FALSE
#define STM32_ST_USE_TIM22 FALSE
#define GD32_ST_USE_SYSTICK TRUE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#else
#define STM32_ST_USE_SYSTICK FALSE
#define STM32_ST_USE_TIM2 FALSE
#define STM32_ST_USE_TIM3 FALSE
#define STM32_ST_USE_TIM4 FALSE
#define STM32_ST_USE_TIM5 FALSE
#define STM32_ST_USE_TIM9 FALSE
#define STM32_ST_USE_TIM10 FALSE
#define STM32_ST_USE_TIM11 FALSE
#define STM32_ST_USE_TIM12 FALSE
#define STM32_ST_USE_TIM13 FALSE
#define STM32_ST_USE_TIM14 FALSE
#define STM32_ST_USE_TIM21 FALSE
#define STM32_ST_USE_TIM22 FALSE
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#endif
@ -538,7 +538,7 @@ extern "C" {
*/
static inline systime_t st_lld_get_counter(void) {
return (systime_t)STM32_ST_TIM->CNT;
return (systime_t)GD32_ST_TIM->CNT;
}
/**
@ -552,12 +552,12 @@ static inline systime_t st_lld_get_counter(void) {
*/
static inline void st_lld_start_alarm(systime_t abstime) {
STM32_ST_TIM->CCR[0] = (uint32_t)abstime;
STM32_ST_TIM->SR = 0;
GD32_ST_TIM->CCR[0] = (uint32_t)abstime;
GD32_ST_TIM->SR = 0;
#if ST_LLD_NUM_ALARMS == 1
STM32_ST_TIM->DIER = STM32_TIM_DIER_CC1IE;
GD32_ST_TIM->DIER = GD32_TIM_DIER_CC1IE;
#else
STM32_ST_TIM->DIER |= STM32_TIM_DIER_CC1IE;
GD32_ST_TIM->DIER |= GD32_TIM_DIER_CC1IE;
#endif
}
@ -569,9 +569,9 @@ static inline void st_lld_start_alarm(systime_t abstime) {
static inline void st_lld_stop_alarm(void) {
#if ST_LLD_NUM_ALARMS == 1
STM32_ST_TIM->DIER = 0U;
GD32_ST_TIM->DIER = 0U;
#else
STM32_ST_TIM->DIER &= ~STM32_TIM_DIER_CC1IE;
GD32_ST_TIM->DIER &= ~GD32_TIM_DIER_CC1IE;
#endif
}
@ -584,7 +584,7 @@ static inline void st_lld_stop_alarm(void) {
*/
static inline void st_lld_set_alarm(systime_t abstime) {
STM32_ST_TIM->CCR[0] = (uint32_t)abstime;
GD32_ST_TIM->CCR[0] = (uint32_t)abstime;
}
/**
@ -596,7 +596,7 @@ static inline void st_lld_set_alarm(systime_t abstime) {
*/
static inline systime_t st_lld_get_alarm(void) {
return (systime_t)STM32_ST_TIM->CCR[0];
return (systime_t)GD32_ST_TIM->CCR[0];
}
/**
@ -610,7 +610,7 @@ static inline systime_t st_lld_get_alarm(void) {
*/
static inline bool st_lld_is_alarm_active(void) {
return (bool)((STM32_ST_TIM->DIER & STM32_TIM_DIER_CC1IE) != 0);
return (bool)((GD32_ST_TIM->DIER & GD32_TIM_DIER_CC1IE) != 0);
}
#if (ST_LLD_NUM_ALARMS > 1) || defined(__DOXYGEN__)
@ -629,9 +629,9 @@ static inline bool st_lld_is_alarm_active(void) {
static inline void st_lld_start_alarm_n(unsigned alarm, systime_t abstime) {
STM32_ST_TIM->CCR[alarm] = (uint32_t)abstime;
STM32_ST_TIM->SR = 0;
STM32_ST_TIM->DIER |= (STM32_TIM_DIER_CC1IE << alarm);
GD32_ST_TIM->CCR[alarm] = (uint32_t)abstime;
GD32_ST_TIM->SR = 0;
GD32_ST_TIM->DIER |= (GD32_TIM_DIER_CC1IE << alarm);
}
/**
@ -645,7 +645,7 @@ static inline void st_lld_start_alarm_n(unsigned alarm, systime_t abstime) {
*/
static inline void st_lld_stop_alarm_n(unsigned alarm) {
STM32_ST_TIM->DIER &= ~(STM32_TIM_DIER_CC1IE << alarm);
GD32_ST_TIM->DIER &= ~(GD32_TIM_DIER_CC1IE << alarm);
}
/**
@ -660,7 +660,7 @@ static inline void st_lld_stop_alarm_n(unsigned alarm) {
*/
static inline void st_lld_set_alarm_n(unsigned alarm, systime_t abstime) {
STM32_ST_TIM->CCR[alarm] = (uint32_t)abstime;
GD32_ST_TIM->CCR[alarm] = (uint32_t)abstime;
}
/**
@ -675,7 +675,7 @@ static inline void st_lld_set_alarm_n(unsigned alarm, systime_t abstime) {
*/
static inline systime_t st_lld_get_alarm_n(unsigned alarm) {
return (systime_t)STM32_ST_TIM->CCR[alarm];
return (systime_t)GD32_ST_TIM->CCR[alarm];
}
/**
@ -690,7 +690,7 @@ static inline systime_t st_lld_get_alarm_n(unsigned alarm) {
*/
static inline bool st_lld_is_alarm_active_n(unsigned alarm) {
return (bool)((STM32_ST_TIM->DIER & (STM32_TIM_DIER_CC1IE << alarm)) != 0);
return (bool)((GD32_ST_TIM->DIER & (GD32_TIM_DIER_CC1IE << alarm)) != 0);
}
#endif /* ST_LLD_NUM_ALARMS > 1 */

518
os/hal/ports/GD/GD32VF103/TIM/stm32_tim.h
View File

@ -19,12 +19,12 @@
* @brief STM32 TIM units common header.
* @note This file requires definitions from the ST STM32 header file.
*
* @addtogroup STM32_TIM
* @addtogroup GD32_TIM
* @{
*/
#ifndef STM32_TIM_H
#define STM32_TIM_H
#ifndef GD32_TIM_H
#define GD32_TIM_H
/*===========================================================================*/
/* Driver constants. */
@ -34,102 +34,102 @@
* @name TIM_CR1 register
* @{
*/
#define STM32_TIM_CR1_CEN (1U << 0)
#define STM32_TIM_CR1_UDIS (1U << 1)
#define STM32_TIM_CR1_URS (1U << 2)
#define STM32_TIM_CR1_OPM (1U << 3)
#define STM32_TIM_CR1_DIR (1U << 4)
#define GD32_TIM_CR1_CEN (1U << 0)
#define GD32_TIM_CR1_UDIS (1U << 1)
#define GD32_TIM_CR1_URS (1U << 2)
#define GD32_TIM_CR1_OPM (1U << 3)
#define GD32_TIM_CR1_DIR (1U << 4)
#define STM32_TIM_CR1_CMS_MASK (3U << 5)
#define STM32_TIM_CR1_CMS(n) ((n) << 5)
#define GD32_TIM_CR1_CMS_MASK (3U << 5)
#define GD32_TIM_CR1_CMS(n) ((n) << 5)
#define STM32_TIM_CR1_ARPE (1U << 7)
#define GD32_TIM_CR1_ARPE (1U << 7)
#define STM32_TIM_CR1_CKD_MASK (3U << 8)
#define STM32_TIM_CR1_CKD(n) ((n) << 8)
#define GD32_TIM_CR1_CKD_MASK (3U << 8)
#define GD32_TIM_CR1_CKD(n) ((n) << 8)
#define STM32_TIM_CR1_UIFREMAP (1U << 11)
#define GD32_TIM_CR1_UIFREMAP (1U << 11)
/** @} */
/**
* @name TIM_CR2 register
* @{
*/
#define STM32_TIM_CR2_CCPC (1U << 0)
#define STM32_TIM_CR2_CCUS (1U << 2)
#define STM32_TIM_CR2_CCDS (1U << 3)
#define GD32_TIM_CR2_CCPC (1U << 0)
#define GD32_TIM_CR2_CCUS (1U << 2)
#define GD32_TIM_CR2_CCDS (1U << 3)
#define STM32_TIM_CR2_MMS_MASK (7U << 4)
#define STM32_TIM_CR2_MMS(n) ((n) << 4)
#define GD32_TIM_CR2_MMS_MASK (7U << 4)
#define GD32_TIM_CR2_MMS(n) ((n) << 4)
#define STM32_TIM_CR2_TI1S (1U << 7)
#define STM32_TIM_CR2_OIS1 (1U << 8)
#define STM32_TIM_CR2_OIS1N (1U << 9)
#define STM32_TIM_CR2_OIS2 (1U << 10)
#define STM32_TIM_CR2_OIS2N (1U << 11)
#define STM32_TIM_CR2_OIS3 (1U << 12)
#define STM32_TIM_CR2_OIS3N (1U << 13)
#define STM32_TIM_CR2_OIS4 (1U << 14)
#define STM32_TIM_CR2_OIS5 (1U << 16)
#define STM32_TIM_CR2_OIS6 (1U << 18)
#define GD32_TIM_CR2_TI1S (1U << 7)
#define GD32_TIM_CR2_OIS1 (1U << 8)
#define GD32_TIM_CR2_OIS1N (1U << 9)
#define GD32_TIM_CR2_OIS2 (1U << 10)
#define GD32_TIM_CR2_OIS2N (1U << 11)
#define GD32_TIM_CR2_OIS3 (1U << 12)
#define GD32_TIM_CR2_OIS3N (1U << 13)
#define GD32_TIM_CR2_OIS4 (1U << 14)
#define GD32_TIM_CR2_OIS5 (1U << 16)
#define GD32_TIM_CR2_OIS6 (1U << 18)
#define STM32_TIM_CR2_MMS2_MASK (15U << 20)
#define STM32_TIM_CR2_MMS2(n) ((n) << 20)
#define GD32_TIM_CR2_MMS2_MASK (15U << 20)
#define GD32_TIM_CR2_MMS2(n) ((n) << 20)
/** @} */
/**
* @name TIM_SMCR register
* @{
*/
#define STM32_TIM_SMCR_SMS_MASK ((7U << 0) | (1U << 16))
#define STM32_TIM_SMCR_SMS(n) ((((n) & 7) << 0) | \
#define GD32_TIM_SMCR_SMS_MASK ((7U << 0) | (1U << 16))
#define GD32_TIM_SMCR_SMS(n) ((((n) & 7) << 0) | \
(((n) >> 3) << 16))
#define STM32_TIM_SMCR_OCCS (1U << 3)
#define GD32_TIM_SMCR_OCCS (1U << 3)
#define STM32_TIM_SMCR_TS_MASK (7U << 4)
#define STM32_TIM_SMCR_TS(n) ((n) << 4)
#define GD32_TIM_SMCR_TS_MASK (7U << 4)
#define GD32_TIM_SMCR_TS(n) ((n) << 4)
#define STM32_TIM_SMCR_MSM (1U << 7)
#define GD32_TIM_SMCR_MSM (1U << 7)
#define STM32_TIM_SMCR_ETF_MASK (15U << 8)
#define STM32_TIM_SMCR_ETF(n) ((n) << 8)
#define GD32_TIM_SMCR_ETF_MASK (15U << 8)
#define GD32_TIM_SMCR_ETF(n) ((n) << 8)
#define STM32_TIM_SMCR_ETPS_MASK (3U << 12)
#define STM32_TIM_SMCR_ETPS(n) ((n) << 12)
#define GD32_TIM_SMCR_ETPS_MASK (3U << 12)
#define GD32_TIM_SMCR_ETPS(n) ((n) << 12)
#define STM32_TIM_SMCR_ECE (1U << 14)
#define STM32_TIM_SMCR_ETP (1U << 15)
#define GD32_TIM_SMCR_ECE (1U << 14)
#define GD32_TIM_SMCR_ETP (1U << 15)
/** @} */
/**
* @name TIM_DIER register
* @{
*/
#define STM32_TIM_DIER_UIE (1U << 0)
#define STM32_TIM_DIER_CC1IE (1U << 1)
#define STM32_TIM_DIER_CC2IE (1U << 2)
#define STM32_TIM_DIER_CC3IE (1U << 3)
#define STM32_TIM_DIER_CC4IE (1U << 4)
#define STM32_TIM_DIER_COMIE (1U << 5)
#define STM32_TIM_DIER_TIE (1U << 6)
#define STM32_TIM_DIER_BIE (1U << 7)
#define STM32_TIM_DIER_UDE (1U << 8)
#define STM32_TIM_DIER_CC1DE (1U << 9)
#define STM32_TIM_DIER_CC2DE (1U << 10)
#define STM32_TIM_DIER_CC3DE (1U << 11)
#define STM32_TIM_DIER_CC4DE (1U << 12)
#define STM32_TIM_DIER_COMDE (1U << 13)
#define STM32_TIM_DIER_TDE (1U << 14)
#define GD32_TIM_DIER_UIE (1U << 0)
#define GD32_TIM_DIER_CC1IE (1U << 1)
#define GD32_TIM_DIER_CC2IE (1U << 2)
#define GD32_TIM_DIER_CC3IE (1U << 3)
#define GD32_TIM_DIER_CC4IE (1U << 4)
#define GD32_TIM_DIER_COMIE (1U << 5)
#define GD32_TIM_DIER_TIE (1U << 6)
#define GD32_TIM_DIER_BIE (1U << 7)
#define GD32_TIM_DIER_UDE (1U << 8)
#define GD32_TIM_DIER_CC1DE (1U << 9)
#define GD32_TIM_DIER_CC2DE (1U << 10)
#define GD32_TIM_DIER_CC3DE (1U << 11)
#define GD32_TIM_DIER_CC4DE (1U << 12)
#define GD32_TIM_DIER_COMDE (1U << 13)
#define GD32_TIM_DIER_TDE (1U << 14)
#define STM32_TIM_DIER_IRQ_MASK (STM32_TIM_DIER_UIE | \
STM32_TIM_DIER_CC1IE | \
STM32_TIM_DIER_CC2IE | \
STM32_TIM_DIER_CC3IE | \
STM32_TIM_DIER_CC4IE | \
STM32_TIM_DIER_COMIE | \
STM32_TIM_DIER_TIE | \
STM32_TIM_DIER_BIE)
#define GD32_TIM_DIER_IRQ_MASK (GD32_TIM_DIER_UIE | \
GD32_TIM_DIER_CC1IE | \
GD32_TIM_DIER_CC2IE | \
GD32_TIM_DIER_CC3IE | \
GD32_TIM_DIER_CC4IE | \
GD32_TIM_DIER_COMIE | \
GD32_TIM_DIER_TIE | \
GD32_TIM_DIER_BIE)
/** @} */
@ -137,349 +137,349 @@
* @name TIM_SR register
* @{
*/
#define STM32_TIM_SR_UIF (1U << 0)
#define STM32_TIM_SR_CC1IF (1U << 1)
#define STM32_TIM_SR_CC2IF (1U << 2)
#define STM32_TIM_SR_CC3IF (1U << 3)
#define STM32_TIM_SR_CC4IF (1U << 4)
#define STM32_TIM_SR_COMIF (1U << 5)
#define STM32_TIM_SR_TIF (1U << 6)
#define STM32_TIM_SR_BIF (1U << 7)
#define STM32_TIM_SR_B2IF (1U << 8)
#define STM32_TIM_SR_CC1OF (1U << 9)
#define STM32_TIM_SR_CC2OF (1U << 10)
#define STM32_TIM_SR_CC3OF (1U << 11)
#define STM32_TIM_SR_CC4OF (1U << 12)
#define STM32_TIM_SR_CC5IF (1U << 16)
#define STM32_TIM_SR_CC6IF (1U << 17)
#define GD32_TIM_SR_UIF (1U << 0)
#define GD32_TIM_SR_CC1IF (1U << 1)
#define GD32_TIM_SR_CC2IF (1U << 2)
#define GD32_TIM_SR_CC3IF (1U << 3)
#define GD32_TIM_SR_CC4IF (1U << 4)
#define GD32_TIM_SR_COMIF (1U << 5)
#define GD32_TIM_SR_TIF (1U << 6)
#define GD32_TIM_SR_BIF (1U << 7)
#define GD32_TIM_SR_B2IF (1U << 8)
#define GD32_TIM_SR_CC1OF (1U << 9)
#define GD32_TIM_SR_CC2OF (1U << 10)
#define GD32_TIM_SR_CC3OF (1U << 11)
#define GD32_TIM_SR_CC4OF (1U << 12)
#define GD32_TIM_SR_CC5IF (1U << 16)
#define GD32_TIM_SR_CC6IF (1U << 17)
/** @} */
/**
* @name TIM_EGR register
* @{
*/
#define STM32_TIM_EGR_UG (1U << 0)
#define STM32_TIM_EGR_CC1G (1U << 1)
#define STM32_TIM_EGR_CC2G (1U << 2)
#define STM32_TIM_EGR_CC3G (1U << 3)
#define STM32_TIM_EGR_CC4G (1U << 4)
#define STM32_TIM_EGR_COMG (1U << 5)
#define STM32_TIM_EGR_TG (1U << 6)
#define STM32_TIM_EGR_BG (1U << 7)
#define STM32_TIM_EGR_B2G (1U << 8)
#define GD32_TIM_EGR_UG (1U << 0)
#define GD32_TIM_EGR_CC1G (1U << 1)
#define GD32_TIM_EGR_CC2G (1U << 2)
#define GD32_TIM_EGR_CC3G (1U << 3)
#define GD32_TIM_EGR_CC4G (1U << 4)
#define GD32_TIM_EGR_COMG (1U << 5)
#define GD32_TIM_EGR_TG (1U << 6)
#define GD32_TIM_EGR_BG (1U << 7)
#define GD32_TIM_EGR_B2G (1U << 8)
/** @} */
/**
* @name TIM_CCMR1 register (output)
* @{
*/
#define STM32_TIM_CCMR1_CC1S_MASK (3U << 0)
#define STM32_TIM_CCMR1_CC1S(n) ((n) << 0)
#define GD32_TIM_CCMR1_CC1S_MASK (3U << 0)
#define GD32_TIM_CCMR1_CC1S(n) ((n) << 0)
#define STM32_TIM_CCMR1_OC1FE (1U << 2)
#define STM32_TIM_CCMR1_OC1PE (1U << 3)
#define GD32_TIM_CCMR1_OC1FE (1U << 2)
#define GD32_TIM_CCMR1_OC1PE (1U << 3)
#define STM32_TIM_CCMR1_OC1M_MASK ((7U << 4) | (1U << 16))
#define STM32_TIM_CCMR1_OC1M(n) ((((n) & 7) << 4) | \
#define GD32_TIM_CCMR1_OC1M_MASK ((7U << 4) | (1U << 16))
#define GD32_TIM_CCMR1_OC1M(n) ((((n) & 7) << 4) | \
(((n) >> 3) << 16))
#define STM32_TIM_CCMR1_OC1CE (1U << 7)
#define GD32_TIM_CCMR1_OC1CE (1U << 7)
#define STM32_TIM_CCMR1_CC2S_MASK (3U << 8)
#define STM32_TIM_CCMR1_CC2S(n) ((n) << 8)
#define GD32_TIM_CCMR1_CC2S_MASK (3U << 8)
#define GD32_TIM_CCMR1_CC2S(n) ((n) << 8)
#define STM32_TIM_CCMR1_OC2FE (1U << 10)
#define STM32_TIM_CCMR1_OC2PE (1U << 11)
#define GD32_TIM_CCMR1_OC2FE (1U << 10)
#define GD32_TIM_CCMR1_OC2PE (1U << 11)
#define STM32_TIM_CCMR1_OC2M_MASK ((7U << 12) | (1U << 24))
#define STM32_TIM_CCMR1_OC2M(n) ((((n) & 7) << 12) | \
#define GD32_TIM_CCMR1_OC2M_MASK ((7U << 12) | (1U << 24))
#define GD32_TIM_CCMR1_OC2M(n) ((((n) & 7) << 12) | \
(((n) >> 3) << 24))
#define STM32_TIM_CCMR1_OC2CE (1U << 15)
#define GD32_TIM_CCMR1_OC2CE (1U << 15)
/** @} */
/**
* @name CCMR1 register (input)
* @{
*/
#define STM32_TIM_CCMR1_IC1PSC_MASK (3U << 2)
#define STM32_TIM_CCMR1_IC1PSC(n) ((n) << 2)
#define GD32_TIM_CCMR1_IC1PSC_MASK (3U << 2)
#define GD32_TIM_CCMR1_IC1PSC(n) ((n) << 2)
#define STM32_TIM_CCMR1_IC1F_MASK (15U << 4)
#define STM32_TIM_CCMR1_IC1F(n) ((n) << 4)
#define GD32_TIM_CCMR1_IC1F_MASK (15U << 4)
#define GD32_TIM_CCMR1_IC1F(n) ((n) << 4)
#define STM32_TIM_CCMR1_IC2PSC_MASK (3U << 10)
#define STM32_TIM_CCMR1_IC2PSC(n) ((n) << 10)
#define GD32_TIM_CCMR1_IC2PSC_MASK (3U << 10)
#define GD32_TIM_CCMR1_IC2PSC(n) ((n) << 10)
#define STM32_TIM_CCMR1_IC2F_MASK (15U << 12)
#define STM32_TIM_CCMR1_IC2F(n) ((n) << 12)
#define GD32_TIM_CCMR1_IC2F_MASK (15U << 12)
#define GD32_TIM_CCMR1_IC2F(n) ((n) << 12)
/** @} */
/**
* @name TIM_CCMR2 register (output)
* @{
*/
#define STM32_TIM_CCMR2_CC3S_MASK (3U << 0)
#define STM32_TIM_CCMR2_CC3S(n) ((n) << 0)
#define GD32_TIM_CCMR2_CC3S_MASK (3U << 0)
#define GD32_TIM_CCMR2_CC3S(n) ((n) << 0)
#define STM32_TIM_CCMR2_OC3FE (1U << 2)
#define STM32_TIM_CCMR2_OC3PE (1U << 3)
#define GD32_TIM_CCMR2_OC3FE (1U << 2)
#define GD32_TIM_CCMR2_OC3PE (1U << 3)
#define STM32_TIM_CCMR2_OC3M_MASK ((7U << 4) | (1U << 16))
#define STM32_TIM_CCMR2_OC3M(n) ((((n) & 7) << 4) | \
#define GD32_TIM_CCMR2_OC3M_MASK ((7U << 4) | (1U << 16))
#define GD32_TIM_CCMR2_OC3M(n) ((((n) & 7) << 4) | \
(((n) >> 3) << 16))
#define STM32_TIM_CCMR2_OC3CE (1U << 7)
#define GD32_TIM_CCMR2_OC3CE (1U << 7)
#define STM32_TIM_CCMR2_CC4S_MASK (3U << 8)
#define STM32_TIM_CCMR2_CC4S(n) ((n) << 8)
#define GD32_TIM_CCMR2_CC4S_MASK (3U << 8)
#define GD32_TIM_CCMR2_CC4S(n) ((n) << 8)
#define STM32_TIM_CCMR2_OC4FE (1U << 10)
#define STM32_TIM_CCMR2_OC4PE (1U << 11)
#define GD32_TIM_CCMR2_OC4FE (1U << 10)
#define GD32_TIM_CCMR2_OC4PE (1U << 11)
#define STM32_TIM_CCMR2_OC4M_MASK ((7U << 12) | (1U << 24))
#define STM32_TIM_CCMR2_OC4M(n) ((((n) & 7) << 12) | \
#define GD32_TIM_CCMR2_OC4M_MASK ((7U << 12) | (1U << 24))
#define GD32_TIM_CCMR2_OC4M(n) ((((n) & 7) << 12) | \
(((n) >> 3) << 24))
#define STM32_TIM_CCMR2_OC4CE (1U << 15)
#define GD32_TIM_CCMR2_OC4CE (1U << 15)
/** @} */
/**
* @name TIM_CCMR2 register (input)
* @{
*/
#define STM32_TIM_CCMR2_IC3PSC_MASK (3U << 2)
#define STM32_TIM_CCMR2_IC3PSC(n) ((n) << 2)
#define GD32_TIM_CCMR2_IC3PSC_MASK (3U << 2)
#define GD32_TIM_CCMR2_IC3PSC(n) ((n) << 2)
#define STM32_TIM_CCMR2_IC3F_MASK (15U << 4)
#define STM32_TIM_CCMR2_IC3F(n) ((n) << 4)
#define GD32_TIM_CCMR2_IC3F_MASK (15U << 4)
#define GD32_TIM_CCMR2_IC3F(n) ((n) << 4)
#define STM32_TIM_CCMR2_IC4PSC_MASK (3U << 10)
#define STM32_TIM_CCMR2_IC4PSC(n) ((n) << 10)
#define GD32_TIM_CCMR2_IC4PSC_MASK (3U << 10)
#define GD32_TIM_CCMR2_IC4PSC(n) ((n) << 10)
#define STM32_TIM_CCMR2_IC4F_MASK (15U << 12)
#define STM32_TIM_CCMR2_IC4F(n) ((n) << 12)
#define GD32_TIM_CCMR2_IC4F_MASK (15U << 12)
#define GD32_TIM_CCMR2_IC4F(n) ((n) << 12)
/** @} */
/**
* @name TIM_CCER register
* @{
*/
#define STM32_TIM_CCER_CC1E (1U << 0)
#define STM32_TIM_CCER_CC1P (1U << 1)
#define STM32_TIM_CCER_CC1NE (1U << 2)
#define STM32_TIM_CCER_CC1NP (1U << 3)
#define STM32_TIM_CCER_CC2E (1U << 4)
#define STM32_TIM_CCER_CC2P (1U << 5)
#define STM32_TIM_CCER_CC2NE (1U << 6)
#define STM32_TIM_CCER_CC2NP (1U << 7)
#define STM32_TIM_CCER_CC3E (1U << 8)
#define STM32_TIM_CCER_CC3P (1U << 9)
#define STM32_TIM_CCER_CC3NE (1U << 10)
#define STM32_TIM_CCER_CC3NP (1U << 11)
#define STM32_TIM_CCER_CC4E (1U << 12)
#define STM32_TIM_CCER_CC4P (1U << 13)
#define STM32_TIM_CCER_CC4NE (1U << 14)
#define STM32_TIM_CCER_CC4NP (1U << 15)
#define STM32_TIM_CCER_CC5E (1U << 16)
#define STM32_TIM_CCER_CC5P (1U << 17)
#define STM32_TIM_CCER_CC6E (1U << 20)
#define STM32_TIM_CCER_CC6P (1U << 21)
#define GD32_TIM_CCER_CC1E (1U << 0)
#define GD32_TIM_CCER_CC1P (1U << 1)
#define GD32_TIM_CCER_CC1NE (1U << 2)
#define GD32_TIM_CCER_CC1NP (1U << 3)
#define GD32_TIM_CCER_CC2E (1U << 4)
#define GD32_TIM_CCER_CC2P (1U << 5)
#define GD32_TIM_CCER_CC2NE (1U << 6)
#define GD32_TIM_CCER_CC2NP (1U << 7)
#define GD32_TIM_CCER_CC3E (1U << 8)
#define GD32_TIM_CCER_CC3P (1U << 9)
#define GD32_TIM_CCER_CC3NE (1U << 10)
#define GD32_TIM_CCER_CC3NP (1U << 11)
#define GD32_TIM_CCER_CC4E (1U << 12)
#define GD32_TIM_CCER_CC4P (1U << 13)
#define GD32_TIM_CCER_CC4NE (1U << 14)
#define GD32_TIM_CCER_CC4NP (1U << 15)
#define GD32_TIM_CCER_CC5E (1U << 16)
#define GD32_TIM_CCER_CC5P (1U << 17)
#define GD32_TIM_CCER_CC6E (1U << 20)
#define GD32_TIM_CCER_CC6P (1U << 21)
/** @} */
/**
* @name TIM_CNT register
* @{
*/
#define STM32_TIM_CNT_UIFCPY (1U << 31)
#define GD32_TIM_CNT_UIFCPY (1U << 31)
/** @} */
/**
* @name TIM_BDTR register
* @{
*/
#define STM32_TIM_BDTR_DTG_MASK (255U << 0)
#define STM32_TIM_BDTR_DTG(n) ((n) << 0)
#define GD32_TIM_BDTR_DTG_MASK (255U << 0)
#define GD32_TIM_BDTR_DTG(n) ((n) << 0)
#define STM32_TIM_BDTR_LOCK_MASK (3U << 8)
#define STM32_TIM_BDTR_LOCK(n) ((n) << 8)
#define GD32_TIM_BDTR_LOCK_MASK (3U << 8)
#define GD32_TIM_BDTR_LOCK(n) ((n) << 8)
#define STM32_TIM_BDTR_OSSI (1U << 10)
#define STM32_TIM_BDTR_OSSR (1U << 11)
#define STM32_TIM_BDTR_BKE (1U << 12)
#define STM32_TIM_BDTR_BKP (1U << 13)
#define STM32_TIM_BDTR_AOE (1U << 14)
#define STM32_TIM_BDTR_MOE (1U << 15)
#define GD32_TIM_BDTR_OSSI (1U << 10)
#define GD32_TIM_BDTR_OSSR (1U << 11)
#define GD32_TIM_BDTR_BKE (1U << 12)
#define GD32_TIM_BDTR_BKP (1U << 13)
#define GD32_TIM_BDTR_AOE (1U << 14)
#define GD32_TIM_BDTR_MOE (1U << 15)
#define STM32_TIM_BDTR_BKF_MASK (15U << 16)
#define STM32_TIM_BDTR_BKF(n) ((n) << 16)
#define STM32_TIM_BDTR_BK2F_MASK (15U << 20)
#define STM32_TIM_BDTR_BK2F(n) ((n) << 20)
#define GD32_TIM_BDTR_BKF_MASK (15U << 16)
#define GD32_TIM_BDTR_BKF(n) ((n) << 16)
#define GD32_TIM_BDTR_BK2F_MASK (15U << 20)
#define GD32_TIM_BDTR_BK2F(n) ((n) << 20)
#define STM32_TIM_BDTR_BK2E (1U << 24)
#define STM32_TIM_BDTR_BK2P (1U << 25)
#define GD32_TIM_BDTR_BK2E (1U << 24)
#define GD32_TIM_BDTR_BK2P (1U << 25)
/** @} */
/**
* @name TIM_DCR register
* @{
*/
#define STM32_TIM_DCR_DBA_MASK (31U << 0)
#define STM32_TIM_DCR_DBA(n) ((n) << 0)
#define GD32_TIM_DCR_DBA_MASK (31U << 0)
#define GD32_TIM_DCR_DBA(n) ((n) << 0)
#define STM32_TIM_DCR_DBL_MASK (31U << 8)
#define STM32_TIM_DCR_DBL(n) ((n) << 8)
#define GD32_TIM_DCR_DBL_MASK (31U << 8)
#define GD32_TIM_DCR_DBL(n) ((n) << 8)
/** @} */
/**
* @name TIM16_OR register
* @{
*/
#define STM32_TIM16_OR_TI1_RMP_MASK (3U << 6)
#define STM32_TIM16_OR_TI1_RMP(n) ((n) << 6)
#define GD32_TIM16_OR_TI1_RMP_MASK (3U << 6)
#define GD32_TIM16_OR_TI1_RMP(n) ((n) << 6)
/** @} */
/**
* @name TIM_OR register
* @{
*/
#define STM32_TIM_OR_ETR_RMP_MASK (15U << 0)
#define STM32_TIM_OR_ETR_RMP(n) ((n) << 0)
#define GD32_TIM_OR_ETR_RMP_MASK (15U << 0)
#define GD32_TIM_OR_ETR_RMP(n) ((n) << 0)
/** @} */
/**
* @name TIM_CCMR3 register
* @{
*/
#define STM32_TIM_CCMR3_OC5FE (1U << 2)
#define STM32_TIM_CCMR3_OC5PE (1U << 3)
#define GD32_TIM_CCMR3_OC5FE (1U << 2)
#define GD32_TIM_CCMR3_OC5PE (1U << 3)
#define STM32_TIM_CCMR3_OC5M_MASK ((7U << 4) | (1U << 16))
#define STM32_TIM_CCMR3_OC5M(n) ((((n) & 7) << 4) | \
#define GD32_TIM_CCMR3_OC5M_MASK ((7U << 4) | (1U << 16))
#define GD32_TIM_CCMR3_OC5M(n) ((((n) & 7) << 4) | \
(((n) >> 2) << 16))
#define STM32_TIM_CCMR3_OC5CE (1U << 7)
#define GD32_TIM_CCMR3_OC5CE (1U << 7)
#define STM32_TIM_CCMR3_OC6FE (1U << 10)
#define STM32_TIM_CCMR3_OC6PE (1U << 11)
#define GD32_TIM_CCMR3_OC6FE (1U << 10)
#define GD32_TIM_CCMR3_OC6PE (1U << 11)
#define STM32_TIM_CCMR3_OC6M_MASK ((7U << 12) | (1U << 24))
#define STM32_TIM_CCMR3_OC6M(n) ((((n) & 7) << 12) | \
#define GD32_TIM_CCMR3_OC6M_MASK ((7U << 12) | (1U << 24))
#define GD32_TIM_CCMR3_OC6M(n) ((((n) & 7) << 12) | \
(((n) >> 2) << 24))
#define STM32_TIM_CCMR3_OC6CE (1U << 15)
#define GD32_TIM_CCMR3_OC6CE (1U << 15)
/** @} */
/**
* @name LPTIM_ISR register
* @{
*/
#define STM32_LPTIM_ISR_CMPM (1U << 0)
#define STM32_LPTIM_ISR_ARRM (1U << 1)
#define STM32_LPTIM_ISR_EXTTRIG (1U << 2)
#define STM32_LPTIM_ISR_CMPOK (1U << 3)
#define STM32_LPTIM_ISR_ARROK (1U << 4)
#define STM32_LPTIM_ISR_UP (1U << 5)
#define STM32_LPTIM_ISR_DOWN (1U << 6)
#define GD32_LPTIM_ISR_CMPM (1U << 0)
#define GD32_LPTIM_ISR_ARRM (1U << 1)
#define GD32_LPTIM_ISR_EXTTRIG (1U << 2)
#define GD32_LPTIM_ISR_CMPOK (1U << 3)
#define GD32_LPTIM_ISR_ARROK (1U << 4)
#define GD32_LPTIM_ISR_UP (1U << 5)
#define GD32_LPTIM_ISR_DOWN (1U << 6)
/** @} */
/**
* @name LPTIM_ICR register
* @{
*/
#define STM32_LPTIM_ICR_CMPMCF (1U << 0)
#define STM32_LPTIM_ICR_ARRMCF (1U << 1)
#define STM32_LPTIM_ICR_EXTTRIGCF (1U << 2)
#define STM32_LPTIM_ICR_CMPOKCF (1U << 3)
#define STM32_LPTIM_ICR_ARROKCF (1U << 4)
#define STM32_LPTIM_ICR_UPCF (1U << 5)
#define STM32_LPTIM_ICR_DOWNCF (1U << 6)
#define GD32_LPTIM_ICR_CMPMCF (1U << 0)
#define GD32_LPTIM_ICR_ARRMCF (1U << 1)
#define GD32_LPTIM_ICR_EXTTRIGCF (1U << 2)
#define GD32_LPTIM_ICR_CMPOKCF (1U << 3)
#define GD32_LPTIM_ICR_ARROKCF (1U << 4)
#define GD32_LPTIM_ICR_UPCF (1U << 5)
#define GD32_LPTIM_ICR_DOWNCF (1U << 6)
/** @} */
/**
* @name LPTIM_IER register
* @{
*/
#define STM32_LPTIM_IER_CMPMIE (1U << 0)
#define STM32_LPTIM_IER_ARRMIE (1U << 1)
#define STM32_LPTIM_IER_EXTTRIGIE (1U << 2)
#define STM32_LPTIM_IER_CMPOKIE (1U << 3)
#define STM32_LPTIM_IER_ARROKIE (1U << 4)
#define STM32_LPTIM_IER_UPIE (1U << 5)
#define STM32_LPTIM_IER_DOWNIE (1U << 6)
#define GD32_LPTIM_IER_CMPMIE (1U << 0)
#define GD32_LPTIM_IER_ARRMIE (1U << 1)
#define GD32_LPTIM_IER_EXTTRIGIE (1U << 2)
#define GD32_LPTIM_IER_CMPOKIE (1U << 3)
#define GD32_LPTIM_IER_ARROKIE (1U << 4)
#define GD32_LPTIM_IER_UPIE (1U << 5)
#define GD32_LPTIM_IER_DOWNIE (1U << 6)
/** @} */
/**
* @name LPTIM_CFGR register
* @{
*/
#define STM32_LPTIM_CFGR_CKSEL (1U << 0)
#define STM32_LPTIM_CFGR_CKPOL_MASK (3U << 1)
#define STM32_LPTIM_CFGR_CKPOL(n) ((n) << 1)
#define STM32_LPTIM_CFGR_CKFLT_MASK (3U << 3)
#define STM32_LPTIM_CFGR_CKFLT(n) ((n) << 3)
#define STM32_LPTIM_CFGR_TRGFLT_MASK (3U << 6)
#define STM32_LPTIM_CFGR_TRGFLT(n) ((n) << 6)
#define STM32_LPTIM_CFGR_PRESC_MASK (7U << 9)
#define STM32_LPTIM_CFGR_PRESC(n) ((n) << 9)
#define STM32_LPTIM_CFGR_TRIGSEL_MASK (7U << 13)
#define STM32_LPTIM_CFGR_TRIGSEL(n) ((n) << 13)
#define STM32_LPTIM_CFGR_TRIGEN_MASK (3U << 17)
#define STM32_LPTIM_CFGR_TRIGEN(n) ((n) << 17)
#define STM32_LPTIM_CFGR_TIMOUT (1U << 19)
#define STM32_LPTIM_CFGR_WAVE (1U << 20)
#define STM32_LPTIM_CFGR_WAVPOL (1U << 21)
#define STM32_LPTIM_CFGR_PRELOAD (1U << 22)
#define STM32_LPTIM_CFGR_COUNTMODE (1U << 23)
#define STM32_LPTIM_CFGR_ENC (1U << 24)
#define GD32_LPTIM_CFGR_CKSEL (1U << 0)
#define GD32_LPTIM_CFGR_CKPOL_MASK (3U << 1)
#define GD32_LPTIM_CFGR_CKPOL(n) ((n) << 1)
#define GD32_LPTIM_CFGR_CKFLT_MASK (3U << 3)
#define GD32_LPTIM_CFGR_CKFLT(n) ((n) << 3)
#define GD32_LPTIM_CFGR_TRGFLT_MASK (3U << 6)
#define GD32_LPTIM_CFGR_TRGFLT(n) ((n) << 6)
#define GD32_LPTIM_CFGR_PRESC_MASK (7U << 9)
#define GD32_LPTIM_CFGR_PRESC(n) ((n) << 9)
#define GD32_LPTIM_CFGR_TRIGSEL_MASK (7U << 13)
#define GD32_LPTIM_CFGR_TRIGSEL(n) ((n) << 13)
#define GD32_LPTIM_CFGR_TRIGEN_MASK (3U << 17)
#define GD32_LPTIM_CFGR_TRIGEN(n) ((n) << 17)
#define GD32_LPTIM_CFGR_TIMOUT (1U << 19)
#define GD32_LPTIM_CFGR_WAVE (1U << 20)
#define GD32_LPTIM_CFGR_WAVPOL (1U << 21)
#define GD32_LPTIM_CFGR_PRELOAD (1U << 22)
#define GD32_LPTIM_CFGR_COUNTMODE (1U << 23)
#define GD32_LPTIM_CFGR_ENC (1U << 24)
/** @} */
/**
* @name LPTIM_CR register
* @{
*/
#define STM32_LPTIM_CR_ENABLE (1U << 0)
#define STM32_LPTIM_CR_SNGSTRT (1U << 1)
#define STM32_LPTIM_CR_CNTSTRT (1U << 2)
#define GD32_LPTIM_CR_ENABLE (1U << 0)
#define GD32_LPTIM_CR_SNGSTRT (1U << 1)
#define GD32_LPTIM_CR_CNTSTRT (1U << 2)
/** @} */
/**
* @name LPTIM_OR register
* @{
*/
#define STM32_LPTIM_OR_0 (1U << 0)
#define STM32_LPTIM_OR_1 (1U << 1)
#define GD32_LPTIM_OR_0 (1U << 0)
#define GD32_LPTIM_OR_1 (1U << 1)
/** @} */
/**
* @name TIM units references
* @{
*/
#define STM32_TIM1 ((stm32_tim_t *)TIM1_BASE)
#define STM32_TIM2 ((stm32_tim_t *)TIM2_BASE)
#define STM32_TIM3 ((stm32_tim_t *)TIM3_BASE)
#define STM32_TIM4 ((stm32_tim_t *)TIM4_BASE)
#define STM32_TIM5 ((stm32_tim_t *)TIM5_BASE)
#define STM32_TIM6 ((stm32_tim_t *)TIM6_BASE)
#define STM32_TIM7 ((stm32_tim_t *)TIM7_BASE)
#define STM32_TIM8 ((stm32_tim_t *)TIM8_BASE)
#define STM32_TIM9 ((stm32_tim_t *)TIM9_BASE)
#define STM32_TIM10 ((stm32_tim_t *)TIM10_BASE)
#define STM32_TIM11 ((stm32_tim_t *)TIM11_BASE)
#define STM32_TIM12 ((stm32_tim_t *)TIM12_BASE)
#define STM32_TIM13 ((stm32_tim_t *)TIM13_BASE)
#define STM32_TIM14 ((stm32_tim_t *)TIM14_BASE)
#define STM32_TIM15 ((stm32_tim_t *)TIM15_BASE)
#define STM32_TIM16 ((stm32_tim_t *)TIM16_BASE)
#define STM32_TIM17 ((stm32_tim_t *)TIM17_BASE)
#define STM32_TIM18 ((stm32_tim_t *)TIM18_BASE)
#define STM32_TIM19 ((stm32_tim_t *)TIM19_BASE)
#define STM32_TIM20 ((stm32_tim_t *)TIM20_BASE)
#define STM32_TIM21 ((stm32_tim_t *)TIM21_BASE)
#define STM32_TIM22 ((stm32_tim_t *)TIM22_BASE)
#define GD32_TIM1 ((stm32_tim_t *)TIM1_BASE)
#define GD32_TIM2 ((stm32_tim_t *)TIM2_BASE)
#define GD32_TIM3 ((stm32_tim_t *)TIM3_BASE)
#define GD32_TIM4 ((stm32_tim_t *)TIM4_BASE)
#define GD32_TIM5 ((stm32_tim_t *)TIM5_BASE)
#define GD32_TIM6 ((stm32_tim_t *)TIM6_BASE)
#define GD32_TIM7 ((stm32_tim_t *)TIM7_BASE)
#define GD32_TIM8 ((stm32_tim_t *)TIM8_BASE)
#define GD32_TIM9 ((stm32_tim_t *)TIM9_BASE)
#define GD32_TIM10 ((stm32_tim_t *)TIM10_BASE)
#define GD32_TIM11 ((stm32_tim_t *)TIM11_BASE)
#define GD32_TIM12 ((stm32_tim_t *)TIM12_BASE)
#define GD32_TIM13 ((stm32_tim_t *)TIM13_BASE)
#define GD32_TIM14 ((stm32_tim_t *)TIM14_BASE)
#define GD32_TIM15 ((stm32_tim_t *)TIM15_BASE)
#define GD32_TIM16 ((stm32_tim_t *)TIM16_BASE)
#define GD32_TIM17 ((stm32_tim_t *)TIM17_BASE)
#define GD32_TIM18 ((stm32_tim_t *)TIM18_BASE)
#define GD32_TIM19 ((stm32_tim_t *)TIM19_BASE)
#define GD32_TIM20 ((stm32_tim_t *)TIM20_BASE)
#define GD32_TIM21 ((stm32_tim_t *)TIM21_BASE)
#define GD32_TIM22 ((stm32_tim_t *)TIM22_BASE)
#define STM32_LPTIM1 ((stm32_lptim_t *)LPTIM1_BASE)
#define STM32_LPTIM2 ((stm32_lptim_t *)LPTIM2_BASE)
#define GD32_LPTIM1 ((stm32_lptim_t *)LPTIM1_BASE)
#define GD32_LPTIM2 ((stm32_lptim_t *)LPTIM2_BASE)
/** @} */
/*===========================================================================*/
@ -547,6 +547,6 @@ typedef struct {
/* External declarations. */
/*===========================================================================*/
#endif /* STM32_TIM_H */
#endif /* GD32_TIM_H */
/** @} */

62
os/hal/ports/GD/GD32VF103/TIM/stm32_tim1.inc
View File

@ -31,45 +31,45 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM1)
#error "STM32_HAS_TIM1 not defined in registry"
#if !defined(GD32_HAS_TIM1)
#error "GD32_HAS_TIM1 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM1)
#define STM32_GPT_USE_TIM1 FALSE
#if !defined(GD32_GPT_USE_TIM1)
#define GD32_GPT_USE_TIM1 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM1)
#define STM32_ICU_USE_TIM1 FALSE
#if !defined(GD32_ICU_USE_TIM1)
#define GD32_ICU_USE_TIM1 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM1)
#define STM32_PWM_USE_TIM1 FALSE
#if !defined(GD32_PWM_USE_TIM1)
#define GD32_PWM_USE_TIM1 FALSE
#endif
#if !defined(STM32_ST_USE_TIM1)
#define STM32_ST_USE_TIM1 FALSE
#if !defined(GD32_ST_USE_TIM1)
#define GD32_ST_USE_TIM1 FALSE
#endif
#if STM32_HAS_TIM1
#if GD32_HAS_TIM1
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM1_UP_PRIORITY)
#error "STM32_IRQ_TIM1_UP_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM1_UP_PRIORITY)
#error "GD32_IRQ_TIM1_UP_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(STM32_IRQ_TIM1_CC_PRIORITY)
#error "STM32_IRQ_TIM1_CC_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM1_CC_PRIORITY)
#error "GD32_IRQ_TIM1_CC_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_UP_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_UP_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_UP_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_CC_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_CC_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_CC_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_CC_PRIORITY"
#endif
#endif /* STM32_HAS_TIM1 */
#endif /* GD32_HAS_TIM1 */
/*===========================================================================*/
/* Driver exported variables. */
@ -84,14 +84,14 @@
/*===========================================================================*/
static inline void tim1_irq_init(void) {
#if defined(STM32_TIM1_IS_USED)
eclicEnableVector(GD32_TIM1_UP_NUMBER, STM32_IRQ_TIM1_UP_PRIORITY, STM32_IRQ_TIM1_UP_TRIGGER);
eclicEnableVector(GD32_TIM1_CC_NUMBER, STM32_IRQ_TIM1_CC_PRIORITY, STM32_IRQ_TIM1_CC_TRIGGER);
#if defined(GD32_TIM1_IS_USED)
eclicEnableVector(GD32_TIM1_UP_NUMBER, GD32_IRQ_TIM1_UP_PRIORITY, GD32_IRQ_TIM1_UP_TRIGGER);
eclicEnableVector(GD32_TIM1_CC_NUMBER, GD32_IRQ_TIM1_CC_PRIORITY, GD32_IRQ_TIM1_CC_TRIGGER);
#endif
}
static inline void tim1_irq_deinit(void) {
#if defined(STM32_TIM1_IS_USED)
#if defined(GD32_TIM1_IS_USED)
eclicDisableVector(GD32_TIM1_UP_NUMBER);
eclicDisableVector(GD32_TIM1_CC_NUMBER);
#endif
@ -101,7 +101,7 @@ static inline void tim1_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM1_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM1_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM1-UP interrupt handler.
*
@ -112,22 +112,22 @@ OSAL_IRQ_HANDLER(GD32_TIM1_UP_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM1
#if GD32_GPT_USE_TIM1
gpt_lld_serve_interrupt(&GPTD1);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM1
#if GD32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM1
#if GD32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM1
#if GD32_ST_USE_TIM1
st_lld_serve_interrupt();
#endif
#endif
@ -148,12 +148,12 @@ OSAL_IRQ_HANDLER(GD32_TIM1_CC_HANDLER) {
/* Not used by GPT.*/
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM1
#if GD32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM1
#if GD32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#endif

48
os/hal/ports/GD/GD32VF103/TIM/stm32_tim14.inc
View File

@ -31,37 +31,37 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM14)
#error "STM32_HAS_TIM14 not defined in registry"
#if !defined(GD32_HAS_TIM14)
#error "GD32_HAS_TIM14 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM14)
#define STM32_GPT_USE_TIM14 FALSE
#if !defined(GD32_GPT_USE_TIM14)
#define GD32_GPT_USE_TIM14 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM14)
#define STM32_ICU_USE_TIM14 FALSE
#if !defined(GD32_ICU_USE_TIM14)
#define GD32_ICU_USE_TIM14 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM14)
#define STM32_PWM_USE_TIM14 FALSE
#if !defined(GD32_PWM_USE_TIM14)
#define GD32_PWM_USE_TIM14 FALSE
#endif
#if !defined(STM32_ST_USE_TIM14)
#define STM32_ST_USE_TIM14 FALSE
#if !defined(GD32_ST_USE_TIM14)
#define GD32_ST_USE_TIM14 FALSE
#endif
#if STM32_HAS_TIM14
#if GD32_HAS_TIM14
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM14_PRIORITY)
#error "STM32_IRQ_TIM14_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM14_PRIORITY)
#error "GD32_IRQ_TIM14_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM14_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM14_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM14_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM14_PRIORITY"
#endif
#endif /* STM32_HAS_TIM14 */
#endif /* GD32_HAS_TIM14 */
/*===========================================================================*/
/* Driver exported variables. */
@ -76,13 +76,13 @@
/*===========================================================================*/
static inline void tim14_irq_init(void) {
#if defined(STM32_TIM14_IS_USED)
eclicEnableVector(GD32_TIM14_NUMBER, STM32_IRQ_TIM14_PRIORITY, STM32_IRQ_TIM14_TRIGGER);
#if defined(GD32_TIM14_IS_USED)
eclicEnableVector(GD32_TIM14_NUMBER, GD32_IRQ_TIM14_PRIORITY, GD32_IRQ_TIM14_TRIGGER);
#endif
}
static inline void tim14_irq_deinit(void) {
#if defined(STM32_TIM14_IS_USED)
#if defined(GD32_TIM14_IS_USED)
eclicDisableVector(GD32_TIM14_NUMBER);
#endif
}
@ -91,7 +91,7 @@ static inline void tim14_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM14_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM14_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM14 interrupt handler.
*
@ -102,22 +102,22 @@ OSAL_IRQ_HANDLER(GD32_TIM14_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM14
#if GD32_GPT_USE_TIM14
gpt_lld_serve_interrupt(&GPTD14);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM14
#if GD32_ICU_USE_TIM14
icu_lld_serve_interrupt(&ICUD14);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM14
#if GD32_PWM_USE_TIM14
pwm_lld_serve_interrupt(&PWMD14);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM14
#if GD32_ST_USE_TIM14
st_lld_serve_interrupt();
#endif
#endif

48
os/hal/ports/GD/GD32VF103/TIM/stm32_tim15.inc
View File

@ -31,37 +31,37 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM15)
#error "STM32_HAS_TIM15 not defined in registry"
#if !defined(GD32_HAS_TIM15)
#error "GD32_HAS_TIM15 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM15)
#define STM32_GPT_USE_TIM15 FALSE
#if !defined(GD32_GPT_USE_TIM15)
#define GD32_GPT_USE_TIM15 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM15)
#define STM32_ICU_USE_TIM15 FALSE
#if !defined(GD32_ICU_USE_TIM15)
#define GD32_ICU_USE_TIM15 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM15)
#define STM32_PWM_USE_TIM15 FALSE
#if !defined(GD32_PWM_USE_TIM15)
#define GD32_PWM_USE_TIM15 FALSE
#endif
#if !defined(STM32_ST_USE_TIM15)
#define STM32_ST_USE_TIM15 FALSE
#if !defined(GD32_ST_USE_TIM15)
#define GD32_ST_USE_TIM15 FALSE
#endif
#if STM32_HAS_TIM15
#if GD32_HAS_TIM15
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM15_PRIORITY)
#error "STM32_IRQ_TIM15_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM15_PRIORITY)
#error "GD32_IRQ_TIM15_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM15_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM15_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM15_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM15_PRIORITY"
#endif
#endif /* STM32_HAS_TIM15 */
#endif /* GD32_HAS_TIM15 */
/*===========================================================================*/
/* Driver exported variables. */
@ -76,13 +76,13 @@
/*===========================================================================*/
static inline void tim15_irq_init(void) {
#if defined(STM32_TIM15_IS_USED)
eclicEnableVector(GD32_TIM15_NUMBER, STM32_IRQ_TIM15_PRIORITY, STM32_IRQ_TIM15_TRIGGER);
#if defined(GD32_TIM15_IS_USED)
eclicEnableVector(GD32_TIM15_NUMBER, GD32_IRQ_TIM15_PRIORITY, GD32_IRQ_TIM15_TRIGGER);
#endif
}
static inline void tim15_irq_deinit(void) {
#if defined(STM32_TIM15_IS_USED)
#if defined(GD32_TIM15_IS_USED)
eclicDisableVector(GD32_TIM15_NUMBER);
#endif
}
@ -91,7 +91,7 @@ static inline void tim15_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM15_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM15_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM15 interrupt handler.
*
@ -102,22 +102,22 @@ OSAL_IRQ_HANDLER(GD32_TIM15_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM15
#if GD32_GPT_USE_TIM15
gpt_lld_serve_interrupt(&GPTD15);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM15
#if GD32_ICU_USE_TIM15
icu_lld_serve_interrupt(&ICUD15);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM15
#if GD32_PWM_USE_TIM15
pwm_lld_serve_interrupt(&PWMD15);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM15
#if GD32_ST_USE_TIM15
st_lld_serve_interrupt();
#endif
#endif

48
os/hal/ports/GD/GD32VF103/TIM/stm32_tim16.inc
View File

@ -31,37 +31,37 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM16)
#error "STM32_HAS_TIM16 not defined in registry"
#if !defined(GD32_HAS_TIM16)
#error "GD32_HAS_TIM16 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM16)
#define STM32_GPT_USE_TIM16 FALSE
#if !defined(GD32_GPT_USE_TIM16)
#define GD32_GPT_USE_TIM16 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM16)
#define STM32_ICU_USE_TIM16 FALSE
#if !defined(GD32_ICU_USE_TIM16)
#define GD32_ICU_USE_TIM16 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM16)
#define STM32_PWM_USE_TIM16 FALSE
#if !defined(GD32_PWM_USE_TIM16)
#define GD32_PWM_USE_TIM16 FALSE
#endif
#if !defined(STM32_ST_USE_TIM16)
#define STM32_ST_USE_TIM16 FALSE
#if !defined(GD32_ST_USE_TIM16)
#define GD32_ST_USE_TIM16 FALSE
#endif
#if STM32_HAS_TIM16
#if GD32_HAS_TIM16
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM16_PRIORITY)
#error "STM32_IRQ_TIM16_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM16_PRIORITY)
#error "GD32_IRQ_TIM16_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM16_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM16_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM16_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM16_PRIORITY"
#endif
#endif /* STM32_HAS_TIM16 */
#endif /* GD32_HAS_TIM16 */
/*===========================================================================*/
/* Driver exported variables. */
@ -76,13 +76,13 @@
/*===========================================================================*/
static inline void tim16_irq_init(void) {
#if defined(STM32_TIM16_IS_USED)
eclicEnableVector(GD32_TIM16_NUMBER, STM32_IRQ_TIM16_PRIORITY, STM32_IRQ_TIM16_TRIGGER);
#if defined(GD32_TIM16_IS_USED)
eclicEnableVector(GD32_TIM16_NUMBER, GD32_IRQ_TIM16_PRIORITY, GD32_IRQ_TIM16_TRIGGER);
#endif
}
static inline void tim16_irq_deinit(void) {
#if defined(STM32_TIM16_IS_USED)
#if defined(GD32_TIM16_IS_USED)
eclicDisableVector(GD32_TIM16_NUMBER);
#endif
}
@ -91,7 +91,7 @@ static inline void tim16_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM16_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM16_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM16 interrupt handler.
*
@ -102,22 +102,22 @@ OSAL_IRQ_HANDLER(GD32_TIM16_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM16
#if GD32_GPT_USE_TIM16
gpt_lld_serve_interrupt(&GPTD16);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM16
#if GD32_ICU_USE_TIM16
icu_lld_serve_interrupt(&ICUD16);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM16
#if GD32_PWM_USE_TIM16
pwm_lld_serve_interrupt(&PWMD16);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM16
#if GD32_ST_USE_TIM16
st_lld_serve_interrupt();
#endif
#endif

48
os/hal/ports/GD/GD32VF103/TIM/stm32_tim17.inc
View File

@ -31,37 +31,37 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM17)
#error "STM32_HAS_TIM17 not defined in registry"
#if !defined(GD32_HAS_TIM17)
#error "GD32_HAS_TIM17 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM17)
#define STM32_GPT_USE_TIM17 FALSE
#if !defined(GD32_GPT_USE_TIM17)
#define GD32_GPT_USE_TIM17 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM17)
#define STM32_ICU_USE_TIM17 FALSE
#if !defined(GD32_ICU_USE_TIM17)
#define GD32_ICU_USE_TIM17 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM17)
#define STM32_PWM_USE_TIM17 FALSE
#if !defined(GD32_PWM_USE_TIM17)
#define GD32_PWM_USE_TIM17 FALSE
#endif
#if !defined(STM32_ST_USE_TIM17)
#define STM32_ST_USE_TIM17 FALSE
#if !defined(GD32_ST_USE_TIM17)
#define GD32_ST_USE_TIM17 FALSE
#endif
#if STM32_HAS_TIM17
#if GD32_HAS_TIM17
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM17_PRIORITY)
#error "STM32_IRQ_TIM17_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM17_PRIORITY)
#error "GD32_IRQ_TIM17_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM17_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM17_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM17_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM17_PRIORITY"
#endif
#endif /* STM32_HAS_TIM17 */
#endif /* GD32_HAS_TIM17 */
/*===========================================================================*/
/* Driver exported variables. */
@ -76,13 +76,13 @@
/*===========================================================================*/
static inline void tim17_irq_init(void) {
#if defined(STM32_TIM17_IS_USED)
eclicEnableVector(GD32_TIM17_NUMBER, STM32_IRQ_TIM17_PRIORITY, STM32_IRQ_TIM17_TRIGGER);
#if defined(GD32_TIM17_IS_USED)
eclicEnableVector(GD32_TIM17_NUMBER, GD32_IRQ_TIM17_PRIORITY, GD32_IRQ_TIM17_TRIGGER);
#endif
}
static inline void tim17_irq_deinit(void) {
#if defined(STM32_TIM17_IS_USED)
#if defined(GD32_TIM17_IS_USED)
eclicDisableVector(GD32_TIM17_NUMBER);
#endif
}
@ -91,7 +91,7 @@ static inline void tim17_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM17_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM17_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM17 interrupt handler.
*
@ -102,22 +102,22 @@ OSAL_IRQ_HANDLER(GD32_TIM17_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM17
#if GD32_GPT_USE_TIM17
gpt_lld_serve_interrupt(&GPTD17);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM17
#if GD32_ICU_USE_TIM17
icu_lld_serve_interrupt(&ICUD17);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM17
#if GD32_PWM_USE_TIM17
pwm_lld_serve_interrupt(&PWMD17);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM17
#if GD32_ST_USE_TIM17
st_lld_serve_interrupt();
#endif
#endif

180
os/hal/ports/GD/GD32VF103/TIM/stm32_tim1_15_16_17.inc
View File

@ -31,112 +31,112 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM1)
#error "STM32_HAS_TIM1 not defined in registry"
#if !defined(GD32_HAS_TIM1)
#error "GD32_HAS_TIM1 not defined in registry"
#endif
#if !defined(STM32_HAS_TIM15)
#error "STM32_HAS_TIM15 not defined in registry"
#if !defined(GD32_HAS_TIM15)
#error "GD32_HAS_TIM15 not defined in registry"
#endif
#if !defined(STM32_HAS_TIM16)
#error "STM32_HAS_TIM16 not defined in registry"
#if !defined(GD32_HAS_TIM16)
#error "GD32_HAS_TIM16 not defined in registry"
#endif
#if !defined(STM32_HAS_TIM17)
#error "STM32_HAS_TIM17 not defined in registry"
#if !defined(GD32_HAS_TIM17)
#error "GD32_HAS_TIM17 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM1)
#define STM32_GPT_USE_TIM1 FALSE
#if !defined(GD32_GPT_USE_TIM1)
#define GD32_GPT_USE_TIM1 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM1)
#define STM32_ICU_USE_TIM1 FALSE
#if !defined(GD32_ICU_USE_TIM1)
#define GD32_ICU_USE_TIM1 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM1)
#define STM32_PWM_USE_TIM1 FALSE
#if !defined(GD32_PWM_USE_TIM1)
#define GD32_PWM_USE_TIM1 FALSE
#endif
#if !defined(STM32_ST_USE_TIM1)
#define STM32_ST_USE_TIM1 FALSE
#if !defined(GD32_ST_USE_TIM1)
#define GD32_ST_USE_TIM1 FALSE
#endif
#if !defined(STM32_GPT_USE_TIM15)
#define STM32_GPT_USE_TIM15 FALSE
#if !defined(GD32_GPT_USE_TIM15)
#define GD32_GPT_USE_TIM15 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM15)
#define STM32_ICU_USE_TIM15 FALSE
#if !defined(GD32_ICU_USE_TIM15)
#define GD32_ICU_USE_TIM15 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM15)
#define STM32_PWM_USE_TIM15 FALSE
#if !defined(GD32_PWM_USE_TIM15)
#define GD32_PWM_USE_TIM15 FALSE
#endif
#if !defined(STM32_ST_USE_TIM15)
#define STM32_ST_USE_TIM15 FALSE
#if !defined(GD32_ST_USE_TIM15)
#define GD32_ST_USE_TIM15 FALSE
#endif
#if !defined(STM32_GPT_USE_TIM16)
#define STM32_GPT_USE_TIM16 FALSE
#if !defined(GD32_GPT_USE_TIM16)
#define GD32_GPT_USE_TIM16 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM16)
#define STM32_ICU_USE_TIM16 FALSE
#if !defined(GD32_ICU_USE_TIM16)
#define GD32_ICU_USE_TIM16 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM16)
#define STM32_PWM_USE_TIM16 FALSE
#if !defined(GD32_PWM_USE_TIM16)
#define GD32_PWM_USE_TIM16 FALSE
#endif
#if !defined(STM32_ST_USE_TIM16)
#define STM32_ST_USE_TIM16 FALSE
#if !defined(GD32_ST_USE_TIM16)
#define GD32_ST_USE_TIM16 FALSE
#endif
#if !defined(STM32_GPT_USE_TIM17)
#define STM32_GPT_USE_TIM17 FALSE
#if !defined(GD32_GPT_USE_TIM17)
#define GD32_GPT_USE_TIM17 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM17)
#define STM32_ICU_USE_TIM17 FALSE
#if !defined(GD32_ICU_USE_TIM17)
#define GD32_ICU_USE_TIM17 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM17)
#define STM32_PWM_USE_TIM17 FALSE
#if !defined(GD32_PWM_USE_TIM17)
#define GD32_PWM_USE_TIM17 FALSE
#endif
#if !defined(STM32_ST_USE_TIM17)
#define STM32_ST_USE_TIM17 FALSE
#if !defined(GD32_ST_USE_TIM17)
#define GD32_ST_USE_TIM17 FALSE
#endif
#if STM32_HAS_TIM1 || STM32_HAS_TIM15 || STM32_HAS_TIM16 || STM32_HAS_TIM17
#if GD32_HAS_TIM1 || GD32_HAS_TIM15 || GD32_HAS_TIM16 || GD32_HAS_TIM17
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM1_BRK_TIM15_PRIORITY)
#error "STM32_IRQ_TIM1_BRK_TIM15_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM1_BRK_TIM15_PRIORITY)
#error "GD32_IRQ_TIM1_BRK_TIM15_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(STM32_IRQ_TIM1_UP_TIM16_PRIORITY)
#error "STM32_IRQ_TIM1_UP_TIM16_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM1_UP_TIM16_PRIORITY)
#error "GD32_IRQ_TIM1_UP_TIM16_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY)
#error "STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM1_TRGCO_TIM17_PRIORITY)
#error "GD32_IRQ_TIM1_TRGCO_TIM17_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(STM32_IRQ_TIM1_CC_PRIORITY)
#error "STM32_IRQ_TIM1_CC_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM1_CC_PRIORITY)
#error "GD32_IRQ_TIM1_CC_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_BRK_TIM15_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM15_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_BRK_TIM15_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_BRK_TIM15_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_UP_TIM16_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM16_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_UP_TIM16_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_UP_TIM16_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_TRGCO_TIM17_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_TRGCO_TIM17_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_CC_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_CC_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_CC_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_CC_PRIORITY"
#endif
#endif /* STM32_HAS_TIM1 || STM32_HAS_TIM15 || STM32_HAS_TIM16 || STM32_HAS_TIM17 */
#endif /* GD32_HAS_TIM1 || GD32_HAS_TIM15 || GD32_HAS_TIM16 || GD32_HAS_TIM17 */
/*===========================================================================*/
/* Driver exported variables. */
@ -151,35 +151,35 @@
/*===========================================================================*/
static inline void tim1_tim15_tim16_tim17_irq_init(void) {
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM15_IS_USED)
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM15_IS_USED)
nvicEnableVector(GD32_TIM1_BRK_TIM15_NUMBER,
STM32_IRQ_TIM1_BRK_TIM15_PRIORITY);
GD32_IRQ_TIM1_BRK_TIM15_PRIORITY);
#endif
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM16_IS_USED)
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM16_IS_USED)
nvicEnableVector(GD32_TIM1_UP_TIM16_NUMBER,
STM32_IRQ_TIM1_UP_TIM16_PRIORITY);
GD32_IRQ_TIM1_UP_TIM16_PRIORITY);
#endif
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM17_IS_USED)
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM17_IS_USED)
nvicEnableVector(GD32_TIM1_TRGCO_TIM17_NUMBER,
STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY);
GD32_IRQ_TIM1_TRGCO_TIM17_PRIORITY);
#endif
#if defined(STM32_TIM1_IS_USED)
#if defined(GD32_TIM1_IS_USED)
nvicEnableVector(GD32_TIM1_CC_NUMBER,
STM32_IRQ_TIM1_CC_PRIORITY);
GD32_IRQ_TIM1_CC_PRIORITY);
#endif
}
static inline void tim1_tim15_tim16_tim17_irq_deinit(void) {
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM15_IS_USED)
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM15_IS_USED)
eclicDisableVector(GD32_TIM1_BRK_TIM15_NUMBER);
#endif
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM16_IS_USED)
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM16_IS_USED)
eclicDisableVector(GD32_TIM1_UP_TIM16_NUMBER);
#endif
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM17_IS_USED)
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM17_IS_USED)
eclicDisableVector(GD32_TIM1_TRGCO_TIM17_NUMBER);
#endif
#if defined(STM32_TIM1_IS_USED)
#if defined(GD32_TIM1_IS_USED)
eclicDisableVector(GD32_TIM1_CC_NUMBER);
#endif
}
@ -188,7 +188,7 @@ static inline void tim1_tim15_tim16_tim17_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM15_IS_USED) || \
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM15_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM1-BRK, TIM15 interrupt handler.
@ -200,22 +200,22 @@ OSAL_IRQ_HANDLER(GD32_TIM1_BRK_TIM15_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM15
#if GD32_GPT_USE_TIM15
gpt_lld_serve_interrupt(&GPTD15);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM15
#if GD32_ICU_USE_TIM15
icu_lld_serve_interrupt(&ICUD15);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM15
#if GD32_PWM_USE_TIM15
pwm_lld_serve_interrupt(&PWMD15);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM15
#if GD32_ST_USE_TIM15
st_lld_serve_interrupt();
#endif
#endif
@ -224,7 +224,7 @@ OSAL_IRQ_HANDLER(GD32_TIM1_BRK_TIM15_HANDLER) {
}
#endif
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM16_IS_USED) || \
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM16_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM1-UP, TIM16 interrupt handler.
@ -236,31 +236,31 @@ OSAL_IRQ_HANDLER(GD32_TIM1_UP_TIM16_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM1
#if GD32_GPT_USE_TIM1
gpt_lld_serve_interrupt(&GPTD1);
#endif
#if STM32_GPT_USE_TIM16
#if GD32_GPT_USE_TIM16
gpt_lld_serve_interrupt(&GPTD16);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM1
#if GD32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM1
#if GD32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#if STM32_PWM_USE_TIM16
#if GD32_PWM_USE_TIM16
pwm_lld_serve_interrupt(&PWMD16);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM1
#if GD32_ST_USE_TIM1
st_lld_serve_interrupt();
#endif
#if STM32_ST_USE_TIM16
#if GD32_ST_USE_TIM16
st_lld_serve_interrupt();
#endif
#endif
@ -269,7 +269,7 @@ OSAL_IRQ_HANDLER(GD32_TIM1_UP_TIM16_HANDLER) {
}
#endif
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM17_IS_USED) || \
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM17_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM1-TRG-COM, TIM17 interrupt handler.
@ -281,7 +281,7 @@ OSAL_IRQ_HANDLER(GD32_TIM1_TRGCO_TIM17_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM17
#if GD32_GPT_USE_TIM17
gpt_lld_serve_interrupt(&GPTD17);
#endif
#endif
@ -289,12 +289,12 @@ OSAL_IRQ_HANDLER(GD32_TIM1_TRGCO_TIM17_HANDLER) {
/* Not used by ICU.*/
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM17
#if GD32_PWM_USE_TIM17
pwm_lld_serve_interrupt(&PWMD17);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM17
#if GD32_ST_USE_TIM17
st_lld_serve_interrupt();
#endif
#endif
@ -303,7 +303,7 @@ OSAL_IRQ_HANDLER(GD32_TIM1_TRGCO_TIM17_HANDLER) {
}
#endif
#if defined(STM32_TIM1_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM1_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM1-CC interrupt handler.
*
@ -317,12 +317,12 @@ OSAL_IRQ_HANDLER(GD32_TIM1_CC_HANDLER) {
/* Not used by GPT.*/
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM1
#if GD32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM1
#if GD32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#endif

184
os/hal/ports/GD/GD32VF103/TIM/stm32_tim1_9_10_11.inc
View File

@ -31,112 +31,112 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM1)
#error "STM32_HAS_TIM1 not defined in registry"
#if !defined(GD32_HAS_TIM1)
#error "GD32_HAS_TIM1 not defined in registry"
#endif
#if !defined(STM32_HAS_TIM9)
#error "STM32_HAS_TIM9 not defined in registry"
#if !defined(GD32_HAS_TIM9)
#error "GD32_HAS_TIM9 not defined in registry"
#endif
#if !defined(STM32_HAS_TIM10)
#error "STM32_HAS_TIM10 not defined in registry"
#if !defined(GD32_HAS_TIM10)
#error "GD32_HAS_TIM10 not defined in registry"
#endif
#if !defined(STM32_HAS_TIM11)
#error "STM32_HAS_TIM11 not defined in registry"
#if !defined(GD32_HAS_TIM11)
#error "GD32_HAS_TIM11 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM1)
#define STM32_GPT_USE_TIM1 FALSE
#if !defined(GD32_GPT_USE_TIM1)
#define GD32_GPT_USE_TIM1 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM1)
#define STM32_ICU_USE_TIM1 FALSE
#if !defined(GD32_ICU_USE_TIM1)
#define GD32_ICU_USE_TIM1 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM1)
#define STM32_PWM_USE_TIM1 FALSE
#if !defined(GD32_PWM_USE_TIM1)
#define GD32_PWM_USE_TIM1 FALSE
#endif
#if !defined(STM32_ST_USE_TIM1)
#define STM32_ST_USE_TIM1 FALSE
#if !defined(GD32_ST_USE_TIM1)
#define GD32_ST_USE_TIM1 FALSE
#endif
#if !defined(STM32_GPT_USE_TIM9)
#define STM32_GPT_USE_TIM9 FALSE
#if !defined(GD32_GPT_USE_TIM9)
#define GD32_GPT_USE_TIM9 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM9)
#define STM32_ICU_USE_TIM9 FALSE
#if !defined(GD32_ICU_USE_TIM9)
#define GD32_ICU_USE_TIM9 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM9)
#define STM32_PWM_USE_TIM9 FALSE
#if !defined(GD32_PWM_USE_TIM9)
#define GD32_PWM_USE_TIM9 FALSE
#endif
#if !defined(STM32_ST_USE_TIM9)
#define STM32_ST_USE_TIM9 FALSE
#if !defined(GD32_ST_USE_TIM9)
#define GD32_ST_USE_TIM9 FALSE
#endif
#if !defined(STM32_GPT_USE_TIM10)
#define STM32_GPT_USE_TIM10 FALSE
#if !defined(GD32_GPT_USE_TIM10)
#define GD32_GPT_USE_TIM10 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM10)
#define STM32_ICU_USE_TIM10 FALSE
#if !defined(GD32_ICU_USE_TIM10)
#define GD32_ICU_USE_TIM10 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM10)
#define STM32_PWM_USE_TIM10 FALSE
#if !defined(GD32_PWM_USE_TIM10)
#define GD32_PWM_USE_TIM10 FALSE
#endif
#if !defined(STM32_ST_USE_TIM10)
#define STM32_ST_USE_TIM10 FALSE
#if !defined(GD32_ST_USE_TIM10)
#define GD32_ST_USE_TIM10 FALSE
#endif
#if !defined(STM32_GPT_USE_TIM11)
#define STM32_GPT_USE_TIM11 FALSE
#if !defined(GD32_GPT_USE_TIM11)
#define GD32_GPT_USE_TIM11 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM11)
#define STM32_ICU_USE_TIM11 FALSE
#if !defined(GD32_ICU_USE_TIM11)
#define GD32_ICU_USE_TIM11 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM11)
#define STM32_PWM_USE_TIM11 FALSE
#if !defined(GD32_PWM_USE_TIM11)
#define GD32_PWM_USE_TIM11 FALSE
#endif
#if !defined(STM32_ST_USE_TIM11)
#define STM32_ST_USE_TIM11 FALSE
#if !defined(GD32_ST_USE_TIM11)
#define GD32_ST_USE_TIM11 FALSE
#endif
#if STM32_HAS_TIM1 || STM32_HAS_TIM9 || STM32_HAS_TIM10 || STM32_HAS_TIM11
#if GD32_HAS_TIM1 || GD32_HAS_TIM9 || GD32_HAS_TIM10 || GD32_HAS_TIM11
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM1_BRK_TIM9_PRIORITY)
#error "STM32_IRQ_TIM1_BRK_TIM9_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM1_BRK_TIM9_PRIORITY)
#error "GD32_IRQ_TIM1_BRK_TIM9_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(STM32_IRQ_TIM1_UP_TIM10_PRIORITY)
#error "STM32_IRQ_TIM1_UP_TIM10_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM1_UP_TIM10_PRIORITY)
#error "GD32_IRQ_TIM1_UP_TIM10_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY)
#error "STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM1_TRGCO_TIM11_PRIORITY)
#error "GD32_IRQ_TIM1_TRGCO_TIM11_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(STM32_IRQ_TIM1_CC_PRIORITY)
#error "STM32_IRQ_TIM1_CC_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM1_CC_PRIORITY)
#error "GD32_IRQ_TIM1_CC_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_BRK_TIM9_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM9_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_BRK_TIM9_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_BRK_TIM9_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_UP_TIM10_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM10_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_UP_TIM10_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_UP_TIM10_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_TRGCO_TIM11_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_TRGCO_TIM11_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_CC_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_CC_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_CC_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_CC_PRIORITY"
#endif
#endif /* STM32_HAS_TIM1 || STM32_HAS_TIM9 || STM32_HAS_TIM10 || STM32_HAS_TIM11 */
#endif /* GD32_HAS_TIM1 || GD32_HAS_TIM9 || GD32_HAS_TIM10 || GD32_HAS_TIM11 */
/*===========================================================================*/
/* Driver exported variables. */
@ -151,35 +151,35 @@
/*===========================================================================*/
static inline void tim1_tim9_tim10_tim11_irq_init(void) {
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM9_IS_USED)
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM9_IS_USED)
nvicEnableVector(GD32_TIM1_BRK_TIM9_NUMBER,
STM32_IRQ_TIM1_BRK_TIM9_PRIORITY);
GD32_IRQ_TIM1_BRK_TIM9_PRIORITY);
#endif
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM10_IS_USED)
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM10_IS_USED)
nvicEnableVector(GD32_TIM1_UP_TIM10_NUMBER,
STM32_IRQ_TIM1_UP_TIM10_PRIORITY);
GD32_IRQ_TIM1_UP_TIM10_PRIORITY);
#endif
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM11_IS_USED)
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM11_IS_USED)
nvicEnableVector(GD32_TIM1_TRGCO_TIM11_NUMBER,
STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY);
GD32_IRQ_TIM1_TRGCO_TIM11_PRIORITY);
#endif
#if defined(STM32_TIM1_IS_USED)
#if defined(GD32_TIM1_IS_USED)
nvicEnableVector(GD32_TIM1_CC_NUMBER,
STM32_IRQ_TIM1_CC_PRIORITY);
GD32_IRQ_TIM1_CC_PRIORITY);
#endif
}
static inline void tim1_tim9_tim10_tim11_irq_deinit(void) {
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM9_IS_USED)
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM9_IS_USED)
eclicDisableVector(GD32_TIM1_BRK_TIM9_NUMBER);
#endif
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM10_IS_USED)
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM10_IS_USED)
eclicDisableVector(GD32_TIM1_UP_TIM10_NUMBER);
#endif
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM11_IS_USED)
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM11_IS_USED)
eclicDisableVector(GD32_TIM1_TRGCO_TIM11_NUMBER);
#endif
#if defined(STM32_TIM1_IS_USED)
#if defined(GD32_TIM1_IS_USED)
eclicDisableVector(GD32_TIM1_CC_NUMBER);
#endif
}
@ -188,7 +188,7 @@ static inline void tim1_tim9_tim10_tim11_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM19_IS_USED) || \
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM19_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM1-BRK, TIM9 interrupt handler.
@ -200,22 +200,22 @@ OSAL_IRQ_HANDLER(GD32_TIM1_BRK_TIM9_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM9
#if GD32_GPT_USE_TIM9
gpt_lld_serve_interrupt(&GPTD9);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM9
#if GD32_ICU_USE_TIM9
icu_lld_serve_interrupt(&ICUD9);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM9
#if GD32_PWM_USE_TIM9
pwm_lld_serve_interrupt(&PWMD9);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM9
#if GD32_ST_USE_TIM9
st_lld_serve_interrupt();
#endif
#endif
@ -224,7 +224,7 @@ OSAL_IRQ_HANDLER(GD32_TIM1_BRK_TIM9_HANDLER) {
}
#endif
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM10_IS_USED) || \
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM10_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM1-UP, TIM10 interrupt handler.
@ -236,34 +236,34 @@ OSAL_IRQ_HANDLER(GD32_TIM1_UP_TIM10_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM1
#if GD32_GPT_USE_TIM1
gpt_lld_serve_interrupt(&GPTD1);
#endif
#if STM32_GPT_USE_TIM10
#if GD32_GPT_USE_TIM10
gpt_lld_serve_interrupt(&GPTD10);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM1
#if GD32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#if STM32_ICU_USE_TIM10
#if GD32_ICU_USE_TIM10
icu_lld_serve_interrupt(&ICUD10);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM1
#if GD32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#if STM32_PWM_USE_TIM10
#if GD32_PWM_USE_TIM10
pwm_lld_serve_interrupt(&PWMD10);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM1
#if GD32_ST_USE_TIM1
st_lld_serve_interrupt();
#endif
#if STM32_ST_USE_TIM10
#if GD32_ST_USE_TIM10
st_lld_serve_interrupt();
#endif
#endif
@ -272,7 +272,7 @@ OSAL_IRQ_HANDLER(GD32_TIM1_UP_TIM10_HANDLER) {
}
#endif
#if defined(STM32_TIM1_IS_USED) || defined(STM32_TIM11_IS_USED) || \
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM11_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM1-TRG-COM, TIM11 interrupt handler.
@ -284,22 +284,22 @@ OSAL_IRQ_HANDLER(GD32_TIM1_TRGCO_TIM11_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM11
#if GD32_GPT_USE_TIM11
gpt_lld_serve_interrupt(&GPTD11);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM11
#if GD32_ICU_USE_TIM11
icu_lld_serve_interrupt(&ICUD11);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM11
#if GD32_PWM_USE_TIM11
pwm_lld_serve_interrupt(&PWMD11);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM11
#if GD32_ST_USE_TIM11
st_lld_serve_interrupt();
#endif
#endif
@ -308,7 +308,7 @@ OSAL_IRQ_HANDLER(GD32_TIM1_TRGCO_TIM11_HANDLER) {
}
#endif
#if defined(STM32_TIM1_IS_USED)
#if defined(GD32_TIM1_IS_USED)
/**
* @brief TIM1-CC interrupt handler.
*
@ -322,12 +322,12 @@ OSAL_IRQ_HANDLER(GD32_TIM1_CC_HANDLER) {
/* Not used by GPT.*/
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM1
#if GD32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM1
#if GD32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#endif

48
os/hal/ports/GD/GD32VF103/TIM/stm32_tim2.inc
View File

@ -31,37 +31,37 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM2)
#error "STM32_HAS_TIM2 not defined in registry"
#if !defined(GD32_HAS_TIM2)
#error "GD32_HAS_TIM2 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM2)
#define STM32_GPT_USE_TIM2 FALSE
#if !defined(GD32_GPT_USE_TIM2)
#define GD32_GPT_USE_TIM2 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM2)
#define STM32_ICU_USE_TIM2 FALSE
#if !defined(GD32_ICU_USE_TIM2)
#define GD32_ICU_USE_TIM2 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM2)
#define STM32_PWM_USE_TIM2 FALSE
#if !defined(GD32_PWM_USE_TIM2)
#define GD32_PWM_USE_TIM2 FALSE
#endif
#if !defined(STM32_ST_USE_TIM2)
#define STM32_ST_USE_TIM2 FALSE
#if !defined(GD32_ST_USE_TIM2)
#define GD32_ST_USE_TIM2 FALSE
#endif
#if STM32_HAS_TIM2
#if GD32_HAS_TIM2
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM2_PRIORITY)
#error "STM32_IRQ_TIM2_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM2_PRIORITY)
#error "GD32_IRQ_TIM2_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM2_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM2_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM2_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM2_PRIORITY"
#endif
#endif /* STM32_HAS_TIM2 */
#endif /* GD32_HAS_TIM2 */
/*===========================================================================*/
/* Driver exported variables. */
@ -76,13 +76,13 @@
/*===========================================================================*/
static inline void tim2_irq_init(void) {
#if defined(STM32_TIM2_IS_USED)
eclicEnableVector(GD32_TIM2_NUMBER, STM32_IRQ_TIM2_PRIORITY, STM32_IRQ_TIM2_TRIGGER);
#if defined(GD32_TIM2_IS_USED)
eclicEnableVector(GD32_TIM2_NUMBER, GD32_IRQ_TIM2_PRIORITY, GD32_IRQ_TIM2_TRIGGER);
#endif
}
static inline void tim2_irq_deinit(void) {
#if defined(STM32_TIM2_IS_USED)
#if defined(GD32_TIM2_IS_USED)
eclicDisableVector(GD32_TIM2_NUMBER);
#endif
}
@ -91,7 +91,7 @@ static inline void tim2_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM2_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM2_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM2 interrupt handler.
*
@ -102,22 +102,22 @@ OSAL_IRQ_HANDLER(GD32_TIM2_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM2
#if GD32_GPT_USE_TIM2
gpt_lld_serve_interrupt(&GPTD2);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM2
#if GD32_ICU_USE_TIM2
icu_lld_serve_interrupt(&ICUD2);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM2
#if GD32_PWM_USE_TIM2
pwm_lld_serve_interrupt(&PWMD2);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM2
#if GD32_ST_USE_TIM2
st_lld_serve_interrupt();
#endif
#endif

62
os/hal/ports/GD/GD32VF103/TIM/stm32_tim20.inc
View File

@ -31,45 +31,45 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM20)
#error "STM32_HAS_TIM20 not defined in registry"
#if !defined(GD32_HAS_TIM20)
#error "GD32_HAS_TIM20 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM20)
#define STM32_GPT_USE_TIM20 FALSE
#if !defined(GD32_GPT_USE_TIM20)
#define GD32_GPT_USE_TIM20 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM20)
#define STM32_ICU_USE_TIM20 FALSE
#if !defined(GD32_ICU_USE_TIM20)
#define GD32_ICU_USE_TIM20 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM20)
#define STM32_PWM_USE_TIM20 FALSE
#if !defined(GD32_PWM_USE_TIM20)
#define GD32_PWM_USE_TIM20 FALSE
#endif
#if !defined(STM32_ST_USE_TIM20)
#define STM32_ST_USE_TIM20 FALSE
#if !defined(GD32_ST_USE_TIM20)
#define GD32_ST_USE_TIM20 FALSE
#endif
#if STM32_HAS_TIM20
#if GD32_HAS_TIM20
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM20_UP_PRIORITY)
#error "STM32_IRQ_TIM20_UP_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM20_UP_PRIORITY)
#error "GD32_IRQ_TIM20_UP_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(STM32_IRQ_TIM20_CC_PRIORITY)
#error "STM32_IRQ_TIM20_CC_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM20_CC_PRIORITY)
#error "GD32_IRQ_TIM20_CC_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM20_UP_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM20_UP_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM20_UP_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM20_UP_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM20_CC_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM20_CC_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM20_CC_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM20_CC_PRIORITY"
#endif
#endif /* STM32_HAS_TIM20 */
#endif /* GD32_HAS_TIM20 */
/*===========================================================================*/
/* Driver exported variables. */
@ -84,14 +84,14 @@
/*===========================================================================*/
static inline void tim20_irq_init(void) {
#if defined(STM32_TIM20_IS_USED)
eclicEnableVector(GD32_TIM20_UP_NUMBER, STM32_IRQ_TIM20_UP_PRIORITY, STM32_IRQ_TIM20_UP_TRIGGER);
eclicEnableVector(GD32_TIM20_CC_NUMBER, STM32_IRQ_TIM20_CC_PRIORITY, STM32_IRQ_TIM20_CC_TRIGGER);
#if defined(GD32_TIM20_IS_USED)
eclicEnableVector(GD32_TIM20_UP_NUMBER, GD32_IRQ_TIM20_UP_PRIORITY, GD32_IRQ_TIM20_UP_TRIGGER);
eclicEnableVector(GD32_TIM20_CC_NUMBER, GD32_IRQ_TIM20_CC_PRIORITY, GD32_IRQ_TIM20_CC_TRIGGER);
#endif
}
static inline void tim20_irq_deinit(void) {
#if defined(STM32_TIM20_IS_USED)
#if defined(GD32_TIM20_IS_USED)
eclicDisableVector(GD32_TIM20_UP_NUMBER);
eclicDisableVector(GD32_TIM20_CC_NUMBER);
#endif
@ -101,7 +101,7 @@ static inline void tim20_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM20_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM20_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM20-UP interrupt handler.
*
@ -112,22 +112,22 @@ OSAL_IRQ_HANDLER(GD32_TIM20_UP_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM20
#if GD32_GPT_USE_TIM20
pwm_lld_serve_interrupt(&GPTD20);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM20
#if GD32_ICU_USE_TIM20
pwm_lld_serve_interrupt(&ICUD20);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM20
#if GD32_PWM_USE_TIM20
pwm_lld_serve_interrupt(&PWMD20);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM20
#if GD32_ST_USE_TIM20
st_lld_serve_interrupt();
#endif
#endif
@ -147,11 +147,11 @@ OSAL_IRQ_HANDLER(GD32_TIM20_CC_HANDLER) {
#if HAL_USE_GPT
/* Not used by GPT.*/
#endif
#if STM32_ICU_USE_TIM20
#if GD32_ICU_USE_TIM20
pwm_lld_serve_interrupt(&ICUD20);
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM20
#if GD32_PWM_USE_TIM20
pwm_lld_serve_interrupt(&PWMD20);
#endif
#endif

48
os/hal/ports/GD/GD32VF103/TIM/stm32_tim21.inc
View File

@ -31,37 +31,37 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM21)
#error "STM32_HAS_TIM21 not defined in registry"
#if !defined(GD32_HAS_TIM21)
#error "GD32_HAS_TIM21 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM21)
#define STM32_GPT_USE_TIM21 FALSE
#if !defined(GD32_GPT_USE_TIM21)
#define GD32_GPT_USE_TIM21 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM21)
#define STM32_ICU_USE_TIM21 FALSE
#if !defined(GD32_ICU_USE_TIM21)
#define GD32_ICU_USE_TIM21 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM21)
#define STM32_PWM_USE_TIM21 FALSE
#if !defined(GD32_PWM_USE_TIM21)
#define GD32_PWM_USE_TIM21 FALSE
#endif
#if !defined(STM32_ST_USE_TIM21)
#define STM32_ST_USE_TIM21 FALSE
#if !defined(GD32_ST_USE_TIM21)
#define GD32_ST_USE_TIM21 FALSE
#endif
#if STM32_HAS_TIM21
#if GD32_HAS_TIM21
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM21_PRIORITY)
#error "STM32_IRQ_TIM21_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM21_PRIORITY)
#error "GD32_IRQ_TIM21_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM21_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM21_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM21_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM21_PRIORITY"
#endif
#endif /* STM32_HAS_TIM21 */
#endif /* GD32_HAS_TIM21 */
/*===========================================================================*/
/* Driver exported variables. */
@ -76,13 +76,13 @@
/*===========================================================================*/
static inline void tim21_irq_init(void) {
#if defined(STM32_TIM21_IS_USED)
eclicEnableVector(GD32_TIM21_NUMBER, STM32_IRQ_TIM21_PRIORITY, STM32_IRQ_TIM21_TRIGGER);
#if defined(GD32_TIM21_IS_USED)
eclicEnableVector(GD32_TIM21_NUMBER, GD32_IRQ_TIM21_PRIORITY, GD32_IRQ_TIM21_TRIGGER);
#endif
}
static inline void tim21_irq_deinit(void) {
#if defined(STM32_TIM21_IS_USED)
#if defined(GD32_TIM21_IS_USED)
eclicDisableVector(GD32_TIM21_NUMBER);
#endif
}
@ -91,7 +91,7 @@ static inline void tim21_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM21_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM21_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM21 interrupt handler.
*
@ -102,22 +102,22 @@ OSAL_IRQ_HANDLER(GD32_TIM21_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM21
#if GD32_GPT_USE_TIM21
gpt_lld_serve_interrupt(&GPTD21);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM21
#if GD32_ICU_USE_TIM21
icu_lld_serve_interrupt(&ICUD21);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM21
#if GD32_PWM_USE_TIM21
pwm_lld_serve_interrupt(&PWMD21);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM21
#if GD32_ST_USE_TIM21
st_lld_serve_interrupt();
#endif
#endif

48
os/hal/ports/GD/GD32VF103/TIM/stm32_tim22.inc
View File

@ -31,37 +31,37 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM22)
#error "STM32_HAS_TIM22 not defined in registry"
#if !defined(GD32_HAS_TIM22)
#error "GD32_HAS_TIM22 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM22)
#define STM32_GPT_USE_TIM22 FALSE
#if !defined(GD32_GPT_USE_TIM22)
#define GD32_GPT_USE_TIM22 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM22)
#define STM32_ICU_USE_TIM22 FALSE
#if !defined(GD32_ICU_USE_TIM22)
#define GD32_ICU_USE_TIM22 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM22)
#define STM32_PWM_USE_TIM22 FALSE
#if !defined(GD32_PWM_USE_TIM22)
#define GD32_PWM_USE_TIM22 FALSE
#endif
#if !defined(STM32_ST_USE_TIM22)
#define STM32_ST_USE_TIM22 FALSE
#if !defined(GD32_ST_USE_TIM22)
#define GD32_ST_USE_TIM22 FALSE
#endif
#if STM32_HAS_TIM22
#if GD32_HAS_TIM22
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM22_PRIORITY)
#error "STM32_IRQ_TIM22_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM22_PRIORITY)
#error "GD32_IRQ_TIM22_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM22_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM22_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM22_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM22_PRIORITY"
#endif
#endif /* STM32_HAS_TIM22 */
#endif /* GD32_HAS_TIM22 */
/*===========================================================================*/
/* Driver exported variables. */
@ -76,13 +76,13 @@
/*===========================================================================*/
static inline void tim22_irq_init(void) {
#if defined(STM32_TIM22_IS_USED)
eclicEnableVector(GD32_TIM22_NUMBER, STM32_IRQ_TIM22_PRIORITY, STM32_IRQ_TIM22_TRIGGER);
#if defined(GD32_TIM22_IS_USED)
eclicEnableVector(GD32_TIM22_NUMBER, GD32_IRQ_TIM22_PRIORITY, GD32_IRQ_TIM22_TRIGGER);
#endif
}
static inline void tim22_irq_deinit(void) {
#if defined(STM32_TIM22_IS_USED)
#if defined(GD32_TIM22_IS_USED)
eclicDisableVector(GD32_TIM22_NUMBER);
#endif
}
@ -91,7 +91,7 @@ static inline void tim22_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM22_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM22_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM22 interrupt handler.
*
@ -102,22 +102,22 @@ OSAL_IRQ_HANDLER(GD32_TIM22_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM22
#if GD32_GPT_USE_TIM22
gpt_lld_serve_interrupt(&GPTD22);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM22
#if GD32_ICU_USE_TIM22
icu_lld_serve_interrupt(&ICUD22);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM22
#if GD32_PWM_USE_TIM22
pwm_lld_serve_interrupt(&PWMD22);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM22
#if GD32_ST_USE_TIM22
st_lld_serve_interrupt();
#endif
#endif

48
os/hal/ports/GD/GD32VF103/TIM/stm32_tim3.inc
View File

@ -31,37 +31,37 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM3)
#error "STM32_HAS_TIM3 not defined in registry"
#if !defined(GD32_HAS_TIM3)
#error "GD32_HAS_TIM3 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM3)
#define STM32_GPT_USE_TIM3 FALSE
#if !defined(GD32_GPT_USE_TIM3)
#define GD32_GPT_USE_TIM3 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM3)
#define STM32_ICU_USE_TIM3 FALSE
#if !defined(GD32_ICU_USE_TIM3)
#define GD32_ICU_USE_TIM3 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM3)
#define STM32_PWM_USE_TIM3 FALSE
#if !defined(GD32_PWM_USE_TIM3)
#define GD32_PWM_USE_TIM3 FALSE
#endif
#if !defined(STM32_ST_USE_TIM3)
#define STM32_ST_USE_TIM3 FALSE
#if !defined(GD32_ST_USE_TIM3)
#define GD32_ST_USE_TIM3 FALSE
#endif
#if STM32_HAS_TIM3
#if GD32_HAS_TIM3
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM3_PRIORITY)
#error "STM32_IRQ_TIM3_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM3_PRIORITY)
#error "GD32_IRQ_TIM3_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM3_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM3_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM3_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM3_PRIORITY"
#endif
#endif /* STM32_HAS_TIM3 */
#endif /* GD32_HAS_TIM3 */
/*===========================================================================*/
/* Driver exported variables. */
@ -76,13 +76,13 @@
/*===========================================================================*/
static inline void tim3_irq_init(void) {
#if defined(STM32_TIM3_IS_USED)
eclicEnableVector(GD32_TIM3_NUMBER, STM32_IRQ_TIM3_PRIORITY, STM32_IRQ_TIM3_TRIGGER);
#if defined(GD32_TIM3_IS_USED)
eclicEnableVector(GD32_TIM3_NUMBER, GD32_IRQ_TIM3_PRIORITY, GD32_IRQ_TIM3_TRIGGER);
#endif
}
static inline void tim3_irq_deinit(void) {
#if defined(STM32_TIM3_IS_USED)
#if defined(GD32_TIM3_IS_USED)
eclicDisableVector(GD32_TIM3_NUMBER);
#endif
}
@ -91,7 +91,7 @@ static inline void tim3_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM3_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM3_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM3 interrupt handler.
*
@ -102,22 +102,22 @@ OSAL_IRQ_HANDLER(GD32_TIM3_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM3
#if GD32_GPT_USE_TIM3
gpt_lld_serve_interrupt(&GPTD3);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM3
#if GD32_ICU_USE_TIM3
icu_lld_serve_interrupt(&ICUD3);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM3
#if GD32_PWM_USE_TIM3
pwm_lld_serve_interrupt(&PWMD3);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM3
#if GD32_ST_USE_TIM3
st_lld_serve_interrupt();
#endif
#endif

48
os/hal/ports/GD/GD32VF103/TIM/stm32_tim4.inc
View File

@ -31,37 +31,37 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM4)
#error "STM32_HAS_TIM4 not defined in registry"
#if !defined(GD32_HAS_TIM4)
#error "GD32_HAS_TIM4 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM4)
#define STM32_GPT_USE_TIM4 FALSE
#if !defined(GD32_GPT_USE_TIM4)
#define GD32_GPT_USE_TIM4 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM4)
#define STM32_ICU_USE_TIM4 FALSE
#if !defined(GD32_ICU_USE_TIM4)
#define GD32_ICU_USE_TIM4 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM4)
#define STM32_PWM_USE_TIM4 FALSE
#if !defined(GD32_PWM_USE_TIM4)
#define GD32_PWM_USE_TIM4 FALSE
#endif
#if !defined(STM32_ST_USE_TIM4)
#define STM32_ST_USE_TIM4 FALSE
#if !defined(GD32_ST_USE_TIM4)
#define GD32_ST_USE_TIM4 FALSE
#endif
#if STM32_HAS_TIM4
#if GD32_HAS_TIM4
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM4_PRIORITY)
#error "STM32_IRQ_TIM4_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM4_PRIORITY)
#error "GD32_IRQ_TIM4_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM4_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM4_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM4_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM4_PRIORITY"
#endif
#endif /* STM32_HAS_TIM4 */
#endif /* GD32_HAS_TIM4 */
/*===========================================================================*/
/* Driver exported variables. */
@ -76,13 +76,13 @@
/*===========================================================================*/
static inline void tim4_irq_init(void) {
#if defined(STM32_TIM4_IS_USED)
eclicEnableVector(GD32_TIM4_NUMBER, STM32_IRQ_TIM4_PRIORITY, STM32_IRQ_TIM4_TRIGGER);
#if defined(GD32_TIM4_IS_USED)
eclicEnableVector(GD32_TIM4_NUMBER, GD32_IRQ_TIM4_PRIORITY, GD32_IRQ_TIM4_TRIGGER);
#endif
}
static inline void tim4_irq_deinit(void) {
#if defined(STM32_TIM4_IS_USED)
#if defined(GD32_TIM4_IS_USED)
eclicDisableVector(GD32_TIM4_NUMBER);
#endif
}
@ -91,7 +91,7 @@ static inline void tim4_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM4_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM4_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM4 interrupt handler.
*
@ -102,22 +102,22 @@ OSAL_IRQ_HANDLER(GD32_TIM4_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM4
#if GD32_GPT_USE_TIM4
gpt_lld_serve_interrupt(&GPTD4);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM4
#if GD32_ICU_USE_TIM4
icu_lld_serve_interrupt(&ICUD4);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM4
#if GD32_PWM_USE_TIM4
pwm_lld_serve_interrupt(&PWMD4);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM4
#if GD32_ST_USE_TIM4
st_lld_serve_interrupt();
#endif
#endif

48
os/hal/ports/GD/GD32VF103/TIM/stm32_tim5.inc
View File

@ -31,37 +31,37 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM5)
#error "STM32_HAS_TIM5 not defined in registry"
#if !defined(GD32_HAS_TIM5)
#error "GD32_HAS_TIM5 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM5)
#define STM32_GPT_USE_TIM5 FALSE
#if !defined(GD32_GPT_USE_TIM5)
#define GD32_GPT_USE_TIM5 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM5)
#define STM32_ICU_USE_TIM5 FALSE
#if !defined(GD32_ICU_USE_TIM5)
#define GD32_ICU_USE_TIM5 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM5)
#define STM32_PWM_USE_TIM5 FALSE
#if !defined(GD32_PWM_USE_TIM5)
#define GD32_PWM_USE_TIM5 FALSE
#endif
#if !defined(STM32_ST_USE_TIM5)
#define STM32_ST_USE_TIM5 FALSE
#if !defined(GD32_ST_USE_TIM5)
#define GD32_ST_USE_TIM5 FALSE
#endif
#if STM32_HAS_TIM5
#if GD32_HAS_TIM5
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM5_PRIORITY)
#error "STM32_IRQ_TIM5_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM5_PRIORITY)
#error "GD32_IRQ_TIM5_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM5_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM5_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM5_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM5_PRIORITY"
#endif
#endif /* STM32_HAS_TIM5 */
#endif /* GD32_HAS_TIM5 */
/*===========================================================================*/
/* Driver exported variables. */
@ -76,13 +76,13 @@
/*===========================================================================*/
static inline void tim5_irq_init(void) {
#if defined(STM32_TIM5_IS_USED)
eclicEnableVector(GD32_TIM5_NUMBER, STM32_IRQ_TIM5_PRIORITY, STM32_IRQ_TIM5_TRIGGER);
#if defined(GD32_TIM5_IS_USED)
eclicEnableVector(GD32_TIM5_NUMBER, GD32_IRQ_TIM5_PRIORITY, GD32_IRQ_TIM5_TRIGGER);
#endif
}
static inline void tim5_irq_deinit(void) {
#if defined(STM32_TIM5_IS_USED)
#if defined(GD32_TIM5_IS_USED)
eclicDisableVector(GD32_TIM5_NUMBER);
#endif
}
@ -91,7 +91,7 @@ static inline void tim5_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM5_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM5_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM5 interrupt handler.
*
@ -102,22 +102,22 @@ OSAL_IRQ_HANDLER(GD32_TIM5_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM5
#if GD32_GPT_USE_TIM5
gpt_lld_serve_interrupt(&GPTD5);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM5
#if GD32_ICU_USE_TIM5
icu_lld_serve_interrupt(&ICUD5);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM5
#if GD32_PWM_USE_TIM5
pwm_lld_serve_interrupt(&PWMD5);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM5
#if GD32_ST_USE_TIM5
st_lld_serve_interrupt();
#endif
#endif

48
os/hal/ports/GD/GD32VF103/TIM/stm32_tim6.inc
View File

@ -31,37 +31,37 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM6)
#error "STM32_HAS_TIM6 not defined in registry"
#if !defined(GD32_HAS_TIM6)
#error "GD32_HAS_TIM6 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM6)
#define STM32_GPT_USE_TIM6 FALSE
#if !defined(GD32_GPT_USE_TIM6)
#define GD32_GPT_USE_TIM6 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM6)
#define STM32_ICU_USE_TIM6 FALSE
#if !defined(GD32_ICU_USE_TIM6)
#define GD32_ICU_USE_TIM6 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM6)
#define STM32_PWM_USE_TIM6 FALSE
#if !defined(GD32_PWM_USE_TIM6)
#define GD32_PWM_USE_TIM6 FALSE
#endif
#if !defined(STM32_ST_USE_TIM6)
#define STM32_ST_USE_TIM6 FALSE
#if !defined(GD32_ST_USE_TIM6)
#define GD32_ST_USE_TIM6 FALSE
#endif
#if STM32_HAS_TIM6
#if GD32_HAS_TIM6
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM6_PRIORITY)
#error "STM32_IRQ_TIM6_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM6_PRIORITY)
#error "GD32_IRQ_TIM6_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM6_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM6_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM6_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM6_PRIORITY"
#endif
#endif /* STM32_HAS_TIM6 */
#endif /* GD32_HAS_TIM6 */
/*===========================================================================*/
/* Driver exported variables. */
@ -76,13 +76,13 @@
/*===========================================================================*/
static inline void tim6_irq_init(void) {
#if defined(STM32_TIM6_IS_USED)
eclicEnableVector(GD32_TIM6_NUMBER, STM32_IRQ_TIM6_PRIORITY, STM32_IRQ_TIM6_TRIGGER);
#if defined(GD32_TIM6_IS_USED)
eclicEnableVector(GD32_TIM6_NUMBER, GD32_IRQ_TIM6_PRIORITY, GD32_IRQ_TIM6_TRIGGER);
#endif
}
static inline void tim6_irq_deinit(void) {
#if defined(STM32_TIM6_IS_USED)
#if defined(GD32_TIM6_IS_USED)
eclicDisableVector(GD32_TIM6_NUMBER);
#endif
}
@ -91,7 +91,7 @@ static inline void tim6_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM6_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM6_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM6 interrupt handler.
*
@ -102,22 +102,22 @@ OSAL_IRQ_HANDLER(GD32_TIM6_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM6
#if GD32_GPT_USE_TIM6
gpt_lld_serve_interrupt(&GPTD6);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM6
#if GD32_ICU_USE_TIM6
icu_lld_serve_interrupt(&ICUD6);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM6
#if GD32_PWM_USE_TIM6
pwm_lld_serve_interrupt(&PWMD6);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM6
#if GD32_ST_USE_TIM6
st_lld_serve_interrupt();
#endif
#endif

48
os/hal/ports/GD/GD32VF103/TIM/stm32_tim7.inc
View File

@ -31,37 +31,37 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM7)
#error "STM32_HAS_TIM7 not defined in registry"
#if !defined(GD32_HAS_TIM7)
#error "GD32_HAS_TIM7 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM7)
#define STM32_GPT_USE_TIM7 FALSE
#if !defined(GD32_GPT_USE_TIM7)
#define GD32_GPT_USE_TIM7 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM7)
#define STM32_ICU_USE_TIM7 FALSE
#if !defined(GD32_ICU_USE_TIM7)
#define GD32_ICU_USE_TIM7 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM7)
#define STM32_PWM_USE_TIM7 FALSE
#if !defined(GD32_PWM_USE_TIM7)
#define GD32_PWM_USE_TIM7 FALSE
#endif
#if !defined(STM32_ST_USE_TIM7)
#define STM32_ST_USE_TIM7 FALSE
#if !defined(GD32_ST_USE_TIM7)
#define GD32_ST_USE_TIM7 FALSE
#endif
#if STM32_HAS_TIM7
#if GD32_HAS_TIM7
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM7_PRIORITY)
#error "STM32_IRQ_TIM7_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM7_PRIORITY)
#error "GD32_IRQ_TIM7_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM7_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM7_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM7_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM7_PRIORITY"
#endif
#endif /* STM32_HAS_TIM7 */
#endif /* GD32_HAS_TIM7 */
/*===========================================================================*/
/* Driver exported variables. */
@ -76,13 +76,13 @@
/*===========================================================================*/
static inline void tim7_irq_init(void) {
#if defined(STM32_TIM7_IS_USED)
eclicEnableVector(GD32_TIM7_NUMBER, STM32_IRQ_TIM7_PRIORITY, STM32_IRQ_TIM7_TRIGGER);
#if defined(GD32_TIM7_IS_USED)
eclicEnableVector(GD32_TIM7_NUMBER, GD32_IRQ_TIM7_PRIORITY, GD32_IRQ_TIM7_TRIGGER);
#endif
}
static inline void tim7_irq_deinit(void) {
#if defined(STM32_TIM7_IS_USED)
#if defined(GD32_TIM7_IS_USED)
eclicDisableVector(GD32_TIM7_NUMBER);
#endif
}
@ -91,7 +91,7 @@ static inline void tim7_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM7_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM7_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM7 interrupt handler.
*
@ -102,22 +102,22 @@ OSAL_IRQ_HANDLER(GD32_TIM7_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM7
#if GD32_GPT_USE_TIM7
gpt_lld_serve_interrupt(&GPTD7);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM7
#if GD32_ICU_USE_TIM7
icu_lld_serve_interrupt(&ICUD7);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM7
#if GD32_PWM_USE_TIM7
pwm_lld_serve_interrupt(&PWMD7);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM7
#if GD32_ST_USE_TIM7
st_lld_serve_interrupt();
#endif
#endif

62
os/hal/ports/GD/GD32VF103/TIM/stm32_tim8.inc
View File

@ -31,45 +31,45 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM8)
#error "STM32_HAS_TIM8 not defined in registry"
#if !defined(GD32_HAS_TIM8)
#error "GD32_HAS_TIM8 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM8)
#define STM32_GPT_USE_TIM8 FALSE
#if !defined(GD32_GPT_USE_TIM8)
#define GD32_GPT_USE_TIM8 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM8)
#define STM32_ICU_USE_TIM8 FALSE
#if !defined(GD32_ICU_USE_TIM8)
#define GD32_ICU_USE_TIM8 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM8)
#define STM32_PWM_USE_TIM8 FALSE
#if !defined(GD32_PWM_USE_TIM8)
#define GD32_PWM_USE_TIM8 FALSE
#endif
#if !defined(STM32_ST_USE_TIM8)
#define STM32_ST_USE_TIM8 FALSE
#if !defined(GD32_ST_USE_TIM8)
#define GD32_ST_USE_TIM8 FALSE
#endif
#if STM32_HAS_TIM8
#if GD32_HAS_TIM8
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM8_UP_PRIORITY)
#error "STM32_IRQ_TIM8_UP_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM8_UP_PRIORITY)
#error "GD32_IRQ_TIM8_UP_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(STM32_IRQ_TIM8_CC_PRIORITY)
#error "STM32_IRQ_TIM8_CC_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM8_CC_PRIORITY)
#error "GD32_IRQ_TIM8_CC_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_UP_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM8_UP_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM8_UP_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM8_UP_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_CC_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM8_CC_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM8_CC_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM8_CC_PRIORITY"
#endif
#endif /* STM32_HAS_TIM8 */
#endif /* GD32_HAS_TIM8 */
/*===========================================================================*/
/* Driver exported variables. */
@ -84,14 +84,14 @@
/*===========================================================================*/
static inline void tim8_irq_init(void) {
#if defined(STM32_TIM8_IS_USED)
eclicEnableVector(GD32_TIM8_UP_NUMBER, STM32_IRQ_TIM8_UP_PRIORITY, STM32_IRQ_TIM8_UP_TRIGGER);
eclicEnableVector(GD32_TIM8_CC_NUMBER, STM32_IRQ_TIM8_CC_PRIORITY, STM32_IRQ_TIM8_CC_TRIGGER);
#if defined(GD32_TIM8_IS_USED)
eclicEnableVector(GD32_TIM8_UP_NUMBER, GD32_IRQ_TIM8_UP_PRIORITY, GD32_IRQ_TIM8_UP_TRIGGER);
eclicEnableVector(GD32_TIM8_CC_NUMBER, GD32_IRQ_TIM8_CC_PRIORITY, GD32_IRQ_TIM8_CC_TRIGGER);
#endif
}
static inline void tim8_irq_deinit(void) {
#if defined(STM32_TIM8_IS_USED)
#if defined(GD32_TIM8_IS_USED)
eclicDisableVector(GD32_TIM8_UP_NUMBER);
eclicDisableVector(GD32_TIM8_CC_NUMBER);
#endif
@ -101,7 +101,7 @@ static inline void tim8_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM8_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM8_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM8-UP interrupt handler.
*
@ -112,22 +112,22 @@ OSAL_IRQ_HANDLER(GD32_TIM8_UP_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM8
#if GD32_GPT_USE_TIM8
gpt_lld_serve_interrupt(&GPTD8);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM8
#if GD32_ICU_USE_TIM8
icu_lld_serve_interrupt(&ICUD8);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM8
#if GD32_PWM_USE_TIM8
pwm_lld_serve_interrupt(&PWMD8);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM8
#if GD32_ST_USE_TIM8
st_lld_serve_interrupt();
#endif
#endif
@ -148,12 +148,12 @@ OSAL_IRQ_HANDLER(GD32_TIM8_CC_HANDLER) {
/* Not used by GPT.*/
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM8
#if GD32_ICU_USE_TIM8
icu_lld_serve_interrupt(&ICUD8);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM8
#if GD32_PWM_USE_TIM8
pwm_lld_serve_interrupt(&PWMD8);
#endif
#endif

184
os/hal/ports/GD/GD32VF103/TIM/stm32_tim8_12_13_14.inc
View File

@ -31,112 +31,112 @@
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(STM32_HAS_TIM8)
#error "STM32_HAS_TIM8 not defined in registry"
#if !defined(GD32_HAS_TIM8)
#error "GD32_HAS_TIM8 not defined in registry"
#endif
#if !defined(STM32_HAS_TIM12)
#error "STM32_HAS_TIM12 not defined in registry"
#if !defined(GD32_HAS_TIM12)
#error "GD32_HAS_TIM12 not defined in registry"
#endif
#if !defined(STM32_HAS_TIM13)
#error "STM32_HAS_TIM13 not defined in registry"
#if !defined(GD32_HAS_TIM13)
#error "GD32_HAS_TIM13 not defined in registry"
#endif
#if !defined(STM32_HAS_TIM14)
#error "STM32_HAS_TIM14 not defined in registry"
#if !defined(GD32_HAS_TIM14)
#error "GD32_HAS_TIM14 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(STM32_GPT_USE_TIM8)
#define STM32_GPT_USE_TIM8 FALSE
#if !defined(GD32_GPT_USE_TIM8)
#define GD32_GPT_USE_TIM8 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM8)
#define STM32_ICU_USE_TIM8 FALSE
#if !defined(GD32_ICU_USE_TIM8)
#define GD32_ICU_USE_TIM8 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM8)
#define STM32_PWM_USE_TIM8 FALSE
#if !defined(GD32_PWM_USE_TIM8)
#define GD32_PWM_USE_TIM8 FALSE
#endif
#if !defined(STM32_ST_USE_TIM8)
#define STM32_ST_USE_TIM8 FALSE
#if !defined(GD32_ST_USE_TIM8)
#define GD32_ST_USE_TIM8 FALSE
#endif
#if !defined(STM32_GPT_USE_TIM12)
#define STM32_GPT_USE_TIM12 FALSE
#if !defined(GD32_GPT_USE_TIM12)
#define GD32_GPT_USE_TIM12 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM12)
#define STM32_ICU_USE_TIM12 FALSE
#if !defined(GD32_ICU_USE_TIM12)
#define GD32_ICU_USE_TIM12 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM12)
#define STM32_PWM_USE_TIM12 FALSE
#if !defined(GD32_PWM_USE_TIM12)
#define GD32_PWM_USE_TIM12 FALSE
#endif
#if !defined(STM32_ST_USE_TIM12)
#define STM32_ST_USE_TIM12 FALSE
#if !defined(GD32_ST_USE_TIM12)
#define GD32_ST_USE_TIM12 FALSE
#endif
#if !defined(STM32_GPT_USE_TIM13)
#define STM32_GPT_USE_TIM13 FALSE
#if !defined(GD32_GPT_USE_TIM13)
#define GD32_GPT_USE_TIM13 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM13)
#define STM32_ICU_USE_TIM13 FALSE
#if !defined(GD32_ICU_USE_TIM13)
#define GD32_ICU_USE_TIM13 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM13)
#define STM32_PWM_USE_TIM13 FALSE
#if !defined(GD32_PWM_USE_TIM13)
#define GD32_PWM_USE_TIM13 FALSE
#endif
#if !defined(STM32_ST_USE_TIM13)
#define STM32_ST_USE_TIM13 FALSE
#if !defined(GD32_ST_USE_TIM13)
#define GD32_ST_USE_TIM13 FALSE
#endif
#if !defined(STM32_GPT_USE_TIM14)
#define STM32_GPT_USE_TIM14 FALSE
#if !defined(GD32_GPT_USE_TIM14)
#define GD32_GPT_USE_TIM14 FALSE
#endif
#if !defined(STM32_ICU_USE_TIM14)
#define STM32_ICU_USE_TIM14 FALSE
#if !defined(GD32_ICU_USE_TIM14)
#define GD32_ICU_USE_TIM14 FALSE
#endif
#if !defined(STM32_PWM_USE_TIM14)
#define STM32_PWM_USE_TIM14 FALSE
#if !defined(GD32_PWM_USE_TIM14)
#define GD32_PWM_USE_TIM14 FALSE
#endif
#if !defined(STM32_ST_USE_TIM14)
#define STM32_ST_USE_TIM14 FALSE
#if !defined(GD32_ST_USE_TIM14)
#define GD32_ST_USE_TIM14 FALSE
#endif
#if STM32_HAS_TIM8 || STM32_HAS_TIM12 || STM32_HAS_TIM13 || STM32_HAS_TIM14
#if GD32_HAS_TIM8 || GD32_HAS_TIM12 || GD32_HAS_TIM13 || GD32_HAS_TIM14
/* Priority settings checks.*/
#if !defined(STM32_IRQ_TIM8_BRK_TIM12_PRIORITY)
#error "STM32_IRQ_TIM8_BRK_TIM12_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM8_BRK_TIM12_PRIORITY)
#error "GD32_IRQ_TIM8_BRK_TIM12_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(STM32_IRQ_TIM8_UP_TIM13_PRIORITY)
#error "STM32_IRQ_TIM8_UP_TIM13_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM8_UP_TIM13_PRIORITY)
#error "GD32_IRQ_TIM8_UP_TIM13_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY)
#error "STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM8_TRGCO_TIM14_PRIORITY)
#error "GD32_IRQ_TIM8_TRGCO_TIM14_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(STM32_IRQ_TIM8_CC_PRIORITY)
#error "STM32_IRQ_TIM8_CC_PRIORITY not defined in mcuconf.h"
#if !defined(GD32_IRQ_TIM8_CC_PRIORITY)
#error "GD32_IRQ_TIM8_CC_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_BRK_TIM12_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM8_BRK_TIM12_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM8_BRK_TIM12_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM8_BRK_TIM12_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_UP_TIM13_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM8_UP_TIM13_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM8_UP_TIM13_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM8_UP_TIM13_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM8_TRGCO_TIM14_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM8_TRGCO_TIM14_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_CC_PRIORITY)
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM8_CC_PRIORITY"
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM8_CC_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM8_CC_PRIORITY"
#endif
#endif /* STM32_HAS_TIM8 || STM32_HAS_TIM12 || STM32_HAS_TIM13 || STM32_HAS_TIM14 */
#endif /* GD32_HAS_TIM8 || GD32_HAS_TIM12 || GD32_HAS_TIM13 || GD32_HAS_TIM14 */
/*===========================================================================*/
/* Driver exported variables. */
@ -151,35 +151,35 @@
/*===========================================================================*/
static inline void tim8_tim12_tim13_tim14_irq_init(void) {
#if defined(STM32_TIM8_IS_USED) || defined(STM32_TIM12_IS_USED)
#if defined(GD32_TIM8_IS_USED) || defined(GD32_TIM12_IS_USED)
nvicEnableVector(GD32_TIM8_BRK_TIM12_NUMBER,
STM32_IRQ_TIM8_BRK_TIM12_PRIORITY);
GD32_IRQ_TIM8_BRK_TIM12_PRIORITY);
#endif
#if defined(STM32_TIM8_IS_USED) || defined(STM32_TIM13_IS_USED)
#if defined(GD32_TIM8_IS_USED) || defined(GD32_TIM13_IS_USED)
nvicEnableVector(GD32_TIM8_UP_TIM13_NUMBER,
STM32_IRQ_TIM8_UP_TIM13_PRIORITY);
GD32_IRQ_TIM8_UP_TIM13_PRIORITY);
#endif
#if defined(STM32_TIM8_IS_USED) || defined(STM32_TIM14_IS_USED)
#if defined(GD32_TIM8_IS_USED) || defined(GD32_TIM14_IS_USED)
nvicEnableVector(GD32_TIM8_TRGCO_TIM14_NUMBER,
STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY);
GD32_IRQ_TIM8_TRGCO_TIM14_PRIORITY);
#endif
#if defined(STM32_TIM8_IS_USED)
#if defined(GD32_TIM8_IS_USED)
nvicEnableVector(GD32_TIM8_CC_NUMBER,
STM32_IRQ_TIM8_CC_PRIORITY);
GD32_IRQ_TIM8_CC_PRIORITY);
#endif
}
static inline void tim8_tim12_tim13_tim14_irq_deinit(void) {
#if defined(STM32_TIM8_IS_USED) || defined(STM32_TIM12_IS_USED)
#if defined(GD32_TIM8_IS_USED) || defined(GD32_TIM12_IS_USED)
eclicDisableVector(GD32_TIM8_BRK_TIM12_NUMBER);
#endif
#if defined(STM32_TIM8_IS_USED) || defined(STM32_TIM13_IS_USED)
#if defined(GD32_TIM8_IS_USED) || defined(GD32_TIM13_IS_USED)
eclicDisableVector(GD32_TIM8_UP_TIM13_NUMBER);
#endif
#if defined(STM32_TIM8_IS_USED) || defined(STM32_TIM14_IS_USED)
#if defined(GD32_TIM8_IS_USED) || defined(GD32_TIM14_IS_USED)
eclicDisableVector(GD32_TIM8_TRGCO_TIM14_NUMBER);
#endif
#if defined(STM32_TIM8_IS_USED)
#if defined(GD32_TIM8_IS_USED)
eclicDisableVector(GD32_TIM8_CC_NUMBER);
#endif
}
@ -188,7 +188,7 @@ static inline void tim8_tim12_tim13_tim14_irq_deinit(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_TIM8_IS_USED) || defined(STM32_TIM12_IS_USED) || \
#if defined(GD32_TIM8_IS_USED) || defined(GD32_TIM12_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM8-BRK, TIM12 interrupt handler.
@ -200,22 +200,22 @@ OSAL_IRQ_HANDLER(GD32_TIM8_BRK_TIM12_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM12
#if GD32_GPT_USE_TIM12
gpt_lld_serve_interrupt(&GPTD12);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM12
#if GD32_ICU_USE_TIM12
icu_lld_serve_interrupt(&ICUD12);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM12
#if GD32_PWM_USE_TIM12
pwm_lld_serve_interrupt(&PWMD12);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM12
#if GD32_ST_USE_TIM12
st_lld_serve_interrupt();
#endif
#endif
@ -224,7 +224,7 @@ OSAL_IRQ_HANDLER(GD32_TIM8_BRK_TIM12_HANDLER) {
}
#endif
#if defined(STM32_TIM8_IS_USED) || defined(STM32_TIM13_IS_USED) || \
#if defined(GD32_TIM8_IS_USED) || defined(GD32_TIM13_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM8-UP, TIM13 interrupt handler.
@ -236,34 +236,34 @@ OSAL_IRQ_HANDLER(GD32_TIM8_UP_TIM13_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM8
#if GD32_GPT_USE_TIM8
gpt_lld_serve_interrupt(&GPTD8);
#endif
#if STM32_GPT_USE_TIM13
#if GD32_GPT_USE_TIM13
gpt_lld_serve_interrupt(&GPTD13);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM8
#if GD32_ICU_USE_TIM8
icu_lld_serve_interrupt(&ICUD8);
#endif
#if STM32_ICU_USE_TIM13
#if GD32_ICU_USE_TIM13
icu_lld_serve_interrupt(&ICUD13);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM8
#if GD32_PWM_USE_TIM8
pwm_lld_serve_interrupt(&PWMD8);
#endif
#if STM32_PWM_USE_TIM13
#if GD32_PWM_USE_TIM13
pwm_lld_serve_interrupt(&PWMD13);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM8
#if GD32_ST_USE_TIM8
st_lld_serve_interrupt();
#endif
#if STM32_ST_USE_TIM13
#if GD32_ST_USE_TIM13
st_lld_serve_interrupt();
#endif
#endif
@ -272,7 +272,7 @@ OSAL_IRQ_HANDLER(GD32_TIM8_UP_TIM13_HANDLER) {
}
#endif
#if defined(STM32_TIM8_IS_USED) || defined(STM32_TIM14_IS_USED) || \
#if defined(GD32_TIM8_IS_USED) || defined(GD32_TIM14_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM8-TRG-COM, TIM14 interrupt handler.
@ -284,22 +284,22 @@ OSAL_IRQ_HANDLER(GD32_TIM8_TRGCO_TIM14_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if STM32_GPT_USE_TIM14
#if GD32_GPT_USE_TIM14
gpt_lld_serve_interrupt(&GPTD14);
#endif
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM14
#if GD32_ICU_USE_TIM14
icu_lld_serve_interrupt(&ICUD14);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM14
#if GD32_PWM_USE_TIM14
pwm_lld_serve_interrupt(&PWMD14);
#endif
#endif
#if 1
#if STM32_ST_USE_TIM14
#if GD32_ST_USE_TIM14
st_lld_serve_interrupt();
#endif
#endif
@ -308,7 +308,7 @@ OSAL_IRQ_HANDLER(GD32_TIM8_TRGCO_TIM14_HANDLER) {
}
#endif
#if defined(STM32_TIM8_IS_USED) || defined(__DOXYGEN__)
#if defined(GD32_TIM8_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM8-CC interrupt handler.
*
@ -322,12 +322,12 @@ OSAL_IRQ_HANDLER(GD32_TIM8_CC_HANDLER) {
/* Not used by GPT.*/
#endif
#if HAL_USE_ICU
#if STM32_ICU_USE_TIM8
#if GD32_ICU_USE_TIM8
icu_lld_serve_interrupt(&ICUD8);
#endif
#endif
#if HAL_USE_PWM
#if STM32_PWM_USE_TIM8
#if GD32_PWM_USE_TIM8
pwm_lld_serve_interrupt(&PWMD8);
#endif
#endif

118
os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.c
View File

@ -35,42 +35,42 @@
/*===========================================================================*/
/** @brief USART1 serial driver identifier.*/
#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
SerialDriver SD1;
#endif
/** @brief USART2 serial driver identifier.*/
#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
SerialDriver SD2;
#endif
/** @brief USART3 serial driver identifier.*/
#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
SerialDriver SD3;
#endif
/** @brief UART4 serial driver identifier.*/
#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
SerialDriver SD4;
#endif
/** @brief UART5 serial driver identifier.*/
#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
SerialDriver SD5;
#endif
/** @brief USART6 serial driver identifier.*/
#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
SerialDriver SD6;
#endif
/** @brief UART7 serial driver identifier.*/
#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
SerialDriver SD7;
#endif
/** @brief UART8 serial driver identifier.*/
#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
SerialDriver SD8;
#endif
@ -103,14 +103,14 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
USART_TypeDef *u = sdp->usart;
/* Baud rate setting.*/
#if STM32_HAS_USART6
#if GD32_HAS_USART6
if ((sdp->usart == USART1) || (sdp->usart == USART6))
#else
if (sdp->usart == USART1)
#endif
fck = STM32_PCLK2 / config->speed;
fck = GD32_PCLK2 / config->speed;
else
fck = STM32_PCLK1 / config->speed;
fck = GD32_PCLK1 / config->speed;
/* Correcting USARTDIV when oversampling by 8 instead of 16.
Fraction is still 4 bits wide, but only lower 3 bits used.
@ -233,7 +233,7 @@ static void serve_interrupt(SerialDriver *sdp) {
}
}
#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
static void notify1(io_queue_t *qp) {
(void)qp;
@ -241,7 +241,7 @@ static void notify1(io_queue_t *qp) {
}
#endif
#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
static void notify2(io_queue_t *qp) {
(void)qp;
@ -249,7 +249,7 @@ static void notify2(io_queue_t *qp) {
}
#endif
#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
static void notify3(io_queue_t *qp) {
(void)qp;
@ -257,7 +257,7 @@ static void notify3(io_queue_t *qp) {
}
#endif
#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
static void notify4(io_queue_t *qp) {
(void)qp;
@ -265,7 +265,7 @@ static void notify4(io_queue_t *qp) {
}
#endif
#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
static void notify5(io_queue_t *qp) {
(void)qp;
@ -273,7 +273,7 @@ static void notify5(io_queue_t *qp) {
}
#endif
#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
static void notify6(io_queue_t *qp) {
(void)qp;
@ -281,7 +281,7 @@ static void notify6(io_queue_t *qp) {
}
#endif
#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
static void notify7(io_queue_t *qp) {
(void)qp;
@ -289,7 +289,7 @@ static void notify7(io_queue_t *qp) {
}
#endif
#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
static void notify8(io_queue_t *qp) {
(void)qp;
@ -301,7 +301,7 @@ static void notify8(io_queue_t *qp) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
#if !defined(GD32_USART1_HANDLER)
#error "GD32_USART1_HANDLER not defined"
#endif
@ -320,7 +320,7 @@ OSAL_IRQ_HANDLER(GD32_USART1_HANDLER) {
}
#endif
#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
#if !defined(GD32_USART2_HANDLER)
#error "GD32_USART2_HANDLER not defined"
#endif
@ -339,7 +339,7 @@ OSAL_IRQ_HANDLER(GD32_USART2_HANDLER) {
}
#endif
#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
#if !defined(GD32_USART3_HANDLER)
#error "GD32_USART3_HANDLER not defined"
#endif
@ -358,7 +358,7 @@ OSAL_IRQ_HANDLER(GD32_USART3_HANDLER) {
}
#endif
#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
#if !defined(GD32_UART4_HANDLER)
#error "GD32_UART4_HANDLER not defined"
#endif
@ -377,7 +377,7 @@ OSAL_IRQ_HANDLER(GD32_UART4_HANDLER) {
}
#endif
#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
#if !defined(GD32_UART5_HANDLER)
#error "GD32_UART5_HANDLER not defined"
#endif
@ -396,7 +396,7 @@ OSAL_IRQ_HANDLER(GD32_UART5_HANDLER) {
}
#endif
#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
#if !defined(GD32_USART6_HANDLER)
#error "GD32_USART6_HANDLER not defined"
#endif
@ -415,7 +415,7 @@ OSAL_IRQ_HANDLER(GD32_USART6_HANDLER) {
}
#endif
#if STM32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART7 || defined(__DOXYGEN__)
#if !defined(GD32_UART7_HANDLER)
#error "GD32_UART7_HANDLER not defined"
#endif
@ -434,7 +434,7 @@ OSAL_IRQ_HANDLER(GD32_UART7_HANDLER) {
}
#endif
#if STM32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART8 || defined(__DOXYGEN__)
#if !defined(GD32_UART8_HANDLER)
#error "GD32_UART8_HANDLER not defined"
#endif
@ -464,42 +464,42 @@ OSAL_IRQ_HANDLER(GD32_UART8_HANDLER) {
*/
void sd_lld_init(void) {
#if STM32_SERIAL_USE_USART1
#if GD32_SERIAL_USE_USART1
sdObjectInit(&SD1, NULL, notify1);
SD1.usart = USART1;
#endif
#if STM32_SERIAL_USE_USART2
#if GD32_SERIAL_USE_USART2
sdObjectInit(&SD2, NULL, notify2);
SD2.usart = USART2;
#endif
#if STM32_SERIAL_USE_USART3
#if GD32_SERIAL_USE_USART3
sdObjectInit(&SD3, NULL, notify3);
SD3.usart = USART3;
#endif
#if STM32_SERIAL_USE_UART4
#if GD32_SERIAL_USE_UART4
sdObjectInit(&SD4, NULL, notify4);
SD4.usart = UART4;
#endif
#if STM32_SERIAL_USE_UART5
#if GD32_SERIAL_USE_UART5
sdObjectInit(&SD5, NULL, notify5);
SD5.usart = UART5;
#endif
#if STM32_SERIAL_USE_USART6
#if GD32_SERIAL_USE_USART6
sdObjectInit(&SD6, NULL, notify6);
SD6.usart = USART6;
#endif
#if STM32_SERIAL_USE_UART7
#if GD32_SERIAL_USE_UART7
sdObjectInit(&SD7, NULL, notify7);
SD7.usart = UART7;
#endif
#if STM32_SERIAL_USE_UART8
#if GD32_SERIAL_USE_UART8
sdObjectInit(&SD8, NULL, notify8);
SD8.usart = UART8;
#endif
@ -521,52 +521,52 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
config = &default_config;
if (sdp->state == SD_STOP) {
#if STM32_SERIAL_USE_USART1
#if GD32_SERIAL_USE_USART1
if (&SD1 == sdp) {
rccEnableUSART1(true);
eclicEnableVector(GD32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY, STM32_SERIAL_USART1_TRIGGER);
eclicEnableVector(GD32_USART1_NUMBER, GD32_SERIAL_USART1_PRIORITY, GD32_SERIAL_USART1_TRIGGER);
}
#endif
#if STM32_SERIAL_USE_USART2
#if GD32_SERIAL_USE_USART2
if (&SD2 == sdp) {
rccEnableUSART2(true);
eclicEnableVector(GD32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY, STM32_SERIAL_USART2_TRIGGER);
eclicEnableVector(GD32_USART2_NUMBER, GD32_SERIAL_USART2_PRIORITY, GD32_SERIAL_USART2_TRIGGER);
}
#endif
#if STM32_SERIAL_USE_USART3
#if GD32_SERIAL_USE_USART3
if (&SD3 == sdp) {
rccEnableUSART3(true);
eclicEnableVector(GD32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY, STM32_SERIAL_USART3_TRIGGER);
eclicEnableVector(GD32_USART3_NUMBER, GD32_SERIAL_USART3_PRIORITY, GD32_SERIAL_USART3_TRIGGER);
}
#endif
#if STM32_SERIAL_USE_UART4
#if GD32_SERIAL_USE_UART4
if (&SD4 == sdp) {
rccEnableUART4(true);
eclicEnableVector(GD32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY, STM32_SERIAL_UART4_TRIGGER);
eclicEnableVector(GD32_UART4_NUMBER, GD32_SERIAL_UART4_PRIORITY, GD32_SERIAL_UART4_TRIGGER);
}
#endif
#if STM32_SERIAL_USE_UART5
#if GD32_SERIAL_USE_UART5
if (&SD5 == sdp) {
rccEnableUART5(true);
eclicEnableVector(GD32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY, STM32_SERIAL_UART5_TRIGGER);
eclicEnableVector(GD32_UART5_NUMBER, GD32_SERIAL_UART5_PRIORITY, GD32_SERIAL_UART5_TRIGGER);
}
#endif
#if STM32_SERIAL_USE_USART6
#if GD32_SERIAL_USE_USART6
if (&SD6 == sdp) {
rccEnableUSART6(true);
eclicEnableVector(GD32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY, STM32_SERIAL_USART6_TRIGGER);
eclicEnableVector(GD32_USART6_NUMBER, GD32_SERIAL_USART6_PRIORITY, GD32_SERIAL_USART6_TRIGGER);
}
#endif
#if STM32_SERIAL_USE_UART7
#if GD32_SERIAL_USE_UART7
if (&SD7 == sdp) {
rccEnableUART7(true);
eclicEnableVector(GD32_UART7_NUMBER, STM32_SERIAL_UART7_PRIORITY, STM32_SERIAL_UART7_TRIGGER);
eclicEnableVector(GD32_UART7_NUMBER, GD32_SERIAL_UART7_PRIORITY, GD32_SERIAL_UART7_TRIGGER);
}
#endif
#if STM32_SERIAL_USE_UART8
#if GD32_SERIAL_USE_UART8
if (&SD8 == sdp) {
rccEnableUART8(true);
eclicEnableVector(GD32_UART8_NUMBER, STM32_SERIAL_UART8_PRIORITY, STM32_SERIAL_UART8_TRIGGER);
eclicEnableVector(GD32_UART8_NUMBER, GD32_SERIAL_UART8_PRIORITY, GD32_SERIAL_UART8_TRIGGER);
}
#endif
}
@ -586,56 +586,56 @@ void sd_lld_stop(SerialDriver *sdp) {
if (sdp->state == SD_READY) {
usart_deinit(sdp->usart);
#if STM32_SERIAL_USE_USART1
#if GD32_SERIAL_USE_USART1
if (&SD1 == sdp) {
rccDisableUSART1();
eclicDisableVector(GD32_USART1_NUMBER);
return;
}
#endif
#if STM32_SERIAL_USE_USART2
#if GD32_SERIAL_USE_USART2
if (&SD2 == sdp) {
rccDisableUSART2();
eclicDisableVector(GD32_USART2_NUMBER);
return;
}
#endif
#if STM32_SERIAL_USE_USART3
#if GD32_SERIAL_USE_USART3
if (&SD3 == sdp) {
rccDisableUSART3();
eclicDisableVector(GD32_USART3_NUMBER);
return;
}
#endif
#if STM32_SERIAL_USE_UART4
#if GD32_SERIAL_USE_UART4
if (&SD4 == sdp) {
rccDisableUART4();
eclicDisableVector(GD32_UART4_NUMBER);
return;
}
#endif
#if STM32_SERIAL_USE_UART5
#if GD32_SERIAL_USE_UART5
if (&SD5 == sdp) {
rccDisableUART5();
eclicDisableVector(GD32_UART5_NUMBER);
return;
}
#endif
#if STM32_SERIAL_USE_USART6
#if GD32_SERIAL_USE_USART6
if (&SD6 == sdp) {
rccDisableUSART6();
eclicDisableVector(GD32_USART6_NUMBER);
return;
}
#endif
#if STM32_SERIAL_USE_UART7
#if GD32_SERIAL_USE_UART7
if (&SD7 == sdp) {
rccDisableUART7();
eclicDisableVector(GD32_UART7_NUMBER);
return;
}
#endif
#if STM32_SERIAL_USE_UART8
#if GD32_SERIAL_USE_UART8
if (&SD8 == sdp) {
rccDisableUART8();
eclicDisableVector(GD32_UART8_NUMBER);

136
os/hal/ports/GD/GD32VF103/USART/hal_serial_lld.h
View File

@ -44,8 +44,8 @@
* @details If set to @p TRUE the support for USART1 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_USART1 FALSE
#if !defined(GD32_SERIAL_USE_USART1) || defined(__DOXYGEN__)
#define GD32_SERIAL_USE_USART1 FALSE
#endif
/**
@ -53,8 +53,8 @@
* @details If set to @p TRUE the support for USART2 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_USART2 FALSE
#if !defined(GD32_SERIAL_USE_USART2) || defined(__DOXYGEN__)
#define GD32_SERIAL_USE_USART2 FALSE
#endif
/**
@ -62,8 +62,8 @@
* @details If set to @p TRUE the support for USART3 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_USART3 FALSE
#if !defined(GD32_SERIAL_USE_USART3) || defined(__DOXYGEN__)
#define GD32_SERIAL_USE_USART3 FALSE
#endif
/**
@ -71,8 +71,8 @@
* @details If set to @p TRUE the support for UART4 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_UART4 FALSE
#if !defined(GD32_SERIAL_USE_UART4) || defined(__DOXYGEN__)
#define GD32_SERIAL_USE_UART4 FALSE
#endif
/**
@ -80,8 +80,8 @@
* @details If set to @p TRUE the support for UART5 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_UART5 FALSE
#if !defined(GD32_SERIAL_USE_UART5) || defined(__DOXYGEN__)
#define GD32_SERIAL_USE_UART5 FALSE
#endif
/**
@ -89,8 +89,8 @@
* @details If set to @p TRUE the support for USART6 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_USART6 FALSE
#if !defined(GD32_SERIAL_USE_USART6) || defined(__DOXYGEN__)
#define GD32_SERIAL_USE_USART6 FALSE
#endif
/**
@ -98,8 +98,8 @@
* @details If set to @p TRUE the support for UART7 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_UART7) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_UART7 FALSE
#if !defined(GD32_SERIAL_USE_UART7) || defined(__DOXYGEN__)
#define GD32_SERIAL_USE_UART7 FALSE
#endif
/**
@ -107,64 +107,64 @@
* @details If set to @p TRUE the support for UART8 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_SERIAL_USE_UART8) || defined(__DOXYGEN__)
#define STM32_SERIAL_USE_UART8 FALSE
#if !defined(GD32_SERIAL_USE_UART8) || defined(__DOXYGEN__)
#define GD32_SERIAL_USE_UART8 FALSE
#endif
/**
* @brief USART1 interrupt priority level setting.
*/
#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SERIAL_USART1_PRIORITY 12
#if !defined(GD32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SERIAL_USART1_PRIORITY 12
#endif
/**
* @brief USART2 interrupt priority level setting.
*/
#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SERIAL_USART2_PRIORITY 12
#if !defined(GD32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SERIAL_USART2_PRIORITY 12
#endif
/**
* @brief USART3 interrupt priority level setting.
*/
#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SERIAL_USART3_PRIORITY 12
#if !defined(GD32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SERIAL_USART3_PRIORITY 12
#endif
/**
* @brief UART4 interrupt priority level setting.
*/
#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SERIAL_UART4_PRIORITY 12
#if !defined(GD32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SERIAL_UART4_PRIORITY 12
#endif
/**
* @brief UART5 interrupt priority level setting.
*/
#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SERIAL_UART5_PRIORITY 12
#if !defined(GD32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SERIAL_UART5_PRIORITY 12
#endif
/**
* @brief USART6 interrupt priority level setting.
*/
#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SERIAL_USART6_PRIORITY 12
#if !defined(GD32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SERIAL_USART6_PRIORITY 12
#endif
/**
* @brief UART7 interrupt priority level setting.
*/
#if !defined(STM32_SERIAL_UART7_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SERIAL_UART7_PRIORITY 12
#if !defined(GD32_SERIAL_UART7_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SERIAL_UART7_PRIORITY 12
#endif
/**
* @brief UART8 interrupt priority level setting.
*/
#if !defined(STM32_SERIAL_UART8_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SERIAL_UART8_PRIORITY 12
#if !defined(GD32_SERIAL_UART8_PRIORITY) || defined(__DOXYGEN__)
#define GD32_SERIAL_UART8_PRIORITY 12
#endif
/** @} */
@ -172,82 +172,82 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1
#if GD32_SERIAL_USE_USART1 && !GD32_HAS_USART1
#error "USART1 not present in the selected device"
#endif
#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2
#if GD32_SERIAL_USE_USART2 && !GD32_HAS_USART2
#error "USART2 not present in the selected device"
#endif
#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3
#if GD32_SERIAL_USE_USART3 && !GD32_HAS_USART3
#error "USART3 not present in the selected device"
#endif
#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4
#if GD32_SERIAL_USE_UART4 && !GD32_HAS_UART4
#error "UART4 not present in the selected device"
#endif
#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5
#if GD32_SERIAL_USE_UART5 && !GD32_HAS_UART5
#error "UART5 not present in the selected device"
#endif
#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6
#if GD32_SERIAL_USE_USART6 && !GD32_HAS_USART6
#error "USART6 not present in the selected device"
#endif
#if STM32_SERIAL_USE_UART7 && !STM32_HAS_UART7
#if GD32_SERIAL_USE_UART7 && !GD32_HAS_UART7
#error "UART7 not present in the selected device"
#endif
#if STM32_SERIAL_USE_UART8 && !STM32_HAS_UART8
#if GD32_SERIAL_USE_UART8 && !GD32_HAS_UART8
#error "UART8 not present in the selected device"
#endif
#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 && \
!STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4 && \
!STM32_SERIAL_USE_UART5 && !STM32_SERIAL_USE_USART6 && \
!STM32_SERIAL_USE_UART7 && !STM32_SERIAL_USE_UART8
#if !GD32_SERIAL_USE_USART1 && !GD32_SERIAL_USE_USART2 && \
!GD32_SERIAL_USE_USART3 && !GD32_SERIAL_USE_UART4 && \
!GD32_SERIAL_USE_UART5 && !GD32_SERIAL_USE_USART6 && \
!GD32_SERIAL_USE_UART7 && !GD32_SERIAL_USE_UART8
#error "SERIAL driver activated but no USART/UART peripheral assigned"
#endif
#if STM32_SERIAL_USE_USART1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART1_PRIORITY)
#if GD32_SERIAL_USE_USART1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_USART1_PRIORITY)
#error "Invalid IRQ priority assigned to USART1"
#endif
#if STM32_SERIAL_USE_USART2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART2_PRIORITY)
#if GD32_SERIAL_USE_USART2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_USART2_PRIORITY)
#error "Invalid IRQ priority assigned to USART2"
#endif
#if STM32_SERIAL_USE_USART3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART3_PRIORITY)
#if GD32_SERIAL_USE_USART3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_USART3_PRIORITY)
#error "Invalid IRQ priority assigned to USART3"
#endif
#if STM32_SERIAL_USE_UART4 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART4_PRIORITY)
#if GD32_SERIAL_USE_UART4 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_UART4_PRIORITY)
#error "Invalid IRQ priority assigned to UART4"
#endif
#if STM32_SERIAL_USE_UART5 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART5_PRIORITY)
#if GD32_SERIAL_USE_UART5 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_UART5_PRIORITY)
#error "Invalid IRQ priority assigned to UART5"
#endif
#if STM32_SERIAL_USE_USART6 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_USART6_PRIORITY)
#if GD32_SERIAL_USE_USART6 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_USART6_PRIORITY)
#error "Invalid IRQ priority assigned to USART6"
#endif
#if STM32_SERIAL_USE_UART7 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART7_PRIORITY)
#if GD32_SERIAL_USE_UART7 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_UART7_PRIORITY)
#error "Invalid IRQ priority assigned to UART7"
#endif
#if STM32_SERIAL_USE_UART8 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_UART8_PRIORITY)
#if GD32_SERIAL_USE_UART8 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_SERIAL_UART8_PRIORITY)
#error "Invalid IRQ priority assigned to UART8"
#endif
@ -320,28 +320,28 @@ typedef struct {
/* External declarations. */
/*===========================================================================*/
#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART1 && !defined(__DOXYGEN__)
extern SerialDriver SD1;
#endif
#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART2 && !defined(__DOXYGEN__)
extern SerialDriver SD2;
#endif
#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART3 && !defined(__DOXYGEN__)
extern SerialDriver SD3;
#endif
#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
extern SerialDriver SD4;
#endif
#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
extern SerialDriver SD5;
#endif
#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__)
#if GD32_SERIAL_USE_USART6 && !defined(__DOXYGEN__)
extern SerialDriver SD6;
#endif
#if STM32_SERIAL_USE_UART7 && !defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART7 && !defined(__DOXYGEN__)
extern SerialDriver SD7;
#endif
#if STM32_SERIAL_USE_UART8 && !defined(__DOXYGEN__)
#if GD32_SERIAL_USE_UART8 && !defined(__DOXYGEN__)
extern SerialDriver SD8;
#endif

390
os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.c
View File

@ -31,74 +31,74 @@
/*===========================================================================*/
#define USART1_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM, \
STM32_USART1_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_USART1_RX_DMA_STREAM, \
GD32_USART1_RX_DMA_CHN)
#define USART1_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM, \
STM32_USART1_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_USART1_TX_DMA_STREAM, \
GD32_USART1_TX_DMA_CHN)
#define USART2_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM, \
STM32_USART2_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_USART2_RX_DMA_STREAM, \
GD32_USART2_RX_DMA_CHN)
#define USART2_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM, \
STM32_USART2_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_USART2_TX_DMA_STREAM, \
GD32_USART2_TX_DMA_CHN)
#define USART3_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM, \
STM32_USART3_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_USART3_RX_DMA_STREAM, \
GD32_USART3_RX_DMA_CHN)
#define USART3_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM, \
STM32_USART3_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_USART3_TX_DMA_STREAM, \
GD32_USART3_TX_DMA_CHN)
#define UART4_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_UART4_RX_DMA_STREAM, \
STM32_UART4_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_UART4_RX_DMA_STREAM, \
GD32_UART4_RX_DMA_CHN)
#define UART4_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_UART4_TX_DMA_STREAM, \
STM32_UART4_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_UART4_TX_DMA_STREAM, \
GD32_UART4_TX_DMA_CHN)
#define UART5_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_UART5_RX_DMA_STREAM, \
STM32_UART5_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_UART5_RX_DMA_STREAM, \
GD32_UART5_RX_DMA_CHN)
#define UART5_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_UART5_TX_DMA_STREAM, \
STM32_UART5_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_UART5_TX_DMA_STREAM, \
GD32_UART5_TX_DMA_CHN)
#define USART6_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_USART6_RX_DMA_STREAM, \
STM32_USART6_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_USART6_RX_DMA_STREAM, \
GD32_USART6_RX_DMA_CHN)
#define USART6_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_USART6_TX_DMA_STREAM, \
STM32_USART6_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_USART6_TX_DMA_STREAM, \
GD32_USART6_TX_DMA_CHN)
#define UART7_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_UART7_RX_DMA_STREAM, \
STM32_UART7_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_UART7_RX_DMA_STREAM, \
GD32_UART7_RX_DMA_CHN)
#define UART7_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_UART7_TX_DMA_STREAM, \
STM32_UART7_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_UART7_TX_DMA_STREAM, \
GD32_UART7_TX_DMA_CHN)
#define UART8_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_UART8_RX_DMA_STREAM, \
STM32_UART8_RX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_UART8_RX_DMA_STREAM, \
GD32_UART8_RX_DMA_CHN)
#define UART8_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_UART_UART8_TX_DMA_STREAM, \
STM32_UART8_TX_DMA_CHN)
GD32_DMA_GETCHANNEL(GD32_UART_UART8_TX_DMA_STREAM, \
GD32_UART8_TX_DMA_CHN)
#define STM32_UART45_CR2_CHECK_MASK \
#define GD32_UART45_CR2_CHECK_MASK \
(USART_CR2_STOP_0 | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
USART_CR2_LBCL)
#define STM32_UART45_CR3_CHECK_MASK \
#define GD32_UART45_CR3_CHECK_MASK \
(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_SCEN | \
USART_CR3_NACK)
@ -107,42 +107,42 @@
/*===========================================================================*/
/** @brief USART1 UART driver identifier.*/
#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
#if GD32_UART_USE_USART1 || defined(__DOXYGEN__)
UARTDriver UARTD1;
#endif
/** @brief USART2 UART driver identifier.*/
#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
#if GD32_UART_USE_USART2 || defined(__DOXYGEN__)
UARTDriver UARTD2;
#endif
/** @brief USART3 UART driver identifier.*/
#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
#if GD32_UART_USE_USART3 || defined(__DOXYGEN__)
UARTDriver UARTD3;
#endif
/** @brief UART4 UART driver identifier.*/
#if STM32_UART_USE_UART4 || defined(__DOXYGEN__)
#if GD32_UART_USE_UART4 || defined(__DOXYGEN__)
UARTDriver UARTD4;
#endif
/** @brief UART5 UART driver identifier.*/
#if STM32_UART_USE_UART5 || defined(__DOXYGEN__)
#if GD32_UART_USE_UART5 || defined(__DOXYGEN__)
UARTDriver UARTD5;
#endif
/** @brief USART6 UART driver identifier.*/
#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
#if GD32_UART_USE_USART6 || defined(__DOXYGEN__)
UARTDriver UARTD6;
#endif
/** @brief UART7 UART driver identifier.*/
#if STM32_UART_USE_UART7 || defined(__DOXYGEN__)
#if GD32_UART_USE_UART7 || defined(__DOXYGEN__)
UARTDriver UARTD7;
#endif
/** @brief UART8 UART driver identifier.*/
#if STM32_UART_USE_UART8 || defined(__DOXYGEN__)
#if GD32_UART_USE_UART8 || defined(__DOXYGEN__)
UARTDriver UARTD8;
#endif
@ -188,9 +188,9 @@ static void uart_enter_rx_idle_loop(UARTDriver *uartp) {
/* RX DMA channel preparation, if the char callback is defined then the
TCIE interrupt is enabled too.*/
if (uartp->config->rxchar_cb == NULL)
mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC;
mode = GD32_DMA_CR_DIR_P2M | GD32_DMA_CR_CIRC;
else
mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE;
mode = GD32_DMA_CR_DIR_P2M | GD32_DMA_CR_CIRC | GD32_DMA_CR_TCIE;
dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf);
dmaStreamSetTransactionSize(uartp->dmarx, 1);
dmaStreamSetMode(uartp->dmarx, uartp->dmarxmode | mode);
@ -230,14 +230,14 @@ static void usart_start(UARTDriver *uartp) {
usart_stop(uartp);
/* Baud rate setting.*/
#if STM32_HAS_USART6
#if GD32_HAS_USART6
if ((uartp->usart == USART1) || (uartp->usart == USART6))
#else
if (uartp->usart == USART1)
#endif
fck = STM32_PCLK2 / uartp->config->speed;
fck = GD32_PCLK2 / uartp->config->speed;
else
fck = STM32_PCLK1 / uartp->config->speed;
fck = GD32_PCLK1 / uartp->config->speed;
/* Correcting USARTDIV when oversampling by 8 instead of 16.
Fraction is still 4 bits wide, but only lower 3 bits used.
@ -277,9 +277,9 @@ static void usart_start(UARTDriver *uartp) {
static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
/* DMA errors handling.*/
#if defined(STM32_UART_DMA_ERROR_HOOK)
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
STM32_UART_DMA_ERROR_HOOK(uartp);
#if defined(GD32_UART_DMA_ERROR_HOOK)
if ((flags & (GD32_DMA_ISR_TEIF | GD32_DMA_ISR_DMEIF)) != 0) {
GD32_UART_DMA_ERROR_HOOK(uartp);
}
#else
(void)flags;
@ -307,9 +307,9 @@ static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
/* DMA errors handling.*/
#if defined(STM32_UART_DMA_ERROR_HOOK)
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
STM32_UART_DMA_ERROR_HOOK(uartp);
#if defined(GD32_UART_DMA_ERROR_HOOK)
if ((flags & (GD32_DMA_ISR_TEIF | GD32_DMA_ISR_DMEIF)) != 0) {
GD32_UART_DMA_ERROR_HOOK(uartp);
}
#else
(void)flags;
@ -359,7 +359,7 @@ static void serve_usart_irq(UARTDriver *uartp) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
#if GD32_UART_USE_USART1 || defined(__DOXYGEN__)
#if !defined(GD32_USART1_HANDLER)
#error "GD32_USART1_HANDLER not defined"
#endif
@ -376,9 +376,9 @@ OSAL_IRQ_HANDLER(GD32_USART1_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_USART1 */
#endif /* GD32_UART_USE_USART1 */
#if STM32_UART_USE_USART2 || defined(__DOXYGEN__)
#if GD32_UART_USE_USART2 || defined(__DOXYGEN__)
#if !defined(GD32_USART2_HANDLER)
#error "GD32_USART2_HANDLER not defined"
#endif
@ -395,9 +395,9 @@ OSAL_IRQ_HANDLER(GD32_USART2_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_USART2 */
#endif /* GD32_UART_USE_USART2 */
#if STM32_UART_USE_USART3 || defined(__DOXYGEN__)
#if GD32_UART_USE_USART3 || defined(__DOXYGEN__)
#if !defined(GD32_USART3_HANDLER)
#error "GD32_USART3_HANDLER not defined"
#endif
@ -414,9 +414,9 @@ OSAL_IRQ_HANDLER(GD32_USART3_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_USART3 */
#endif /* GD32_UART_USE_USART3 */
#if STM32_UART_USE_UART4 || defined(__DOXYGEN__)
#if GD32_UART_USE_UART4 || defined(__DOXYGEN__)
#if !defined(GD32_UART4_HANDLER)
#error "GD32_UART4_HANDLER not defined"
#endif
@ -433,9 +433,9 @@ OSAL_IRQ_HANDLER(GD32_UART4_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_UART4 */
#endif /* GD32_UART_USE_UART4 */
#if STM32_UART_USE_UART5 || defined(__DOXYGEN__)
#if GD32_UART_USE_UART5 || defined(__DOXYGEN__)
#if !defined(GD32_UART5_HANDLER)
#error "GD32_UART5_HANDLER not defined"
#endif
@ -452,9 +452,9 @@ OSAL_IRQ_HANDLER(GD32_UART5_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_UART5 */
#endif /* GD32_UART_USE_UART5 */
#if STM32_UART_USE_USART6 || defined(__DOXYGEN__)
#if GD32_UART_USE_USART6 || defined(__DOXYGEN__)
#if !defined(GD32_USART6_HANDLER)
#error "GD32_USART6_HANDLER not defined"
#endif
@ -471,9 +471,9 @@ OSAL_IRQ_HANDLER(GD32_USART6_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_USART6 */
#endif /* GD32_UART_USE_USART6 */
#if STM32_UART_USE_UART7 || defined(__DOXYGEN__)
#if GD32_UART_USE_UART7 || defined(__DOXYGEN__)
#if !defined(GD32_UART7_HANDLER)
#error "GD32_UART7_HANDLER not defined"
#endif
@ -490,9 +490,9 @@ OSAL_IRQ_HANDLER(GD32_UART7_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_UART7 */
#endif /* GD32_UART_USE_UART7 */
#if STM32_UART_USE_UART8 || defined(__DOXYGEN__)
#if GD32_UART_USE_UART8 || defined(__DOXYGEN__)
#if !defined(GD32_UART8_HANDLER)
#error "GD32_UART8_HANDLER not defined"
#endif
@ -509,7 +509,7 @@ OSAL_IRQ_HANDLER(GD32_UART8_HANDLER) {
OSAL_IRQ_EPILOGUE();
}
#endif /* STM32_UART_USE_UART8 */
#endif /* GD32_UART_USE_UART8 */
/*===========================================================================*/
/* Driver exported functions. */
@ -522,74 +522,74 @@ OSAL_IRQ_HANDLER(GD32_UART8_HANDLER) {
*/
void uart_lld_init(void) {
#if STM32_UART_USE_USART1
#if GD32_UART_USE_USART1
uartObjectInit(&UARTD1);
UARTD1.usart = USART1;
UARTD1.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD1.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD1.dmarxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD1.dmatxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD1.dmarx = NULL;
UARTD1.dmatx = NULL;
#endif
#if STM32_UART_USE_USART2
#if GD32_UART_USE_USART2
uartObjectInit(&UARTD2);
UARTD2.usart = USART2;
UARTD2.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD2.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD2.dmarxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD2.dmatxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD2.dmarx = NULL;
UARTD2.dmatx = NULL;
#endif
#if STM32_UART_USE_USART3
#if GD32_UART_USE_USART3
uartObjectInit(&UARTD3);
UARTD3.usart = USART3;
UARTD3.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD3.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD3.dmarxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD3.dmatxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD3.dmarx = NULL;
UARTD3.dmatx = NULL;
#endif
#if STM32_UART_USE_UART4
#if GD32_UART_USE_UART4
uartObjectInit(&UARTD4);
UARTD4.usart = UART4;
UARTD4.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD4.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD4.dmarxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD4.dmatxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD4.dmarx = NULL;
UARTD4.dmatx = NULL;
#endif
#if STM32_UART_USE_UART5
#if GD32_UART_USE_UART5
uartObjectInit(&UARTD5);
UARTD5.usart = UART5;
UARTD5.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD5.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD5.dmarxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD5.dmatxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD5.dmarx = NULL;
UARTD5.dmatx = NULL;
#endif
#if STM32_UART_USE_USART6
#if GD32_UART_USE_USART6
uartObjectInit(&UARTD6);
UARTD6.usart = USART6;
UARTD6.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD6.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD6.dmarxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD6.dmatxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD6.dmarx = NULL;
UARTD6.dmatx = NULL;
#endif
#if STM32_UART_USE_UART7
#if GD32_UART_USE_UART7
uartObjectInit(&UARTD7);
UARTD7.usart = UART7;
UARTD7.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD7.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD7.dmarxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD7.dmatxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD7.dmarx = NULL;
UARTD7.dmatx = NULL;
#endif
#if STM32_UART_USE_UART8
#if GD32_UART_USE_UART8
uartObjectInit(&UARTD8);
UARTD8.usart = UART8;
UARTD8.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD8.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
UARTD8.dmarxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD8.dmatxmode = GD32_DMA_CR_DMEIE | GD32_DMA_CR_TEIE;
UARTD8.dmarx = NULL;
UARTD8.dmatx = NULL;
#endif
@ -605,211 +605,211 @@ void uart_lld_init(void) {
void uart_lld_start(UARTDriver *uartp) {
if (uartp->state == UART_STOP) {
#if STM32_UART_USE_USART1
#if GD32_UART_USE_USART1
if (&UARTD1 == uartp) {
uartp->dmarx = dmaStreamAllocI(STM32_UART_USART1_RX_DMA_STREAM,
STM32_UART_USART1_IRQ_PRIORITY,
uartp->dmarx = dmaStreamAllocI(GD32_UART_USART1_RX_DMA_STREAM,
GD32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_USART1_TX_DMA_STREAM,
STM32_UART_USART1_IRQ_PRIORITY,
uartp->dmatx = dmaStreamAllocI(GD32_UART_USART1_TX_DMA_STREAM,
GD32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART1(true);
eclicEnableVector(GD32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY, STM32_UART_USART1_IRQ_TRIGGER);
uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
eclicEnableVector(GD32_USART1_NUMBER, GD32_UART_USART1_IRQ_PRIORITY, GD32_UART_USART1_IRQ_TRIGGER);
uartp->dmarxmode |= GD32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_USART1_DMA_PRIORITY);
uartp->dmatxmode |= GD32_DMA_CR_CHSEL(USART1_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_USART1_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_USART2
#if GD32_UART_USE_USART2
if (&UARTD2 == uartp) {
uartp->dmarx = dmaStreamAllocI(STM32_UART_USART2_RX_DMA_STREAM,
STM32_UART_USART2_IRQ_PRIORITY,
uartp->dmarx = dmaStreamAllocI(GD32_UART_USART2_RX_DMA_STREAM,
GD32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_USART2_TX_DMA_STREAM,
STM32_UART_USART2_IRQ_PRIORITY,
uartp->dmatx = dmaStreamAllocI(GD32_UART_USART2_TX_DMA_STREAM,
GD32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART2(true);
eclicEnableVector(GD32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY, STM32_UART_USART2_IRQ_TRIGGER);
uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART2_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
eclicEnableVector(GD32_USART2_NUMBER, GD32_UART_USART2_IRQ_PRIORITY, GD32_UART_USART2_IRQ_TRIGGER);
uartp->dmarxmode |= GD32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_USART2_DMA_PRIORITY);
uartp->dmatxmode |= GD32_DMA_CR_CHSEL(USART2_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_USART2_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_USART3
#if GD32_UART_USE_USART3
if (&UARTD3 == uartp) {
uartp->dmarx = dmaStreamAllocI(STM32_UART_USART3_RX_DMA_STREAM,
STM32_UART_USART3_IRQ_PRIORITY,
uartp->dmarx = dmaStreamAllocI(GD32_UART_USART3_RX_DMA_STREAM,
GD32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_USART3_TX_DMA_STREAM,
STM32_UART_USART3_IRQ_PRIORITY,
uartp->dmatx = dmaStreamAllocI(GD32_UART_USART3_TX_DMA_STREAM,
GD32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART3(true);
eclicEnableVector(GD32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY, STM32_UART_USART3_IRQ_TRIGGER);
uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
eclicEnableVector(GD32_USART3_NUMBER, GD32_UART_USART3_IRQ_PRIORITY, GD32_UART_USART3_IRQ_TRIGGER);
uartp->dmarxmode |= GD32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_USART3_DMA_PRIORITY);
uartp->dmatxmode |= GD32_DMA_CR_CHSEL(USART3_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_USART3_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_UART4
#if GD32_UART_USE_UART4
if (&UARTD4 == uartp) {
osalDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->cr2 & GD32_UART45_CR2_CHECK_MASK) == 0,
"specified invalid bits in UART4 CR2 register settings");
osalDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->cr3 & GD32_UART45_CR3_CHECK_MASK) == 0,
"specified invalid bits in UART4 CR3 register settings");
uartp->dmarx = dmaStreamAllocI(STM32_UART_UART4_RX_DMA_STREAM,
STM32_UART_UART4_IRQ_PRIORITY,
uartp->dmarx = dmaStreamAllocI(GD32_UART_UART4_RX_DMA_STREAM,
GD32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_UART4_TX_DMA_STREAM,
STM32_UART_UART4_IRQ_PRIORITY,
uartp->dmatx = dmaStreamAllocI(GD32_UART_UART4_TX_DMA_STREAM,
GD32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUART4(true);
eclicEnableVector(GD32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY, STM32_UART_UART4_IRQ_TRIGGER);
uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);
uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART4_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);
eclicEnableVector(GD32_UART4_NUMBER, GD32_UART_UART4_IRQ_PRIORITY, GD32_UART_UART4_IRQ_TRIGGER);
uartp->dmarxmode |= GD32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_UART4_DMA_PRIORITY);
uartp->dmatxmode |= GD32_DMA_CR_CHSEL(UART4_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_UART4_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_UART5
#if GD32_UART_USE_UART5
if (&UARTD5 == uartp) {
osalDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->cr2 & GD32_UART45_CR2_CHECK_MASK) == 0,
"specified invalid bits in UART5 CR2 register settings");
osalDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->cr3 & GD32_UART45_CR3_CHECK_MASK) == 0,
"specified invalid bits in UART5 CR3 register settings");
uartp->dmarx = dmaStreamAllocI(STM32_UART_UART5_RX_DMA_STREAM,
STM32_UART_UART5_IRQ_PRIORITY,
uartp->dmarx = dmaStreamAllocI(GD32_UART_UART5_RX_DMA_STREAM,
GD32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_UART5_TX_DMA_STREAM,
STM32_UART_UART5_IRQ_PRIORITY,
uartp->dmatx = dmaStreamAllocI(GD32_UART_UART5_TX_DMA_STREAM,
GD32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUART5(true);
eclicEnableVector(GD32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY, STM32_UART_UART5_IRQ_TRIGGER);
uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);
uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART5_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);
eclicEnableVector(GD32_UART5_NUMBER, GD32_UART_UART5_IRQ_PRIORITY, GD32_UART_UART5_IRQ_TRIGGER);
uartp->dmarxmode |= GD32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_UART5_DMA_PRIORITY);
uartp->dmatxmode |= GD32_DMA_CR_CHSEL(UART5_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_UART5_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_USART6
#if GD32_UART_USE_USART6
if (&UARTD6 == uartp) {
uartp->dmarx = dmaStreamAllocI(STM32_UART_USART6_RX_DMA_STREAM,
STM32_UART_USART6_IRQ_PRIORITY,
uartp->dmarx = dmaStreamAllocI(GD32_UART_USART6_RX_DMA_STREAM,
GD32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_USART6_TX_DMA_STREAM,
STM32_UART_USART6_IRQ_PRIORITY,
uartp->dmatx = dmaStreamAllocI(GD32_UART_USART6_TX_DMA_STREAM,
GD32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUSART6(true);
eclicEnableVector(GD32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY, STM32_UART_USART6_IRQ_TRIGGER);
uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);
uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART6_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);
eclicEnableVector(GD32_USART6_NUMBER, GD32_UART_USART6_IRQ_PRIORITY, GD32_UART_USART6_IRQ_TRIGGER);
uartp->dmarxmode |= GD32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_USART6_DMA_PRIORITY);
uartp->dmatxmode |= GD32_DMA_CR_CHSEL(USART6_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_USART6_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_UART7
#if GD32_UART_USE_UART7
if (&UARTD7 == uartp) {
osalDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->cr2 & GD32_UART45_CR2_CHECK_MASK) == 0,
"specified invalid bits in UART7 CR2 register settings");
osalDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->cr3 & GD32_UART45_CR3_CHECK_MASK) == 0,
"specified invalid bits in UART7 CR3 register settings");
uartp->dmarx = dmaStreamAllocI(STM32_UART_UART7_RX_DMA_STREAM,
STM32_UART_UART7_IRQ_PRIORITY,
uartp->dmarx = dmaStreamAllocI(GD32_UART_UART7_RX_DMA_STREAM,
GD32_UART_UART7_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_UART7_TX_DMA_STREAM,
STM32_UART_UART7_IRQ_PRIORITY,
uartp->dmatx = dmaStreamAllocI(GD32_UART_UART7_TX_DMA_STREAM,
GD32_UART_UART7_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUART7(true);
eclicEnableVector(GD32_UART7_NUMBER, STM32_UART_UART7_IRQ_PRIORITY, STM32_UART_UART7_IRQ_TRIGGER);
uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY);
uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART7_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY);
eclicEnableVector(GD32_UART7_NUMBER, GD32_UART_UART7_IRQ_PRIORITY, GD32_UART_UART7_IRQ_TRIGGER);
uartp->dmarxmode |= GD32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_UART7_DMA_PRIORITY);
uartp->dmatxmode |= GD32_DMA_CR_CHSEL(UART7_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_UART7_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_UART8
#if GD32_UART_USE_UART8
if (&UARTD8 == uartp) {
osalDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->cr2 & GD32_UART45_CR2_CHECK_MASK) == 0,
"specified invalid bits in UART8 CR2 register settings");
osalDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
osalDbgAssert((uartp->config->cr3 & GD32_UART45_CR3_CHECK_MASK) == 0,
"specified invalid bits in UART8 CR3 register settings");
uartp->dmarx = dmaStreamAllocI(STM32_UART_UART8_RX_DMA_STREAM,
STM32_UART_UART8_IRQ_PRIORITY,
uartp->dmarx = dmaStreamAllocI(GD32_UART_UART8_RX_DMA_STREAM,
GD32_UART_UART8_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmarx != NULL, "unable to allocate stream");
uartp->dmatx = dmaStreamAllocI(STM32_UART_UART8_TX_DMA_STREAM,
STM32_UART_UART8_IRQ_PRIORITY,
uartp->dmatx = dmaStreamAllocI(GD32_UART_UART8_TX_DMA_STREAM,
GD32_UART_UART8_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream");
rccEnableUART8(true);
eclicEnableVector(GD32_UART8_NUMBER, STM32_UART_UART8_IRQ_PRIORITY, STM32_UART_UART8_IRQ_TRIGGER);
uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY);
uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART8_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY);
eclicEnableVector(GD32_UART8_NUMBER, GD32_UART_UART8_IRQ_PRIORITY, GD32_UART_UART8_IRQ_TRIGGER);
uartp->dmarxmode |= GD32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_UART8_DMA_PRIORITY);
uartp->dmatxmode |= GD32_DMA_CR_CHSEL(UART8_TX_DMA_CHANNEL) |
GD32_DMA_CR_PL(GD32_UART_UART8_DMA_PRIORITY);
}
#endif
/* Static DMA setup, the transfer size depends on the USART settings,
it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) {
uartp->dmarxmode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
uartp->dmatxmode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
uartp->dmarxmode |= GD32_DMA_CR_PSIZE_HWORD | GD32_DMA_CR_MSIZE_HWORD;
uartp->dmatxmode |= GD32_DMA_CR_PSIZE_HWORD | GD32_DMA_CR_MSIZE_HWORD;
}
dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR);
dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR);
@ -837,7 +837,7 @@ void uart_lld_stop(UARTDriver *uartp) {
uartp->dmarx = NULL;
uartp->dmatx = NULL;
#if STM32_UART_USE_USART1
#if GD32_UART_USE_USART1
if (&UARTD1 == uartp) {
eclicDisableVector(GD32_USART1_NUMBER);
rccDisableUSART1();
@ -845,7 +845,7 @@ void uart_lld_stop(UARTDriver *uartp) {
}
#endif
#if STM32_UART_USE_USART2
#if GD32_UART_USE_USART2
if (&UARTD2 == uartp) {
eclicDisableVector(GD32_USART2_NUMBER);
rccDisableUSART2();
@ -853,7 +853,7 @@ void uart_lld_stop(UARTDriver *uartp) {
}
#endif
#if STM32_UART_USE_USART3
#if GD32_UART_USE_USART3
if (&UARTD3 == uartp) {
eclicDisableVector(GD32_USART3_NUMBER);
rccDisableUSART3();
@ -861,7 +861,7 @@ void uart_lld_stop(UARTDriver *uartp) {
}
#endif
#if STM32_UART_USE_UART4
#if GD32_UART_USE_UART4
if (&UARTD4 == uartp) {
eclicDisableVector(GD32_UART4_NUMBER);
rccDisableUART4();
@ -869,7 +869,7 @@ void uart_lld_stop(UARTDriver *uartp) {
}
#endif
#if STM32_UART_USE_UART5
#if GD32_UART_USE_UART5
if (&UARTD5 == uartp) {
eclicDisableVector(GD32_UART5_NUMBER);
rccDisableUART5();
@ -877,7 +877,7 @@ void uart_lld_stop(UARTDriver *uartp) {
}
#endif
#if STM32_UART_USE_USART6
#if GD32_UART_USE_USART6
if (&UARTD6 == uartp) {
eclicDisableVector(GD32_USART6_NUMBER);
rccDisableUSART6();
@ -885,7 +885,7 @@ void uart_lld_stop(UARTDriver *uartp) {
}
#endif
#if STM32_UART_USE_UART7
#if GD32_UART_USE_UART7
if (&UARTD7 == uartp) {
eclicDisableVector(GD32_UART7_NUMBER);
rccDisableUART7();
@ -893,7 +893,7 @@ void uart_lld_stop(UARTDriver *uartp) {
}
#endif
#if STM32_UART_USE_UART8
#if GD32_UART_USE_UART8
if (&UARTD8 == uartp) {
eclicDisableVector(GD32_UART8_NUMBER);
rccDisableUART8();
@ -919,8 +919,8 @@ void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
/* TX DMA channel preparation.*/
dmaStreamSetMemory0(uartp->dmatx, txbuf);
dmaStreamSetTransactionSize(uartp->dmatx, n);
dmaStreamSetMode(uartp->dmatx, uartp->dmatxmode | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
dmaStreamSetMode(uartp->dmatx, uartp->dmatxmode | GD32_DMA_CR_DIR_M2P |
GD32_DMA_CR_MINC | GD32_DMA_CR_TCIE);
/* Only enable TC interrupt if there's a callback attached to it or
if called from uartSendFullTimeout(). Also we need to clear TC flag
@ -975,8 +975,8 @@ void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
/* RX DMA channel preparation.*/
dmaStreamSetMemory0(uartp->dmarx, rxbuf);
dmaStreamSetTransactionSize(uartp->dmarx, n);
dmaStreamSetMode(uartp->dmarx, uartp->dmarxmode | STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);
dmaStreamSetMode(uartp->dmarx, uartp->dmarxmode | GD32_DMA_CR_DIR_P2M |
GD32_DMA_CR_MINC | GD32_DMA_CR_TCIE);
/* Starting transfer.*/
dmaStreamEnable(uartp->dmarx);

348
os/hal/ports/GD/GD32VF103/USART/hal_uart_lld.h
View File

@ -44,8 +44,8 @@
* @details If set to @p TRUE the support for USART1 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__)
#define STM32_UART_USE_USART1 FALSE
#if !defined(GD32_UART_USE_USART1) || defined(__DOXYGEN__)
#define GD32_UART_USE_USART1 FALSE
#endif
/**
@ -53,8 +53,8 @@
* @details If set to @p TRUE the support for USART2 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__)
#define STM32_UART_USE_USART2 FALSE
#if !defined(GD32_UART_USE_USART2) || defined(__DOXYGEN__)
#define GD32_UART_USE_USART2 FALSE
#endif
/**
@ -62,8 +62,8 @@
* @details If set to @p TRUE the support for USART3 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__)
#define STM32_UART_USE_USART3 FALSE
#if !defined(GD32_UART_USE_USART3) || defined(__DOXYGEN__)
#define GD32_UART_USE_USART3 FALSE
#endif
/**
@ -71,8 +71,8 @@
* @details If set to @p TRUE the support for UART4 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_UART_USE_UART4) || defined(__DOXYGEN__)
#define STM32_UART_USE_UART4 FALSE
#if !defined(GD32_UART_USE_UART4) || defined(__DOXYGEN__)
#define GD32_UART_USE_UART4 FALSE
#endif
/**
@ -80,8 +80,8 @@
* @details If set to @p TRUE the support for UART5 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_UART_USE_UART5) || defined(__DOXYGEN__)
#define STM32_UART_USE_UART5 FALSE
#if !defined(GD32_UART_USE_UART5) || defined(__DOXYGEN__)
#define GD32_UART_USE_UART5 FALSE
#endif
/**
@ -89,8 +89,8 @@
* @details If set to @p TRUE the support for USART6 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_UART_USE_USART6) || defined(__DOXYGEN__)
#define STM32_UART_USE_USART6 FALSE
#if !defined(GD32_UART_USE_USART6) || defined(__DOXYGEN__)
#define GD32_UART_USE_USART6 FALSE
#endif
/**
@ -98,8 +98,8 @@
* @details If set to @p TRUE the support for UART7 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_UART_USE_UART7) || defined(__DOXYGEN__)
#define STM32_UART_USE_UART7 FALSE
#if !defined(GD32_UART_USE_UART7) || defined(__DOXYGEN__)
#define GD32_UART_USE_UART7 FALSE
#endif
/**
@ -107,64 +107,64 @@
* @details If set to @p TRUE the support for UART8 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_UART_USE_UART8) || defined(__DOXYGEN__)
#define STM32_UART_USE_UART8 FALSE
#if !defined(GD32_UART_USE_UART8) || defined(__DOXYGEN__)
#define GD32_UART_USE_UART8 FALSE
#endif
/**
* @brief USART1 interrupt priority level setting.
*/
#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#if !defined(GD32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_USART1_IRQ_PRIORITY 12
#endif
/**
* @brief USART2 interrupt priority level setting.
*/
#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_USART2_IRQ_PRIORITY 12
#if !defined(GD32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_USART2_IRQ_PRIORITY 12
#endif
/**
* @brief USART3 interrupt priority level setting.
*/
#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_USART3_IRQ_PRIORITY 12
#if !defined(GD32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_USART3_IRQ_PRIORITY 12
#endif
/**
* @brief UART4 interrupt priority level setting.
*/
#if !defined(STM32_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_UART4_IRQ_PRIORITY 12
#if !defined(GD32_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_UART4_IRQ_PRIORITY 12
#endif
/**
* @brief UART5 interrupt priority level setting.
*/
#if !defined(STM32_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_UART5_IRQ_PRIORITY 12
#if !defined(GD32_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_UART5_IRQ_PRIORITY 12
#endif
/**
* @brief USART6 interrupt priority level setting.
*/
#if !defined(STM32_UART_USART6_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_USART6_IRQ_PRIORITY 12
#if !defined(GD32_UART_USART6_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_USART6_IRQ_PRIORITY 12
#endif
/**
* @brief UART7 interrupt priority level setting.
*/
#if !defined(STM32_UART_UART7_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_UART7_IRQ_PRIORITY 12
#if !defined(GD32_UART_UART7_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_UART7_IRQ_PRIORITY 12
#endif
/**
* @brief UART8 interrupt priority level setting.
*/
#if !defined(STM32_UART_UART8_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_UART8_IRQ_PRIORITY 12
#if !defined(GD32_UART_UART8_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_UART8_IRQ_PRIORITY 12
#endif
/**
@ -173,8 +173,8 @@
* because of the channels ordering the RX channel has always priority
* over the TX channel.
*/
#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_USART1_DMA_PRIORITY 0
#if !defined(GD32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_USART1_DMA_PRIORITY 0
#endif
/**
@ -183,8 +183,8 @@
* because of the channels ordering the RX channel has always priority
* over the TX channel.
*/
#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_USART2_DMA_PRIORITY 0
#if !defined(GD32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_USART2_DMA_PRIORITY 0
#endif
/**
@ -193,8 +193,8 @@
* because of the channels ordering the RX channel has always priority
* over the TX channel.
*/
#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_USART3_DMA_PRIORITY 0
#if !defined(GD32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_USART3_DMA_PRIORITY 0
#endif
/**
@ -203,8 +203,8 @@
* because of the channels ordering the RX channel has always priority
* over the TX channel.
*/
#if !defined(STM32_UART_UART4_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_UART4_DMA_PRIORITY 0
#if !defined(GD32_UART_UART4_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_UART4_DMA_PRIORITY 0
#endif
/**
@ -213,8 +213,8 @@
* because of the channels ordering the RX channel has always priority
* over the TX channel.
*/
#if !defined(STM32_UART_UART5_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_UART5_DMA_PRIORITY 0
#if !defined(GD32_UART_UART5_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_UART5_DMA_PRIORITY 0
#endif
/**
@ -223,8 +223,8 @@
* because of the channels ordering the RX channel has always priority
* over the TX channel.
*/
#if !defined(STM32_UART_USART6_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_USART6_DMA_PRIORITY 0
#if !defined(GD32_UART_USART6_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_USART6_DMA_PRIORITY 0
#endif
/**
@ -233,8 +233,8 @@
* because of the channels ordering the RX channel has always priority
* over the TX channel.
*/
#if !defined(STM32_UART_UART7_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_UART7_DMA_PRIORITY 0
#if !defined(GD32_UART_UART7_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_UART7_DMA_PRIORITY 0
#endif
/**
@ -243,8 +243,8 @@
* because of the channels ordering the RX channel has always priority
* over the TX channel.
*/
#if !defined(STM32_UART_UART8_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART_UART8_DMA_PRIORITY 0
#if !defined(GD32_UART_UART8_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_UART_UART8_DMA_PRIORITY 0
#endif
/**
@ -252,8 +252,8 @@
* @note The default action for DMA errors is a system halt because DMA
* error can only happen because programming errors.
*/
#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
#if !defined(GD32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define GD32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
#endif
/** @} */
@ -261,20 +261,20 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if STM32_UART_USE_USART1 && !STM32_HAS_USART1
#if GD32_UART_USE_USART1 && !GD32_HAS_USART1
#error "USART1 not present in the selected device"
#endif
#if STM32_UART_USE_USART2 && !STM32_HAS_USART2
#if GD32_UART_USE_USART2 && !GD32_HAS_USART2
#error "USART2 not present in the selected device"
#endif
#if STM32_UART_USE_USART3 && !STM32_HAS_USART3
#if GD32_UART_USE_USART3 && !GD32_HAS_USART3
#error "USART3 not present in the selected device"
#endif
#if STM32_UART_USE_UART4
#if !STM32_HAS_UART4
#if GD32_UART_USE_UART4
#if !GD32_HAS_UART4
#error "UART4 not present in the selected device"
#endif
@ -282,10 +282,10 @@
!defined(STM32L152xE) && !defined(STM32L162xE)
#error "UART4 DMA access not supported in this platform"
#endif
#endif /* STM32_UART_USE_UART4 */
#endif /* GD32_UART_USE_UART4 */
#if STM32_UART_USE_UART5
#if !STM32_HAS_UART5
#if GD32_UART_USE_UART5
#if !GD32_HAS_UART5
#error "UART5 not present in the selected device"
#endif
@ -293,251 +293,251 @@
!defined(STM32L152xE) && !defined(STM32L162xE)
#error "UART5 DMA access not supported in this platform"
#endif
#endif /* STM32_UART_USE_UART5 */
#endif /* GD32_UART_USE_UART5 */
#if STM32_UART_USE_USART6 && !STM32_HAS_USART6
#if GD32_UART_USE_USART6 && !GD32_HAS_USART6
#error "USART6 not present in the selected device"
#endif
#if STM32_UART_USE_UART7 && !STM32_HAS_UART7
#if GD32_UART_USE_UART7 && !GD32_HAS_UART7
#error "UART7 not present in the selected device"
#endif
#if STM32_UART_USE_UART8 && !STM32_HAS_UART8
#if GD32_UART_USE_UART8 && !GD32_HAS_UART8
#error "UART8 not present in the selected device"
#endif
#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \
!STM32_UART_USE_USART3 && !STM32_UART_USE_UART4 && \
!STM32_UART_USE_UART5 && !STM32_UART_USE_USART6 && \
!STM32_UART_USE_UART7 && !STM32_UART_USE_UART8
#if !GD32_UART_USE_USART1 && !GD32_UART_USE_USART2 && \
!GD32_UART_USE_USART3 && !GD32_UART_USE_UART4 && \
!GD32_UART_USE_UART5 && !GD32_UART_USE_USART6 && \
!GD32_UART_USE_UART7 && !GD32_UART_USE_UART8
#error "UART driver activated but no USART/UART peripheral assigned"
#endif
#if STM32_UART_USE_USART1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY)
#if GD32_UART_USE_USART1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_USART1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to USART1"
#endif
#if STM32_UART_USE_USART2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY)
#if GD32_UART_USE_USART2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_USART2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to USART2"
#endif
#if STM32_UART_USE_USART3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY)
#if GD32_UART_USE_USART3 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_USART3_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to USART3"
#endif
#if STM32_UART_USE_UART4 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART4_IRQ_PRIORITY)
#if GD32_UART_USE_UART4 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_UART4_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to UART4"
#endif
#if STM32_UART_USE_UART5 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART5_IRQ_PRIORITY)
#if GD32_UART_USE_UART5 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_UART5_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to UART5"
#endif
#if STM32_UART_USE_USART6 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_USART6_IRQ_PRIORITY)
#if GD32_UART_USE_USART6 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_USART6_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to USART6"
#endif
#if STM32_UART_USE_UART7 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART7_IRQ_PRIORITY)
#if GD32_UART_USE_UART7 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_UART7_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to UART7"
#endif
#if STM32_UART_USE_UART8 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_UART_UART8_IRQ_PRIORITY)
#if GD32_UART_USE_UART8 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_UART_UART8_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to UART8"
#endif
#if STM32_UART_USE_USART1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY)
#if GD32_UART_USE_USART1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_UART_USART1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to USART1"
#endif
#if STM32_UART_USE_USART2 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY)
#if GD32_UART_USE_USART2 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_UART_USART2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to USART2"
#endif
#if STM32_UART_USE_USART3 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY)
#if GD32_UART_USE_USART3 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_UART_USART3_DMA_PRIORITY)
#error "Invalid DMA priority assigned to USART3"
#endif
#if STM32_UART_USE_UART4 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART4_DMA_PRIORITY)
#if GD32_UART_USE_UART4 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_UART_UART4_DMA_PRIORITY)
#error "Invalid DMA priority assigned to UART4"
#endif
#if STM32_UART_USE_UART5 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART5_DMA_PRIORITY)
#if GD32_UART_USE_UART5 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_UART_UART5_DMA_PRIORITY)
#error "Invalid DMA priority assigned to UART5"
#endif
#if STM32_UART_USE_USART6 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART6_DMA_PRIORITY)
#if GD32_UART_USE_USART6 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_UART_USART6_DMA_PRIORITY)
#error "Invalid DMA priority assigned to USART6"
#endif
#if STM32_UART_USE_UART7 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART7_DMA_PRIORITY)
#if GD32_UART_USE_UART7 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_UART_UART7_DMA_PRIORITY)
#error "Invalid DMA priority assigned to UART7"
#endif
#if STM32_UART_USE_UART8 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_UART8_DMA_PRIORITY)
#if GD32_UART_USE_UART8 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_UART_UART8_DMA_PRIORITY)
#error "Invalid DMA priority assigned to UART8"
#endif
/* The following checks are only required when there is a DMA able to
reassign streams to different channels.*/
#if STM32_ADVANCED_DMA
#if GD32_ADVANCED_DMA
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_UART_USE_USART1 && (!defined(STM32_UART_USART1_RX_DMA_STREAM) || \
!defined(STM32_UART_USART1_TX_DMA_STREAM))
#if GD32_UART_USE_USART1 && (!defined(GD32_UART_USART1_RX_DMA_STREAM) || \
!defined(GD32_UART_USART1_TX_DMA_STREAM))
#error "USART1 DMA streams not defined"
#endif
#if STM32_UART_USE_USART2 && (!defined(STM32_UART_USART2_RX_DMA_STREAM) || \
!defined(STM32_UART_USART2_TX_DMA_STREAM))
#if GD32_UART_USE_USART2 && (!defined(GD32_UART_USART2_RX_DMA_STREAM) || \
!defined(GD32_UART_USART2_TX_DMA_STREAM))
#error "USART2 DMA streams not defined"
#endif
#if STM32_UART_USE_USART3 && (!defined(STM32_UART_USART3_RX_DMA_STREAM) || \
!defined(STM32_UART_USART3_TX_DMA_STREAM))
#if GD32_UART_USE_USART3 && (!defined(GD32_UART_USART3_RX_DMA_STREAM) || \
!defined(GD32_UART_USART3_TX_DMA_STREAM))
#error "USART3 DMA streams not defined"
#endif
#if STM32_UART_USE_UART4 && (!defined(STM32_UART_UART4_RX_DMA_STREAM) || \
!defined(STM32_UART_UART4_TX_DMA_STREAM))
#if GD32_UART_USE_UART4 && (!defined(GD32_UART_UART4_RX_DMA_STREAM) || \
!defined(GD32_UART_UART4_TX_DMA_STREAM))
#error "UART4 DMA streams not defined"
#endif
#if STM32_UART_USE_UART5 && (!defined(STM32_UART_UART5_RX_DMA_STREAM) || \
!defined(STM32_UART_UART5_TX_DMA_STREAM))
#if GD32_UART_USE_UART5 && (!defined(GD32_UART_UART5_RX_DMA_STREAM) || \
!defined(GD32_UART_UART5_TX_DMA_STREAM))
#error "UART5 DMA streams not defined"
#endif
#if STM32_UART_USE_USART6 && (!defined(STM32_UART_USART6_RX_DMA_STREAM) || \
!defined(STM32_UART_USART6_TX_DMA_STREAM))
#if GD32_UART_USE_USART6 && (!defined(GD32_UART_USART6_RX_DMA_STREAM) || \
!defined(GD32_UART_USART6_TX_DMA_STREAM))
#error "USART6 DMA streams not defined"
#endif
#if STM32_UART_USE_UART7 && (!defined(STM32_UART_UART7_RX_DMA_STREAM) || \
!defined(STM32_UART_UART7_TX_DMA_STREAM))
#if GD32_UART_USE_UART7 && (!defined(GD32_UART_UART7_RX_DMA_STREAM) || \
!defined(GD32_UART_UART7_TX_DMA_STREAM))
#error "UART7 DMA streams not defined"
#endif
#if STM32_UART_USE_UART8 && (!defined(STM32_UART_UART8_RX_DMA_STREAM) || \
!defined(STM32_UART_UART8_TX_DMA_STREAM))
#if GD32_UART_USE_UART8 && (!defined(GD32_UART_UART8_RX_DMA_STREAM) || \
!defined(GD32_UART_UART8_TX_DMA_STREAM))
#error "UART8 DMA streams not defined"
#endif
/* Check on the validity of the assigned DMA channels.*/
#if STM32_UART_USE_USART1 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \
STM32_USART1_RX_DMA_MSK)
#if GD32_UART_USE_USART1 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_USART1_RX_DMA_STREAM, \
GD32_USART1_RX_DMA_MSK)
#error "invalid DMA stream associated to USART1 RX"
#endif
#if STM32_UART_USE_USART1 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \
STM32_USART1_TX_DMA_MSK)
#if GD32_UART_USE_USART1 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_USART1_TX_DMA_STREAM, \
GD32_USART1_TX_DMA_MSK)
#error "invalid DMA stream associated to USART1 TX"
#endif
#if STM32_UART_USE_USART2 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \
STM32_USART2_RX_DMA_MSK)
#if GD32_UART_USE_USART2 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_USART2_RX_DMA_STREAM, \
GD32_USART2_RX_DMA_MSK)
#error "invalid DMA stream associated to USART2 RX"
#endif
#if STM32_UART_USE_USART2 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \
STM32_USART2_TX_DMA_MSK)
#if GD32_UART_USE_USART2 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_USART2_TX_DMA_STREAM, \
GD32_USART2_TX_DMA_MSK)
#error "invalid DMA stream associated to USART2 TX"
#endif
#if STM32_UART_USE_USART3 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \
STM32_USART3_RX_DMA_MSK)
#if GD32_UART_USE_USART3 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_USART3_RX_DMA_STREAM, \
GD32_USART3_RX_DMA_MSK)
#error "invalid DMA stream associated to USART3 RX"
#endif
#if STM32_UART_USE_USART3 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \
STM32_USART3_TX_DMA_MSK)
#if GD32_UART_USE_USART3 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_USART3_TX_DMA_STREAM, \
GD32_USART3_TX_DMA_MSK)
#error "invalid DMA stream associated to USART3 TX"
#endif
#if STM32_UART_USE_UART4 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_UART4_RX_DMA_STREAM, \
STM32_UART4_RX_DMA_MSK)
#if GD32_UART_USE_UART4 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_UART4_RX_DMA_STREAM, \
GD32_UART4_RX_DMA_MSK)
#error "invalid DMA stream associated to UART4 RX"
#endif
#if STM32_UART_USE_UART4 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_UART4_TX_DMA_STREAM, \
STM32_UART4_TX_DMA_MSK)
#if GD32_UART_USE_UART4 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_UART4_TX_DMA_STREAM, \
GD32_UART4_TX_DMA_MSK)
#error "invalid DMA stream associated to UART4 TX"
#endif
#if STM32_UART_USE_UART5 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_UART5_RX_DMA_STREAM, \
STM32_UART5_RX_DMA_MSK)
#if GD32_UART_USE_UART5 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_UART5_RX_DMA_STREAM, \
GD32_UART5_RX_DMA_MSK)
#error "invalid DMA stream associated to UART5 RX"
#endif
#if STM32_UART_USE_UART5 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_UART5_TX_DMA_STREAM, \
STM32_UART5_TX_DMA_MSK)
#if GD32_UART_USE_UART5 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_UART5_TX_DMA_STREAM, \
GD32_UART5_TX_DMA_MSK)
#error "invalid DMA stream associated to UART5 TX"
#endif
#if STM32_UART_USE_USART6 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_USART6_RX_DMA_STREAM, \
STM32_USART6_RX_DMA_MSK)
#if GD32_UART_USE_USART6 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_USART6_RX_DMA_STREAM, \
GD32_USART6_RX_DMA_MSK)
#error "invalid DMA stream associated to USART6 RX"
#endif
#if STM32_UART_USE_USART6 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_USART6_TX_DMA_STREAM, \
STM32_USART6_TX_DMA_MSK)
#if GD32_UART_USE_USART6 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_USART6_TX_DMA_STREAM, \
GD32_USART6_TX_DMA_MSK)
#error "invalid DMA stream associated to USART6 TX"
#endif
#endif /* STM32_ADVANCED_DMA */
#endif /* GD32_ADVANCED_DMA */
#if STM32_UART_USE_UART7 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_UART7_RX_DMA_STREAM, \
STM32_UART7_RX_DMA_MSK)
#if GD32_UART_USE_UART7 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_UART7_RX_DMA_STREAM, \
GD32_UART7_RX_DMA_MSK)
#error "invalid DMA stream associated to UART7 RX"
#endif
#if STM32_UART_USE_UART7 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_UART7_TX_DMA_STREAM, \
STM32_UART7_TX_DMA_MSK)
#if GD32_UART_USE_UART7 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_UART7_TX_DMA_STREAM, \
GD32_UART7_TX_DMA_MSK)
#error "invalid DMA stream associated to UART7 TX"
#endif
#if STM32_UART_USE_UART8 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_UART8_RX_DMA_STREAM, \
STM32_UART8_RX_DMA_MSK)
#if GD32_UART_USE_UART8 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_UART8_RX_DMA_STREAM, \
GD32_UART8_RX_DMA_MSK)
#error "invalid DMA stream associated to UART8 RX"
#endif
#if STM32_UART_USE_UART8 && \
!STM32_DMA_IS_VALID_ID(STM32_UART_UART8_TX_DMA_STREAM, \
STM32_UART8_TX_DMA_MSK)
#if GD32_UART_USE_UART8 && \
!GD32_DMA_IS_VALID_ID(GD32_UART_UART8_TX_DMA_STREAM, \
GD32_UART8_TX_DMA_MSK)
#error "invalid DMA stream associated to UART8 TX"
#endif
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#if !defined(GD32_DMA_REQUIRED)
#define GD32_DMA_REQUIRED
#endif
/*===========================================================================*/
@ -705,35 +705,35 @@ struct UARTDriver {
/* External declarations. */
/*===========================================================================*/
#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__)
#if GD32_UART_USE_USART1 && !defined(__DOXYGEN__)
extern UARTDriver UARTD1;
#endif
#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__)
#if GD32_UART_USE_USART2 && !defined(__DOXYGEN__)
extern UARTDriver UARTD2;
#endif
#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__)
#if GD32_UART_USE_USART3 && !defined(__DOXYGEN__)
extern UARTDriver UARTD3;
#endif
#if STM32_UART_USE_UART4 && !defined(__DOXYGEN__)
#if GD32_UART_USE_UART4 && !defined(__DOXYGEN__)
extern UARTDriver UARTD4;
#endif
#if STM32_UART_USE_UART5 && !defined(__DOXYGEN__)
#if GD32_UART_USE_UART5 && !defined(__DOXYGEN__)
extern UARTDriver UARTD5;
#endif
#if STM32_UART_USE_USART6 && !defined(__DOXYGEN__)
#if GD32_UART_USE_USART6 && !defined(__DOXYGEN__)
extern UARTDriver UARTD6;
#endif
#if STM32_UART_USE_UART7 && !defined(__DOXYGEN__)
#if GD32_UART_USE_UART7 && !defined(__DOXYGEN__)
extern UARTDriver UARTD7;
#endif
#if STM32_UART_USE_UART8 && !defined(__DOXYGEN__)
#if GD32_UART_USE_UART8 && !defined(__DOXYGEN__)
extern UARTDriver UARTD8;
#endif

14
os/hal/ports/GD/GD32VF103/gd32_isr.c
View File

@ -244,13 +244,13 @@ void irqInit(void) {
__enable_irq();
#if HAL_USE_PAL
eclicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY, STM32_IRQ_EXTI0_TRIGGER);
eclicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY, STM32_IRQ_EXTI1_TRIGGER);
eclicEnableVector(EXTI2_IRQn, STM32_IRQ_EXTI2_PRIORITY, STM32_IRQ_EXTI2_TRIGGER);
eclicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY, STM32_IRQ_EXTI3_TRIGGER);
eclicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY, STM32_IRQ_EXTI4_TRIGGER);
eclicEnableVector(EXTI5_9_IRQn, STM32_IRQ_EXTI5_9_PRIORITY, STM32_IRQ_EXTI5_9_TRIGGER);
eclicEnableVector(EXTI10_15_IRQn, STM32_IRQ_EXTI10_15_PRIORITY, STM32_IRQ_EXTI10_15_TRIGGER);
eclicEnableVector(EXTI0_IRQn, GD32_IRQ_EXTI0_PRIORITY, GD32_IRQ_EXTI0_TRIGGER);
eclicEnableVector(EXTI1_IRQn, GD32_IRQ_EXTI1_PRIORITY, GD32_IRQ_EXTI1_TRIGGER);
eclicEnableVector(EXTI2_IRQn, GD32_IRQ_EXTI2_PRIORITY, GD32_IRQ_EXTI2_TRIGGER);
eclicEnableVector(EXTI3_IRQn, GD32_IRQ_EXTI3_PRIORITY, GD32_IRQ_EXTI3_TRIGGER);
eclicEnableVector(EXTI4_IRQn, GD32_IRQ_EXTI4_PRIORITY, GD32_IRQ_EXTI4_TRIGGER);
eclicEnableVector(EXTI5_9_IRQn, GD32_IRQ_EXTI5_9_PRIORITY, GD32_IRQ_EXTI5_9_TRIGGER);
eclicEnableVector(EXTI10_15_IRQn, GD32_IRQ_EXTI10_15_PRIORITY, GD32_IRQ_EXTI10_15_TRIGGER);
#endif
}

278
os/hal/ports/GD/GD32VF103/gd32_isr.h
View File

@ -127,78 +127,78 @@
/**
* @brief EXTI0 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI0_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI0_PRIORITY 6
#if !defined(GD32_IRQ_EXTI0_PRIORITY) || defined(__DOXYGEN__)
#define GD32_IRQ_EXTI0_PRIORITY 6
#endif
/**
* @brief EXTI1 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI1_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI1_PRIORITY 6
#if !defined(GD32_IRQ_EXTI1_PRIORITY) || defined(__DOXYGEN__)
#define GD32_IRQ_EXTI1_PRIORITY 6
#endif
/**
* @brief EXTI2 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI2_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI2_PRIORITY 6
#if !defined(GD32_IRQ_EXTI2_PRIORITY) || defined(__DOXYGEN__)
#define GD32_IRQ_EXTI2_PRIORITY 6
#endif
/**
* @brief EXTI3 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI3_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI3_PRIORITY 6
#if !defined(GD32_IRQ_EXTI3_PRIORITY) || defined(__DOXYGEN__)
#define GD32_IRQ_EXTI3_PRIORITY 6
#endif
/**
* @brief EXTI4 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI4_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI4_PRIORITY 6
#if !defined(GD32_IRQ_EXTI4_PRIORITY) || defined(__DOXYGEN__)
#define GD32_IRQ_EXTI4_PRIORITY 6
#endif
/**
* @brief EXTI9..5 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI5_9_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI5_9_PRIORITY 6
#if !defined(GD32_IRQ_EXTI5_9_PRIORITY) || defined(__DOXYGEN__)
#define GD32_IRQ_EXTI5_9_PRIORITY 6
#endif
/**
* @brief EXTI15..10 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI10_15_PRIORITY 6
#if !defined(GD32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__)
#define GD32_IRQ_EXTI10_15_PRIORITY 6
#endif
/**
* @brief EXTI16 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI16_PRIORITY 6
#if !defined(GD32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__)
#define GD32_IRQ_EXTI16_PRIORITY 6
#endif
/**
* @brief EXTI17 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI17_PRIORITY 6
#if !defined(GD32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__)
#define GD32_IRQ_EXTI17_PRIORITY 6
#endif
/**
* @brief EXTI18 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI18_PRIORITY 6
#if !defined(GD32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__)
#define GD32_IRQ_EXTI18_PRIORITY 6
#endif
/**
* @brief EXTI19 interrupt priority level setting.
*/
#if !defined(STM32_IRQ_EXTI19_PRIORITY) || defined(__DOXYGEN__)
#define STM32_IRQ_EXTI19_PRIORITY 6
#if !defined(GD32_IRQ_EXTI19_PRIORITY) || defined(__DOXYGEN__)
#define GD32_IRQ_EXTI19_PRIORITY 6
#endif
/** @} */
@ -209,123 +209,123 @@
#define ECLIC_TRIGGER_DEFAULT ECLIC_POSTIVE_EDGE_TRIGGER
#define ECLIC_DMA_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI3_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI4_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI5_9_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI10_15_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI0_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI1_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI2_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI3_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI4_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI5_9_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI10_15_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_USB_OTG1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_USB_OTG1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI0_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI1_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI2_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI3_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI4_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI5_9_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_EXTI10_15_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_CAN_CAN3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_I2C_I2C1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_I2C_I2C1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_I2C_I2C2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_I2C_I2C2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_I2C_I2C3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_I2C_I2C3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_USB_OTG1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_USB_OTG2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_RTC_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_SDC_SDIO_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM6_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM7_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM9_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM10_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM11_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM12_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM13_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM14_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM21_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_GPT_TIM22_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ICU_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ICU_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ICU_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ICU_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ICU_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ICU_TIM5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ICU_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ICU_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_PWM_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_PWM_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_PWM_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_PWM_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_PWM_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_PWM_TIM5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_PWM_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_PWM_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM1_UP_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM1_CC_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM2_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM3_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM4_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM5_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM6_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM7_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM8_UP_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM8_CC_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM14_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM15_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM16_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM17_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM20_UP_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM20_CC_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM21_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_IRQ_TIM22_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_SERIAL_USART1_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_SERIAL_USART2_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_SERIAL_USART3_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_SERIAL_UART4_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_SERIAL_UART5_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_SERIAL_USART6_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_SERIAL_UART7_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_SERIAL_UART8_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_UART_USART1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_UART_USART2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_UART_USART3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_UART_UART4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_UART_UART5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_UART_USART6_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_UART_UART7_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define STM32_UART_UART8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI3_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI4_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI5_9_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI10_15_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI0_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI1_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI2_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI3_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI4_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI5_9_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI10_15_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_USB_OTG1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_USB_OTG1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI0_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI1_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI2_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI3_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI4_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI5_9_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_EXTI10_15_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_CAN_CAN3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_I2C_I2C3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_USB_OTG1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_USB_OTG2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_RTC_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SDC_SDIO_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM6_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM7_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM9_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM10_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM11_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM12_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM13_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM14_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM21_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_GPT_TIM22_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ICU_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_PWM_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_PWM_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_PWM_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_PWM_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_PWM_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_PWM_TIM5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_PWM_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_PWM_TIM8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM1_UP_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM1_CC_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM2_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM3_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM4_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM5_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM6_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM7_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM8_UP_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM8_CC_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM14_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM15_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM16_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM17_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM20_UP_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM20_CC_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM21_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_IRQ_TIM22_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_USART1_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_USART2_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_USART3_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_UART4_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_UART5_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_USART6_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_UART7_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_SERIAL_UART8_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_USART1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_USART2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_USART3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_UART4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_UART5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_USART6_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_UART7_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
#define GD32_UART_UART8_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT
/*===========================================================================*/
/* Derived constants and error checks. */

232
os/hal/ports/GD/GD32VF103/gd32_registry.h
View File

@ -98,27 +98,27 @@
* @{
*/
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 TRUE
#define GD32_HAS_ADC1 TRUE
#define GD32_HAS_ADC2 TRUE
/* CAN attributes.*/
#define STM32_HAS_CAN1 TRUE
#define STM32_HAS_CAN2 TRUE
#define STM32_CAN_MAX_FILTERS 28
#define GD32_HAS_CAN1 TRUE
#define GD32_HAS_CAN2 TRUE
#define GD32_CAN_MAX_FILTERS 28
/* DAC attributes.*/
#define STM32_HAS_DAC1_CH1 TRUE
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define GD32_HAS_DAC1_CH1 TRUE
#define GD32_DAC_DAC1_CH1_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define STM32_HAS_DAC1_CH2 TRUE
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_DAC1_CH2 TRUE
#define GD32_DAC_DAC1_CH2_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
/* DMA attributes.*/
#define STM32_ADVANCED_DMA FALSE
#define STM32_DMA_SUPPORTS_DMAMUX FALSE
#define STM32_DMA_SUPPORTS_CSELR FALSE
#define GD32_ADVANCED_DMA FALSE
#define GD32_DMA_SUPPORTS_DMAMUX FALSE
#define GD32_DMA_SUPPORTS_CSELR FALSE
#define STM32_DMA1_NUM_CHANNELS 7
#define GD32_DMA1_NUM_CHANNELS 7
#define GD32_DMA1_CH1_HANDLER vector30
#define GD32_DMA1_CH2_HANDLER vector31
#define GD32_DMA1_CH3_HANDLER vector32
@ -134,12 +134,12 @@
#define GD32_DMA1_CH6_NUMBER 35
#define GD32_DMA1_CH7_NUMBER 36
#define STM32_DMA2_NUM_CHANNELS 5
#define STM32_DMA2_CH1_HANDLER vector75
#define STM32_DMA2_CH2_HANDLER vector76
#define STM32_DMA2_CH3_HANDLER vector77
#define STM32_DMA2_CH4_HANDLER vector78
#define STM32_DMA2_CH5_HANDLER vector79
#define GD32_DMA2_NUM_CHANNELS 5
#define GD32_DMA2_CH1_HANDLER vector75
#define GD32_DMA2_CH2_HANDLER vector76
#define GD32_DMA2_CH3_HANDLER vector77
#define GD32_DMA2_CH4_HANDLER vector78
#define GD32_DMA2_CH5_HANDLER vector79
#define GD32_DMA2_CH1_NUMBER 75
#define GD32_DMA2_CH2_NUMBER 76
#define GD32_DMA2_CH3_NUMBER 77
@ -147,182 +147,182 @@
#define GD32_DMA2_CH5_NUMBER 79
/* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 19
#define STM32_EXTI_IMR_MASK 0x00000000U
#define GD32_EXTI_NUM_LINES 19
#define GD32_EXTI_IMR_MASK 0x00000000U
/* Flash attributes.*/
#define GD32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH_SECTOR_SIZE 1024U
#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
#define STM32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/
#define GD32_FLASH_SECTOR_SIZE 1024U
#if !defined(GD32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
#define GD32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/
#endif
/* GPIO attributes.*/
#if GD32_HAS_GPIO_AB || GD32_HAS_GPIO_ABCD || GD32_HAS_GPIO_ABCDE
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
#define GD32_HAS_GPIOA TRUE
#define GD32_HAS_GPIOB TRUE
#else
#define STM32_HAS_GPIOA FALSE
#define STM32_HAS_GPIOB FALSE
#define GD32_HAS_GPIOA FALSE
#define GD32_HAS_GPIOB FALSE
#endif
#if GD32_HAS_GPIO_ABCD || GD32_HAS_GPIO_ABCDE
#define STM32_HAS_GPIOC TRUE
#define STM32_HAS_GPIOD TRUE
#define GD32_HAS_GPIOC TRUE
#define GD32_HAS_GPIOD TRUE
#else
#define STM32_HAS_GPIOC FALSE
#define STM32_HAS_GPIOD FALSE
#define GD32_HAS_GPIOC FALSE
#define GD32_HAS_GPIOD FALSE
#endif
#if GD32_HAS_GPIO_ABCDE
#define STM32_HAS_GPIOE TRUE
#define GD32_HAS_GPIOE TRUE
#else
#define STM32_HAS_GPIOE FALSE
#define GD32_HAS_GPIOE FALSE
#endif
/* I2C attributes.*/
#if GD32_HAS_I2C_0 || GD32_HAS_I2C_01
#define STM32_HAS_I2C1 TRUE
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define GD32_HAS_I2C1 TRUE
#define GD32_I2C_I2C1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#define GD32_I2C_I2C1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#else
#define STM32_HAS_I2C1 FALSE
#define GD32_HAS_I2C1 FALSE
#endif
#if GD32_HAS_I2C_01
#define STM32_HAS_I2C2 TRUE
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_I2C2 TRUE
#define GD32_I2C_I2C2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_I2C_I2C2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#else
#define STM32_HAS_I2C2 FALSE
#define GD32_HAS_I2C2 FALSE
#endif
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_IS_CALENDAR FALSE
#define GD32_HAS_RTC TRUE
#define GD32_RTC_HAS_SUBSECONDS TRUE
#define GD32_RTC_IS_CALENDAR FALSE
/* SPI attributes.*/
#if GD32_HAS_SPI_0 || GD32_HAS_SPI_012
#define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_SUPPORTS_I2S FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define GD32_HAS_SPI1 TRUE
#define GD32_SPI1_SUPPORTS_I2S FALSE
#define GD32_SPI_SPI1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_SPI_SPI1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#else
#define STM32_HAS_SPI1 FALSE
#define GD32_HAS_SPI1 FALSE
#endif
#if GD32_HAS_SPI_012
#define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_SUPPORTS_I2S TRUE
#define STM32_SPI2_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define GD32_HAS_SPI2 TRUE
#define GD32_SPI2_SUPPORTS_I2S TRUE
#define GD32_SPI2_I2S_FULLDUPLEX FALSE
#define GD32_SPI_SPI2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define GD32_SPI_SPI2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_SUPPORTS_I2S TRUE
#define STM32_SPI3_I2S_FULLDUPLEX FALSE
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define GD32_HAS_SPI3 TRUE
#define GD32_SPI3_SUPPORTS_I2S TRUE
#define GD32_SPI3_I2S_FULLDUPLEX FALSE
#define GD32_SPI_SPI3_RX_DMA_STREAM GD32_DMA_STREAM_ID(2, 1)
#define GD32_SPI_SPI3_TX_DMA_STREAM GD32_DMA_STREAM_ID(2, 2)
#else
#define STM32_HAS_SPI2 FALSE
#define STM32_HAS_SPI3 FALSE
#define GD32_HAS_SPI2 FALSE
#define GD32_HAS_SPI3 FALSE
#endif
/* TIM attributes.*/
#define STM32_TIM_MAX_CHANNELS 4
#define GD32_TIM_MAX_CHANNELS 4
#define STM32_HAS_TIM1 TRUE
#define STM32_TIM1_IS_32BITS FALSE
#define STM32_TIM1_CHANNELS 4
#define GD32_HAS_TIM1 TRUE
#define GD32_TIM1_IS_32BITS FALSE
#define GD32_TIM1_CHANNELS 4
#if GD32_HAS_TIM_12 || GD32_HAS_TIM_1234
#define STM32_HAS_TIM2 TRUE
#define STM32_TIM2_IS_32BITS FALSE
#define STM32_TIM2_CHANNELS 4
#define GD32_HAS_TIM2 TRUE
#define GD32_TIM2_IS_32BITS FALSE
#define GD32_TIM2_CHANNELS 4
#define STM32_HAS_TIM3 TRUE
#define STM32_TIM3_IS_32BITS FALSE
#define STM32_TIM3_CHANNELS 4
#define GD32_HAS_TIM3 TRUE
#define GD32_TIM3_IS_32BITS FALSE
#define GD32_TIM3_CHANNELS 4
#else
#define STM32_HAS_TIM2 FALSE
#define STM32_HAS_TIM3 FALSE
#define GD32_HAS_TIM2 FALSE
#define GD32_HAS_TIM3 FALSE
#endif
#if GD32_HAS_TIM_1234
#define STM32_HAS_TIM4 TRUE
#define STM32_TIM4_IS_32BITS FALSE
#define STM32_TIM4_CHANNELS 4
#define GD32_HAS_TIM4 TRUE
#define GD32_TIM4_IS_32BITS FALSE
#define GD32_TIM4_CHANNELS 4
#define STM32_HAS_TIM5 TRUE
#define STM32_TIM5_IS_32BITS FALSE
#define STM32_TIM5_CHANNELS 4
#define GD32_HAS_TIM5 TRUE
#define GD32_TIM5_IS_32BITS FALSE
#define GD32_TIM5_CHANNELS 4
#else
#define STM32_HAS_TIM4 FALSE
#define STM32_HAS_TIM5 FALSE
#define GD32_HAS_TIM4 FALSE
#define GD32_HAS_TIM5 FALSE
#endif
#define STM32_HAS_TIM6 TRUE
#define STM32_TIM6_IS_32BITS FALSE
#define STM32_TIM6_CHANNELS 0
#define GD32_HAS_TIM6 TRUE
#define GD32_TIM6_IS_32BITS FALSE
#define GD32_TIM6_CHANNELS 0
#define STM32_HAS_TIM7 TRUE
#define STM32_TIM7_IS_32BITS FALSE
#define STM32_TIM7_CHANNELS 0
#define GD32_HAS_TIM7 TRUE
#define GD32_TIM7_IS_32BITS FALSE
#define GD32_TIM7_CHANNELS 0
/* USART attributes.*/
#if GD32_HAS_USART_01 || GD32_HAS_USART_012 || GD32_HAS_USART_01234
#define STM32_HAS_USART1 TRUE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define GD32_HAS_USART1 TRUE
#define GD32_UART_USART1_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 5)
#define GD32_UART_USART1_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 4)
#define STM32_HAS_USART2 TRUE
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define GD32_HAS_USART2 TRUE
#define GD32_UART_USART2_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 6)
#define GD32_UART_USART2_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 7)
#else
#define STM32_HAS_USART1 FALSE
#define STM32_HAS_USART2 FALSE
#define GD32_HAS_USART1 FALSE
#define GD32_HAS_USART2 FALSE
#endif
#if GD32_HAS_USART_012 || GD32_HAS_USART_01234
#define STM32_HAS_USART3 TRUE
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define GD32_HAS_USART3 TRUE
#define GD32_UART_USART3_RX_DMA_STREAM GD32_DMA_STREAM_ID(1, 3)
#define GD32_UART_USART3_TX_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#else
#define STM32_HAS_USART3 FALSE
#define GD32_HAS_USART3 FALSE
#endif
#if GD32_HAS_USART_01234
#define STM32_HAS_UART4 TRUE
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_HAS_UART5 TRUE
#define GD32_HAS_UART4 TRUE
#define GD32_UART_UART4_RX_DMA_STREAM GD32_DMA_STREAM_ID(2, 3)
#define GD32_UART_UART4_TX_DMA_STREAM GD32_DMA_STREAM_ID(2, 5)
#define GD32_HAS_UART5 TRUE
#else
#define STM32_HAS_UART4 FALSE
#define STM32_HAS_UART5 FALSE
#define GD32_HAS_UART4 FALSE
#define GD32_HAS_UART5 FALSE
#endif
/* USB attributes.*/
#define STM32_OTG_STEPPING 1
#define STM32_HAS_OTG1 TRUE
#define STM32_OTG1_ENDPOINTS 3
#define GD32_OTG_STEPPING 1
#define GD32_HAS_OTG1 TRUE
#define GD32_OTG1_ENDPOINTS 3
#define STM32_HAS_USB TRUE
#define GD32_HAS_USB TRUE
/* IWDG attributes.*/
#define STM32_HAS_IWDG TRUE
#define STM32_IWDG_IS_WINDOWED FALSE
#define GD32_HAS_IWDG TRUE
#define GD32_IWDG_IS_WINDOWED FALSE
/* FSMC attributes.*/
#if GD32_HAS_EXMC
#define STM32_HAS_FSMC TRUE
#define GD32_HAS_FSMC TRUE
#else
#define STM32_HAS_FSMC FALSE
#define GD32_HAS_FSMC FALSE
#endif
/* CRC attributes.*/
#define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE FALSE
#define GD32_HAS_CRC TRUE
#define GD32_CRC_PROGRAMMABLE FALSE
#endif

30
os/hal/ports/GD/GD32VF103/hal_adc_lld.c
View File

@ -35,7 +35,7 @@
/*===========================================================================*/
/** @brief ADC1 driver identifier.*/
#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
#if GD32_ADC_USE_ADC1 || defined(__DOXYGEN__)
ADCDriver ADCD1;
#endif
@ -56,17 +56,17 @@ ADCDriver ADCD1;
static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
/* DMA errors handling.*/
if ((flags & STM32_DMA_ISR_TEIF) != 0) {
if ((flags & GD32_DMA_ISR_TEIF) != 0) {
/* DMA, this could help only if the DMA tries to access an unmapped
address space or violates alignment rules.*/
_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
}
else {
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
if ((flags & GD32_DMA_ISR_TCIF) != 0) {
/* Transfer complete processing.*/
_adc_isr_full_code(adcp);
}
else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
else if ((flags & GD32_DMA_ISR_HTIF) != 0) {
/* Half transfer processing.*/
_adc_isr_half_code(adcp);
}
@ -88,15 +88,15 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
*/
void adc_lld_init(void) {
#if STM32_ADC_USE_ADC1
#if GD32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
ADCD1.dmastp = NULL;
ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_TEIE;
ADCD1.dmamode = GD32_DMA_CR_PL(GD32_ADC_ADC1_DMA_PRIORITY) |
GD32_DMA_CR_MSIZE_HWORD | GD32_DMA_CR_PSIZE_HWORD |
GD32_DMA_CR_MINC | GD32_DMA_CR_TCIE |
GD32_DMA_CR_TEIE;
/* Temporary activation.*/
rccEnableADC1(true);
@ -130,10 +130,10 @@ void adc_lld_start(ADCDriver *adcp) {
/* If in stopped state then enables the ADC and DMA clocks.*/
if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1
#if GD32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
adcp->dmastp = dmaStreamAllocI(STM32_DMA_STREAM_ID(1, 1),
STM32_ADC_ADC1_IRQ_PRIORITY,
adcp->dmastp = dmaStreamAllocI(GD32_DMA_STREAM_ID(1, 1),
GD32_ADC_ADC1_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
@ -160,7 +160,7 @@ void adc_lld_stop(ADCDriver *adcp) {
/* If in ready state then disables the ADC clock.*/
if (adcp->state == ADC_READY) {
#if STM32_ADC_USE_ADC1
#if GD32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
ADC1->CR1 = 0;
ADC1->CR2 = 0;
@ -188,11 +188,11 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
/* DMA setup.*/
mode = adcp->dmamode;
if (grpp->circular) {
mode |= STM32_DMA_CR_CIRC;
mode |= GD32_DMA_CR_CIRC;
if (adcp->depth > 1) {
/* If circular buffer depth > 1, then the half transfer interrupt
is enabled in order to allow streaming processing.*/
mode |= STM32_DMA_CR_HTIE;
mode |= GD32_DMA_CR_HTIE;
}
}
dmaStreamSetMemory0(adcp->dmastp, adcp->samples);

22
os/hal/ports/GD/GD32VF103/hal_adc_lld.h
View File

@ -90,22 +90,22 @@
* @details If set to @p TRUE the support for ADC1 is included.
* @note The default is @p TRUE.
*/
#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
#define STM32_ADC_USE_ADC1 FALSE
#if !defined(GD32_ADC_USE_ADC1) || defined(__DOXYGEN__)
#define GD32_ADC_USE_ADC1 FALSE
#endif
/**
* @brief ADC1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#if !defined(GD32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ADC_ADC1_DMA_PRIORITY 2
#endif
/**
* @brief ADC1 interrupt priority level setting.
*/
#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#if !defined(GD32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ADC_ADC1_IRQ_PRIORITY 5
#endif
/** @} */
@ -113,16 +113,16 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
#if GD32_ADC_USE_ADC1 && !GD32_HAS_ADC1
#error "ADC1 not present in the selected device"
#endif
#if !STM32_ADC_USE_ADC1
#if !GD32_ADC_USE_ADC1
#error "ADC driver activated but no ADC peripheral assigned"
#endif
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#if !defined(GD32_DMA_REQUIRED)
#define GD32_DMA_REQUIRED
#endif
/*===========================================================================*/
@ -261,7 +261,7 @@ typedef enum {
/* External declarations. */
/*===========================================================================*/
#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
#if GD32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
extern ADCDriver ADCD1;
#endif

32
os/hal/ports/GD/GD32VF103/hal_efl_lld.c
View File

@ -32,8 +32,8 @@
/* Driver local definitions. */
/*===========================================================================*/
#define STM32_FLASH_LINE_SIZE 2U
#define STM32_FLASH_LINE_MASK (STM32_FLASH_LINE_SIZE - 1U)
#define GD32_FLASH_LINE_SIZE 2U
#define GD32_FLASH_LINE_MASK (GD32_FLASH_LINE_SIZE - 1U)
/*===========================================================================*/
/* Driver exported variables. */
@ -51,15 +51,15 @@ EFlashDriver EFLD1;
static const flash_descriptor_t efl_lld_descriptor = {
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH_NUMBER_OF_BANKS *
STM32_FLASH_SECTORS_PER_BANK,
.page_size = GD32_FLASH_LINE_SIZE,
.sectors_count = GD32_FLASH_NUMBER_OF_BANKS *
GD32_FLASH_SECTORS_PER_BANK,
.sectors = NULL,
.sectors_size = STM32_FLASH_SECTOR_SIZE,
.sectors_size = GD32_FLASH_SECTOR_SIZE,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH_NUMBER_OF_BANKS *
STM32_FLASH_SECTORS_PER_BANK *
STM32_FLASH_SECTOR_SIZE
.size = GD32_FLASH_NUMBER_OF_BANKS *
GD32_FLASH_SECTORS_PER_BANK *
GD32_FLASH_SECTOR_SIZE
};
/*===========================================================================*/
@ -274,8 +274,8 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
volatile uint16_t *address;
union {
uint16_t hw[STM32_FLASH_LINE_SIZE / sizeof (uint16_t)];
uint8_t b[STM32_FLASH_LINE_SIZE / sizeof (uint8_t)];
uint16_t hw[GD32_FLASH_LINE_SIZE / sizeof (uint16_t)];
uint8_t b[GD32_FLASH_LINE_SIZE / sizeof (uint8_t)];
} line;
/* Unwritten bytes are initialized to all ones.*/
@ -283,16 +283,16 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
/* Programming address aligned to flash lines.*/
address = (volatile uint16_t *)(efl_lld_descriptor.address +
(offset & ~STM32_FLASH_LINE_MASK));
(offset & ~GD32_FLASH_LINE_MASK));
/* Copying data inside the prepared line.*/
do {
line.b[offset & STM32_FLASH_LINE_MASK] = *pp;
line.b[offset & GD32_FLASH_LINE_MASK] = *pp;
offset++;
n--;
pp++;
}
while ((n > 0U) & ((offset & STM32_FLASH_LINE_MASK) != 0U));
while ((n > 0U) & ((offset & GD32_FLASH_LINE_MASK) != 0U));
/* Programming line.*/
address[0] = line.hw[0];
@ -420,7 +420,7 @@ flash_error_t efl_lld_query_erase(void *instance, uint32_t *wait_time) {
/* Recommended time before polling again, this is a simplified
implementation.*/
if (wait_time != NULL) {
*wait_time = (uint32_t)STM32_FLASH_WAIT_TIME_MS;
*wait_time = (uint32_t)GD32_FLASH_WAIT_TIME_MS;
}
err = FLASH_BUSY_ERASING;
@ -470,7 +470,7 @@ flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) {
devp->state = FLASH_READ;
/* Scanning the sector space.*/
for (i = 0U; i < STM32_FLASH_SECTOR_SIZE / sizeof(uint32_t); i++) {
for (i = 0U; i < GD32_FLASH_SECTOR_SIZE / sizeof(uint32_t); i++) {
if (*address != 0xFFFFFFFFU) {
err = FLASH_ERROR_VERIFY;
break;

16
os/hal/ports/GD/GD32VF103/hal_efl_lld.h
View File

@ -42,8 +42,8 @@
/**
* @brief Suggested wait time during erase operations polling.
*/
#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__)
#define STM32_FLASH_WAIT_TIME_MS 1
#if !defined(GD32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__)
#define GD32_FLASH_WAIT_TIME_MS 1
#endif
/** @} */
@ -51,16 +51,16 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if !defined(STM32_FLASH_SECTOR_SIZE)
#error "STM32_FLASH_SECTOR_SIZE not defined in registry"
#if !defined(GD32_FLASH_SECTOR_SIZE)
#error "GD32_FLASH_SECTOR_SIZE not defined in registry"
#endif
#if !defined(STM32_FLASH_NUMBER_OF_BANKS)
#error "STM32_FLASH_NUMBER_OF_BANKS not defined in registry"
#if !defined(GD32_FLASH_NUMBER_OF_BANKS)
#error "GD32_FLASH_NUMBER_OF_BANKS not defined in registry"
#endif
#if !defined(STM32_FLASH_SECTORS_PER_BANK)
#error "STM32_FLASH_SECTORS_PER_BANK not defined in registry"
#if !defined(GD32_FLASH_SECTORS_PER_BANK)
#error "GD32_FLASH_SECTORS_PER_BANK not defined in registry"
#endif
/*===========================================================================*/

78
os/hal/ports/GD/GD32VF103/hal_lld.c
View File

@ -36,7 +36,7 @@
* @brief CMSIS system core clock variable.
* @note It is declared in system_stm32f10x.h.
*/
uint32_t SystemCoreClock = STM32_HCLK;
uint32_t SystemCoreClock = GD32_HCLK;
/*===========================================================================*/
/* Driver local variables and types. */
@ -58,15 +58,15 @@ static void hal_lld_backup_domain_init(void) {
#if HAL_USE_RTC
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
if ((RCC->BDCR & GD32_RTCSEL_MASK) != GD32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
}
/* If enabled then the LSE is started.*/
#if STM32_LSE_ENABLED
#if defined(STM32_LSE_BYPASS)
#if GD32_LSE_ENABLED
#if defined(GD32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
@ -75,14 +75,14 @@ static void hal_lld_backup_domain_init(void) {
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
#endif /* STM32_LSE_ENABLED */
#endif /* GD32_LSE_ENABLED */
#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
#if GD32_RTCSEL != GD32_RTCSEL_NOCLOCK
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
RCC->BDCR |= STM32_RTCSEL;
RCC->BDCR |= GD32_RTCSEL;
/* Prescaler value loaded in registers.*/
rtc_lld_set_prescaler();
@ -90,7 +90,7 @@ static void hal_lld_backup_domain_init(void) {
/* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
}
#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
#endif /* GD32_RTCSEL != GD32_RTCSEL_NOCLOCK */
#endif /* HAL_USE_RTC */
}
@ -98,7 +98,7 @@ static void hal_lld_backup_domain_init(void) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
#if defined(GD32_DMA_REQUIRED) || defined(__DOXYGEN__)
#if defined(GD32_DMA2_CH45_HANDLER) || defined(__DOXYGEN__)
/**
* @brief DMA2 streams 4 and 5 shared ISR.
@ -110,15 +110,15 @@ OSAL_IRQ_HANDLER(GD32_DMA2_CH45_HANDLER) {
OSAL_IRQ_PROLOGUE();
/* Check on channel 4 of DMA2.*/
dmaServeInterrupt(STM32_DMA2_STREAM4);
dmaServeInterrupt(GD32_DMA2_STREAM4);
/* Check on channel 5 of DMA2.*/
dmaServeInterrupt(STM32_DMA2_STREAM5);
dmaServeInterrupt(GD32_DMA2_STREAM5);
OSAL_IRQ_EPILOGUE();
}
#endif /* defined(GD32_DMA2_CH45_HANDLER) */
#endif /* defined(STM32_DMA_REQUIRED) */
#endif /* defined(GD32_DMA_REQUIRED) */
/*===========================================================================*/
/* Driver exported functions. */
@ -143,7 +143,7 @@ void hal_lld_init(void) {
hal_lld_backup_domain_init();
/* DMA subsystems initialization.*/
#if defined(STM32_DMA_REQUIRED)
#if defined(GD32_DMA_REQUIRED)
dmaInit();
#endif
@ -151,9 +151,9 @@ void hal_lld_init(void) {
irqInit();
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
#endif /* STM32_PVD_ENABLE */
#if GD32_PVD_ENABLE
PWR->CR |= PWR_CR_PVDE | (GD32_PLS & GD32_PLS_MASK);
#endif /* GD32_PVD_ENABLE */
}
/**
@ -170,7 +170,7 @@ void hal_lld_init(void) {
*/
void gd32_clock_init(void) {
#if !STM32_NO_INIT
#if !GD32_NO_INIT
/* HSI setup, it enforces the reset situation in order to handle possible
problems with JTAG probes and re-initializations.*/
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
@ -188,8 +188,8 @@ void gd32_clock_init(void) {
RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
RCC->CFGR = 0; /* CFGR reset value. */
#if STM32_HSE_ENABLED
#if defined(STM32_HSE_BYPASS)
#if GD32_HSE_ENABLED
#if defined(GD32_HSE_BYPASS)
/* HSE Bypass.*/
RCC->CR |= RCC_CR_HSEBYP;
#endif
@ -199,7 +199,7 @@ void gd32_clock_init(void) {
; /* Waits until HSE is stable. */
#endif
#if STM32_LSI_ENABLED
#if GD32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSION;
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
@ -207,58 +207,58 @@ void gd32_clock_init(void) {
#endif
/* Settings of various dividers and multipliers in CFGR2.*/
/*RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 |
STM32_PREDIV1 | STM32_PREDIV1SRC;*/
/*RCC->CFGR2 = GD32_PLL3MUL | GD32_PLL2MUL | GD32_PREDIV2 |
GD32_PREDIV1 | GD32_PREDIV1SRC;*/
/* PLL2 setup, if activated.*/
#if STM32_ACTIVATE_PLL2
#if GD32_ACTIVATE_PLL2
RCC->CR |= RCC_CR_PLL2ON;
while (!(RCC->CR & RCC_CR_PLL2RDY))
; /* Waits until PLL2 is stable. */
#endif
/* PLL3 setup, if activated.*/
#if STM32_ACTIVATE_PLL3
#if GD32_ACTIVATE_PLL3
RCC->CR |= RCC_CR_PLL3ON;
while (!(RCC->CR & RCC_CR_PLL3RDY))
; /* Waits until PLL3 is stable. */
#endif
/* PLL1 setup, if activated.*/
//#if STM32_ACTIVATE_PLL1
#if STM32_ACTIVATE_PLL
RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
//#if GD32_ACTIVATE_PLL1
#if GD32_ACTIVATE_PLL
RCC->CFGR |= GD32_PLLMUL | GD32_PLLSRC;
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL1 is stable. */
#endif
/* Clock settings.*/
#if STM32_HAS_OTG1
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLSRC |
STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
#if GD32_HAS_OTG1
RCC->CFGR = GD32_MCOSEL | GD32_USBPRE | GD32_PLLMUL | GD32_PLLSRC |
GD32_ADCPRE | GD32_PPRE2 | GD32_PPRE1 | GD32_HPRE;
#else
RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC |
STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
RCC->CFGR = GD32_MCO | GD32_PLLMUL | GD32_PLLSRC |
GD32_ADCPRE | GD32_PPRE2 | GD32_PPRE1 | GD32_HPRE;
#endif
/* Flash setup and final clock selection. */
FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */
FLASH->ACR = GD32_FLASHBITS; /* Flash wait states depending on clock. */
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
(STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
(GD32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
}
/* Switching to the configured clock source if it is different from HSI.*/
#if (STM32_SW != STM32_SW_HSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
#if (GD32_SW != GD32_SW_HSI)
RCC->CFGR |= GD32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (GD32_SW << 2))
;
#endif
#if !STM32_HSI_ENABLED
#if !GD32_HSI_ENABLED
RCC->CR &= ~RCC_CR_HSION;
#endif
#endif /* !STM32_NO_INIT */
#endif /* !GD32_NO_INIT */
}
#else
void gd32_clock_init(void) {}

58
os/hal/ports/GD/GD32VF103/hal_lld.h
View File

@ -20,10 +20,10 @@
* @brief STM32F1xx HAL subsystem low level driver header.
* @pre This module requires the following macros to be defined in the
* @p board.h file:
* - STM32_LSECLK.
* - STM32_LSE_BYPASS (optionally).
* - STM32_HSECLK.
* - STM32_HSE_BYPASS (optionally).
* - GD32_LSECLK.
* - GD32_LSE_BYPASS (optionally).
* - GD32_HSECLK.
* - GD32_HSE_BYPASS (optionally).
* .
* One of the following macros must also be defined:
* - STM32F100xB for Value Line Medium Density devices.
@ -76,23 +76,23 @@
* @name Internal clock sources
* @{
*/
#define STM32_HSICLK 8000000 /**< High speed internal clock. */
#define STM32_LSICLK 40000 /**< Low speed internal clock. */
#define GD32_HSICLK 8000000 /**< High speed internal clock. */
#define GD32_LSICLK 40000 /**< Low speed internal clock. */
/** @} */
/**
* @name PWR_CR register bits definitions
* @{
*/
#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
#define GD32_PLS_MASK (7 << 5) /**< PLS bits mask. */
#define GD32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
#define GD32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
#define GD32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
#define GD32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
#define GD32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
#define GD32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
#define GD32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
#define GD32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
/** @} */
/*===========================================================================*/
@ -110,50 +110,50 @@
/**
* @brief Disables the PWR/RCC initialization in the HAL.
*/
#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
#define STM32_NO_INIT FALSE
#if !defined(GD32_NO_INIT) || defined(__DOXYGEN__)
#define GD32_NO_INIT FALSE
#endif
/**
* @brief Enables or disables the programmable voltage detector.
*/
#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
#define STM32_PVD_ENABLE FALSE
#if !defined(GD32_PVD_ENABLE) || defined(__DOXYGEN__)
#define GD32_PVD_ENABLE FALSE
#endif
/**
* @brief Sets voltage level for programmable voltage detector.
*/
#if !defined(STM32_PLS) || defined(__DOXYGEN__)
#define STM32_PLS STM32_PLS_LEV0
#if !defined(GD32_PLS) || defined(__DOXYGEN__)
#define GD32_PLS GD32_PLS_LEV0
#endif
/**
* @brief Enables or disables the HSI clock source.
*/
#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
#define STM32_HSI_ENABLED TRUE
#if !defined(GD32_HSI_ENABLED) || defined(__DOXYGEN__)
#define GD32_HSI_ENABLED TRUE
#endif
/**
* @brief Enables or disables the LSI clock source.
*/
#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
#define STM32_LSI_ENABLED FALSE
#if !defined(GD32_LSI_ENABLED) || defined(__DOXYGEN__)
#define GD32_LSI_ENABLED FALSE
#endif
/**
* @brief Enables or disables the HSE clock source.
*/
#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
#define STM32_HSE_ENABLED TRUE
#if !defined(GD32_HSE_ENABLED) || defined(__DOXYGEN__)
#define GD32_HSE_ENABLED TRUE
#endif
/**
* @brief Enables or disables the LSE clock source.
*/
#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
#define STM32_LSE_ENABLED FALSE
#if !defined(GD32_LSE_ENABLED) || defined(__DOXYGEN__)
#define GD32_LSE_ENABLED FALSE
#endif
/** @} */

486
os/hal/ports/GD/GD32VF103/hal_lld_f103.h
View File

@ -43,126 +43,126 @@
/**
* @brief Maximum system clock frequency.
*/
#define STM32_SYSCLK_MAX 120000000
#define GD32_SYSCLK_MAX 120000000
/**
* @brief Maximum HSE clock frequency.
*/
#define STM32_HSECLK_MAX 25000000
#define GD32_HSECLK_MAX 25000000
/**
* @brief Minimum HSE clock frequency.
*/
#define STM32_HSECLK_MIN 1000000
#define GD32_HSECLK_MIN 1000000
/**
* @brief Maximum LSE clock frequency.
*/
#define STM32_LSECLK_MAX 1000000
#define GD32_LSECLK_MAX 1000000
/**
* @brief Minimum LSE clock frequency.
*/
#define STM32_LSECLK_MIN 32768
#define GD32_LSECLK_MIN 32768
/**
* @brief Maximum PLLs input clock frequency.
*/
#define STM32_PLLIN_MAX 25000000
#define GD32_PLLIN_MAX 25000000
/**
* @brief Minimum PLLs input clock frequency.
*/
#define STM32_PLLIN_MIN 1000000
#define GD32_PLLIN_MIN 1000000
/**
* @brief Maximum PLL output clock frequency.
*/
#define STM32_PLLOUT_MAX 120000000
#define GD32_PLLOUT_MAX 120000000
/**
* @brief Minimum PLL output clock frequency.
*/
#define STM32_PLLOUT_MIN 16000000
#define GD32_PLLOUT_MIN 16000000
/**
* @brief Maximum APB1 clock frequency.
*/
#define STM32_PCLK1_MAX 36000000
#define GD32_PCLK1_MAX 36000000
/**
* @brief Maximum APB2 clock frequency.
*/
#define STM32_PCLK2_MAX 72000000
#define GD32_PCLK2_MAX 72000000
/**
* @brief Maximum ADC clock frequency.
*/
#define STM32_ADCCLK_MAX 14000000
#define GD32_ADCCLK_MAX 14000000
/** @} */
/**
* @name RCU_CFG0 register bits definitions
* @{
*/
#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
#define GD32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
#define GD32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
#define GD32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
#define GD32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
#define GD32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
#define GD32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
#define GD32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
#define GD32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
#define GD32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
#define GD32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
#define GD32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
#define GD32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
#define GD32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
#define GD32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
#define GD32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
#define GD32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
#define GD32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
#define GD32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
#define GD32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
#define GD32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
#define GD32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
#define GD32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
#define GD32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
#define GD32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
#define GD32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
#define GD32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
#define GD32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
#define GD32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
#define GD32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
#define GD32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
#define STM32_USBPRE_DIV1P5 (0 << 22) /**< PLLOUT divided by 1.5. */
#define STM32_USBPRE_DIV1 (1 << 22) /**< PLLOUT divided by 1. */
#define STM32_USBPRE_DIV2P5 (2 << 22) /**< PLLOUT divided by 2.5. */
#define STM32_USBPRE_DIV2 (3 << 22) /**< PLLOUT divided by 2. */
#define GD32_USBPRE_DIV1P5 (0 << 22) /**< PLLOUT divided by 1.5. */
#define GD32_USBPRE_DIV1 (1 << 22) /**< PLLOUT divided by 1. */
#define GD32_USBPRE_DIV2P5 (2 << 22) /**< PLLOUT divided by 2.5. */
#define GD32_USBPRE_DIV2 (3 << 22) /**< PLLOUT divided by 2. */
#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
#define GD32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define GD32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
#define GD32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
#define GD32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define GD32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
/** @} */
/**
* @name RCU_BDCR register bits definitions
* @{
*/
#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
#define GD32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
#define GD32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define GD32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
#define GD32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
#define GD32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
RTC clock. */
/** @} */
@ -181,8 +181,8 @@
* @note The default value is calculated for a 72MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_SW) || defined(__DOXYGEN__)
#define STM32_SW STM32_SW_PLL
#if !defined(GD32_SW) || defined(__DOXYGEN__)
#define GD32_SW GD32_SW_PLL
#endif
/**
@ -192,8 +192,8 @@
* @note The default value is calculated for a 72MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
#define STM32_PLLSRC STM32_PLLSRC_HSE
#if !defined(GD32_PLLSRC) || defined(__DOXYGEN__)
#define GD32_PLLSRC GD32_PLLSRC_HSE
#endif
/**
@ -203,8 +203,8 @@
* @note The default value is calculated for a 72MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#if !defined(GD32_PLLXTPRE) || defined(__DOXYGEN__)
#define GD32_PLLXTPRE GD32_PLLXTPRE_DIV1
#endif
/**
@ -213,8 +213,8 @@
* @note The default value is calculated for a 72MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLMUL_VALUE 9
#if !defined(GD32_PLLMUL_VALUE) || defined(__DOXYGEN__)
#define GD32_PLLMUL_VALUE 9
#endif
/**
@ -222,57 +222,57 @@
* @note The default value is calculated for a 72MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
#define STM32_HPRE STM32_HPRE_DIV1
#if !defined(GD32_HPRE) || defined(__DOXYGEN__)
#define GD32_HPRE GD32_HPRE_DIV1
#endif
/**
* @brief APB1 prescaler value.
*/
#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
#define STM32_PPRE1 STM32_PPRE1_DIV2
#if !defined(GD32_PPRE1) || defined(__DOXYGEN__)
#define GD32_PPRE1 GD32_PPRE1_DIV2
#endif
/**
* @brief APB2 prescaler value.
*/
#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
#define STM32_PPRE2 STM32_PPRE2_DIV2
#if !defined(GD32_PPRE2) || defined(__DOXYGEN__)
#define GD32_PPRE2 GD32_PPRE2_DIV2
#endif
/**
* @brief ADC prescaler value.
*/
#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#if !defined(GD32_ADCPRE) || defined(__DOXYGEN__)
#define GD32_ADCPRE GD32_ADCPRE_DIV4
#endif
/**
* @brief USB clock setting.
*/
#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
#define STM32_USB_CLOCK_REQUIRED TRUE
#if !defined(GD32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
#define GD32_USB_CLOCK_REQUIRED TRUE
#endif
/**
* @brief USB prescaler initialization.
*/
#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
#define STM32_USBPRE STM32_USBPRE_DIV1P5
#if !defined(GD32_USBPRE) || defined(__DOXYGEN__)
#define GD32_USBPRE GD32_USBPRE_DIV1P5
#endif
/**
* @brief MCO pin setting.
*/
#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#if !defined(GD32_MCOSEL) || defined(__DOXYGEN__)
#define GD32_MCOSEL GD32_MCOSEL_NOCLOCK
#endif
/**
* @brief RTC clock source.
*/
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCSEL STM32_RTCSEL_LSI
#if !defined(GD32_RTCSEL) || defined(__DOXYGEN__)
#define GD32_RTCSEL GD32_RTCSEL_LSI
#endif
/** @} */
@ -290,259 +290,259 @@
/*
* HSI related checks.
*/
#if STM32_HSI_ENABLED
#else /* !STM32_HSI_ENABLED */
#if GD32_HSI_ENABLED
#else /* !GD32_HSI_ENABLED */
#if STM32_SW == STM32_SW_HSI
#error "HSI not enabled, required by STM32_SW"
#if GD32_SW == GD32_SW_HSI
#error "HSI not enabled, required by GD32_SW"
#endif
#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
#if (GD32_SW == GD32_SW_PLL) && (GD32_PLLSRC == GD32_PLLSRC_HSI)
#error "HSI not enabled, required by GD32_SW and GD32_PLLSRC"
#endif
#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
(STM32_PLLSRC == STM32_PLLSRC_HSI))
#error "HSI not enabled, required by STM32_MCOSEL"
#if (GD32_MCOSEL == GD32_MCOSEL_HSI) || \
((GD32_MCOSEL == GD32_MCOSEL_PLLDIV2) && \
(GD32_PLLSRC == GD32_PLLSRC_HSI))
#error "HSI not enabled, required by GD32_MCOSEL"
#endif
#endif /* !STM32_HSI_ENABLED */
#endif /* !GD32_HSI_ENABLED */
/*
* HSE related checks.
*/
#if STM32_HSE_ENABLED
#if GD32_HSE_ENABLED
#if STM32_HSECLK == 0
#if GD32_HSECLK == 0
#error "HSE frequency not defined"
#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
#elif (GD32_HSECLK < GD32_HSECLK_MIN) || (GD32_HSECLK > GD32_HSECLK_MAX)
#error "GD32_HSECLK outside acceptable range (GD32_HSECLK_MIN...GD32_HSECLK_MAX)"
#endif
#else /* !STM32_HSE_ENABLED */
#else /* !GD32_HSE_ENABLED */
#if STM32_SW == STM32_SW_HSE
#error "HSE not enabled, required by STM32_SW"
#if GD32_SW == GD32_SW_HSE
#error "HSE not enabled, required by GD32_SW"
#endif
#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
#if (GD32_SW == GD32_SW_PLL) && (GD32_PLLSRC == GD32_PLLSRC_HSE)
#error "HSE not enabled, required by GD32_SW and GD32_PLLSRC"
#endif
#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
(STM32_PLLSRC == STM32_PLLSRC_HSE))
#error "HSE not enabled, required by STM32_MCOSEL"
#if (GD32_MCOSEL == GD32_MCOSEL_HSE) || \
((GD32_MCOSEL == GD32_MCOSEL_PLLDIV2) && \
(GD32_PLLSRC == GD32_PLLSRC_HSE))
#error "HSE not enabled, required by GD32_MCOSEL"
#endif
#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
#error "HSE not enabled, required by STM32_RTCSEL"
#if GD32_RTCSEL == GD32_RTCSEL_HSEDIV
#error "HSE not enabled, required by GD32_RTCSEL"
#endif
#endif /* !STM32_HSE_ENABLED */
#endif /* !GD32_HSE_ENABLED */
/*
* LSI related checks.
*/
#if STM32_LSI_ENABLED
#else /* !STM32_LSI_ENABLED */
#if GD32_LSI_ENABLED
#else /* !GD32_LSI_ENABLED */
#if STM32_RTCSEL == STM32_RTCSEL_LSI
#error "LSI not enabled, required by STM32_RTCSEL"
#if GD32_RTCSEL == GD32_RTCSEL_LSI
#error "LSI not enabled, required by GD32_RTCSEL"
#endif
#endif /* !STM32_LSI_ENABLED */
#endif /* !GD32_LSI_ENABLED */
/*
* LSE related checks.
*/
#if STM32_LSE_ENABLED
#if GD32_LSE_ENABLED
#if (STM32_LSECLK == 0)
#if (GD32_LSECLK == 0)
#error "LSE frequency not defined"
#endif
#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
#if (GD32_LSECLK < GD32_LSECLK_MIN) || (GD32_LSECLK > GD32_LSECLK_MAX)
#error "GD32_LSECLK outside acceptable range (GD32_LSECLK_MIN...GD32_LSECLK_MAX)"
#endif
#else /* !STM32_LSE_ENABLED */
#else /* !GD32_LSE_ENABLED */
#if STM32_RTCSEL == STM32_RTCSEL_LSE
#error "LSE not enabled, required by STM32_RTCSEL"
#if GD32_RTCSEL == GD32_RTCSEL_LSE
#error "LSE not enabled, required by GD32_RTCSEL"
#endif
#endif /* !STM32_LSE_ENABLED */
#endif /* !GD32_LSE_ENABLED */
/* PLL activation conditions.*/
#if STM32_USB_CLOCK_REQUIRED || \
(STM32_SW == STM32_SW_PLL) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
#if GD32_USB_CLOCK_REQUIRED || \
(GD32_SW == GD32_SW_PLL) || \
(GD32_MCOSEL == GD32_MCOSEL_PLLDIV2) || \
defined(__DOXYGEN__)
/**
* @brief PLL activation flag.
*/
#define STM32_ACTIVATE_PLL TRUE
#define GD32_ACTIVATE_PLL TRUE
#else
#define STM32_ACTIVATE_PLL FALSE
#define GD32_ACTIVATE_PLL FALSE
#endif
/* HSE prescaler setting check.*/
#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \
(STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
#error "invalid STM32_PLLXTPRE value specified"
#if (GD32_PLLXTPRE != GD32_PLLXTPRE_DIV1) && \
(GD32_PLLXTPRE != GD32_PLLXTPRE_DIV2)
#error "invalid GD32_PLLXTPRE value specified"
#endif
/**
* @brief PLLMUL field.
*/
/*#if STM32_PLLMUL_VALUE == 6.5
#define STM32_PLLMUL 13 << 18*/
#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
/*#if GD32_PLLMUL_VALUE == 6.5
#define GD32_PLLMUL 13 << 18*/
#if ((GD32_PLLMUL_VALUE >= 2) && (GD32_PLLMUL_VALUE <= 16)) || \
defined(__DOXYGEN__)
#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
#elif ((STM32_PLLMUL_VALUE >= 17) && (STM32_PLLMUL_VALUE <= 32))
#define STM32_PLLMUL ((1 << 29) | ((STM32_PLLMUL_VALUE - 17) << 18))
#define GD32_PLLMUL ((GD32_PLLMUL_VALUE - 2) << 18)
#elif ((GD32_PLLMUL_VALUE >= 17) && (GD32_PLLMUL_VALUE <= 32))
#define GD32_PLLMUL ((1 << 29) | ((GD32_PLLMUL_VALUE - 17) << 18))
#else
#error "invalid STM32_PLLMUL_VALUE value specified"
#error "invalid GD32_PLLMUL_VALUE value specified"
#endif
//#pragma message(STRING(STM32_PLLMUL))
//#pragma message(STRING(GD32_PLLMUL))
/**
* @brief PLL input clock frequency.
*/
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
#define STM32_PLLCLKIN (STM32_HSECLK / 1)
#if (GD32_PLLSRC == GD32_PLLSRC_HSE) || defined(__DOXYGEN__)
#if GD32_PLLXTPRE == GD32_PLLXTPRE_DIV1
#define GD32_PLLCLKIN (GD32_HSECLK / 1)
#else
#define STM32_PLLCLKIN (STM32_HSECLK / 2)
#define GD32_PLLCLKIN (GD32_HSECLK / 2)
#endif
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
#define STM32_PLLCLKIN (STM32_HSICLK / 2)
#elif GD32_PLLSRC == GD32_PLLSRC_HSI
#define GD32_PLLCLKIN (GD32_HSICLK / 2)
#else
#error "invalid STM32_PLLSRC value specified"
#error "invalid GD32_PLLSRC value specified"
#endif
/* PLL input frequency range check.*/
#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
#if (GD32_PLLCLKIN < GD32_PLLIN_MIN) || (GD32_PLLCLKIN > GD32_PLLIN_MAX)
#error "GD32_PLLCLKIN outside acceptable range (GD32_PLLIN_MIN...GD32_PLLIN_MAX)"
#endif
/**
* @brief PLL output clock frequency.
*/
#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
#define GD32_PLLCLKOUT (GD32_PLLCLKIN * GD32_PLLMUL_VALUE)
/* PLL output frequency range check.*/
#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
#if (GD32_PLLCLKOUT < GD32_PLLOUT_MIN) || (GD32_PLLCLKOUT > GD32_PLLOUT_MAX)
#error "GD32_PLLCLKOUT outside acceptable range (GD32_PLLOUT_MIN...GD32_PLLOUT_MAX)"
#endif
/**
* @brief System clock source.
*/
#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
#define STM32_SYSCLK STM32_PLLCLKOUT
#elif (STM32_SW == STM32_SW_HSI)
#define STM32_SYSCLK STM32_HSICLK
#elif (STM32_SW == STM32_SW_HSE)
#define STM32_SYSCLK STM32_HSECLK
#if (GD32_SW == GD32_SW_PLL) || defined(__DOXYGEN__)
#define GD32_SYSCLK GD32_PLLCLKOUT
#elif (GD32_SW == GD32_SW_HSI)
#define GD32_SYSCLK GD32_HSICLK
#elif (GD32_SW == GD32_SW_HSE)
#define GD32_SYSCLK GD32_HSECLK
#else
#error "invalid STM32_SW value specified"
#error "invalid GD32_SW value specified"
#endif
/* Check on the system clock.*/
#if STM32_SYSCLK > STM32_SYSCLK_MAX
#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
#if GD32_SYSCLK > GD32_SYSCLK_MAX
#error "GD32_SYSCLK above maximum rated frequency (GD32_SYSCLK_MAX)"
#endif
/**
* @brief AHB frequency.
*/
#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
#define STM32_HCLK (STM32_SYSCLK / 1)
#elif STM32_HPRE == STM32_HPRE_DIV2
#define STM32_HCLK (STM32_SYSCLK / 2)
#elif STM32_HPRE == STM32_HPRE_DIV4
#define STM32_HCLK (STM32_SYSCLK / 4)
#elif STM32_HPRE == STM32_HPRE_DIV8
#define STM32_HCLK (STM32_SYSCLK / 8)
#elif STM32_HPRE == STM32_HPRE_DIV16
#define STM32_HCLK (STM32_SYSCLK / 16)
#elif STM32_HPRE == STM32_HPRE_DIV64
#define STM32_HCLK (STM32_SYSCLK / 64)
#elif STM32_HPRE == STM32_HPRE_DIV128
#define STM32_HCLK (STM32_SYSCLK / 128)
#elif STM32_HPRE == STM32_HPRE_DIV256
#define STM32_HCLK (STM32_SYSCLK / 256)
#elif STM32_HPRE == STM32_HPRE_DIV512
#define STM32_HCLK (STM32_SYSCLK / 512)
#if (GD32_HPRE == GD32_HPRE_DIV1) || defined(__DOXYGEN__)
#define GD32_HCLK (GD32_SYSCLK / 1)
#elif GD32_HPRE == GD32_HPRE_DIV2
#define GD32_HCLK (GD32_SYSCLK / 2)
#elif GD32_HPRE == GD32_HPRE_DIV4
#define GD32_HCLK (GD32_SYSCLK / 4)
#elif GD32_HPRE == GD32_HPRE_DIV8
#define GD32_HCLK (GD32_SYSCLK / 8)
#elif GD32_HPRE == GD32_HPRE_DIV16
#define GD32_HCLK (GD32_SYSCLK / 16)
#elif GD32_HPRE == GD32_HPRE_DIV64
#define GD32_HCLK (GD32_SYSCLK / 64)
#elif GD32_HPRE == GD32_HPRE_DIV128
#define GD32_HCLK (GD32_SYSCLK / 128)
#elif GD32_HPRE == GD32_HPRE_DIV256
#define GD32_HCLK (GD32_SYSCLK / 256)
#elif GD32_HPRE == GD32_HPRE_DIV512
#define GD32_HCLK (GD32_SYSCLK / 512)
#else
#error "invalid STM32_HPRE value specified"
#error "invalid GD32_HPRE value specified"
#endif
/* AHB frequency check.*/
#if STM32_HCLK > STM32_SYSCLK_MAX
#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
#if GD32_HCLK > GD32_SYSCLK_MAX
#error "GD32_HCLK exceeding maximum frequency (GD32_SYSCLK_MAX)"
#endif
/**
* @brief APB1 frequency.
*/
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
#define STM32_PCLK1 (STM32_HCLK / 1)
#elif STM32_PPRE1 == STM32_PPRE1_DIV2
#define STM32_PCLK1 (STM32_HCLK / 2)
#elif STM32_PPRE1 == STM32_PPRE1_DIV4
#define STM32_PCLK1 (STM32_HCLK / 4)
#elif STM32_PPRE1 == STM32_PPRE1_DIV8
#define STM32_PCLK1 (STM32_HCLK / 8)
#elif STM32_PPRE1 == STM32_PPRE1_DIV16
#define STM32_PCLK1 (STM32_HCLK / 16)
#if (GD32_PPRE1 == GD32_PPRE1_DIV1) || defined(__DOXYGEN__)
#define GD32_PCLK1 (GD32_HCLK / 1)
#elif GD32_PPRE1 == GD32_PPRE1_DIV2
#define GD32_PCLK1 (GD32_HCLK / 2)
#elif GD32_PPRE1 == GD32_PPRE1_DIV4
#define GD32_PCLK1 (GD32_HCLK / 4)
#elif GD32_PPRE1 == GD32_PPRE1_DIV8
#define GD32_PCLK1 (GD32_HCLK / 8)
#elif GD32_PPRE1 == GD32_PPRE1_DIV16
#define GD32_PCLK1 (GD32_HCLK / 16)
#else
#error "invalid STM32_PPRE1 value specified"
#error "invalid GD32_PPRE1 value specified"
#endif
/* APB1 frequency check.*/
#if STM32_PCLK1 > STM32_PCLK1_MAX
#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
#if GD32_PCLK1 > GD32_PCLK1_MAX
#error "GD32_PCLK1 exceeding maximum frequency (GD32_PCLK1_MAX)"
#endif
/**
* @brief APB2 frequency.
*/
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
#define STM32_PCLK2 (STM32_HCLK / 1)
#elif STM32_PPRE2 == STM32_PPRE2_DIV2
#define STM32_PCLK2 (STM32_HCLK / 2)
#elif STM32_PPRE2 == STM32_PPRE2_DIV4
#define STM32_PCLK2 (STM32_HCLK / 4)
#elif STM32_PPRE2 == STM32_PPRE2_DIV8
#define STM32_PCLK2 (STM32_HCLK / 8)
#elif STM32_PPRE2 == STM32_PPRE2_DIV16
#define STM32_PCLK2 (STM32_HCLK / 16)
#if (GD32_PPRE2 == GD32_PPRE2_DIV1) || defined(__DOXYGEN__)
#define GD32_PCLK2 (GD32_HCLK / 1)
#elif GD32_PPRE2 == GD32_PPRE2_DIV2
#define GD32_PCLK2 (GD32_HCLK / 2)
#elif GD32_PPRE2 == GD32_PPRE2_DIV4
#define GD32_PCLK2 (GD32_HCLK / 4)
#elif GD32_PPRE2 == GD32_PPRE2_DIV8
#define GD32_PCLK2 (GD32_HCLK / 8)
#elif GD32_PPRE2 == GD32_PPRE2_DIV16
#define GD32_PCLK2 (GD32_HCLK / 16)
#else
#error "invalid STM32_PPRE2 value specified"
#error "invalid GD32_PPRE2 value specified"
#endif
/* APB2 frequency check.*/
#if STM32_PCLK2 > STM32_PCLK2_MAX
#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
#if GD32_PCLK2 > GD32_PCLK2_MAX
#error "GD32_PCLK2 exceeding maximum frequency (GD32_PCLK2_MAX)"
#endif
/**
* @brief RTC clock.
*/
#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
#define STM32_RTCCLK STM32_LSECLK
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
#define STM32_RTCCLK STM32_LSICLK
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
#define STM32_RTCCLK (STM32_HSECLK / 128)
#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
#define STM32_RTCCLK 0
#if (GD32_RTCSEL == GD32_RTCSEL_LSE) || defined(__DOXYGEN__)
#define GD32_RTCCLK GD32_LSECLK
#elif GD32_RTCSEL == GD32_RTCSEL_LSI
#define GD32_RTCCLK GD32_LSICLK
#elif GD32_RTCSEL == GD32_RTCSEL_HSEDIV
#define GD32_RTCCLK (GD32_HSECLK / 128)
#elif GD32_RTCSEL == GD32_RTCSEL_NOCLOCK
#define GD32_RTCCLK 0
#else
#error "invalid source selected for RTC clock"
#endif
@ -550,65 +550,65 @@
/**
* @brief ADC frequency.
*/
#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
#define STM32_ADCCLK (STM32_PCLK2 / 2)
#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
#define STM32_ADCCLK (STM32_PCLK2 / 4)
#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
#define STM32_ADCCLK (STM32_PCLK2 / 6)
#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
#define STM32_ADCCLK (STM32_PCLK2 / 8)
#if (GD32_ADCPRE == GD32_ADCPRE_DIV2) || defined(__DOXYGEN__)
#define GD32_ADCCLK (GD32_PCLK2 / 2)
#elif GD32_ADCPRE == GD32_ADCPRE_DIV4
#define GD32_ADCCLK (GD32_PCLK2 / 4)
#elif GD32_ADCPRE == GD32_ADCPRE_DIV6
#define GD32_ADCCLK (GD32_PCLK2 / 6)
#elif GD32_ADCPRE == GD32_ADCPRE_DIV8
#define GD32_ADCCLK (GD32_PCLK2 / 8)
#else
#error "invalid STM32_ADCPRE value specified"
#error "invalid GD32_ADCPRE value specified"
#endif
/* ADC frequency check.*/
#if STM32_ADCCLK > STM32_ADCCLK_MAX
#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
#if GD32_ADCCLK > GD32_ADCCLK_MAX
#error "GD32_ADCCLK exceeding maximum frequency (GD32_ADCCLK_MAX)"
#endif
/**
* @brief USB frequency.
*/
#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
#define STM32_OTGFSCLK ((STM32_PLLCLKOUT * 2) / 3)
#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
#define STM32_OTGFSCLK STM32_PLLCLKOUT
#elif (STM32_USBPRE == STM32_USBPRE_DIV2)
#define STM32_OTGFSCLK STM32_PLLCLKOUT / 2
#elif (STM32_USBPRE == STM32_USBPRE_DIV2P5)
#define STM32_OTGFSCLK ((STM32_PLLCLKOUT * 2) / 5)
#if (GD32_USBPRE == GD32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
#define GD32_OTGFSCLK ((GD32_PLLCLKOUT * 2) / 3)
#elif (GD32_USBPRE == GD32_USBPRE_DIV1)
#define GD32_OTGFSCLK GD32_PLLCLKOUT
#elif (GD32_USBPRE == GD32_USBPRE_DIV2)
#define GD32_OTGFSCLK GD32_PLLCLKOUT / 2
#elif (GD32_USBPRE == GD32_USBPRE_DIV2P5)
#define GD32_OTGFSCLK ((GD32_PLLCLKOUT * 2) / 5)
#else
#error "invalid STM32_USBPRE value specified"
#error "invalid GD32_USBPRE value specified"
#endif
/**
* @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
*/
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
#if (GD32_PPRE1 == GD32_PPRE1_DIV1) || defined(__DOXYGEN__)
#define GD32_TIMCLK1 (GD32_PCLK1 * 1)
#else
#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
#define GD32_TIMCLK1 (GD32_PCLK1 * 2)
#endif
/**
* @brief Timers 1, 8, 9, 10, 11 clock.
*/
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
#if (GD32_PPRE2 == GD32_PPRE2_DIV1) || defined(__DOXYGEN__)
#define GD32_TIMCLK2 (GD32_PCLK2 * 1)
#else
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
#define GD32_TIMCLK2 (GD32_PCLK2 * 2)
#endif
/**
* @brief Flash settings.
*/
#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
#define STM32_FLASHBITS 0x00000010
#elif STM32_HCLK <= 48000000
#define STM32_FLASHBITS 0x00000011
#if (GD32_HCLK <= 24000000) || defined(__DOXYGEN__)
#define GD32_FLASHBITS 0x00000010
#elif GD32_HCLK <= 48000000
#define GD32_FLASHBITS 0x00000011
#else
#define STM32_FLASHBITS 0x00000012
#define GD32_FLASHBITS 0x00000012
#endif
#endif /* _HAL_LLD_F103_H_ */

606
os/hal/ports/GD/GD32VF103/hal_lld_f105_f107.h
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File diff suppressed because it is too large Load Diff

6
os/hal/ports/GD/GD32VF103/stm32_rcc.h
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@ -24,8 +24,8 @@
* @{
*/
#ifndef STM32_RCC_H
#define STM32_RCC_H
#ifndef GD32_RCC_H
#define GD32_RCC_H
/*===========================================================================*/
/* Driver constants. */
@ -1225,6 +1225,6 @@ extern "C" {
}
#endif
#endif /* STM32_RCC_H */
#endif /* GD32_RCC_H */
/** @} */

1832
os/hal/ports/GD/GD32VF103/stm32_registry.h
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File diff suppressed because it is too large Load Diff

6
os/hal/ports/GD/GD32VF103/xWDG/hal_wdg_lld.c
View File

@ -43,7 +43,7 @@
/* Driver exported variables. */
/*===========================================================================*/
#if STM32_WDG_USE_IWDG || defined(__DOXYGEN__)
#if GD32_WDG_USE_IWDG || defined(__DOXYGEN__)
WDGDriver WDGD1;
#endif
@ -70,7 +70,7 @@ WDGDriver WDGD1;
*/
void wdg_lld_init(void) {
#if STM32_WDG_USE_IWDG
#if GD32_WDG_USE_IWDG
WDGD1.state = WDG_STOP;
WDGD1.wdg = IWDG;
#endif
@ -97,7 +97,7 @@ void wdg_lld_start(WDGDriver *wdgp) {
while (wdgp->wdg->SR != 0)
;
#if STM32_IWDG_IS_WINDOWED
#if GD32_IWDG_IS_WINDOWED
/* This also triggers a refresh.*/
wdgp->wdg->WINR = wdgp->config->winr;
#else

44
os/hal/ports/GD/GD32VF103/xWDG/hal_wdg_lld.h
View File

@ -35,31 +35,31 @@
* @name RLR register definitions
* @{
*/
#define STM32_IWDG_RL_MASK (0x00000FFF << 0)
#define STM32_IWDG_RL(n) ((n) << 0)
#define GD32_IWDG_RL_MASK (0x00000FFF << 0)
#define GD32_IWDG_RL(n) ((n) << 0)
/** @} */
/**
* @name PR register definitions
* @{
*/
#define STM32_IWDG_PR_MASK (7 << 0)
#define STM32_IWDG_PR_4 0U
#define STM32_IWDG_PR_8 1U
#define STM32_IWDG_PR_16 2U
#define STM32_IWDG_PR_32 3U
#define STM32_IWDG_PR_64 4U
#define STM32_IWDG_PR_128 5U
#define STM32_IWDG_PR_256 6U
#define GD32_IWDG_PR_MASK (7 << 0)
#define GD32_IWDG_PR_4 0U
#define GD32_IWDG_PR_8 1U
#define GD32_IWDG_PR_16 2U
#define GD32_IWDG_PR_32 3U
#define GD32_IWDG_PR_64 4U
#define GD32_IWDG_PR_128 5U
#define GD32_IWDG_PR_256 6U
/** @} */
/**
* @name WINR register definitions
* @{
*/
#define STM32_IWDG_WIN_MASK (0x00000FFF << 0)
#define STM32_IWDG_WIN(n) ((n) << 0)
#define STM32_IWDG_WIN_DISABLED STM32_IWDG_WIN(0x00000FFF)
#define GD32_IWDG_WIN_MASK (0x00000FFF << 0)
#define GD32_IWDG_WIN(n) ((n) << 0)
#define GD32_IWDG_WIN_DISABLED GD32_IWDG_WIN(0x00000FFF)
/** @} */
/*===========================================================================*/
@ -75,8 +75,8 @@
* @details If set to @p TRUE the support for IWDG is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_WDG_USE_IWDG) || defined(__DOXYGEN__)
#define STM32_WDG_USE_IWDG FALSE
#if !defined(GD32_WDG_USE_IWDG) || defined(__DOXYGEN__)
#define GD32_WDG_USE_IWDG FALSE
#endif
/** @} */
@ -84,19 +84,19 @@
/* Derived constants and error checks. */
/*===========================================================================*/
#if STM32_WDG_USE_IWDG && !STM32_HAS_IWDG
#if GD32_WDG_USE_IWDG && !GD32_HAS_IWDG
#error "IWDG not present in the selected device"
#endif
#if !STM32_WDG_USE_IWDG
#if !GD32_WDG_USE_IWDG
#error "WDG driver activated but no xWDG peripheral assigned"
#endif
#if !defined(STM32_LSI_ENABLED)
#error "STM32_LSI_ENABLED not defined"
#if !defined(GD32_LSI_ENABLED)
#error "GD32_LSI_ENABLED not defined"
#endif
#if (STM32_WDG_USE_IWDG == TRUE) && (STM32_LSI_ENABLED == FALSE)
#if (GD32_WDG_USE_IWDG == TRUE) && (GD32_LSI_ENABLED == FALSE)
#error "IWDG requires LSI clock"
#endif
@ -124,7 +124,7 @@ typedef struct {
* @details See the STM32 reference manual for details.
*/
uint32_t rlr;
#if STM32_IWDG_IS_WINDOWED || defined(__DOXYGEN__)
#if GD32_IWDG_IS_WINDOWED || defined(__DOXYGEN__)
/**
* @brief Configuration of the IWDG_WINR register.
* @details See the STM32 reference manual for details.
@ -161,7 +161,7 @@ struct WDGDriver {
/* External declarations. */
/*===========================================================================*/
#if STM32_WDG_USE_IWDG && !defined(__DOXYGEN__)
#if GD32_WDG_USE_IWDG && !defined(__DOXYGEN__)
extern WDGDriver WDGD1;
#endif