Rename DMA CNDTR CPAR CMAR registers
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5cec991524
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@ -252,12 +252,12 @@ typedef struct {
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* @post After use the stream can be released using @p dmaStreamRelease().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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*
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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* @param[in] addr value to be written in the CPAR register
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* @param[in] addr value to be written in the PADDR register
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*
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*
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* @special
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* @special
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*/
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*/
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#define dmaStreamSetPeripheral(dmastp, addr) { \
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#define dmaStreamSetPeripheral(dmastp, addr) { \
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(dmastp)->channel->CPAR = (uint32_t)(addr); \
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(dmastp)->channel->PADDR = (uint32_t)(addr); \
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}
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}
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/**
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/**
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@ -267,12 +267,12 @@ typedef struct {
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* @post After use the stream can be released using @p dmaStreamRelease().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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*
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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* @param[in] addr value to be written in the CMAR register
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* @param[in] addr value to be written in the MADDR register
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*
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*
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* @special
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* @special
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*/
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*/
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#define dmaStreamSetMemory0(dmastp, addr) { \
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#define dmaStreamSetMemory0(dmastp, addr) { \
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(dmastp)->channel->CMAR = (uint32_t)(addr); \
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(dmastp)->channel->MADDR = (uint32_t)(addr); \
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}
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}
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/**
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/**
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@ -282,12 +282,12 @@ typedef struct {
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* @post After use the stream can be released using @p dmaStreamRelease().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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*
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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* @param[in] size value to be written in the CNDTR register
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* @param[in] size value to be written in the CNT register
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*
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*
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* @special
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* @special
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*/
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*/
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#define dmaStreamSetTransactionSize(dmastp, size) { \
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#define dmaStreamSetTransactionSize(dmastp, size) { \
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(dmastp)->channel->CNDTR = (uint32_t)(size); \
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(dmastp)->channel->CNT = (uint32_t)(size); \
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}
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}
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/**
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/**
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@ -301,7 +301,7 @@ typedef struct {
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*
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*
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* @special
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* @special
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*/
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*/
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#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
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#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNT))
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/**
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/**
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* @brief Programs the stream mode settings.
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* @brief Programs the stream mode settings.
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@ -402,7 +402,7 @@ typedef struct {
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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* @param[in] dmastp pointer to a gd32_dma_stream_t structure
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*/
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*/
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#define dmaWaitCompletion(dmastp) { \
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#define dmaWaitCompletion(dmastp) { \
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while ((dmastp)->channel->CNDTR > 0U) \
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while ((dmastp)->channel->CNT > 0U) \
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; \
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; \
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dmaStreamDisable(dmastp); \
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dmaStreamDisable(dmastp); \
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}
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}
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@ -292,9 +292,9 @@ typedef struct
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typedef struct
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typedef struct
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{
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{
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__IO uint32_t CTL;
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__IO uint32_t CTL;
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__IO uint32_t CNDTR;
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__IO uint32_t CNT;
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__IO uint32_t CPAR;
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__IO uint32_t PADDR;
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__IO uint32_t CMAR;
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__IO uint32_t MADDR;
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} DMA_Channel_TypeDef;
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} DMA_Channel_TypeDef;
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typedef struct
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typedef struct
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@ -3905,20 +3905,20 @@ typedef struct
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#define DMA_CTL_M2M_Msk (0x1U << DMA_CTL_M2M_Pos) /*!< 0x00004000 */
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#define DMA_CTL_M2M_Msk (0x1U << DMA_CTL_M2M_Pos) /*!< 0x00004000 */
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#define DMA_CTL_M2M DMA_CTL_M2M_Msk /*!< Memory to memory mode */
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#define DMA_CTL_M2M DMA_CTL_M2M_Msk /*!< Memory to memory mode */
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/****************** Bit definition for DMA_CNDTR register ******************/
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/****************** Bit definition for DMA_CNT register ******************/
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#define DMA_CNDTR_NDT_Pos (0U)
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#define DMA_CNT_CNT_Pos (0U)
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#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
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#define DMA_CNT_CNT_Msk (0xFFFFU << DMA_CNT_CNT_Pos) /*!< 0x0000FFFF */
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#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
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#define DMA_CNT_CNT DMA_CNT_CNT_Msk /*!< Number of data to Transfer */
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/****************** Bit definition for DMA_CPAR register *******************/
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/****************** Bit definition for DMA_PADDR register *******************/
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#define DMA_CPAR_PA_Pos (0U)
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#define DMA_PADDR_PADDR_Pos (0U)
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#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
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#define DMA_PADDR_PADDR_Msk (0xFFFFFFFFU << DMA_PADDR_PADDR_Pos) /*!< 0xFFFFFFFF */
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#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
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#define DMA_PADDR_PADDR DMA_PADDR_PADDR_Msk /*!< Peripheral Address */
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/****************** Bit definition for DMA_CMAR register *******************/
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/****************** Bit definition for DMA_MADDR register *******************/
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#define DMA_CMAR_MA_Pos (0U)
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#define DMA_MADDR_MADDR_Pos (0U)
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#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
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#define DMA_MADDR_MADDR_Msk (0xFFFFFFFFU << DMA_MADDR_MADDR_Pos) /*!< 0xFFFFFFFF */
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#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
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#define DMA_MADDR_MADDR DMA_MADDR_MADDR_Msk /*!< Memory Address */
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/******************************************************************************/
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/******************************************************************************/
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/* */
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/* */
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