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Remove timers not found on this device

This commit is contained in:
Stefan Kerkmann 2021-03-30 11:49:23 +02:00
parent 3cfa2c8002
commit b2d27ad990
19 changed files with 18 additions and 5245 deletions
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15
os/hal/ports/GD/GD32VF103/TIM/gd32_tim.h
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@ -351,21 +351,6 @@
#define GD32_TIM5 ((gd32_tim_t *)TIM5_BASE)
#define GD32_TIM6 ((gd32_tim_t *)TIM6_BASE)
#define GD32_TIM7 ((gd32_tim_t *)TIM7_BASE)
#define GD32_TIM8 ((gd32_tim_t *)TIM8_BASE)
#define GD32_TIM9 ((gd32_tim_t *)TIM9_BASE)
#define GD32_TIM10 ((gd32_tim_t *)TIM10_BASE)
#define GD32_TIM11 ((gd32_tim_t *)TIM11_BASE)
#define GD32_TIM12 ((gd32_tim_t *)TIM12_BASE)
#define GD32_TIM13 ((gd32_tim_t *)TIM13_BASE)
#define GD32_TIM14 ((gd32_tim_t *)TIM14_BASE)
#define GD32_TIM15 ((gd32_tim_t *)TIM15_BASE)
#define GD32_TIM16 ((gd32_tim_t *)TIM16_BASE)
#define GD32_TIM17 ((gd32_tim_t *)TIM17_BASE)
#define GD32_TIM18 ((gd32_tim_t *)TIM18_BASE)
#define GD32_TIM19 ((gd32_tim_t *)TIM19_BASE)
#define GD32_TIM20 ((gd32_tim_t *)TIM20_BASE)
#define GD32_TIM21 ((gd32_tim_t *)TIM21_BASE)
#define GD32_TIM22 ((gd32_tim_t *)TIM22_BASE)
/** @} */
/*===========================================================================*/

172
os/hal/ports/GD/GD32VF103/TIM/gd32_tim1.inc
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@ -1,172 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file TIM/gd32_tim1_tim15_tim16_tim17.inc
* @brief Shared TIM1 handler.
*
* @addtogroup GD32_TIM1_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(GD32_HAS_TIM1)
#error "GD32_HAS_TIM1 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(GD32_GPT_USE_TIM1)
#define GD32_GPT_USE_TIM1 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM1)
#define GD32_ICU_USE_TIM1 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM1)
#define GD32_PWM_USE_TIM1 FALSE
#endif
#if !defined(GD32_ST_USE_TIM1)
#define GD32_ST_USE_TIM1 FALSE
#endif
#if GD32_HAS_TIM1
/* Priority settings checks.*/
#if !defined(GD32_IRQ_TIM1_UP_PRIORITY)
#error "GD32_IRQ_TIM1_UP_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(GD32_IRQ_TIM1_CC_PRIORITY)
#error "GD32_IRQ_TIM1_CC_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_UP_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_UP_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_CC_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_CC_PRIORITY"
#endif
#endif /* GD32_HAS_TIM1 */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void tim1_irq_init(void) {
#if defined(GD32_TIM1_IS_USED)
eclicEnableVector(GD32_TIM1_UP_NUMBER, GD32_IRQ_TIM1_UP_PRIORITY, GD32_IRQ_TIM1_UP_TRIGGER);
eclicEnableVector(GD32_TIM1_CC_NUMBER, GD32_IRQ_TIM1_CC_PRIORITY, GD32_IRQ_TIM1_CC_TRIGGER);
#endif
}
static inline void tim1_irq_deinit(void) {
#if defined(GD32_TIM1_IS_USED)
eclicDisableVector(GD32_TIM1_UP_NUMBER);
eclicDisableVector(GD32_TIM1_CC_NUMBER);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(GD32_TIM1_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM1-UP interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM1_UP_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if GD32_GPT_USE_TIM1
gpt_lld_serve_interrupt(&GPTD1);
#endif
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#endif
#if 1
#if GD32_ST_USE_TIM1
st_lld_serve_interrupt();
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
/**
* @brief TIM1-CC interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM1_CC_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
/* Not used by GPT.*/
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#endif
#if 1
/* Not used by ST.*/
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

341
os/hal/ports/GD/GD32VF103/TIM/gd32_tim1_15_16_17.inc
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@ -1,341 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file TIM/gd32_tim1_15_16_17.inc
* @brief Shared TIM1, TIM15, TIM16, TIM17 handler.
*
* @addtogroup GD32_TIM1_TIM15_TIM16_TIM17_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(GD32_HAS_TIM1)
#error "GD32_HAS_TIM1 not defined in registry"
#endif
#if !defined(GD32_HAS_TIM15)
#error "GD32_HAS_TIM15 not defined in registry"
#endif
#if !defined(GD32_HAS_TIM16)
#error "GD32_HAS_TIM16 not defined in registry"
#endif
#if !defined(GD32_HAS_TIM17)
#error "GD32_HAS_TIM17 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(GD32_GPT_USE_TIM1)
#define GD32_GPT_USE_TIM1 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM1)
#define GD32_ICU_USE_TIM1 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM1)
#define GD32_PWM_USE_TIM1 FALSE
#endif
#if !defined(GD32_ST_USE_TIM1)
#define GD32_ST_USE_TIM1 FALSE
#endif
#if !defined(GD32_GPT_USE_TIM15)
#define GD32_GPT_USE_TIM15 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM15)
#define GD32_ICU_USE_TIM15 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM15)
#define GD32_PWM_USE_TIM15 FALSE
#endif
#if !defined(GD32_ST_USE_TIM15)
#define GD32_ST_USE_TIM15 FALSE
#endif
#if !defined(GD32_GPT_USE_TIM16)
#define GD32_GPT_USE_TIM16 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM16)
#define GD32_ICU_USE_TIM16 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM16)
#define GD32_PWM_USE_TIM16 FALSE
#endif
#if !defined(GD32_ST_USE_TIM16)
#define GD32_ST_USE_TIM16 FALSE
#endif
#if !defined(GD32_GPT_USE_TIM17)
#define GD32_GPT_USE_TIM17 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM17)
#define GD32_ICU_USE_TIM17 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM17)
#define GD32_PWM_USE_TIM17 FALSE
#endif
#if !defined(GD32_ST_USE_TIM17)
#define GD32_ST_USE_TIM17 FALSE
#endif
#if GD32_HAS_TIM1 || GD32_HAS_TIM15 || GD32_HAS_TIM16 || GD32_HAS_TIM17
/* Priority settings checks.*/
#if !defined(GD32_IRQ_TIM1_BRK_TIM15_PRIORITY)
#error "GD32_IRQ_TIM1_BRK_TIM15_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(GD32_IRQ_TIM1_UP_TIM16_PRIORITY)
#error "GD32_IRQ_TIM1_UP_TIM16_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(GD32_IRQ_TIM1_TRGCO_TIM17_PRIORITY)
#error "GD32_IRQ_TIM1_TRGCO_TIM17_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(GD32_IRQ_TIM1_CC_PRIORITY)
#error "GD32_IRQ_TIM1_CC_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_BRK_TIM15_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_BRK_TIM15_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_UP_TIM16_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_UP_TIM16_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_TRGCO_TIM17_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_TRGCO_TIM17_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_CC_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_CC_PRIORITY"
#endif
#endif /* GD32_HAS_TIM1 || GD32_HAS_TIM15 || GD32_HAS_TIM16 || GD32_HAS_TIM17 */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void tim1_tim15_tim16_tim17_irq_init(void) {
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM15_IS_USED)
nvicEnableVector(GD32_TIM1_BRK_TIM15_NUMBER,
GD32_IRQ_TIM1_BRK_TIM15_PRIORITY);
#endif
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM16_IS_USED)
nvicEnableVector(GD32_TIM1_UP_TIM16_NUMBER,
GD32_IRQ_TIM1_UP_TIM16_PRIORITY);
#endif
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM17_IS_USED)
nvicEnableVector(GD32_TIM1_TRGCO_TIM17_NUMBER,
GD32_IRQ_TIM1_TRGCO_TIM17_PRIORITY);
#endif
#if defined(GD32_TIM1_IS_USED)
nvicEnableVector(GD32_TIM1_CC_NUMBER,
GD32_IRQ_TIM1_CC_PRIORITY);
#endif
}
static inline void tim1_tim15_tim16_tim17_irq_deinit(void) {
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM15_IS_USED)
eclicDisableVector(GD32_TIM1_BRK_TIM15_NUMBER);
#endif
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM16_IS_USED)
eclicDisableVector(GD32_TIM1_UP_TIM16_NUMBER);
#endif
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM17_IS_USED)
eclicDisableVector(GD32_TIM1_TRGCO_TIM17_NUMBER);
#endif
#if defined(GD32_TIM1_IS_USED)
eclicDisableVector(GD32_TIM1_CC_NUMBER);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM15_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM1-BRK, TIM15 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM1_BRK_TIM15_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if GD32_GPT_USE_TIM15
gpt_lld_serve_interrupt(&GPTD15);
#endif
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM15
icu_lld_serve_interrupt(&ICUD15);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM15
pwm_lld_serve_interrupt(&PWMD15);
#endif
#endif
#if 1
#if GD32_ST_USE_TIM15
st_lld_serve_interrupt();
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM16_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM1-UP, TIM16 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM1_UP_TIM16_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if GD32_GPT_USE_TIM1
gpt_lld_serve_interrupt(&GPTD1);
#endif
#if GD32_GPT_USE_TIM16
gpt_lld_serve_interrupt(&GPTD16);
#endif
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#if GD32_PWM_USE_TIM16
pwm_lld_serve_interrupt(&PWMD16);
#endif
#endif
#if 1
#if GD32_ST_USE_TIM1
st_lld_serve_interrupt();
#endif
#if GD32_ST_USE_TIM16
st_lld_serve_interrupt();
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM17_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM1-TRG-COM, TIM17 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM1_TRGCO_TIM17_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if GD32_GPT_USE_TIM17
gpt_lld_serve_interrupt(&GPTD17);
#endif
#endif
#if HAL_USE_ICU
/* Not used by ICU.*/
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM17
pwm_lld_serve_interrupt(&PWMD17);
#endif
#endif
#if 1
#if GD32_ST_USE_TIM17
st_lld_serve_interrupt();
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
#if defined(GD32_TIM1_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM1-CC interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM1_CC_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
/* Not used by GPT.*/
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#endif
#if 1
/* Not used by ST.*/
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

343
os/hal/ports/GD/GD32VF103/TIM/gd32_tim1_9_10_11.inc
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@ -1,343 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file TIM/gd32_tim1_9_10_11.inc
* @brief Shared TIM1, TIM9, TIM10, TIM11 handler.
*
* @addtogroup GD32_TIM1_TIM9_TIM10_TIM11_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(GD32_HAS_TIM1)
#error "GD32_HAS_TIM1 not defined in registry"
#endif
#if !defined(GD32_HAS_TIM9)
#error "GD32_HAS_TIM9 not defined in registry"
#endif
#if !defined(GD32_HAS_TIM10)
#error "GD32_HAS_TIM10 not defined in registry"
#endif
#if !defined(GD32_HAS_TIM11)
#error "GD32_HAS_TIM11 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(GD32_GPT_USE_TIM1)
#define GD32_GPT_USE_TIM1 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM1)
#define GD32_ICU_USE_TIM1 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM1)
#define GD32_PWM_USE_TIM1 FALSE
#endif
#if !defined(GD32_ST_USE_TIM1)
#define GD32_ST_USE_TIM1 FALSE
#endif
#if !defined(GD32_GPT_USE_TIM9)
#define GD32_GPT_USE_TIM9 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM9)
#define GD32_ICU_USE_TIM9 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM9)
#define GD32_PWM_USE_TIM9 FALSE
#endif
#if !defined(GD32_ST_USE_TIM9)
#define GD32_ST_USE_TIM9 FALSE
#endif
#if !defined(GD32_GPT_USE_TIM10)
#define GD32_GPT_USE_TIM10 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM10)
#define GD32_ICU_USE_TIM10 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM10)
#define GD32_PWM_USE_TIM10 FALSE
#endif
#if !defined(GD32_ST_USE_TIM10)
#define GD32_ST_USE_TIM10 FALSE
#endif
#if !defined(GD32_GPT_USE_TIM11)
#define GD32_GPT_USE_TIM11 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM11)
#define GD32_ICU_USE_TIM11 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM11)
#define GD32_PWM_USE_TIM11 FALSE
#endif
#if !defined(GD32_ST_USE_TIM11)
#define GD32_ST_USE_TIM11 FALSE
#endif
#if GD32_HAS_TIM1 || GD32_HAS_TIM9 || GD32_HAS_TIM10 || GD32_HAS_TIM11
/* Priority settings checks.*/
#if !defined(GD32_IRQ_TIM1_BRK_TIM9_PRIORITY)
#error "GD32_IRQ_TIM1_BRK_TIM9_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(GD32_IRQ_TIM1_UP_TIM10_PRIORITY)
#error "GD32_IRQ_TIM1_UP_TIM10_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(GD32_IRQ_TIM1_TRGCO_TIM11_PRIORITY)
#error "GD32_IRQ_TIM1_TRGCO_TIM11_PRIORITY not defined in mcuconf.h"
#endif
#if !defined(GD32_IRQ_TIM1_CC_PRIORITY)
#error "GD32_IRQ_TIM1_CC_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_BRK_TIM9_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_BRK_TIM9_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_UP_TIM10_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_UP_TIM10_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_TRGCO_TIM11_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_TRGCO_TIM11_PRIORITY"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM1_CC_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM1_CC_PRIORITY"
#endif
#endif /* GD32_HAS_TIM1 || GD32_HAS_TIM9 || GD32_HAS_TIM10 || GD32_HAS_TIM11 */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void tim1_tim9_tim10_tim11_irq_init(void) {
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM9_IS_USED)
nvicEnableVector(GD32_TIM1_BRK_TIM9_NUMBER,
GD32_IRQ_TIM1_BRK_TIM9_PRIORITY);
#endif
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM10_IS_USED)
nvicEnableVector(GD32_TIM1_UP_TIM10_NUMBER,
GD32_IRQ_TIM1_UP_TIM10_PRIORITY);
#endif
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM11_IS_USED)
nvicEnableVector(GD32_TIM1_TRGCO_TIM11_NUMBER,
GD32_IRQ_TIM1_TRGCO_TIM11_PRIORITY);
#endif
#if defined(GD32_TIM1_IS_USED)
nvicEnableVector(GD32_TIM1_CC_NUMBER,
GD32_IRQ_TIM1_CC_PRIORITY);
#endif
}
static inline void tim1_tim9_tim10_tim11_irq_deinit(void) {
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM9_IS_USED)
eclicDisableVector(GD32_TIM1_BRK_TIM9_NUMBER);
#endif
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM10_IS_USED)
eclicDisableVector(GD32_TIM1_UP_TIM10_NUMBER);
#endif
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM11_IS_USED)
eclicDisableVector(GD32_TIM1_TRGCO_TIM11_NUMBER);
#endif
#if defined(GD32_TIM1_IS_USED)
eclicDisableVector(GD32_TIM1_CC_NUMBER);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM19_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM1-BRK, TIM9 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM1_BRK_TIM9_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if GD32_GPT_USE_TIM9
gpt_lld_serve_interrupt(&GPTD9);
#endif
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM9
icu_lld_serve_interrupt(&ICUD9);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM9
pwm_lld_serve_interrupt(&PWMD9);
#endif
#endif
#if 1
#if GD32_ST_USE_TIM9
st_lld_serve_interrupt();
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM10_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM1-UP, TIM10 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM1_UP_TIM10_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if GD32_GPT_USE_TIM1
gpt_lld_serve_interrupt(&GPTD1);
#endif
#if GD32_GPT_USE_TIM10
gpt_lld_serve_interrupt(&GPTD10);
#endif
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#if GD32_ICU_USE_TIM10
icu_lld_serve_interrupt(&ICUD10);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#if GD32_PWM_USE_TIM10
pwm_lld_serve_interrupt(&PWMD10);
#endif
#endif
#if 1
#if GD32_ST_USE_TIM1
st_lld_serve_interrupt();
#endif
#if GD32_ST_USE_TIM10
st_lld_serve_interrupt();
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
#if defined(GD32_TIM1_IS_USED) || defined(GD32_TIM11_IS_USED) || \
defined(__DOXYGEN__)
/**
* @brief TIM1-TRG-COM, TIM11 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM1_TRGCO_TIM11_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if GD32_GPT_USE_TIM11
gpt_lld_serve_interrupt(&GPTD11);
#endif
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM11
icu_lld_serve_interrupt(&ICUD11);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM11
pwm_lld_serve_interrupt(&PWMD11);
#endif
#endif
#if 1
#if GD32_ST_USE_TIM11
st_lld_serve_interrupt();
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
#if defined(GD32_TIM1_IS_USED)
/**
* @brief TIM1-CC interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM1_CC_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
/* Not used by GPT.*/
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM1
icu_lld_serve_interrupt(&ICUD1);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM1
pwm_lld_serve_interrupt(&PWMD1);
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

133
os/hal/ports/GD/GD32VF103/TIM/gd32_tim2.inc
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@ -1,133 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file TIM/gd32_tim2.inc
* @brief Shared TIM2 handler.
*
* @addtogroup GD32_TIM2_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(GD32_HAS_TIM2)
#error "GD32_HAS_TIM2 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(GD32_GPT_USE_TIM2)
#define GD32_GPT_USE_TIM2 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM2)
#define GD32_ICU_USE_TIM2 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM2)
#define GD32_PWM_USE_TIM2 FALSE
#endif
#if !defined(GD32_ST_USE_TIM2)
#define GD32_ST_USE_TIM2 FALSE
#endif
#if GD32_HAS_TIM2
/* Priority settings checks.*/
#if !defined(GD32_IRQ_TIM2_PRIORITY)
#error "GD32_IRQ_TIM2_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM2_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM2_PRIORITY"
#endif
#endif /* GD32_HAS_TIM2 */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void tim2_irq_init(void) {
#if defined(GD32_TIM2_IS_USED)
eclicEnableVector(GD32_TIM2_NUMBER, GD32_IRQ_TIM2_PRIORITY, GD32_IRQ_TIM2_TRIGGER);
#endif
}
static inline void tim2_irq_deinit(void) {
#if defined(GD32_TIM2_IS_USED)
eclicDisableVector(GD32_TIM2_NUMBER);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(GD32_TIM2_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM2 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM2_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if GD32_GPT_USE_TIM2
gpt_lld_serve_interrupt(&GPTD2);
#endif
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM2
icu_lld_serve_interrupt(&ICUD2);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM2
pwm_lld_serve_interrupt(&PWMD2);
#endif
#endif
#if 1
#if GD32_ST_USE_TIM2
st_lld_serve_interrupt();
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

133
os/hal/ports/GD/GD32VF103/TIM/gd32_tim3.inc
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@ -1,133 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file TIM/gd32_tim3.inc
* @brief Shared TIM3 handler.
*
* @addtogroup GD32_TIM3_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(GD32_HAS_TIM3)
#error "GD32_HAS_TIM3 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(GD32_GPT_USE_TIM3)
#define GD32_GPT_USE_TIM3 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM3)
#define GD32_ICU_USE_TIM3 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM3)
#define GD32_PWM_USE_TIM3 FALSE
#endif
#if !defined(GD32_ST_USE_TIM3)
#define GD32_ST_USE_TIM3 FALSE
#endif
#if GD32_HAS_TIM3
/* Priority settings checks.*/
#if !defined(GD32_IRQ_TIM3_PRIORITY)
#error "GD32_IRQ_TIM3_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM3_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM3_PRIORITY"
#endif
#endif /* GD32_HAS_TIM3 */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void tim3_irq_init(void) {
#if defined(GD32_TIM3_IS_USED)
eclicEnableVector(GD32_TIM3_NUMBER, GD32_IRQ_TIM3_PRIORITY, GD32_IRQ_TIM3_TRIGGER);
#endif
}
static inline void tim3_irq_deinit(void) {
#if defined(GD32_TIM3_IS_USED)
eclicDisableVector(GD32_TIM3_NUMBER);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(GD32_TIM3_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM3 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM3_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if GD32_GPT_USE_TIM3
gpt_lld_serve_interrupt(&GPTD3);
#endif
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM3
icu_lld_serve_interrupt(&ICUD3);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM3
pwm_lld_serve_interrupt(&PWMD3);
#endif
#endif
#if 1
#if GD32_ST_USE_TIM3
st_lld_serve_interrupt();
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

133
os/hal/ports/GD/GD32VF103/TIM/gd32_tim4.inc
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@ -1,133 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file TIM/gd32_tim4.inc
* @brief Shared TIM4 handler.
*
* @addtogroup GD32_TIM4_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(GD32_HAS_TIM4)
#error "GD32_HAS_TIM4 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(GD32_GPT_USE_TIM4)
#define GD32_GPT_USE_TIM4 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM4)
#define GD32_ICU_USE_TIM4 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM4)
#define GD32_PWM_USE_TIM4 FALSE
#endif
#if !defined(GD32_ST_USE_TIM4)
#define GD32_ST_USE_TIM4 FALSE
#endif
#if GD32_HAS_TIM4
/* Priority settings checks.*/
#if !defined(GD32_IRQ_TIM4_PRIORITY)
#error "GD32_IRQ_TIM4_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM4_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM4_PRIORITY"
#endif
#endif /* GD32_HAS_TIM4 */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void tim4_irq_init(void) {
#if defined(GD32_TIM4_IS_USED)
eclicEnableVector(GD32_TIM4_NUMBER, GD32_IRQ_TIM4_PRIORITY, GD32_IRQ_TIM4_TRIGGER);
#endif
}
static inline void tim4_irq_deinit(void) {
#if defined(GD32_TIM4_IS_USED)
eclicDisableVector(GD32_TIM4_NUMBER);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(GD32_TIM4_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM4 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM4_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if GD32_GPT_USE_TIM4
gpt_lld_serve_interrupt(&GPTD4);
#endif
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM4
icu_lld_serve_interrupt(&ICUD4);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM4
pwm_lld_serve_interrupt(&PWMD4);
#endif
#endif
#if 1
#if GD32_ST_USE_TIM4
st_lld_serve_interrupt();
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

133
os/hal/ports/GD/GD32VF103/TIM/gd32_tim5.inc
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@ -1,133 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file TIM/gd32_tim5.inc
* @brief Shared TIM5 handler.
*
* @addtogroup GD32_TIM5_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(GD32_HAS_TIM5)
#error "GD32_HAS_TIM5 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(GD32_GPT_USE_TIM5)
#define GD32_GPT_USE_TIM5 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM5)
#define GD32_ICU_USE_TIM5 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM5)
#define GD32_PWM_USE_TIM5 FALSE
#endif
#if !defined(GD32_ST_USE_TIM5)
#define GD32_ST_USE_TIM5 FALSE
#endif
#if GD32_HAS_TIM5
/* Priority settings checks.*/
#if !defined(GD32_IRQ_TIM5_PRIORITY)
#error "GD32_IRQ_TIM5_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM5_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM5_PRIORITY"
#endif
#endif /* GD32_HAS_TIM5 */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void tim5_irq_init(void) {
#if defined(GD32_TIM5_IS_USED)
eclicEnableVector(GD32_TIM5_NUMBER, GD32_IRQ_TIM5_PRIORITY, GD32_IRQ_TIM5_TRIGGER);
#endif
}
static inline void tim5_irq_deinit(void) {
#if defined(GD32_TIM5_IS_USED)
eclicDisableVector(GD32_TIM5_NUMBER);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(GD32_TIM5_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM5 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM5_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if GD32_GPT_USE_TIM5
gpt_lld_serve_interrupt(&GPTD5);
#endif
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM5
icu_lld_serve_interrupt(&ICUD5);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM5
pwm_lld_serve_interrupt(&PWMD5);
#endif
#endif
#if 1
#if GD32_ST_USE_TIM5
st_lld_serve_interrupt();
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

133
os/hal/ports/GD/GD32VF103/TIM/gd32_tim6.inc
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@ -1,133 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file TIM/gd32_tim6.inc
* @brief Shared TIM6 handler.
*
* @addtogroup GD32_TIM6_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(GD32_HAS_TIM6)
#error "GD32_HAS_TIM6 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(GD32_GPT_USE_TIM6)
#define GD32_GPT_USE_TIM6 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM6)
#define GD32_ICU_USE_TIM6 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM6)
#define GD32_PWM_USE_TIM6 FALSE
#endif
#if !defined(GD32_ST_USE_TIM6)
#define GD32_ST_USE_TIM6 FALSE
#endif
#if GD32_HAS_TIM6
/* Priority settings checks.*/
#if !defined(GD32_IRQ_TIM6_PRIORITY)
#error "GD32_IRQ_TIM6_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM6_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM6_PRIORITY"
#endif
#endif /* GD32_HAS_TIM6 */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void tim6_irq_init(void) {
#if defined(GD32_TIM6_IS_USED)
eclicEnableVector(GD32_TIM6_NUMBER, GD32_IRQ_TIM6_PRIORITY, GD32_IRQ_TIM6_TRIGGER);
#endif
}
static inline void tim6_irq_deinit(void) {
#if defined(GD32_TIM6_IS_USED)
eclicDisableVector(GD32_TIM6_NUMBER);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(GD32_TIM6_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM6 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM6_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if GD32_GPT_USE_TIM6
gpt_lld_serve_interrupt(&GPTD6);
#endif
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM6
icu_lld_serve_interrupt(&ICUD6);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM6
pwm_lld_serve_interrupt(&PWMD6);
#endif
#endif
#if 1
#if GD32_ST_USE_TIM6
st_lld_serve_interrupt();
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

133
os/hal/ports/GD/GD32VF103/TIM/gd32_tim7.inc
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@ -1,133 +0,0 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file TIM/gd32_tim7.inc
* @brief Shared TIM7 handler.
*
* @addtogroup GD32_TIM7_HANDLER
* @{
*/
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/* Registry checks for robustness.*/
#if !defined(GD32_HAS_TIM7)
#error "GD32_HAS_TIM7 not defined in registry"
#endif
/* Driver checks for robustness, undefined USE macros are defaulted to
FALSE. This makes this module independent from drivers implementation.*/
#if !defined(GD32_GPT_USE_TIM7)
#define GD32_GPT_USE_TIM7 FALSE
#endif
#if !defined(GD32_ICU_USE_TIM7)
#define GD32_ICU_USE_TIM7 FALSE
#endif
#if !defined(GD32_PWM_USE_TIM7)
#define GD32_PWM_USE_TIM7 FALSE
#endif
#if !defined(GD32_ST_USE_TIM7)
#define GD32_ST_USE_TIM7 FALSE
#endif
#if GD32_HAS_TIM7
/* Priority settings checks.*/
#if !defined(GD32_IRQ_TIM7_PRIORITY)
#error "GD32_IRQ_TIM7_PRIORITY not defined in mcuconf.h"
#endif
#if !OSAL_IRQ_IS_VALID_PRIORITY(GD32_IRQ_TIM7_PRIORITY)
#error "Invalid IRQ priority assigned to GD32_IRQ_TIM7_PRIORITY"
#endif
#endif /* GD32_HAS_TIM7 */
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void tim7_irq_init(void) {
#if defined(GD32_TIM7_IS_USED)
eclicEnableVector(GD32_TIM7_NUMBER, GD32_IRQ_TIM7_PRIORITY, GD32_IRQ_TIM7_TRIGGER);
#endif
}
static inline void tim7_irq_deinit(void) {
#if defined(GD32_TIM7_IS_USED)
eclicDisableVector(GD32_TIM7_NUMBER);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if defined(GD32_TIM7_IS_USED) || defined(__DOXYGEN__)
/**
* @brief TIM7 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM7_HANDLER) {
OSAL_IRQ_PROLOGUE();
#if HAL_USE_GPT
#if GD32_GPT_USE_TIM7
gpt_lld_serve_interrupt(&GPTD7);
#endif
#endif
#if HAL_USE_ICU
#if GD32_ICU_USE_TIM7
icu_lld_serve_interrupt(&ICUD7);
#endif
#endif
#if HAL_USE_PWM
#if GD32_PWM_USE_TIM7
pwm_lld_serve_interrupt(&PWMD7);
#endif
#endif
#if 1
#if GD32_ST_USE_TIM7
st_lld_serve_interrupt();
#endif
#endif
OSAL_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/** @} */

554
os/hal/ports/GD/GD32VF103/TIM/hal_gpt_lld.c
View File

@ -90,102 +90,6 @@ GPTDriver GPTD6;
GPTDriver GPTD7;
#endif
/**
* @brief GPTD8 driver identifier.
* @note The driver GPTD8 allocates the timer TIM8 when enabled.
*/
#if GD32_GPT_USE_TIM8 || defined(__DOXYGEN__)
GPTDriver GPTD8;
#endif
/**
* @brief GPTD9 driver identifier.
* @note The driver GPTD9 allocates the timer TIM9 when enabled.
*/
#if GD32_GPT_USE_TIM9 || defined(__DOXYGEN__)
GPTDriver GPTD9;
#endif
/**
* @brief GPTD10 driver identifier.
* @note The driver GPTD10 allocates the timer TIM10 when enabled.
*/
#if GD32_GPT_USE_TIM10 || defined(__DOXYGEN__)
GPTDriver GPTD10;
#endif
/**
* @brief GPTD11 driver identifier.
* @note The driver GPTD11 allocates the timer TIM11 when enabled.
*/
#if GD32_GPT_USE_TIM11 || defined(__DOXYGEN__)
GPTDriver GPTD11;
#endif
/**
* @brief GPTD12 driver identifier.
* @note The driver GPTD12 allocates the timer TIM12 when enabled.
*/
#if GD32_GPT_USE_TIM12 || defined(__DOXYGEN__)
GPTDriver GPTD12;
#endif
/**
* @brief GPTD13 driver identifier.
* @note The driver GPTD13 allocates the timer TIM13 when enabled.
*/
#if GD32_GPT_USE_TIM13 || defined(__DOXYGEN__)
GPTDriver GPTD13;
#endif
/**
* @brief GPTD14 driver identifier.
* @note The driver GPTD14 allocates the timer TIM14 when enabled.
*/
#if GD32_GPT_USE_TIM14 || defined(__DOXYGEN__)
GPTDriver GPTD14;
#endif
/**
* @brief GPTD15 driver identifier.
* @note The driver GPTD14 allocates the timer TIM14 when enabled.
*/
#if GD32_GPT_USE_TIM15 || defined(__DOXYGEN__)
GPTDriver GPTD15;
#endif
/**
* @brief GPTD16 driver identifier.
* @note The driver GPTD14 allocates the timer TIM14 when enabled.
*/
#if GD32_GPT_USE_TIM16 || defined(__DOXYGEN__)
GPTDriver GPTD16;
#endif
/**
* @brief GPTD17 driver identifier.
* @note The driver GPTD14 allocates the timer TIM14 when enabled.
*/
#if GD32_GPT_USE_TIM17 || defined(__DOXYGEN__)
GPTDriver GPTD17;
#endif
/**
* @brief GPTD21 driver identifier.
* @note The driver GPTD21 allocates the timer TIM21 when enabled.
*/
#if GD32_GPT_USE_TIM21 || defined(__DOXYGEN__)
GPTDriver GPTD21;
#endif
/**
* @brief GPTD22 driver identifier.
* @note The driver GPTD22 allocates the timer TIM22 when enabled.
*/
#if GD32_GPT_USE_TIM22 || defined(__DOXYGEN__)
GPTDriver GPTD22;
#endif
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@ -345,123 +249,6 @@ OSAL_IRQ_HANDLER(GD32_TIM7_HANDLER) {
#endif /* !defined(GD32_TIM7_SUPPRESS_ISR) */
#endif /* GD32_GPT_USE_TIM7 */
#if GD32_GPT_USE_TIM8 || defined(__DOXYGEN__)
#if !defined(GD32_TIM8_SUPPRESS_ISR)
#if !defined(GD32_TIM8_UP_HANDLER)
#error "GD32_TIM8_UP_HANDLER not defined"
#endif
/**
* @brief TIM8 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM8_UP_HANDLER) {
OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD8);
OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(GD32_TIM8_SUPPRESS_ISR) */
#endif /* GD32_GPT_USE_TIM8 */
#if GD32_GPT_USE_TIM9 || defined(__DOXYGEN__)
#if !defined(GD32_TIM9_SUPPRESS_ISR)
#error "TIM9 ISR not defined by platform"
#endif /* !defined(GD32_TIM9_SUPPRESS_ISR) */
#endif /* GD32_GPT_USE_TIM9 */
#if GD32_GPT_USE_TIM10 || defined(__DOXYGEN__)
#if !defined(GD32_TIM10_SUPPRESS_ISR)
#error "TIM10 ISR not defined by platform"
#endif /* !defined(GD32_TIM10_SUPPRESS_ISR) */
#endif /* GD32_GPT_USE_TIM10 */
#if GD32_GPT_USE_TIM11 || defined(__DOXYGEN__)
#if !defined(GD32_TIM11_SUPPRESS_ISR)
#error "TIM11 ISR not defined by platform"
#endif /* !defined(GD32_TIM11_SUPPRESS_ISR) */
#endif /* GD32_GPT_USE_TIM11 */
#if GD32_GPT_USE_TIM12 || defined(__DOXYGEN__)
#if !defined(GD32_TIM12_SUPPRESS_ISR)
#error "TIM12 ISR not defined by platform"
#endif /* !defined(GD32_TIM12_SUPPRESS_ISR) */
#endif /* GD32_GPT_USE_TIM12 */
#if GD32_GPT_USE_TIM13 || defined(__DOXYGEN__)
#if !defined(GD32_TIM13_SUPPRESS_ISR)
#error "TIM13 ISR not defined by platform"
#endif /* !defined(GD32_TIM13_SUPPRESS_ISR) */
#endif /* GD32_GPT_USE_TIM13 */
#if GD32_GPT_USE_TIM14 || defined(__DOXYGEN__)
#if !defined(GD32_TIM14_SUPPRESS_ISR)
#error "TIM14 ISR not defined by platform"
#endif /* !defined(GD32_TIM14_SUPPRESS_ISR) */
#endif /* GD32_GPT_USE_TIM14 */
#if GD32_GPT_USE_TIM15 || defined(__DOXYGEN__)
#if !defined(GD32_TIM15_SUPPRESS_ISR)
#error "TIM15 ISR not defined by platform"
#endif /* !defined(GD32_TIM15_SUPPRESS_ISR) */
#endif /* GD32_GPT_USE_TIM15 */
#if GD32_GPT_USE_TIM16 || defined(__DOXYGEN__)
#if !defined(GD32_TIM16_SUPPRESS_ISR)
#error "TIM16 ISR not defined by platform"
#endif /* !defined(GD32_TIM16_SUPPRESS_ISR) */
#endif /* GD32_GPT_USE_TIM16 */
#if GD32_GPT_USE_TIM17 || defined(__DOXYGEN__)
#if !defined(GD32_TIM17_SUPPRESS_ISR)
#error "TIM17 ISR not defined by platform"
#endif /* !defined(GD32_TIM17_SUPPRESS_ISR) */
#endif /* GD32_GPT_USE_TIM17 */
#if GD32_GPT_USE_TIM21 || defined(__DOXYGEN__)
#if !defined(GD32_TIM21_SUPPRESS_ISR)
#if !defined(GD32_TIM21_HANDLER)
#error "GD32_TIM21_HANDLER not defined"
#endif
/**
* @brief TIM21 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM21_HANDLER) {
OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD21);
OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(GD32_TIM21_SUPPRESS_ISR) */
#endif /* GD32_GPT_USE_TIM21 */
#if GD32_GPT_USE_TIM22 || defined(__DOXYGEN__)
#if !defined(GD32_TIM22_SUPPRESS_ISR)
#if !defined(GD32_TIM22_HANDLER)
#error "GD32_TIM22_HANDLER not defined"
#endif
/**
* @brief TIM22 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM22_HANDLER) {
OSAL_IRQ_PROLOGUE();
gpt_lld_serve_interrupt(&GPTD22);
OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(GD32_TIM22_SUPPRESS_ISR) */
#endif /* GD32_GPT_USE_TIM22 */
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@ -514,78 +301,6 @@ void gpt_lld_init(void) {
GPTD7.tim = GD32_TIM7;
gptObjectInit(&GPTD7);
#endif
#if GD32_GPT_USE_TIM8
/* Driver initialization.*/
GPTD8.tim = GD32_TIM8;
gptObjectInit(&GPTD8);
#endif
#if GD32_GPT_USE_TIM9
/* Driver initialization.*/
GPTD9.tim = GD32_TIM9;
gptObjectInit(&GPTD9);
#endif
#if GD32_GPT_USE_TIM10
/* Driver initialization.*/
GPTD10.tim = GD32_TIM10;
gptObjectInit(&GPTD10);
#endif
#if GD32_GPT_USE_TIM11
/* Driver initialization.*/
GPTD11.tim = GD32_TIM11;
gptObjectInit(&GPTD11);
#endif
#if GD32_GPT_USE_TIM12
/* Driver initialization.*/
GPTD12.tim = GD32_TIM12;
gptObjectInit(&GPTD12);
#endif
#if GD32_GPT_USE_TIM13
/* Driver initialization.*/
GPTD13.tim = GD32_TIM13;
gptObjectInit(&GPTD13);
#endif
#if GD32_GPT_USE_TIM14
/* Driver initialization.*/
GPTD14.tim = GD32_TIM14;
gptObjectInit(&GPTD14);
#endif
#if GD32_GPT_USE_TIM15
/* Driver initialization.*/
GPTD15.tim = GD32_TIM15;
gptObjectInit(&GPTD15);
#endif
#if GD32_GPT_USE_TIM16
/* Driver initialization.*/
GPTD16.tim = GD32_TIM16;
gptObjectInit(&GPTD16);
#endif
#if GD32_GPT_USE_TIM17
/* Driver initialization.*/
GPTD17.tim = GD32_TIM17;
gptObjectInit(&GPTD17);
#endif
#if GD32_GPT_USE_TIM21
/* Driver initialization.*/
GPTD21.tim = GD32_TIM21;
gptObjectInit(&GPTD21);
#endif
#if GD32_GPT_USE_TIM22
/* Driver initialization.*/
GPTD22.tim = GD32_TIM22;
gptObjectInit(&GPTD22);
#endif
}
/**
@ -705,176 +420,6 @@ void gpt_lld_start(GPTDriver *gptp) {
}
#endif
#if GD32_GPT_USE_TIM8
if (&GPTD8 == gptp) {
rccEnableTIM8(true);
rccResetTIM8();
#if !defined(GD32_TIM8_SUPPRESS_ISR)
eclicEnableVector(GD32_TIM8_UP_NUMBER, GD32_GPT_TIM8_IRQ_PRIORITY, GD32_GPT_TIM8_IRQ_TRIGGER);
#endif
#if defined(GD32_TIM8CLK)
gptp->clock = GD32_TIM8CLK;
#else
gptp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_GPT_USE_TIM9
if (&GPTD9 == gptp) {
rccEnableTIM9(true);
rccResetTIM9();
#if !defined(GD32_TIM9_SUPPRESS_ISR)
eclicEnableVector(GD32_TIM9_NUMBER, GD32_GPT_TIM9_IRQ_PRIORITY, GD32_GPT_TIM9_IRQ_TRIGGER);
#endif
#if defined(GD32_TIM9CLK)
gptp->clock = GD32_TIM9CLK;
#else
gptp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_GPT_USE_TIM10
if (&GPTD10 == gptp) {
rccEnableTIM10(true);
rccResetTIM10();
#if !defined(GD32_TIM10_SUPPRESS_ISR)
eclicEnableVector(GD32_TIM10_NUMBER, GD32_GPT_TIM10_IRQ_PRIORITY, GD32_GPT_TIM10_IRQ_TRIGGER);
#endif
#if defined(GD32_TIM10CLK)
gptp->clock = GD32_TIM10CLK;
#else
gptp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_GPT_USE_TIM11
if (&GPTD11 == gptp) {
rccEnableTIM11(true);
rccResetTIM11();
#if !defined(GD32_TIM11_SUPPRESS_ISR)
eclicEnableVector(GD32_TIM11_NUMBER, GD32_GPT_TIM11_IRQ_PRIORITY, GD32_GPT_TIM11_IRQ_TRIGGER);
#endif
#if defined(GD32_TIM11CLK)
gptp->clock = GD32_TIM11CLK;
#else
gptp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_GPT_USE_TIM12
if (&GPTD12 == gptp) {
rccEnableTIM12(true);
rccResetTIM12();
#if !defined(GD32_TIM12_SUPPRESS_ISR)
eclicEnableVector(GD32_TIM12_NUMBER, GD32_GPT_TIM12_IRQ_PRIORITY, GD32_GPT_TIM12_IRQ_TRIGGER);
#endif
#if defined(GD32_TIM12CLK)
gptp->clock = GD32_TIM12CLK;
#else
gptp->clock = GD32_TIMCLK1;
#endif
}
#endif
#if GD32_GPT_USE_TIM13
if (&GPTD13 == gptp) {
rccEnableTIM13(true);
rccResetTIM13();
#if !defined(GD32_TIM13_SUPPRESS_ISR)
eclicEnableVector(GD32_TIM13_NUMBER, GD32_GPT_TIM13_IRQ_PRIORITY, GD32_GPT_TIM13_IRQ_TRIGGER);
#endif
#if defined(GD32_TIM13CLK)
gptp->clock = GD32_TIM13CLK;
#else
gptp->clock = GD32_TIMCLK1;
#endif
}
#endif
#if GD32_GPT_USE_TIM14
if (&GPTD14 == gptp) {
rccEnableTIM14(true);
rccResetTIM14();
#if !defined(GD32_TIM14_SUPPRESS_ISR)
eclicEnableVector(GD32_TIM14_NUMBER, GD32_GPT_TIM14_IRQ_PRIORITY, GD32_GPT_TIM14_IRQ_TRIGGER);
#endif
#if defined(GD32_TIM14CLK)
gptp->clock = GD32_TIM14CLK;
#else
gptp->clock = GD32_TIMCLK1;
#endif
}
#endif
#if GD32_GPT_USE_TIM15
if (&GPTD15 == gptp) {
rccEnableTIM15(true);
rccResetTIM15();
#if defined(GD32_TIM15CLK)
gptp->clock = GD32_TIM15CLK;
#else
gptp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_GPT_USE_TIM16
if (&GPTD16 == gptp) {
rccEnableTIM16(true);
rccResetTIM16();
#if defined(GD32_TIM16CLK)
gptp->clock = GD32_TIM16CLK;
#else
gptp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_GPT_USE_TIM17
if (&GPTD17 == gptp) {
rccEnableTIM17(true);
rccResetTIM17();
#if defined(GD32_TIM17CLK)
gptp->clock = GD32_TIM17CLK;
#else
gptp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_GPT_USE_TIM21
if (&GPTD21 == gptp) {
rccEnableTIM21(true);
rccResetTIM21();
#if !defined(GD32_TIM21_SUPPRESS_ISR)
eclicEnableVector(GD32_TIM21_NUMBER, GD32_GPT_TIM21_IRQ_PRIORITY, GD32_GPT_TIM21_IRQ_TRIGGER);
#endif
#if defined(GD32_TIM21CLK)
gptp->clock = GD32_TIM21CLK;
#else
gptp->clock = GD32_TIMCLK1;
#endif
}
#endif
#if GD32_GPT_USE_TIM22
if (&GPTD22 == gptp) {
rccEnableTIM22(true);
rccResetTIM22();
#if !defined(GD32_TIM22_SUPPRESS_ISR)
eclicEnableVector(GD32_TIM22_NUMBER, GD32_GPT_TIM22_IRQ_PRIORITY, GD32_GPT_TIM22_IRQ_TRIGGER);
#endif
#if defined(GD32_TIM22CLK)
gptp->clock = GD32_TIM22CLK;
#else
gptp->clock = GD32_TIMCLK1;
#endif
}
#endif
}
/* Prescaler value calculation.*/
@ -967,105 +512,6 @@ void gpt_lld_stop(GPTDriver *gptp) {
rccDisableTIM7();
}
#endif
#if GD32_GPT_USE_TIM8
if (&GPTD8 == gptp) {
#if !defined(GD32_TIM8_SUPPRESS_ISR)
eclicDisableVector(GD32_TIM8_UP_NUMBER);
#endif
rccDisableTIM8();
}
#endif
#if GD32_GPT_USE_TIM9
if (&GPTD9 == gptp) {
#if !defined(GD32_TIM9_SUPPRESS_ISR)
eclicDisableVector(GD32_TIM9_NUMBER);
#endif
rccDisableTIM9();
}
#endif
#if GD32_GPT_USE_TIM10
if (&GPTD10 == gptp) {
#if !defined(GD32_TIM10_SUPPRESS_ISR)
eclicDisableVector(GD32_TIM10_NUMBER);
#endif
rccDisableTIM10();
}
#endif
#if GD32_GPT_USE_TIM11
if (&GPTD11 == gptp) {
#if !defined(GD32_TIM11_SUPPRESS_ISR)
eclicDisableVector(GD32_TIM11_NUMBER);
#endif
rccDisableTIM11();
}
#endif
#if GD32_GPT_USE_TIM12
if (&GPTD12 == gptp) {
#if !defined(GD32_TIM12_SUPPRESS_ISR)
eclicDisableVector(GD32_TIM12_NUMBER);
#endif
rccDisableTIM12();
}
#endif
#if GD32_GPT_USE_TIM13
if (&GPTD13 == gptp) {
#if !defined(GD32_TIM13_SUPPRESS_ISR)
eclicDisableVector(GD32_TIM13_NUMBER);
#endif
rccDisableTIM13();
}
#endif
#if GD32_GPT_USE_TIM14
if (&GPTD14 == gptp) {
#if !defined(GD32_TIM14_SUPPRESS_ISR)
eclicDisableVector(GD32_TIM14_NUMBER);
#endif
rccDisableTIM14();
}
#endif
#if GD32_GPT_USE_TIM15
if (&GPTD15 == gptp) {
rccDisableTIM15();
}
#endif
#if GD32_GPT_USE_TIM16
if (&GPTD16 == gptp) {
rccDisableTIM16();
}
#endif
#if GD32_GPT_USE_TIM17
if (&GPTD17 == gptp) {
rccDisableTIM17();
}
#endif
#if GD32_GPT_USE_TIM21
if (&GPTD21 == gptp) {
#if !defined(GD32_TIM21_SUPPRESS_ISR)
eclicDisableVector(GD32_TIM21_NUMBER);
#endif
rccDisableTIM21();
}
#endif
#if GD32_GPT_USE_TIM22
if (&GPTD22 == gptp) {
#if !defined(GD32_TIM22_SUPPRESS_ISR)
eclicDisableVector(GD32_TIM22_NUMBER);
#endif
rccDisableTIM22();
}
#endif
}
}

506
os/hal/ports/GD/GD32VF103/TIM/hal_gpt_lld.h
View File

@ -104,114 +104,6 @@
#define GD32_GPT_USE_TIM7 FALSE
#endif
/**
* @brief GPTD8 driver enable switch.
* @details If set to @p TRUE the support for GPTD8 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_GPT_USE_TIM8) || defined(__DOXYGEN__)
#define GD32_GPT_USE_TIM8 FALSE
#endif
/**
* @brief GPTD9 driver enable switch.
* @details If set to @p TRUE the support for GPTD9 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_GPT_USE_TIM9) || defined(__DOXYGEN__)
#define GD32_GPT_USE_TIM9 FALSE
#endif
/**
* @brief GPTD10 driver enable switch.
* @details If set to @p TRUE the support for GPTD10 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_GPT_USE_TIM10) || defined(__DOXYGEN__)
#define GD32_GPT_USE_TIM10 FALSE
#endif
/**
* @brief GPTD11 driver enable switch.
* @details If set to @p TRUE the support for GPTD11 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_GPT_USE_TIM11) || defined(__DOXYGEN__)
#define GD32_GPT_USE_TIM11 FALSE
#endif
/**
* @brief GPTD12 driver enable switch.
* @details If set to @p TRUE the support for GPTD12 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_GPT_USE_TIM12) || defined(__DOXYGEN__)
#define GD32_GPT_USE_TIM12 FALSE
#endif
/**
* @brief GPTD13 driver enable switch.
* @details If set to @p TRUE the support for GPTD13 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_GPT_USE_TIM13) || defined(__DOXYGEN__)
#define GD32_GPT_USE_TIM13 FALSE
#endif
/**
* @brief GPTD14 driver enable switch.
* @details If set to @p TRUE the support for GPTD14 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_GPT_USE_TIM14) || defined(__DOXYGEN__)
#define GD32_GPT_USE_TIM14 FALSE
#endif
/**
* @brief GPTD14 driver enable switch.
* @details If set to @p TRUE the support for GPTD15 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_GPT_USE_TIM15) || defined(__DOXYGEN__)
#define GD32_GPT_USE_TIM15 FALSE
#endif
/**
* @brief GPTD14 driver enable switch.
* @details If set to @p TRUE the support for GPTD16 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_GPT_USE_TIM16) || defined(__DOXYGEN__)
#define GD32_GPT_USE_TIM16 FALSE
#endif
/**
* @brief GPTD14 driver enable switch.
* @details If set to @p TRUE the support for GPTD17 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_GPT_USE_TIM17) || defined(__DOXYGEN__)
#define GD32_GPT_USE_TIM17 FALSE
#endif
/**
* @brief GPTD21 driver enable switch.
* @details If set to @p TRUE the support for GPTD21 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_GPT_USE_TIM21) || defined(__DOXYGEN__)
#define GD32_GPT_USE_TIM21 FALSE
#endif
/**
* @brief GPTD22 driver enable switch.
* @details If set to @p TRUE the support for GPTD22 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_GPT_USE_TIM22) || defined(__DOXYGEN__)
#define GD32_GPT_USE_TIM22 FALSE
#endif
/**
* @brief GPTD1 interrupt priority level setting.
*/
@ -260,90 +152,6 @@
#if !defined(GD32_GPT_TIM7_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_GPT_TIM7_IRQ_PRIORITY 7
#endif
/**
* @brief GPTD8 interrupt priority level setting.
*/
#if !defined(GD32_GPT_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_GPT_TIM8_IRQ_PRIORITY 7
#endif
/**
* @brief GPTD9 interrupt priority level setting.
*/
#if !defined(GD32_GPT_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_GPT_TIM9_IRQ_PRIORITY 7
#endif
/**
* @brief GPTD10 interrupt priority level setting.
*/
#if !defined(GD32_GPT_TIM10_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_GPT_TIM10_IRQ_PRIORITY 7
#endif
/**
* @brief GPTD11 interrupt priority level setting.
*/
#if !defined(GD32_GPT_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_GPT_TIM11_IRQ_PRIORITY 7
#endif
/**
* @brief GPTD12 interrupt priority level setting.
*/
#if !defined(GD32_GPT_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_GPT_TIM12_IRQ_PRIORITY 7
#endif
/**
* @brief GPTD13 interrupt priority level setting.
*/
#if !defined(GD32_GPT_TIM13_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_GPT_TIM13_IRQ_PRIORITY 7
#endif
/**
* @brief GPTD14 interrupt priority level setting.
*/
#if !defined(GD32_GPT_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_GPT_TIM14_IRQ_PRIORITY 7
#endif
/**
* @brief GPTD15 interrupt priority level setting.
*/
#if !defined(GD32_GPT_TIM15_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_GPT_TIM15_IRQ_PRIORITY 7
#endif
/**
* @brief GPTD16 interrupt priority level setting.
*/
#if !defined(GD32_GPT_TIM16_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_GPT_TIM16_IRQ_PRIORITY 7
#endif
/**
* @brief GPTD17 interrupt priority level setting.
*/
#if !defined(GD32_GPT_TIM17_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_GPT_TIM17_IRQ_PRIORITY 7
#endif
/**
* @brief GPTD21 interrupt priority level setting.
*/
#if !defined(GD32_GPT_TIM21_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_GPT_TIM21_IRQ_PRIORITY 7
#endif
/**
* @brief GPTD22 interrupt priority level setting.
*/
#if !defined(GD32_GPT_TIM22_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_GPT_TIM22_IRQ_PRIORITY 7
#endif
/** @} */
/*===========================================================================*/
@ -378,54 +186,6 @@
#define GD32_HAS_TIM7 FALSE
#endif
#if !defined(GD32_HAS_TIM8)
#define GD32_HAS_TIM8 FALSE
#endif
#if !defined(GD32_HAS_TIM9)
#define GD32_HAS_TIM9 FALSE
#endif
#if !defined(GD32_HAS_TIM10)
#define GD32_HAS_TIM10 FALSE
#endif
#if !defined(GD32_HAS_TIM11)
#define GD32_HAS_TIM11 FALSE
#endif
#if !defined(GD32_HAS_TIM12)
#define GD32_HAS_TIM12 FALSE
#endif
#if !defined(GD32_HAS_TIM13)
#define GD32_HAS_TIM13 FALSE
#endif
#if !defined(GD32_HAS_TIM14)
#define GD32_HAS_TIM14 FALSE
#endif
#if !defined(GD32_HAS_TIM15)
#define GD32_HAS_TIM15 FALSE
#endif
#if !defined(GD32_HAS_TIM16)
#define GD32_HAS_TIM16 FALSE
#endif
#if !defined(GD32_HAS_TIM17)
#define GD32_HAS_TIM17 FALSE
#endif
#if !defined(GD32_HAS_TIM21)
#define GD32_HAS_TIM21 FALSE
#endif
#if !defined(GD32_HAS_TIM22)
#define GD32_HAS_TIM22 FALSE
#endif
#if GD32_GPT_USE_TIM1 && !GD32_HAS_TIM1
#error "TIM1 not present in the selected device"
#endif
@ -454,65 +214,11 @@
#error "TIM7 not present in the selected device"
#endif
#if GD32_GPT_USE_TIM8 && !GD32_HAS_TIM8
#error "TIM8 not present in the selected device"
#endif
#if GD32_GPT_USE_TIM9 && !GD32_HAS_TIM9
#error "TIM9 not present in the selected device"
#endif
#if GD32_GPT_USE_TIM10 && !GD32_HAS_TIM10
#error "TIM10 not present in the selected device"
#endif
#if GD32_GPT_USE_TIM11 && !GD32_HAS_TIM11
#error "TIM11 not present in the selected device"
#endif
#if GD32_GPT_USE_TIM12 && !GD32_HAS_TIM12
#error "TIM12 not present in the selected device"
#endif
#if GD32_GPT_USE_TIM13 && !GD32_HAS_TIM13
#error "TIM13 not present in the selected device"
#endif
#if GD32_GPT_USE_TIM14 && !GD32_HAS_TIM14
#error "TIM14 not present in the selected device"
#endif
#if GD32_GPT_USE_TIM15 && !GD32_HAS_TIM15
#error "TIM15 not present in the selected device"
#endif
#if GD32_GPT_USE_TIM16 && !GD32_HAS_TIM16
#error "TIM16 not present in the selected device"
#endif
#if GD32_GPT_USE_TIM17 && !GD32_HAS_TIM17
#error "TIM17 not present in the selected device"
#endif
#if GD32_GPT_USE_TIM21 && !GD32_HAS_TIM21
#error "TIM21 not present in the selected device"
#endif
#if GD32_GPT_USE_TIM22 && !GD32_HAS_TIM22
#error "TIM22 not present in the selected device"
#endif
#if !GD32_GPT_USE_TIM1 && !GD32_GPT_USE_TIM2 && \
!GD32_GPT_USE_TIM3 && !GD32_GPT_USE_TIM4 && \
!GD32_GPT_USE_TIM5 && !GD32_GPT_USE_TIM6 && \
!GD32_GPT_USE_TIM7 && !GD32_GPT_USE_TIM8 && \
!GD32_GPT_USE_TIM9 && !GD32_GPT_USE_TIM10 && \
!GD32_GPT_USE_TIM11 && !GD32_GPT_USE_TIM12 && \
!GD32_GPT_USE_TIM13 && !GD32_GPT_USE_TIM14 && \
!GD32_GPT_USE_TIM15 && !GD32_GPT_USE_TIM16 && \
!GD32_GPT_USE_TIM17 && \
!GD32_GPT_USE_TIM21 && !GD32_GPT_USE_TIM22
#error "GPT driver activated but no TIM peripheral assigned"
!GD32_GPT_USE_TIM7
#error "GPT driver activated but no TIM peripheral assigned"
#endif
/* Checks on allocation of TIMx units.*/
@ -572,102 +278,6 @@
#endif
#endif
#if GD32_GPT_USE_TIM8
#if defined(GD32_TIM8_IS_USED)
#error "GPTD8 requires TIM8 but the timer is already used"
#else
#define GD32_TIM8_IS_USED
#endif
#endif
#if GD32_GPT_USE_TIM9
#if defined(GD32_TIM9_IS_USED)
#error "GPTD9 requires TIM9 but the timer is already used"
#else
#define GD32_TIM9_IS_USED
#endif
#endif
#if GD32_GPT_USE_TIM10
#if defined(GD32_TIM10_IS_USED)
#error "GPTD10 requires TIM10 but the timer is already used"
#else
#define GD32_TIM10_IS_USED
#endif
#endif
#if GD32_GPT_USE_TIM11
#if defined(GD32_TIM11_IS_USED)
#error "GPTD11 requires TIM11 but the timer is already used"
#else
#define GD32_TIM11_IS_USED
#endif
#endif
#if GD32_GPT_USE_TIM12
#if defined(GD32_TIM12_IS_USED)
#error "GPTD12 requires TIM12 but the timer is already used"
#else
#define GD32_TIM12_IS_USED
#endif
#endif
#if GD32_GPT_USE_TIM13
#if defined(GD32_TIM13_IS_USED)
#error "GPTD13 requires TIM13 but the timer is already used"
#else
#define GD32_TIM13_IS_USED
#endif
#endif
#if GD32_GPT_USE_TIM14
#if defined(GD32_TIM14_IS_USED)
#error "GPTD14 requires TIM14 but the timer is already used"
#else
#define GD32_TIM14_IS_USED
#endif
#endif
#if GD32_GPT_USE_TIM15
#if defined(GD32_TIM15_IS_USED)
#error "GPTD14 requires TIM15 but the timer is already used"
#else
#define GD32_TIM15_IS_USED
#endif
#endif
#if GD32_GPT_USE_TIM16
#if defined(GD32_TIM16_IS_USED)
#error "GPTD14 requires TIM16 but the timer is already used"
#else
#define GD32_TIM16_IS_USED
#endif
#endif
#if GD32_GPT_USE_TIM17
#if defined(GD32_TIM17_IS_USED)
#error "GPTD14 requires TIM17 but the timer is already used"
#else
#define GD32_TIM17_IS_USED
#endif
#endif
#if GD32_GPT_USE_TIM21
#if defined(GD32_TIM21_IS_USED)
#error "GPTD21 requires TIM21 but the timer is already used"
#else
#define GD32_TIM21_IS_USED
#endif
#endif
#if GD32_GPT_USE_TIM22
#if defined(GD32_TIM22_IS_USED)
#error "GPTD22 requires TIM22 but the timer is already used"
#else
#define GD32_TIM22_IS_USED
#endif
#endif
/* IRQ priority checks.*/
#if GD32_GPT_USE_TIM1 && !defined(GD32_TIM1_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_GPT_TIM1_IRQ_PRIORITY)
@ -704,66 +314,6 @@
#error "Invalid IRQ priority assigned to TIM7"
#endif
#if GD32_GPT_USE_TIM8 && !defined(GD32_TIM8_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_GPT_TIM8_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM8"
#endif
#if GD32_GPT_USE_TIM9 && !defined(GD32_TIM9_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_GPT_TIM9_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM9"
#endif
#if GD32_GPT_USE_TIM10 && !defined(GD32_TIM10_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_GPT_TIM10_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM10"
#endif
#if GD32_GPT_USE_TIM11 && !defined(GD32_TIM11_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_GPT_TIM11_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM11"
#endif
#if GD32_GPT_USE_TIM12 && !defined(GD32_TIM12_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_GPT_TIM12_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM12"
#endif
#if GD32_GPT_USE_TIM13 && !defined(GD32_TIM13_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_GPT_TIM13_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM13"
#endif
#if GD32_GPT_USE_TIM14 && !defined(GD32_TIM14_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_GPT_TIM14_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM14"
#endif
#if GD32_GPT_USE_TIM15 && !defined(GD32_TIM15_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_GPT_TIM15_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM15"
#endif
#if GD32_GPT_USE_TIM16 && !defined(GD32_TIM16_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_GPT_TIM16_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM16"
#endif
#if GD32_GPT_USE_TIM17 && !defined(GD32_TIM17_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_GPT_TIM17_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM17"
#endif
#if GD32_GPT_USE_TIM21 && !defined(GD32_TIM21_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_GPT_TIM21_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM21"
#endif
#if GD32_GPT_USE_TIM22 && !defined(GD32_TIM22_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_GPT_TIM22_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM22"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@ -801,13 +351,13 @@ typedef struct {
* @brief TIM CR2 register initialization data.
* @note The value of this field should normally be equal to zero.
*/
uint32_t cr2;
uint32_t ctl1;
/**
* @brief TIM DIER register initialization data.
* @note The value of this field should normally be equal to zero.
* @note Only the DMA-related bits can be specified in this field.
*/
uint32_t dier;
uint32_t dmainten;
} GPTConfig;
/**
@ -911,54 +461,6 @@ extern GPTDriver GPTD6;
extern GPTDriver GPTD7;
#endif
#if GD32_GPT_USE_TIM8 && !defined(__DOXYGEN__)
extern GPTDriver GPTD8;
#endif
#if GD32_GPT_USE_TIM9 && !defined(__DOXYGEN__)
extern GPTDriver GPTD9;
#endif
#if GD32_GPT_USE_TIM10 && !defined(__DOXYGEN__)
extern GPTDriver GPTD10;
#endif
#if GD32_GPT_USE_TIM11 && !defined(__DOXYGEN__)
extern GPTDriver GPTD11;
#endif
#if GD32_GPT_USE_TIM12 && !defined(__DOXYGEN__)
extern GPTDriver GPTD12;
#endif
#if GD32_GPT_USE_TIM13 && !defined(__DOXYGEN__)
extern GPTDriver GPTD13;
#endif
#if GD32_GPT_USE_TIM14 && !defined(__DOXYGEN__)
extern GPTDriver GPTD14;
#endif
#if GD32_GPT_USE_TIM15 && !defined(__DOXYGEN__)
extern GPTDriver GPTD15;
#endif
#if GD32_GPT_USE_TIM16 && !defined(__DOXYGEN__)
extern GPTDriver GPTD16;
#endif
#if GD32_GPT_USE_TIM17 && !defined(__DOXYGEN__)
extern GPTDriver GPTD17;
#endif
#if GD32_GPT_USE_TIM21 && !defined(__DOXYGEN__)
extern GPTDriver GPTD21;
#endif
#if GD32_GPT_USE_TIM22 && !defined(__DOXYGEN__)
extern GPTDriver GPTD22;
#endif
#ifdef __cplusplus
extern "C" {
#endif

457
os/hal/ports/GD/GD32VF103/TIM/hal_icu_lld.c
View File

@ -78,94 +78,6 @@ ICUDriver ICUD4;
ICUDriver ICUD5;
#endif
/**
* @brief ICUD8 driver identifier.
* @note The driver ICUD8 allocates the timer TIM8 when enabled.
*/
#if GD32_ICU_USE_TIM8 || defined(__DOXYGEN__)
ICUDriver ICUD8;
#endif
/**
* @brief ICUD9 driver identifier.
* @note The driver ICUD9 allocates the timer TIM9 when enabled.
*/
#if GD32_ICU_USE_TIM9 || defined(__DOXYGEN__)
ICUDriver ICUD9;
#endif
/**
* @brief ICUD10 driver identifier.
* @note The driver ICUD10 allocates the timer TIM10 when enabled.
*/
#if GD32_ICU_USE_TIM10 || defined(__DOXYGEN__)
ICUDriver ICUD10;
#endif
/**
* @brief ICUD11 driver identifier.
* @note The driver ICUD11 allocates the timer TIM11 when enabled.
*/
#if GD32_ICU_USE_TIM11 || defined(__DOXYGEN__)
ICUDriver ICUD11;
#endif
/**
* @brief ICUD12 driver identifier.
* @note The driver ICUD12 allocates the timer TIM12 when enabled.
*/
#if GD32_ICU_USE_TIM12 || defined(__DOXYGEN__)
ICUDriver ICUD12;
#endif
/**
* @brief ICUD13 driver identifier.
* @note The driver ICUD13 allocates the timer TIM13 when enabled.
*/
#if GD32_ICU_USE_TIM13 || defined(__DOXYGEN__)
ICUDriver ICUD13;
#endif
/**
* @brief ICUD14 driver identifier.
* @note The driver ICUD14 allocates the timer TIM14 when enabled.
*/
#if GD32_ICU_USE_TIM14 || defined(__DOXYGEN__)
ICUDriver ICUD14;
#endif
/**
* @brief ICUD15 driver identifier.
* @note The driver ICUD15 allocates the timer TIM15 when enabled.
*/
#if GD32_ICU_USE_TIM15 || defined(__DOXYGEN__)
ICUDriver ICUD15;
#endif
/**
* @brief ICUD20 driver identifier.
* @note The driver ICUD20 allocates the timer TIM20 when enabled.
*/
#if GD32_ICU_USE_TIM20 || defined(__DOXYGEN__)
ICUDriver ICUD20;
#endif
/**
* @brief ICUD21 driver identifier.
* @note The driver ICUD21 allocates the timer TIM21 when enabled.
*/
#if GD32_ICU_USE_TIM21 || defined(__DOXYGEN__)
ICUDriver ICUD21;
#endif
/**
* @brief ICUD22 driver identifier.
* @note The driver ICUD22 allocates the timer TIM22 when enabled.
*/
#if GD32_ICU_USE_TIM22 || defined(__DOXYGEN__)
ICUDriver ICUD22;
#endif
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@ -336,104 +248,6 @@ OSAL_IRQ_HANDLER(GD32_TIM5_HANDLER) {
#endif /* !defined(GD32_TIM5_SUPPRESS_ISR) */
#endif /* GD32_ICU_USE_TIM5 */
#if GD32_ICU_USE_TIM8 || defined(__DOXYGEN__)
#if !defined(GD32_TIM8_SUPPRESS_ISR)
#if !defined(GD32_TIM8_UP_HANDLER)
#error "GD32_TIM8_UP_HANDLER not defined"
#endif
/**
* @brief TIM8 compare interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM8_UP_HANDLER) {
OSAL_IRQ_PROLOGUE();
icu_lld_serve_interrupt(&ICUD8);
OSAL_IRQ_EPILOGUE();
}
#if !defined(GD32_TIM8_CC_HANDLER)
#error "GD32_TIM8_CC_HANDLER not defined"
#endif
/**
* @brief TIM8 compare interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM8_CC_HANDLER) {
OSAL_IRQ_PROLOGUE();
icu_lld_serve_interrupt(&ICUD8);
OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(GD32_TIM8_SUPPRESS_ISR) */
#endif /* GD32_ICU_USE_TIM8 */
#if GD32_ICU_USE_TIM9 || defined(__DOXYGEN__)
#if !defined(GD32_TIM9_SUPPRESS_ISR)
#error "TIM9 ISR not defined by platform"
#endif /* !defined(GD32_TIM9_SUPPRESS_ISR) */
#endif /* GD32_ICU_USE_TIM9 */
#if GD32_ICU_USE_TIM10 || defined(__DOXYGEN__)
#if !defined(GD32_TIM10_SUPPRESS_ISR)
#error "TIM10 ISR not defined by platform"
#endif /* !defined(GD32_TIM10_SUPPRESS_ISR) */
#endif /* GD32_ICU_USE_TIM10 */
#if GD32_ICU_USE_TIM11 || defined(__DOXYGEN__)
#if !defined(GD32_TIM11_SUPPRESS_ISR)
#error "TIM11 ISR not defined by platform"
#endif /* !defined(GD32_TIM11_SUPPRESS_ISR) */
#endif /* GD32_ICU_USE_TIM11 */
#if GD32_ICU_USE_TIM12 || defined(__DOXYGEN__)
#if !defined(GD32_TIM12_SUPPRESS_ISR)
#error "TIM12 ISR not defined by platform"
#endif /* !defined(GD32_TIM12_SUPPRESS_ISR) */
#endif /* GD32_ICU_USE_TIM12 */
#if GD32_ICU_USE_TIM13 || defined(__DOXYGEN__)
#if !defined(GD32_TIM13_SUPPRESS_ISR)
#error "TIM13 ISR not defined by platform"
#endif /* !defined(GD32_TIM13_SUPPRESS_ISR) */
#endif /* GD32_ICU_USE_TIM13 */
#if GD32_ICU_USE_TIM14 || defined(__DOXYGEN__)
#if !defined(GD32_TIM14_SUPPRESS_ISR)
#error "TIM14 ISR not defined by platform"
#endif /* !defined(GD32_TIM14_SUPPRESS_ISR) */
#endif /* GD32_ICU_USE_TIM14 */
#if GD32_ICU_USE_TIM15 || defined(__DOXYGEN__)
#if !defined(GD32_TIM15_SUPPRESS_ISR)
#error "TIM15 ISR not defined by platform"
#endif /* !defined(GD32_TIM15_SUPPRESS_ISR) */
#endif /* GD32_ICU_USE_TIM15 */
#if GD32_ICU_USE_TIM20 || defined(__DOXYGEN__)
#if !defined(GD32_TIM20_SUPPRESS_ISR)
#error "TIM20 ISR not defined by platform"
#endif /* !defined(GD32_TIM20_SUPPRESS_ISR) */
#endif /* GD32_ICU_USE_TIM20 */
#if GD32_ICU_USE_TIM21 || defined(__DOXYGEN__)
#if !defined(GD32_TIM21_SUPPRESS_ISR)
#error "TIM21 ISR not defined by platform"
#endif /* !defined(GD32_TIM21_SUPPRESS_ISR) */
#endif /* GD32_ICU_USE_TIM21 */
#if GD32_ICU_USE_TIM22 || defined(__DOXYGEN__)
#if !defined(GD32_TIM22_SUPPRESS_ISR)
#error "TIM22 ISR not defined by platform"
#endif /* !defined(GD32_TIM22_SUPPRESS_ISR) */
#endif /* GD32_ICU_USE_TIM22 */
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@ -474,72 +288,6 @@ void icu_lld_init(void) {
icuObjectInit(&ICUD5);
ICUD5.tim = GD32_TIM5;
#endif
#if GD32_ICU_USE_TIM8
/* Driver initialization.*/
icuObjectInit(&ICUD8);
ICUD8.tim = GD32_TIM8;
#endif
#if GD32_ICU_USE_TIM9
/* Driver initialization.*/
icuObjectInit(&ICUD9);
ICUD9.tim = GD32_TIM9;
#endif
#if GD32_ICU_USE_TIM10
/* Driver initialization.*/
icuObjectInit(&ICUD10);
ICUD10.tim = GD32_TIM10;
#endif
#if GD32_ICU_USE_TIM11
/* Driver initialization.*/
icuObjectInit(&ICUD11);
ICUD11.tim = GD32_TIM11;
#endif
#if GD32_ICU_USE_TIM12
/* Driver initialization.*/
icuObjectInit(&ICUD12);
ICUD12.tim = GD32_TIM12;
#endif
#if GD32_ICU_USE_TIM13
/* Driver initialization.*/
icuObjectInit(&ICUD13);
ICUD13.tim = GD32_TIM13;
#endif
#if GD32_ICU_USE_TIM14
/* Driver initialization.*/
icuObjectInit(&ICUD14);
ICUD14.tim = GD32_TIM14;
#endif
#if GD32_ICU_USE_TIM15
/* Driver initialization.*/
icuObjectInit(&ICUD15);
ICUD15.tim = GD32_TIM15;
#endif
#if GD32_ICU_USE_TIM20
/* Driver initialization.*/
icuObjectInit(&ICUD20);
ICUD20.tim = GD32_TIM20;
#endif
#if GD32_ICU_USE_TIM21
/* Driver initialization.*/
icuObjectInit(&ICUD21);
ICUD21.tim = GD32_TIM21;
#endif
#if GD32_ICU_USE_TIM22
/* Driver initialization.*/
icuObjectInit(&ICUD22);
ICUD22.tim = GD32_TIM22;
#endif
}
/**
@ -634,141 +382,6 @@ void icu_lld_start(ICUDriver *icup) {
}
#endif
#if GD32_ICU_USE_TIM8
if (&ICUD8 == icup) {
rccEnableTIM8(true);
rccResetTIM8();
#if !defined(GD32_TIM8_SUPPRESS_ISR)
eclicEnableVector(GD32_TIM8_UP_NUMBER, GD32_ICU_TIM8_IRQ_PRIORITY, GD32_ICU_TIM8_IRQ_TRIGGER);
eclicEnableVector(GD32_TIM8_CC_NUMBER, GD32_ICU_TIM8_IRQ_PRIORITY, GD32_ICU_TIM8_IRQ_TRIGGER);
#endif
#if defined(GD32_TIM8CLK)
icup->clock = GD32_TIM8CLK;
#else
icup->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_ICU_USE_TIM9
if (&ICUD9 == icup) {
rccEnableTIM9(true);
rccResetTIM9();
#if defined(GD32_TIM9CLK)
icup->clock = GD32_TIM9CLK;
#else
icup->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_ICU_USE_TIM10
if (&ICUD10 == icup) {
rccEnableTIM10(true);
rccResetTIM10();
#if defined(GD32_TIM10CLK)
icup->clock = GD32_TIM10CLK;
#else
icup->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_ICU_USE_TIM11
if (&ICUD11 == icup) {
rccEnableTIM11(true);
rccResetTIM11();
#if defined(GD32_TIM11CLK)
icup->clock = GD32_TIM11CLK;
#else
icup->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_ICU_USE_TIM12
if (&ICUD12 == icup) {
rccEnableTIM12(true);
rccResetTIM12();
#if defined(GD32_TIM12CLK)
icup->clock = GD32_TIM12CLK;
#else
icup->clock = GD32_TIMCLK1;
#endif
}
#endif
#if GD32_ICU_USE_TIM13
if (&ICUD13 == icup) {
rccEnableTIM13(true);
rccResetTIM13();
#if defined(GD32_TIM13CLK)
icup->clock = GD32_TIM13CLK;
#else
icup->clock = GD32_TIMCLK1;
#endif
}
#endif
#if GD32_ICU_USE_TIM14
if (&ICUD14 == icup) {
rccEnableTIM14(true);
rccResetTIM14();
#if defined(GD32_TIM14CLK)
icup->clock = GD32_TIM14CLK;
#else
icup->clock = GD32_TIMCLK1;
#endif
}
#endif
#if GD32_ICU_USE_TIM15
if (&ICUD15 == icup) {
rccEnableTIM15(true);
rccResetTIM15();
#if defined(GD32_TIM15CLK)
icup->clock = GD32_TIM15CLK;
#else
icup->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_ICU_USE_TIM20
if (&ICUD20 == icup) {
rccEnableTIM20(true);
rccResetTIM20();
#if defined(GD32_TIM20CLK)
icup->clock = GD32_TIM20CLK;
#else
icup->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_ICU_USE_TIM21
if (&ICUD21 == icup) {
rccEnableTIM21(true);
rccResetTIM21();
#if defined(GD32_TIM21CLK)
icup->clock = GD32_TIM21CLK;
#else
icup->clock = GD32_TIMCLK1;
#endif
}
#endif
#if GD32_ICU_USE_TIM22
if (&ICUD22 == icup) {
rccEnableTIM22(true);
rccResetTIM22();
#if defined(GD32_TIM22CLK)
icup->clock = GD32_TIM22CLK;
#else
icup->clock = GD32_TIMCLK1;
#endif
}
#endif
}
else {
/* Driver re-configuration scenario, it must be stopped first.*/
@ -908,76 +521,6 @@ void icu_lld_stop(ICUDriver *icup) {
rccDisableTIM5();
}
#endif
#if GD32_ICU_USE_TIM8
if (&ICUD8 == icup) {
#if !defined(GD32_TIM8_SUPPRESS_ISR)
eclicDisableVector(GD32_TIM8_UP_NUMBER);
eclicDisableVector(GD32_TIM8_CC_NUMBER);
#endif
rccDisableTIM8();
}
#endif
#if GD32_ICU_USE_TIM9
if (&ICUD9 == icup) {
rccDisableTIM9();
}
#endif
#if GD32_ICU_USE_TIM10
if (&ICUD10 == icup) {
rccDisableTIM10();
}
#endif
#if GD32_ICU_USE_TIM11
if (&ICUD11 == icup) {
rccDisableTIM11();
}
#endif
#if GD32_ICU_USE_TIM12
if (&ICUD12 == icup) {
rccDisableTIM12();
}
#endif
#if GD32_ICU_USE_TIM13
if (&ICUD13 == icup) {
rccDisableTIM13();
}
#endif
#if GD32_ICU_USE_TIM14
if (&ICUD14 == icup) {
rccDisableTIM14();
}
#endif
#if GD32_ICU_USE_TIM15
if (&ICUD15 == icup) {
rccDisableTIM15();
}
#endif
#if GD32_ICU_USE_TIM20
if (&ICUD20 == icup) {
rccDisableTIM20();
}
#endif
#if GD32_ICU_USE_TIM21
if (&ICUD21 == icup) {
rccDisableTIM21();
}
#endif
#if GD32_ICU_USE_TIM22
if (&ICUD22 == icup) {
rccDisableTIM22();
}
#endif
}
}

462
os/hal/ports/GD/GD32VF103/TIM/hal_icu_lld.h
View File

@ -86,105 +86,6 @@
#define GD32_ICU_USE_TIM5 FALSE
#endif
/**
* @brief ICUD8 driver enable switch.
* @details If set to @p TRUE the support for ICUD8 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_ICU_USE_TIM8) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM8 FALSE
#endif
/**
* @brief ICUD9 driver enable switch.
* @details If set to @p TRUE the support for ICUD9 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_ICU_USE_TIM9) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM9 FALSE
#endif
/**
* @brief ICUD10 driver enable switch.
* @details If set to @p TRUE the support for ICUD10 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_ICU_USE_TIM10) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM10 FALSE
#endif
/**
* @brief ICUD11 driver enable switch.
* @details If set to @p TRUE the support for ICUD11 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_ICU_USE_TIM11) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM11 FALSE
#endif
/**
* @brief ICUD12 driver enable switch.
* @details If set to @p TRUE the support for ICUD12 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_ICU_USE_TIM12) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM12 FALSE
#endif
/**
* @brief ICUD13 driver enable switch.
* @details If set to @p TRUE the support for ICUD13 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_ICU_USE_TIM13) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM13 FALSE
#endif
/**
* @brief ICUD14 driver enable switch.
* @details If set to @p TRUE the support for ICUD14 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_ICU_USE_TIM14) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM14 FALSE
#endif
/**
* @brief ICUD15 driver enable switch.
* @details If set to @p TRUE the support for ICUD15 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_ICU_USE_TIM15) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM15 FALSE
#endif
/**
* @brief ICUD20 driver enable switch.
* @details If set to @p TRUE the support for ICUD20 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_ICU_USE_TIM20) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM20 FALSE
#endif
/**
* @brief ICUD21 driver enable switch.
* @details If set to @p TRUE the support for ICUD21 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_ICU_USE_TIM21) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM21 FALSE
#endif
/**
* @brief ICUD22 driver enable switch.
* @details If set to @p TRUE the support for ICUD22 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_ICU_USE_TIM22) || defined(__DOXYGEN__)
#define GD32_ICU_USE_TIM22 FALSE
#endif
/**
* @brief ICUD1 interrupt priority level setting.
*/
@ -219,83 +120,6 @@
#if !defined(GD32_ICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM5_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD8 interrupt priority level setting.
*/
#if !defined(GD32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM8_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD9 interrupt priority level setting.
*/
#if !defined(GD32_ICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM9_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD10 interrupt priority level setting.
*/
#if !defined(GD32_ICU_TIM10_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM10_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD11 interrupt priority level setting.
*/
#if !defined(GD32_ICU_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM11_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD12 interrupt priority level setting.
*/
#if !defined(GD32_ICU_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM12_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD13 interrupt priority level setting.
*/
#if !defined(GD32_ICU_TIM13_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM13_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD14 interrupt priority level setting.
*/
#if !defined(GD32_ICU_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM14_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD15 interrupt priority level setting.
*/
#if !defined(GD32_ICU_TIM15_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM15_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD20 interrupt priority level setting.
*/
#if !defined(GD32_ICU_TIM20_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM20_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD21 interrupt priority level setting.
*/
#if !defined(GD32_ICU_TIM21_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM21_IRQ_PRIORITY 7
#endif
/**
* @brief ICUD22 interrupt priority level setting.
*/
#if !defined(GD32_ICU_TIM22_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_ICU_TIM22_IRQ_PRIORITY 7
#endif
/** @} */
/*===========================================================================*/
@ -322,50 +146,6 @@
#define GD32_HAS_TIM5 FALSE
#endif
#if !defined(GD32_HAS_TIM8)
#define GD32_HAS_TIM8 FALSE
#endif
#if !defined(GD32_HAS_TIM9)
#define GD32_HAS_TIM9 FALSE
#endif
#if !defined(GD32_HAS_TIM10)
#define GD32_HAS_TIM10 FALSE
#endif
#if !defined(GD32_HAS_TIM11)
#define GD32_HAS_TIM11 FALSE
#endif
#if !defined(GD32_HAS_TIM12)
#define GD32_HAS_TIM12 FALSE
#endif
#if !defined(GD32_HAS_TIM13)
#define GD32_HAS_TIM13 FALSE
#endif
#if !defined(GD32_HAS_TIM14)
#define GD32_HAS_TIM14 FALSE
#endif
#if !defined(GD32_HAS_TIM15)
#define GD32_HAS_TIM15 FALSE
#endif
#if !defined(GD32_HAS_TIM20)
#define GD32_HAS_TIM20 FALSE
#endif
#if !defined(GD32_HAS_TIM21)
#define GD32_HAS_TIM21 FALSE
#endif
#if !defined(GD32_HAS_TIM22)
#define GD32_HAS_TIM22 FALSE
#endif
#if GD32_ICU_USE_TIM1 && !GD32_HAS_TIM1
#error "TIM1 not present in the selected device"
#endif
@ -386,58 +166,9 @@
#error "TIM5 not present in the selected device"
#endif
#if GD32_ICU_USE_TIM8 && !GD32_HAS_TIM8
#error "TIM8 not present in the selected device"
#endif
#if GD32_ICU_USE_TIM9 && !GD32_HAS_TIM9
#error "TIM9 not present in the selected device"
#endif
#if GD32_ICU_USE_TIM10 && !GD32_HAS_TIM10
#error "TIM10 not present in the selected device"
#endif
#if GD32_ICU_USE_TIM11 && !GD32_HAS_TIM11
#error "TIM11 not present in the selected device"
#endif
#if GD32_ICU_USE_TIM12 && !GD32_HAS_TIM12
#error "TIM12 not present in the selected device"
#endif
#if GD32_ICU_USE_TIM13 && !GD32_HAS_TIM13
#error "TIM13 not present in the selected device"
#endif
#if GD32_ICU_USE_TIM14 && !GD32_HAS_TIM14
#error "TIM14 not present in the selected device"
#endif
#if GD32_ICU_USE_TIM15 && !GD32_HAS_TIM15
#error "TIM15 not present in the selected device"
#endif
#if GD32_ICU_USE_TIM20 && !GD32_HAS_TIM20
#error "TIM20 not present in the selected device"
#endif
#if GD32_ICU_USE_TIM21 && !GD32_HAS_TIM21
#error "TIM21 not present in the selected device"
#endif
#if GD32_ICU_USE_TIM22 && !GD32_HAS_TIM22
#error "TIM22 not present in the selected device"
#endif
#if !GD32_ICU_USE_TIM1 && !GD32_ICU_USE_TIM2 && \
!GD32_ICU_USE_TIM3 && !GD32_ICU_USE_TIM4 && \
!GD32_ICU_USE_TIM5 && !GD32_ICU_USE_TIM8 && \
!GD32_ICU_USE_TIM9 && !GD32_ICU_USE_TIM10 && \
!GD32_ICU_USE_TIM11 && !GD32_ICU_USE_TIM12 && \
!GD32_ICU_USE_TIM13 && !GD32_ICU_USE_TIM14 && \
!GD32_ICU_USE_TIM15 && !GD32_ICU_USE_TIM20 && \
!GD32_ICU_USE_TIM21 && !GD32_ICU_USE_TIM22
!GD32_ICU_USE_TIM5
#error "ICU driver activated but no TIM peripheral assigned"
#endif
@ -482,94 +213,6 @@
#endif
#endif
#if GD32_ICU_USE_TIM8
#if defined(GD32_TIM8_IS_USED)
#error "ICUD8 requires TIM8 but the timer is already used"
#else
#define GD32_TIM8_IS_USED
#endif
#endif
#if GD32_ICU_USE_TIM9
#if defined(GD32_TIM9_IS_USED)
#error "ICUD9 requires TIM9 but the timer is already used"
#else
#define GD32_TIM9_IS_USED
#endif
#endif
#if GD32_ICU_USE_TIM10
#if defined(GD32_TIM10_IS_USED)
#error "ICUD10 requires TIM10 but the timer is already used"
#else
#define GD32_TIM10_IS_USED
#endif
#endif
#if GD32_ICU_USE_TIM11
#if defined(GD32_TIM11_IS_USED)
#error "ICUD11 requires TIM11 but the timer is already used"
#else
#define GD32_TIM11_IS_USED
#endif
#endif
#if GD32_ICU_USE_TIM12
#if defined(GD32_TIM12_IS_USED)
#error "ICUD12 requires TIM12 but the timer is already used"
#else
#define GD32_TIM12_IS_USED
#endif
#endif
#if GD32_ICU_USE_TIM13
#if defined(GD32_TIM13_IS_USED)
#error "ICUD13 requires TIM13 but the timer is already used"
#else
#define GD32_TIM13_IS_USED
#endif
#endif
#if GD32_ICU_USE_TIM14
#if defined(GD32_TIM14_IS_USED)
#error "ICUD14 requires TIM14 but the timer is already used"
#else
#define GD32_TIM14_IS_USED
#endif
#endif
#if GD32_ICU_USE_TIM15
#if defined(GD32_TIM15_IS_USED)
#error "ICUD15 requires TIM15 but the timer is already used"
#else
#define GD32_TIM15_IS_USED
#endif
#endif
#if GD32_ICU_USE_TIM20
#if defined(GD32_TIM20_IS_USED)
#error "ICUD20 requires TIM20 but the timer is already used"
#else
#define GD32_TIM20_IS_USED
#endif
#endif
#if GD32_ICU_USE_TIM21
#if defined(GD32_TIM21_IS_USED)
#error "ICUD21 requires TIM21 but the timer is already used"
#else
#define GD32_TIM21_IS_USED
#endif
#endif
#if GD32_ICU_USE_TIM22
#if defined(GD32_TIM22_IS_USED)
#error "ICUD22 requires TIM22 but the timer is already used"
#else
#define GD32_TIM22_IS_USED
#endif
#endif
/* IRQ priority checks.*/
#if GD32_ICU_USE_TIM1 && !defined(GD32_TIM1_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM1_IRQ_PRIORITY)
@ -596,61 +239,6 @@
#error "Invalid IRQ priority assigned to TIM5"
#endif
#if GD32_ICU_USE_TIM8 && !defined(GD32_TIM8_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM8_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM8"
#endif
#if GD32_ICU_USE_TIM9 && !defined(GD32_TIM9_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM9_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM9"
#endif
#if GD32_ICU_USE_TIM10 && !defined(GD32_TIM10_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM10_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM10"
#endif
#if GD32_ICU_USE_TIM11 && !defined(GD32_TIM11_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM11_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM11"
#endif
#if GD32_ICU_USE_TIM12 && !defined(GD32_TIM12_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM12_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM12"
#endif
#if GD32_ICU_USE_TIM13 && !defined(GD32_TIM13_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM13_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM13"
#endif
#if GD32_ICU_USE_TIM14 && !defined(GD32_TIM14_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM14_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM14"
#endif
#if GD32_ICU_USE_TIM15 && !defined(GD32_TIM15_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM15_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM15"
#endif
#if GD32_ICU_USE_TIM20 && !defined(GD32_TIM20_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM20_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM20"
#endif
#if GD32_ICU_USE_TIM21 && !defined(GD32_TIM21_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM21_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM21"
#endif
#if GD32_ICU_USE_TIM22 && !defined(GD32_TIM22_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_ICU_TIM22_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM22"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@ -719,12 +307,12 @@ typedef struct {
* @note The value of this field should normally be equal to zero.
* @note Only the DMA-related bits can be specified in this field.
*/
uint32_t dier;
uint32_t dmainten;
/**
* @brief TIM ARR register initialization data.
* @note The value of this field should normally be equal to 0xFFFFFFFFU.
*/
uint32_t arr;
uint32_t car;
} ICUConfig;
/**
@ -826,50 +414,6 @@ extern ICUDriver ICUD4;
extern ICUDriver ICUD5;
#endif
#if GD32_ICU_USE_TIM8 && !defined(__DOXYGEN__)
extern ICUDriver ICUD8;
#endif
#if GD32_ICU_USE_TIM9 && !defined(__DOXYGEN__)
extern ICUDriver ICUD9;
#endif
#if GD32_ICU_USE_TIM10 && !defined(__DOXYGEN__)
extern ICUDriver ICUD10;
#endif
#if GD32_ICU_USE_TIM11 && !defined(__DOXYGEN__)
extern ICUDriver ICUD11;
#endif
#if GD32_ICU_USE_TIM12 && !defined(__DOXYGEN__)
extern ICUDriver ICUD12;
#endif
#if GD32_ICU_USE_TIM13 && !defined(__DOXYGEN__)
extern ICUDriver ICUD13;
#endif
#if GD32_ICU_USE_TIM14 && !defined(__DOXYGEN__)
extern ICUDriver ICUD14;
#endif
#if GD32_ICU_USE_TIM15 && !defined(__DOXYGEN__)
extern ICUDriver ICUD15;
#endif
#if GD32_ICU_USE_TIM20 && !defined(__DOXYGEN__)
extern ICUDriver ICUD20;
#endif
#if GD32_ICU_USE_TIM21 && !defined(__DOXYGEN__)
extern ICUDriver ICUD21;
#endif
#if GD32_ICU_USE_TIM22 && !defined(__DOXYGEN__)
extern ICUDriver ICUD22;
#endif
#ifdef __cplusplus
extern "C" {
#endif

571
os/hal/ports/GD/GD32VF103/TIM/hal_pwm_lld.c
View File

@ -74,110 +74,6 @@ PWMDriver PWMD4;
PWMDriver PWMD5;
#endif
/**
* @brief PWMD8 driver identifier.
* @note The driver PWMD8 allocates the timer TIM8 when enabled.
*/
#if GD32_PWM_USE_TIM8 || defined(__DOXYGEN__)
PWMDriver PWMD8;
#endif
/**
* @brief PWMD9 driver identifier.
* @note The driver PWMD9 allocates the timer TIM9 when enabled.
*/
#if GD32_PWM_USE_TIM9 || defined(__DOXYGEN__)
PWMDriver PWMD9;
#endif
/**
* @brief PWMD10 driver identifier.
* @note The driver PWMD10 allocates the timer TIM10 when enabled.
*/
#if GD32_PWM_USE_TIM10 || defined(__DOXYGEN__)
PWMDriver PWMD10;
#endif
/**
* @brief PWMD11 driver identifier.
* @note The driver PWMD11 allocates the timer TIM11 when enabled.
*/
#if GD32_PWM_USE_TIM11 || defined(__DOXYGEN__)
PWMDriver PWMD11;
#endif
/**
* @brief PWMD12 driver identifier.
* @note The driver PWMD12 allocates the timer TIM12 when enabled.
*/
#if GD32_PWM_USE_TIM12 || defined(__DOXYGEN__)
PWMDriver PWMD12;
#endif
/**
* @brief PWMD13 driver identifier.
* @note The driver PWMD13 allocates the timer TIM13 when enabled.
*/
#if GD32_PWM_USE_TIM13 || defined(__DOXYGEN__)
PWMDriver PWMD13;
#endif
/**
* @brief PWMD14 driver identifier.
* @note The driver PWMD14 allocates the timer TIM14 when enabled.
*/
#if GD32_PWM_USE_TIM14 || defined(__DOXYGEN__)
PWMDriver PWMD14;
#endif
/**
* @brief PWMD15 driver identifier.
* @note The driver PWMD15 allocates the timer TIM15 when enabled.
*/
#if GD32_PWM_USE_TIM15 || defined(__DOXYGEN__)
PWMDriver PWMD15;
#endif
/**
* @brief PWMD16 driver identifier.
* @note The driver PWMD16 allocates the timer TIM16 when enabled.
*/
#if GD32_PWM_USE_TIM16 || defined(__DOXYGEN__)
PWMDriver PWMD16;
#endif
/**
* @brief PWMD17 driver identifier.
* @note The driver PWMD17 allocates the timer TIM17 when enabled.
*/
#if GD32_PWM_USE_TIM17 || defined(__DOXYGEN__)
PWMDriver PWMD17;
#endif
/**
* @brief PWMD20 driver identifier.
* @note The driver PWMD20 allocates the timer TIM20 when enabled.
*/
#if GD32_PWM_USE_TIM20 || defined(__DOXYGEN__)
PWMDriver PWMD20;
#endif
/**
* @brief PWMD21 driver identifier.
* @note The driver PWMD21 allocates the timer TIM21 when enabled.
*/
#if GD32_PWM_USE_TIM21 || defined(__DOXYGEN__)
PWMDriver PWMD21;
#endif
/**
* @brief PWMD22 driver identifier.
* @note The driver PWMD22 allocates the timer TIM22 when enabled.
*/
#if GD32_PWM_USE_TIM22 || defined(__DOXYGEN__)
PWMDriver PWMD22;
#endif
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@ -318,122 +214,6 @@ OSAL_IRQ_HANDLER(GD32_TIM5_HANDLER) {
#endif /* !defined(GD32_TIM5_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM5 */
#if GD32_PWM_USE_TIM8 || defined(__DOXYGEN__)
#if !defined(GD32_TIM8_SUPPRESS_ISR)
#if !defined(GD32_TIM8_UP_HANDLER)
#error "GD32_TIM8_UP_HANDLER not defined"
#endif
/**
* @brief TIM8 update interrupt handler.
* @note It is assumed that this interrupt is only activated if the callback
* pointer is not equal to @p NULL in order to not perform an extra
* check in a potentially critical interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM8_UP_HANDLER) {
OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD8);
OSAL_IRQ_EPILOGUE();
}
#if !defined(GD32_TIM8_CC_HANDLER)
#error "GD32_TIM8_CC_HANDLER not defined"
#endif
/**
* @brief TIM8 compare interrupt handler.
* @note It is assumed that the various sources are only activated if the
* associated callback pointer is not equal to @p NULL in order to not
* perform an extra check in a potentially critical interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_TIM8_CC_HANDLER) {
OSAL_IRQ_PROLOGUE();
pwm_lld_serve_interrupt(&PWMD8);
OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(GD32_TIM8_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM8 */
#if GD32_PWM_USE_TIM9 || defined(__DOXYGEN__)
#if !defined(GD32_TIM9_SUPPRESS_ISR)
#error "TIM9 ISR not defined by platform"
#endif /* !defined(GD32_TIM9_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM9 */
#if GD32_PWM_USE_TIM10 || defined(__DOXYGEN__)
#if !defined(GD32_TIM10_SUPPRESS_ISR)
#error "TIM10 ISR not defined by platform"
#endif /* !defined(GD32_TIM10_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM10 */
#if GD32_PWM_USE_TIM11 || defined(__DOXYGEN__)
#if !defined(GD32_TIM11_SUPPRESS_ISR)
#error "TIM11 ISR not defined by platform"
#endif /* !defined(GD32_TIM11_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM11 */
#if GD32_PWM_USE_TIM12 || defined(__DOXYGEN__)
#if !defined(GD32_TIM12_SUPPRESS_ISR)
#error "TIM12 ISR not defined by platform"
#endif /* !defined(GD32_TIM12_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM12 */
#if GD32_PWM_USE_TIM13 || defined(__DOXYGEN__)
#if !defined(GD32_TIM13_SUPPRESS_ISR)
#error "TIM13 ISR not defined by platform"
#endif /* !defined(GD32_TIM13_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM13 */
#if GD32_PWM_USE_TIM14 || defined(__DOXYGEN__)
#if !defined(GD32_TIM14_SUPPRESS_ISR)
#error "TIM14 ISR not defined by platform"
#endif /* !defined(GD32_TIM14_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM14 */
#if GD32_PWM_USE_TIM15 || defined(__DOXYGEN__)
#if !defined(GD32_TIM15_SUPPRESS_ISR)
#error "TIM15 ISR not defined by platform"
#endif /* !defined(GD32_TIM15_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM15 */
#if GD32_PWM_USE_TIM16 || defined(__DOXYGEN__)
#if !defined(GD32_TIM16_SUPPRESS_ISR)
#error "TIM16 ISR not defined by platform"
#endif /* !defined(GD32_TIM16_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM16 */
#if GD32_PWM_USE_TIM17 || defined(__DOXYGEN__)
#if !defined(GD32_TIM17_SUPPRESS_ISR)
#error "TIM17 ISR not defined by platform"
#endif /* !defined(GD32_TIM17_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM17 */
#if GD32_PWM_USE_TIM20 || defined(__DOXYGEN__)
#if !defined(GD32_TIM20_SUPPRESS_ISR)
#error "TIM20 ISR not defined by platform"
#endif /* !defined(GD32_TIM20_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM20 */
#if GD32_PWM_USE_TIM21 || defined(__DOXYGEN__)
#if !defined(GD32_TIM21_SUPPRESS_ISR)
#error "TIM21 ISR not defined by platform"
#endif /* !defined(GD32_TIM21_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM21 */
#if GD32_PWM_USE_TIM22 || defined(__DOXYGEN__)
#if !defined(GD32_TIM22_SUPPRESS_ISR)
#error "TIM22 ISR not defined by platform"
#endif /* !defined(GD32_TIM22_SUPPRESS_ISR) */
#endif /* GD32_PWM_USE_TIM22 */
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@ -479,97 +259,6 @@ void pwm_lld_init(void) {
PWMD5.channels = GD32_TIM5_CHANNELS;
PWMD5.tim = GD32_TIM5;
#endif
#if GD32_PWM_USE_TIM8
/* Driver initialization.*/
pwmObjectInit(&PWMD8);
PWMD8.channels = GD32_TIM8_CHANNELS;
PWMD8.tim = GD32_TIM8;
#endif
#if GD32_PWM_USE_TIM9
/* Driver initialization.*/
pwmObjectInit(&PWMD9);
PWMD9.channels = GD32_TIM9_CHANNELS;
PWMD9.tim = GD32_TIM9;
#endif
#if GD32_PWM_USE_TIM10
/* Driver initialization.*/
pwmObjectInit(&PWMD10);
PWMD10.channels = GD32_TIM10_CHANNELS;
PWMD10.tim = GD32_TIM10;
#endif
#if GD32_PWM_USE_TIM11
/* Driver initialization.*/
pwmObjectInit(&PWMD11);
PWMD11.channels = GD32_TIM11_CHANNELS;
PWMD11.tim = GD32_TIM11;
#endif
#if GD32_PWM_USE_TIM12
/* Driver initialization.*/
pwmObjectInit(&PWMD12);
PWMD12.channels = GD32_TIM12_CHANNELS;
PWMD12.tim = GD32_TIM12;
#endif
#if GD32_PWM_USE_TIM13
/* Driver initialization.*/
pwmObjectInit(&PWMD13);
PWMD13.channels = GD32_TIM13_CHANNELS;
PWMD13.tim = GD32_TIM13;
#endif
#if GD32_PWM_USE_TIM14
/* Driver initialization.*/
pwmObjectInit(&PWMD14);
PWMD14.channels = GD32_TIM14_CHANNELS;
PWMD14.tim = GD32_TIM14;
#endif
#if GD32_PWM_USE_TIM15
/* Driver initialization.*/
pwmObjectInit(&PWMD15);
PWMD15.channels = GD32_TIM15_CHANNELS;
PWMD15.tim = GD32_TIM15;
#endif
#if GD32_PWM_USE_TIM16
/* Driver initialization.*/
pwmObjectInit(&PWMD16);
PWMD16.channels = GD32_TIM16_CHANNELS;
PWMD16.tim = GD32_TIM16;
#endif
#if GD32_PWM_USE_TIM17
/* Driver initialization.*/
pwmObjectInit(&PWMD17);
PWMD17.channels = GD32_TIM17_CHANNELS;
PWMD17.tim = GD32_TIM17;
#endif
#if GD32_PWM_USE_TIM20
/* Driver initialization.*/
pwmObjectInit(&PWMD20);
PWMD20.channels = GD32_TIM20_CHANNELS;
PWMD20.tim = GD32_TIM20;
#endif
#if GD32_PWM_USE_TIM21
/* Driver initialization.*/
pwmObjectInit(&PWMD21);
PWMD21.channels = GD32_TIM21_CHANNELS;
PWMD21.tim = GD32_TIM21;
#endif
#if GD32_PWM_USE_TIM22
/* Driver initialization.*/
pwmObjectInit(&PWMD22);
PWMD22.channels = GD32_TIM22_CHANNELS;
PWMD22.tim = GD32_TIM22;
#endif
}
/**
@ -663,166 +352,6 @@ void pwm_lld_start(PWMDriver *pwmp) {
}
#endif
#if GD32_PWM_USE_TIM8
if (&PWMD8 == pwmp) {
rccEnableTIM8(true);
rccResetTIM8();
#if !defined(GD32_TIM8_SUPPRESS_ISR)
eclicEnableVector(GD32_TIM8_UP_NUMBER, GD32_PWM_TIM8_IRQ_PRIORITY, GD32_PWM_TIM8_IRQ_TRIGGER);
eclicEnableVector(GD32_TIM8_CC_NUMBER, GD32_PWM_TIM8_IRQ_PRIORITY, GD32_PWM_TIM8_IRQ_TRIGGER);
#endif
#if defined(GD32_TIM8CLK)
pwmp->clock = GD32_TIM8CLK;
#else
pwmp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_PWM_USE_TIM9
if (&PWMD9 == pwmp) {
rccEnableTIM9(true);
rccResetTIM9();
#if defined(GD32_TIM9CLK)
pwmp->clock = GD32_TIM9CLK;
#else
pwmp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_PWM_USE_TIM10
if (&PWMD10 == pwmp) {
rccEnableTIM10(true);
rccResetTIM10();
#if defined(GD32_TIM10CLK)
pwmp->clock = GD32_TIM10CLK;
#else
pwmp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_PWM_USE_TIM11
if (&PWMD11 == pwmp) {
rccEnableTIM11(true);
rccResetTIM11();
#if defined(GD32_TIM11CLK)
pwmp->clock = GD32_TIM11CLK;
#else
pwmp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_PWM_USE_TIM12
if (&PWMD12 == pwmp) {
rccEnableTIM12(true);
rccResetTIM12();
#if defined(GD32_TIM12CLK)
pwmp->clock = GD32_TIM12CLK;
#else
pwmp->clock = GD32_TIMCLK1;
#endif
}
#endif
#if GD32_PWM_USE_TIM13
if (&PWMD13 == pwmp) {
rccEnableTIM13(true);
rccResetTIM13();
#if defined(GD32_TIM13CLK)
pwmp->clock = GD32_TIM13CLK;
#else
pwmp->clock = GD32_TIMCLK1;
#endif
}
#endif
#if GD32_PWM_USE_TIM14
if (&PWMD14 == pwmp) {
rccEnableTIM14(true);
rccResetTIM14();
#if defined(GD32_TIM14CLK)
pwmp->clock = GD32_TIM14CLK;
#else
pwmp->clock = GD32_TIMCLK1;
#endif
}
#endif
#if GD32_PWM_USE_TIM15
if (&PWMD15 == pwmp) {
rccEnableTIM15(true);
rccResetTIM15();
#if defined(GD32_TIM15CLK)
pwmp->clock = GD32_TIM15CLK;
#else
pwmp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_PWM_USE_TIM16
if (&PWMD16 == pwmp) {
rccEnableTIM16(true);
rccResetTIM16();
#if defined(GD32_TIM16CLK)
pwmp->clock = GD32_TIM16CLK;
#else
pwmp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_PWM_USE_TIM17
if (&PWMD17 == pwmp) {
rccEnableTIM17(true);
rccResetTIM17();
#if defined(GD32_TIM17CLK)
pwmp->clock = GD32_TIM17CLK;
#else
pwmp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_PWM_USE_TIM20
if (&PWMD20 == pwmp) {
rccEnableTIM20(true);
rccResetTIM20();
#if defined(GD32_TIM20CLK)
pwmp->clock = GD32_TIM20CLK;
#else
pwmp->clock = GD32_TIMCLK2;
#endif
}
#endif
#if GD32_PWM_USE_TIM21
if (&PWMD21 == pwmp) {
rccEnableTIM21(true);
rccResetTIM21();
#if defined(GD32_TIM21CLK)
pwmp->clock = GD32_TIM21CLK;
#else
pwmp->clock = GD32_TIMCLK1;
#endif
}
#endif
#if GD32_PWM_USE_TIM22
if (&PWMD22 == pwmp) {
rccEnableTIM22(true);
rccResetTIM22();
#if defined(GD32_TIM22CLK)
pwmp->clock = GD32_TIM22CLK;
#else
pwmp->clock = GD32_TIMCLK1;
#endif
}
#endif
/* All channels configured in PWM1 mode with preload enabled and will
stay that way until the driver is stopped.*/
pwmp->tim->CHCTL0 = GD32_TIM_CCMR1_OC1M(6) | GD32_TIM_CCMR1_OC1PE |
@ -892,25 +421,25 @@ void pwm_lld_start(PWMDriver *pwmp) {
;
}
#if GD32_PWM_USE_ADVANCED
#if GD32_PWM_USE_TIM1 && !GD32_PWM_USE_TIM8 && !GD32_PWM_USE_TIM20
#if GD32_PWM_USE_TIM1
if (&PWMD1 == pwmp) {
#endif
#if !GD32_PWM_USE_TIM1 && GD32_PWM_USE_TIM8 && !GD32_PWM_USE_TIM20
#if !GD32_PWM_USE_TIM1
if (&PWMD8 == pwmp) {
#endif
#if GD32_PWM_USE_TIM1 && GD32_PWM_USE_TIM8 && !GD32_PWM_USE_TIM20
#if GD32_PWM_USE_TIM1
if ((&PWMD1 == pwmp) || (&PWMD8 == pwmp)) {
#endif
#if !GD32_PWM_USE_TIM1 && !GD32_PWM_USE_TIM8 && GD32_PWM_USE_TIM20
#if !GD32_PWM_USE_TIM1
if (&PWMD20 == pwmp) {
#endif
#if GD32_PWM_USE_TIM1 && !GD32_PWM_USE_TIM8 && GD32_PWM_USE_TIM20
#if GD32_PWM_USE_TIM1
if ((&PWMD1 == pwmp) || (&PWMD20 == pwmp)) {
#endif
#if !GD32_PWM_USE_TIM1 && GD32_PWM_USE_TIM8 && GD32_PWM_USE_TIM20
#if !GD32_PWM_USE_TIM1
if ((&PWMD8 == pwmp) || (&PWMD20 == pwmp)) {
#endif
#if GD32_PWM_USE_TIM1 && GD32_PWM_USE_TIM8 && GD32_PWM_USE_TIM20
#if GD32_PWM_USE_TIM1
if ((&PWMD1 == pwmp) || (&PWMD8 == pwmp) || (&PWMD20 == pwmp)) {
#endif
switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
@ -961,7 +490,7 @@ void pwm_lld_start(PWMDriver *pwmp) {
pwmp->tim->INTF = 0; /* Clear pending IRQs. */
pwmp->tim->DMAINTEN = pwmp->config->dmainten & /* DMA-related DIER settings. */
~GD32_TIM_DIER_IRQ_MASK;
#if GD32_PWM_USE_TIM1 || GD32_PWM_USE_TIM8 || GD32_PWM_USE_TIM20
#if GD32_PWM_USE_TIM1
#if GD32_PWM_USE_ADVANCED
pwmp->tim->CCHP = pwmp->config->cchp | GD32_TIM_BDTR_MOE;
#else
@ -987,7 +516,7 @@ void pwm_lld_stop(PWMDriver *pwmp) {
pwmp->tim->CTL0 = 0; /* Timer disabled. */
pwmp->tim->DMAINTEN = 0; /* All IRQs disabled. */
pwmp->tim->INTF = 0; /* Clear eventual pending IRQs. */
#if GD32_PWM_USE_TIM1 || GD32_PWM_USE_TIM8 || GD32_PWM_USE_TIM20
#if GD32_PWM_USE_TIM1
pwmp->tim->CCHP = 0;
#endif
@ -1036,88 +565,6 @@ void pwm_lld_stop(PWMDriver *pwmp) {
rccDisableTIM5();
}
#endif
#if GD32_PWM_USE_TIM8
if (&PWMD8 == pwmp) {
#if !defined(GD32_TIM8_SUPPRESS_ISR)
eclicDisableVector(GD32_TIM8_UP_NUMBER);
eclicDisableVector(GD32_TIM8_CC_NUMBER);
#endif
rccDisableTIM8();
}
#endif
#if GD32_PWM_USE_TIM9
if (&PWMD9 == pwmp) {
rccDisableTIM9();
}
#endif
#if GD32_PWM_USE_TIM10
if (&PWMD10 == pwmp) {
rccDisableTIM10();
}
#endif
#if GD32_PWM_USE_TIM11
if (&PWMD11 == pwmp) {
rccDisableTIM11();
}
#endif
#if GD32_PWM_USE_TIM12
if (&PWMD12 == pwmp) {
rccDisableTIM12();
}
#endif
#if GD32_PWM_USE_TIM13
if (&PWMD13 == pwmp) {
rccDisableTIM13();
}
#endif
#if GD32_PWM_USE_TIM14
if (&PWMD14 == pwmp) {
rccDisableTIM14();
}
#endif
#if GD32_PWM_USE_TIM15
if (&PWMD15 == pwmp) {
rccDisableTIM15();
}
#endif
#if GD32_PWM_USE_TIM16
if (&PWMD16 == pwmp) {
rccDisableTIM16();
}
#endif
#if GD32_PWM_USE_TIM17
if (&PWMD17 == pwmp) {
rccDisableTIM17();
}
#endif
#if GD32_PWM_USE_TIM20
if (&PWMD20 == pwmp) {
rccDisableTIM20();
}
#endif
#if GD32_PWM_USE_TIM21
if (&PWMD21 == pwmp) {
rccDisableTIM21();
}
#endif
#if GD32_PWM_USE_TIM22
if (&PWMD22 == pwmp) {
rccDisableTIM22();
}
#endif
}
}

544
os/hal/ports/GD/GD32VF103/TIM/hal_pwm_lld.h
View File

@ -136,123 +136,6 @@
#define GD32_PWM_USE_TIM5 FALSE
#endif
/**
* @brief PWMD8 driver enable switch.
* @details If set to @p TRUE the support for PWMD8 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_PWM_USE_TIM8) || defined(__DOXYGEN__)
#define GD32_PWM_USE_TIM8 FALSE
#endif
/**
* @brief PWMD9 driver enable switch.
* @details If set to @p TRUE the support for PWMD9 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_PWM_USE_TIM9) || defined(__DOXYGEN__)
#define GD32_PWM_USE_TIM9 FALSE
#endif
/**
* @brief PWMD10 driver enable switch.
* @details If set to @p TRUE the support for PWMD10 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_PWM_USE_TIM10) || defined(__DOXYGEN__)
#define GD32_PWM_USE_TIM10 FALSE
#endif
/**
* @brief PWMD11 driver enable switch.
* @details If set to @p TRUE the support for PWMD11 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_PWM_USE_TIM11) || defined(__DOXYGEN__)
#define GD32_PWM_USE_TIM11 FALSE
#endif
/**
* @brief PWMD12 driver enable switch.
* @details If set to @p TRUE the support for PWMD12 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_PWM_USE_TIM12) || defined(__DOXYGEN__)
#define GD32_PWM_USE_TIM12 FALSE
#endif
/**
* @brief PWMD13 driver enable switch.
* @details If set to @p TRUE the support for PWMD13 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_PWM_USE_TIM13) || defined(__DOXYGEN__)
#define GD32_PWM_USE_TIM13 FALSE
#endif
/**
* @brief PWMD14 driver enable switch.
* @details If set to @p TRUE the support for PWMD14 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_PWM_USE_TIM14) || defined(__DOXYGEN__)
#define GD32_PWM_USE_TIM14 FALSE
#endif
/**
* @brief PWMD15 driver enable switch.
* @details If set to @p TRUE the support for PWMD15 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_PWM_USE_TIM15) || defined(__DOXYGEN__)
#define GD32_PWM_USE_TIM15 FALSE
#endif
/**
* @brief PWMD16 driver enable switch.
* @details If set to @p TRUE the support for PWMD16 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_PWM_USE_TIM16) || defined(__DOXYGEN__)
#define GD32_PWM_USE_TIM16 FALSE
#endif
/**
* @brief PWMD17 driver enable switch.
* @details If set to @p TRUE the support for PWMD17 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_PWM_USE_TIM17) || defined(__DOXYGEN__)
#define GD32_PWM_USE_TIM17 FALSE
#endif
/**
* @brief PWMD20 driver enable switch.
* @details If set to @p TRUE the support for PWMD20 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_PWM_USE_TIM20) || defined(__DOXYGEN__)
#define GD32_PWM_USE_TIM20 FALSE
#endif
/**
* @brief PWMD21 driver enable switch.
* @details If set to @p TRUE the support for PWMD21 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_PWM_USE_TIM21) || defined(__DOXYGEN__)
#define GD32_PWM_USE_TIM21 FALSE
#endif
/**
* @brief PWMD22 driver enable switch.
* @details If set to @p TRUE the support for PWMD22 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_PWM_USE_TIM22) || defined(__DOXYGEN__)
#define GD32_PWM_USE_TIM22 FALSE
#endif
/**
* @brief PWMD1 interrupt priority level setting.
*/
@ -287,97 +170,6 @@
#if !defined(GD32_PWM_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM5_IRQ_PRIORITY 7
#endif
/**
* @brief PWMD8 interrupt priority level setting.
*/
#if !defined(GD32_PWM_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM8_IRQ_PRIORITY 7
#endif
/**
* @brief PWMD9 interrupt priority level setting.
*/
#if !defined(GD32_PWM_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM9_IRQ_PRIORITY 7
#endif
/**
* @brief PWMD10 interrupt priority level setting.
*/
#if !defined(GD32_PWM_TIM10_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM10_IRQ_PRIORITY 7
#endif
/**
* @brief PWMD11 interrupt priority level setting.
*/
#if !defined(GD32_PWM_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM11_IRQ_PRIORITY 7
#endif
/**
* @brief PWMD12 interrupt priority level setting.
*/
#if !defined(GD32_PWM_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM12_IRQ_PRIORITY 7
#endif
/**
* @brief PWMD13 interrupt priority level setting.
*/
#if !defined(GD32_PWM_TIM13_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM13_IRQ_PRIORITY 7
#endif
/**
* @brief PWMD14 interrupt priority level setting.
*/
#if !defined(GD32_PWM_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM14_IRQ_PRIORITY 7
#endif
/**
* @brief PWMD15 interrupt priority level setting.
*/
#if !defined(GD32_PWM_TIM15_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM15_IRQ_PRIORITY 7
#endif
/**
* @brief PWMD16 interrupt priority level setting.
*/
#if !defined(GD32_PWM_TIM16_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM16_IRQ_PRIORITY 7
#endif
/**
* @brief PWMD17 interrupt priority level setting.
*/
#if !defined(GD32_PWM_TIM17_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM17_IRQ_PRIORITY 7
#endif
/**
* @brief PWMD20 interrupt priority level setting.
*/
#if !defined(GD32_PWM_TIM20_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM20_IRQ_PRIORITY 7
#endif
/**
* @brief PWMD21 interrupt priority level setting.
*/
#if !defined(GD32_PWM_TIM21_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM21_IRQ_PRIORITY 7
#endif
/**
* @brief PWMD22 interrupt priority level setting.
*/
#if !defined(GD32_PWM_TIM22_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_PWM_TIM22_IRQ_PRIORITY 7
#endif
/** @} */
/*===========================================================================*/
@ -404,58 +196,6 @@
#define GD32_HAS_TIM5 FALSE
#endif
#if !defined(GD32_HAS_TIM8)
#define GD32_HAS_TIM8 FALSE
#endif
#if !defined(GD32_HAS_TIM9)
#define GD32_HAS_TIM9 FALSE
#endif
#if !defined(GD32_HAS_TIM10)
#define GD32_HAS_TIM10 FALSE
#endif
#if !defined(GD32_HAS_TIM11)
#define GD32_HAS_TIM11 FALSE
#endif
#if !defined(GD32_HAS_TIM12)
#define GD32_HAS_TIM12 FALSE
#endif
#if !defined(GD32_HAS_TIM13)
#define GD32_HAS_TIM13 FALSE
#endif
#if !defined(GD32_HAS_TIM14)
#define GD32_HAS_TIM14 FALSE
#endif
#if !defined(GD32_HAS_TIM15)
#define GD32_HAS_TIM15 FALSE
#endif
#if !defined(GD32_HAS_TIM16)
#define GD32_HAS_TIM16 FALSE
#endif
#if !defined(GD32_HAS_TIM17)
#define GD32_HAS_TIM17 FALSE
#endif
#if !defined(GD32_HAS_TIM20)
#define GD32_HAS_TIM20 FALSE
#endif
#if !defined(GD32_HAS_TIM21)
#define GD32_HAS_TIM21 FALSE
#endif
#if !defined(GD32_HAS_TIM22)
#define GD32_HAS_TIM22 FALSE
#endif
#if GD32_PWM_USE_TIM1 && !GD32_HAS_TIM1
#error "TIM1 not present in the selected device"
#endif
@ -476,72 +216,13 @@
#error "TIM5 not present in the selected device"
#endif
#if GD32_PWM_USE_TIM8 && !GD32_HAS_TIM8
#error "TIM8 not present in the selected device"
#endif
#if GD32_PWM_USE_TIM9 && !GD32_HAS_TIM9
#error "TIM9 not present in the selected device"
#endif
#if GD32_PWM_USE_TIM10 && !GD32_HAS_TIM10
#error "TIM10 not present in the selected device"
#endif
#if GD32_PWM_USE_TIM11 && !GD32_HAS_TIM11
#error "TIM11 not present in the selected device"
#endif
#if GD32_PWM_USE_TIM12 && !GD32_HAS_TIM12
#error "TIM12 not present in the selected device"
#endif
#if GD32_PWM_USE_TIM13 && !GD32_HAS_TIM13
#error "TIM13 not present in the selected device"
#endif
#if GD32_PWM_USE_TIM14 && !GD32_HAS_TIM14
#error "TIM14 not present in the selected device"
#endif
#if GD32_PWM_USE_TIM15 && !GD32_HAS_TIM15
#error "TIM15 not present in the selected device"
#endif
#if GD32_PWM_USE_TIM16 && !GD32_HAS_TIM16
#error "TIM16 not present in the selected device"
#endif
#if GD32_PWM_USE_TIM17 && !GD32_HAS_TIM17
#error "TIM17 not present in the selected device"
#endif
#if GD32_PWM_USE_TIM20 && !GD32_HAS_TIM20
#error "TIM20 not present in the selected device"
#endif
#if GD32_PWM_USE_TIM21 && !GD32_HAS_TIM21
#error "TIM21 not present in the selected device"
#endif
#if GD32_PWM_USE_TIM22 && !GD32_HAS_TIM22
#error "TIM22 not present in the selected device"
#endif
#if !GD32_PWM_USE_TIM1 && !GD32_PWM_USE_TIM2 && \
!GD32_PWM_USE_TIM3 && !GD32_PWM_USE_TIM4 && \
!GD32_PWM_USE_TIM5 && !GD32_PWM_USE_TIM8 && \
!GD32_PWM_USE_TIM9 && !GD32_PWM_USE_TIM10 && \
!GD32_PWM_USE_TIM11 && !GD32_PWM_USE_TIM11 && \
!GD32_PWM_USE_TIM13 && !GD32_PWM_USE_TIM13 && \
!GD32_PWM_USE_TIM15 && !GD32_PWM_USE_TIM15 && \
!GD32_PWM_USE_TIM17 && !GD32_PWM_USE_TIM20 && \
!GD32_PWM_USE_TIM21 && !GD32_PWM_USE_TIM22
!GD32_PWM_USE_TIM5
#error "PWM driver activated but no TIM peripheral assigned"
#endif
#if GD32_PWM_USE_ADVANCED && !GD32_PWM_USE_TIM1 && !GD32_PWM_USE_TIM8 && \
!GD32_PWM_USE_TIM20
#if GD32_PWM_USE_ADVANCED && !GD32_PWM_USE_TIM1
#error "advanced mode selected but no advanced timer assigned"
#endif
@ -586,110 +267,6 @@
#endif
#endif
#if GD32_PWM_USE_TIM8
#if defined(GD32_TIM8_IS_USED)
#error "PWMD8 requires TIM8 but the timer is already used"
#else
#define GD32_TIM8_IS_USED
#endif
#endif
#if GD32_PWM_USE_TIM9
#if defined(GD32_TIM9_IS_USED)
#error "PWMD9 requires TIM9 but the timer is already used"
#else
#define GD32_TIM9_IS_USED
#endif
#endif
#if GD32_PWM_USE_TIM10
#if defined(GD32_TIM10_IS_USED)
#error "PWMD10 requires TIM10 but the timer is already used"
#else
#define GD32_TIM10_IS_USED
#endif
#endif
#if GD32_PWM_USE_TIM11
#if defined(GD32_TIM11_IS_USED)
#error "PWMD11 requires TIM11 but the timer is already used"
#else
#define GD32_TIM11_IS_USED
#endif
#endif
#if GD32_PWM_USE_TIM12
#if defined(GD32_TIM12_IS_USED)
#error "PWMD12 requires TIM12 but the timer is already used"
#else
#define GD32_TIM12_IS_USED
#endif
#endif
#if GD32_PWM_USE_TIM13
#if defined(GD32_TIM13_IS_USED)
#error "PWMD13 requires TIM13 but the timer is already used"
#else
#define GD32_TIM13_IS_USED
#endif
#endif
#if GD32_PWM_USE_TIM14
#if defined(GD32_TIM14_IS_USED)
#error "PWMD14 requires TIM14 but the timer is already used"
#else
#define GD32_TIM14_IS_USED
#endif
#endif
#if GD32_PWM_USE_TIM15
#if defined(GD32_TIM15_IS_USED)
#error "PWMD15 requires TIM15 but the timer is already used"
#else
#define GD32_TIM15_IS_USED
#endif
#endif
#if GD32_PWM_USE_TIM16
#if defined(GD32_TIM16_IS_USED)
#error "PWMD16 requires TIM16 but the timer is already used"
#else
#define GD32_TIM16_IS_USED
#endif
#endif
#if GD32_PWM_USE_TIM17
#if defined(GD32_TIM17_IS_USED)
#error "PWMD17 requires TIM17 but the timer is already used"
#else
#define GD32_TIM17_IS_USED
#endif
#endif
#if GD32_PWM_USE_TIM20
#if defined(GD32_TIM20_IS_USED)
#error "PWMD20 requires TIM20 but the timer is already used"
#else
#define GD32_TIM20_IS_USED
#endif
#endif
#if GD32_PWM_USE_TIM21
#if defined(GD32_TIM21_IS_USED)
#error "PWMD21 requires TIM21 but the timer is already used"
#else
#define GD32_TIM21_IS_USED
#endif
#endif
#if GD32_PWM_USE_TIM22
#if defined(GD32_TIM22_IS_USED)
#error "PWMD22 requires TIM22 but the timer is already used"
#else
#define GD32_TIM22_IS_USED
#endif
#endif
/* IRQ priority checks.*/
#if GD32_PWM_USE_TIM1 && !defined(GD32_TIM1_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM1_IRQ_PRIORITY)
@ -716,71 +293,6 @@
#error "Invalid IRQ priority assigned to TIM5"
#endif
#if GD32_PWM_USE_TIM8 && !defined(GD32_TIM8_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM8_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM8"
#endif
#if GD32_PWM_USE_TIM9 && !defined(GD32_TIM9_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM9_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM9"
#endif
#if GD32_PWM_USE_TIM10 && !defined(GD32_TIM10_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM10_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM10"
#endif
#if GD32_PWM_USE_TIM11 && !defined(GD32_TIM11_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM11_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM11"
#endif
#if GD32_PWM_USE_TIM12 && !defined(GD32_TIM12_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM12_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM12"
#endif
#if GD32_PWM_USE_TIM13 && !defined(GD32_TIM13_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM13_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM13"
#endif
#if GD32_PWM_USE_TIM14 && !defined(GD32_TIM14_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM14_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM14"
#endif
#if GD32_PWM_USE_TIM15 && !defined(GD32_TIM15_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM15_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM15"
#endif
#if GD32_PWM_USE_TIM16 && !defined(GD32_TIM16_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM16_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM16"
#endif
#if GD32_PWM_USE_TIM17 && !defined(GD32_TIM17_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM17_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM17"
#endif
#if GD32_PWM_USE_TIM20 && !defined(GD32_TIM20_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM20_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM20"
#endif
#if GD32_PWM_USE_TIM21 && !defined(GD32_TIM21_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM21_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM21"
#endif
#if GD32_PWM_USE_TIM22 && !defined(GD32_TIM22_SUPPRESS_ISR) && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_PWM_TIM22_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM22"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@ -954,58 +466,6 @@ extern PWMDriver PWMD4;
extern PWMDriver PWMD5;
#endif
#if GD32_PWM_USE_TIM8 && !defined(__DOXYGEN__)
extern PWMDriver PWMD8;
#endif
#if GD32_PWM_USE_TIM9 && !defined(__DOXYGEN__)
extern PWMDriver PWMD9;
#endif
#if GD32_PWM_USE_TIM10 && !defined(__DOXYGEN__)
extern PWMDriver PWMD10;
#endif
#if GD32_PWM_USE_TIM11 && !defined(__DOXYGEN__)
extern PWMDriver PWMD11;
#endif
#if GD32_PWM_USE_TIM12 && !defined(__DOXYGEN__)
extern PWMDriver PWMD12;
#endif
#if GD32_PWM_USE_TIM13 && !defined(__DOXYGEN__)
extern PWMDriver PWMD13;
#endif
#if GD32_PWM_USE_TIM14 && !defined(__DOXYGEN__)
extern PWMDriver PWMD14;
#endif
#if GD32_PWM_USE_TIM15 && !defined(__DOXYGEN__)
extern PWMDriver PWMD15;
#endif
#if GD32_PWM_USE_TIM16 && !defined(__DOXYGEN__)
extern PWMDriver PWMD16;
#endif
#if GD32_PWM_USE_TIM17 && !defined(__DOXYGEN__)
extern PWMDriver PWMD17;
#endif
#if GD32_PWM_USE_TIM20 && !defined(__DOXYGEN__)
extern PWMDriver PWMD20;
#endif
#if GD32_PWM_USE_TIM21 && !defined(__DOXYGEN__)
extern PWMDriver PWMD21;
#endif
#if GD32_PWM_USE_TIM22 && !defined(__DOXYGEN__)
extern PWMDriver PWMD22;
#endif
#ifdef __cplusplus
extern "C" {
#endif

212
os/hal/ports/GD/GD32VF103/TIM/hal_st_lld.c
View File

@ -52,17 +52,7 @@
#define ST_NUMBER GD32_TIM2_NUMBER
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM2(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM2_STOP
#elif defined(STM32G0XX)
#define ST_ENABLE_STOP() DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM2_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM2
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM2_STOP
#endif
#elif GD32_ST_USE_TIMER == 3
@ -78,17 +68,7 @@
#define ST_NUMBER GD32_TIM3_NUMBER
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM3(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM3_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM3_STOP
#elif defined(STM32G0XX)
#define ST_ENABLE_STOP() DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM3_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM3
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM3_STOP
#endif
#elif GD32_ST_USE_TIMER == 4
@ -104,15 +84,7 @@
#define ST_NUMBER GD32_TIM4_NUMBER
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM4(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM4_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM4_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM4
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM4_STOP
#endif
#elif GD32_ST_USE_TIMER == 5
@ -128,191 +100,7 @@
#define ST_NUMBER GD32_TIM5_NUMBER
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM5(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM5_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM5_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM5
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM5_STOP
#endif
#elif GD32_ST_USE_TIMER == 9
#if !GD32_HAS_TIM9
#error "TIM9 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM9_IS_32BITS
#error "TIM9 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM9_HANDLER
#define ST_NUMBER GD32_TIM9_NUMBER
#define ST_CLOCK_SRC GD32_TIMCLK2
#define ST_ENABLE_CLOCK() rccEnableTIM9(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM9_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB2FZR1 |= DBGMCU_APB2FZR1_DBG_TIM9_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB2LFZ1 |= DBGMCU_APB2LFZ1_DBG_TIM9
#else
#define ST_ENABLE_STOP() DBGMCU->APB2FZ |= DBGMCU_APB2_FZ_DBG_TIM9_STOP
#endif
#elif GD32_ST_USE_TIMER == 10
#if !GD32_HAS_TIM10
#error "TIM10 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM10_IS_32BITS
#error "TIM10 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM10_HANDLER
#define ST_NUMBER GD32_TIM10_NUMBER
#define ST_CLOCK_SRC GD32_TIMCLK2
#define ST_ENABLE_CLOCK() rccEnableTIM10(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM10_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB2FZR1 |= DBGMCU_APB2FZR1_DBG_TIM10_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB2LFZ1 |= DBGMCU_APB2LFZ1_DBG_TIM10
#else
#define ST_ENABLE_STOP() DBGMCU->APB2FZ |= DBGMCU_APB2_FZ_DBG_TIM10_STOP
#endif
#elif GD32_ST_USE_TIMER == 11
#if !GD32_HAS_TIM11
#error "TIM11 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM11_IS_32BITS
#error "TIM11 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM11_HANDLER
#define ST_NUMBER GD32_TIM11_NUMBER
#define ST_CLOCK_SRC GD32_TIMCLK2
#define ST_ENABLE_CLOCK() rccEnableTIM11(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM11_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB2FZR1 |= DBGMCU_APB2FZR1_DBG_TIM11_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB2LFZ1 |= DBGMCU_APB2LFZ1_DBG_TIM11
#else
#define ST_ENABLE_STOP() DBGMCU->APB2FZ |= DBGMCU_APB2_FZ_DBG_TIM11_STOP
#endif
#elif GD32_ST_USE_TIMER == 12
#if !GD32_HAS_TIM12
#error "TIM12 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM12_IS_32BITS
#error "TIM12 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM12_HANDLER
#define ST_NUMBER GD32_TIM12_NUMBER
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM12(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM12_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM12_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM12
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM12_STOP
#endif
#elif GD32_ST_USE_TIMER == 13
#if !GD32_HAS_TIM13
#error "TIM13 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM13_IS_32BITS
#error "TIM13 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM13_HANDLER
#define ST_NUMBER GD32_TIM13_NUMBER
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM13(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM13_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM13_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM13
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM13_STOP
#endif
#elif GD32_ST_USE_TIMER == 14
#if !GD32_HAS_TIM14
#error "TIM14 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM14_IS_32BITS
#error "TIM14 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM14_HANDLER
#define ST_NUMBER GD32_TIM14_NUMBER
#define ST_CLOCK_SRC GD32_TIMCLK1
#define ST_ENABLE_CLOCK() rccEnableTIM14(true)
#if defined(STM32F1XX)
#define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM14_STOP
#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM14_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM14
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM14_STOP
#endif
#elif GD32_ST_USE_TIMER == 21
#if !GD32_HAS_TIM21
#error "TIM21 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM21_IS_32BITS
#error "TIM21 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM21_HANDLER
#define ST_NUMBER GD32_TIM21_NUMBER
#define ST_CLOCK_SRC GD32_TIMCLK2
#define ST_ENABLE_CLOCK() rccEnableTIM21(true)
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB2_FZ_DBG_TIM21_STOP
#elif GD32_ST_USE_TIMER == 22
#if !GD32_HAS_TIM22
#error "TIM22 not present in the selected device"
#endif
#if (OSAL_ST_RESOLUTION == 32) && !GD32_TIM22_IS_32BITS
#error "TIM21 is not a 32bits timer"
#endif
#define ST_HANDLER GD32_TIM22_HANDLER
#define ST_NUMBER GD32_TIM22_NUMBER
#define ST_CLOCK_SRC GD32_TIMCLK2
#define ST_ENABLE_CLOCK() rccEnableTIM22(true)
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB2_FZ_DBG_TIM21_STOP
#else
#error "GD32_ST_USE_TIMER specifies an unsupported timer"

274
os/hal/ports/GD/GD32VF103/TIM/hal_st_lld.h
View File

@ -81,38 +81,6 @@
#if !defined(GD32_HAS_TIM5)
#define GD32_HAS_TIM5 FALSE
#endif
#if !defined(GD32_HAS_TIM9)
#define GD32_HAS_TIM9 FALSE
#endif
#if !defined(GD32_HAS_TIM10)
#define GD32_HAS_TIM10 FALSE
#endif
#if !defined(GD32_HAS_TIM11)
#define GD32_HAS_TIM11 FALSE
#endif
#if !defined(GD32_HAS_TIM12)
#define GD32_HAS_TIM12 FALSE
#endif
#if !defined(GD32_HAS_TIM13)
#define GD32_HAS_TIM13 FALSE
#endif
#if !defined(GD32_HAS_TIM14)
#define GD32_HAS_TIM14 FALSE
#endif
#if !defined(GD32_HAS_TIM21)
#define GD32_HAS_TIM21 FALSE
#endif
#if !defined(GD32_HAS_TIM22)
#define GD32_HAS_TIM22 FALSE
#endif
/**/
#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
@ -228,231 +196,6 @@
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif GD32_ST_USE_TIMER == 9
#if defined(GD32_TIM9_IS_USED)
#error "ST requires TIM9 but the timer is already used"
#else
#define GD32_TIM9_IS_USED
#endif
#if defined(GD32_TIM9_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define GD32_ST_TIM GD32_TIM9
#define ST_LLD_NUM_ALARMS GD32_TIM9_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 TRUE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif GD32_ST_USE_TIMER == 10
#if defined(GD32_TIM10_IS_USED)
#error "ST requires TIM10 but the timer is already used"
#else
#define GD32_TIM10_IS_USED
#endif
#if defined(GD32_TIM10_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define GD32_ST_TIM GD32_TIM10
#define ST_LLD_NUM_ALARMS GD32_TIM10_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 TRUE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif GD32_ST_USE_TIMER == 11
#if defined(GD32_TIM11_IS_USED)
#error "ST requires TIM11 but the timer is already used"
#else
#define GD32_TIM11_IS_USED
#endif
#if defined(GD32_TIM11_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define GD32_ST_TIM GD32_TIM11
#define ST_LLD_NUM_ALARMS GD32_TIM11_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 TRUE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif GD32_ST_USE_TIMER == 12
#if defined(GD32_TIM12_IS_USED)
#error "ST requires TIM12 but the timer is already used"
#else
#define GD32_TIM12_IS_USED
#endif
#if defined(GD32_TIM12_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define GD32_ST_TIM GD32_TIM12
#define ST_LLD_NUM_ALARMS GD32_TIM12_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 TRUE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif GD32_ST_USE_TIMER == 13
#if defined(GD32_TIM13_IS_USED)
#error "ST requires TIM13 but the timer is already used"
#else
#define GD32_TIM13_IS_USED
#endif
#if defined(GD32_TIM13_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define GD32_ST_TIM GD32_TIM13
#define ST_LLD_NUM_ALARMS GD32_TIM13_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 TRUE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif GD32_ST_USE_TIMER == 14
#if defined(GD32_TIM14_IS_USED)
#error "ST requires TIM14 but the timer is already used"
#else
#define GD32_TIM14_IS_USED
#endif
#if defined(GD32_TIM14_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define GD32_ST_TIM GD32_TIM14
#define ST_LLD_NUM_ALARMS GD32_TIM14_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 TRUE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#elif GD32_ST_USE_TIMER == 21
#if defined(GD32_TIM21_IS_USED)
#error "ST requires TIM21 but the timer is already used"
#else
#define GD32_TIM21_IS_USED
#endif
#if defined(GD32_TIM21_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define GD32_ST_TIM GD32_TIM21
#define ST_LLD_NUM_ALARMS GD32_TIM21_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 TRUE
#define GD32_ST_USE_TIM22 FALSE
#elif GD32_ST_USE_TIMER == 22
#if defined(GD32_TIM22_IS_USED)
#error "ST requires TIM22 but the timer is already used"
#else
#define GD32_TIM22_IS_USED
#endif
#if defined(GD32_TIM22_SUPPRESS_ISR)
#define GD32_SYSTICK_SUPPRESS_ISR
#endif
#define GD32_ST_TIM GD32_TIM22
#define ST_LLD_NUM_ALARMS GD32_TIM22_CHANNELS
#define GD32_ST_USE_SYSTICK FALSE
#define GD32_ST_USE_TIM2 FALSE
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 TRUE
#else
#error "GD32_ST_USE_TIMER specifies an unsupported timer"
#endif
@ -474,14 +217,6 @@
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#else
@ -490,15 +225,6 @@
#define GD32_ST_USE_TIM3 FALSE
#define GD32_ST_USE_TIM4 FALSE
#define GD32_ST_USE_TIM5 FALSE
#define GD32_ST_USE_TIM9 FALSE
#define GD32_ST_USE_TIM10 FALSE
#define GD32_ST_USE_TIM11 FALSE
#define GD32_ST_USE_TIM12 FALSE
#define GD32_ST_USE_TIM13 FALSE
#define GD32_ST_USE_TIM14 FALSE
#define GD32_ST_USE_TIM21 FALSE
#define GD32_ST_USE_TIM22 FALSE
#endif
/*===========================================================================*/

14
os/hal/ports/GD/GD32VF103/TIM/tim_irq_mapping.txt
View File

@ -1,14 +0,0 @@
TIM units IRQ collisions mapping.
1B 1UP 1TC 1CC 2 3 4 5 6 7 8B 8UP 8TC 8CC 9 10 11 12 13 14 15 16 17 18 19 20 21 22 LP1 LP2
F0xx 1---1 2---2 * * * * * * * *
F030 1---1 2---2 * * * * *
F1xx 1 2 3 * * * * * * * 1 2 3
F100 1 2 3 * * * * * * * 1 2 3
F3xx 1 2 3 * * * * * * * * * * 1 2 3
F37x * * * * * * * * * * * * * *
F4xx 1 2 3 * * * * * * * 4 5 6 * 1 2 3 4 5 6
F7xx 1 2 3 * * * * * * * 4 5 6 * 1 2 3 4 5 6 *
L0xx * * * * * * *
L1xx * * * * * * * * *
L4xx 1 2 3 * * * * * * * * * * * 1 2 3 * *