Rename missed adc registers
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@ -174,30 +174,30 @@ typedef enum {
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* @brief Low level fields of the ADC configuration structure.
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* @brief Low level fields of the ADC configuration structure.
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*/
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*/
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#define adc_lld_configuration_group_fields \
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#define adc_lld_configuration_group_fields \
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/* ADC CR1 register initialization data. \
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/* ADC CTL0 register initialization data. \
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NOTE: All the required bits must be defined into this field except \
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NOTE: All the required bits must be defined into this field except \
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@p ADC_CTL0_SM that is enforced inside the driver.*/ \
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@p ADC_CTL0_SM that is enforced inside the driver.*/ \
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uint32_t ctl0; \
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uint32_t ctl0; \
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/* ADC CR2 register initialization data. \
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/* ADC CTL1 register initialization data. \
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NOTE: All the required bits must be defined into this field except \
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NOTE: All the required bits must be defined into this field except \
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@p ADC_CTL1_DMA, @p ADC_CTL1_CTN and @p ADC_CTL1_ADCON that are \
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@p ADC_CTL1_DMA, @p ADC_CTL1_CTN and @p ADC_CTL1_ADCON that are \
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enforced inside the driver.*/ \
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enforced inside the driver.*/ \
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uint32_t ctl1; \
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uint32_t ctl1; \
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/* ADC SMPR1 register initialization data. \
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/* ADC SAMPT0 register initialization data. \
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NOTE: In this field must be specified the sample times for channels \
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NOTE: In this field must be specified the sample times for channels \
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10...17.*/ \
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10...17.*/ \
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uint32_t sampt0; \
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uint32_t sampt0; \
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/* ADC SMPR2 register initialization data. \
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/* ADC SAMPT1 register initialization data. \
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NOTE: In this field must be specified the sample times for channels \
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NOTE: In this field must be specified the sample times for channels \
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0...9.*/ \
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0...9.*/ \
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uint32_t sampt1; \
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uint32_t sampt1; \
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/* ADC SQR1 register initialization data. \
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/* ADC RSQ0 register initialization data. \
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NOTE: Conversion group sequence 13...16 + sequence length.*/ \
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NOTE: Conversion group sequence 13...16 + sequence length.*/ \
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uint32_t rsq0; \
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uint32_t rsq0; \
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/* ADC SQR2 register initialization data. \
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/* ADC RSQ1 register initialization data. \
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NOTE: Conversion group sequence 7...12.*/ \
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NOTE: Conversion group sequence 7...12.*/ \
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uint32_t rsq1; \
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uint32_t rsq1; \
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/* ADC SQR3 register initialization data. \
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/* ADC RSQ2 register initialization data. \
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NOTE: Conversion group sequence 1...6.*/ \
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NOTE: Conversion group sequence 1...6.*/ \
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uint32_t rsq2
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uint32_t rsq2
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