Merge pull request #43 from fpoussin/timcap-pull
TIMCAP Driver Merged pull request #43 from fpoussin/timcap-pull. Original driver: https://github.com/dsigma/ChibiOS/tree/master/demos/ARMCM4-STM32F407-WAVESHARE-OPEN-407I-C-TIM_CAP/timcap
This commit is contained in:
Uladzimir Pylinski
commit
b634bd9bee
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@ -12,8 +12,9 @@ HALSRC += ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \
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${CHIBIOS_CONTRIB}/os/hal/src/usbh/usbh_msd.c \
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${CHIBIOS_CONTRIB}/os/hal/src/usbh/usbh_ftdi.c \
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${CHIBIOS_CONTRIB}/os/hal/src/usbh/usbh_uvc.c \
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${CHIBIOS_CONTRIB}/os/hal/src/ee24xx.c \
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${CHIBIOS_CONTRIB}/os/hal/src/ee24xx.c \
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${CHIBIOS_CONTRIB}/os/hal/src/ee25xx.c \
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${CHIBIOS_CONTRIB}/os/hal/src/eeprom.c
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${CHIBIOS_CONTRIB}/os/hal/src/eeprom.c \
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${CHIBIOS_CONTRIB}/os/hal/src/timcap.c \
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HALINC += ${CHIBIOS_CONTRIB}/os/hal/include
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@ -33,6 +33,7 @@
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#include "nand.h"
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#include "eicu.h"
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#include "usbh.h"
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#include "timcap.h"
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/* Complex drivers.*/
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#include "onewire.h"
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@ -0,0 +1,210 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file timcap.h
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* @brief TIMCAP Driver macros and structures.
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*
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* @addtogroup TIMCAP
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* @{
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*/
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#ifndef _TIMCAP_H_
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#define _TIMCAP_H_
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#include "ch.h"
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#include "hal.h"
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#ifndef HAL_USE_TIMCAP
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#define HAL_USE_TIMCAP FALSE
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#endif
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#if HAL_USE_TIMCAP || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Driver state machine possible states.
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*/
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typedef enum {
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TIMCAP_UNINIT = 0, /**< Not initialized. */
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TIMCAP_STOP = 1, /**< Stopped. */
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TIMCAP_READY = 2, /**< Ready. */
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TIMCAP_WAITING = 3, /**< Waiting first edge. */
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TIMCAP_ACTIVE = 4, /**< Active cycle phase. */
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TIMCAP_IDLE = 5, /**< Idle cycle phase. */
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} timcapstate_t;
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/**
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* @brief Type of a structure representing an TIMCAP driver.
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*/
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typedef struct TIMCAPDriver TIMCAPDriver;
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/**
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* @brief TIMCAP notification callback type.
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*
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* @param[in] timcapp pointer to a @p TIMCAPDriver object
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*/
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typedef void (*timcapcallback_t)(TIMCAPDriver *timcapp);
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#include "timcap_lld.h"
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @name Macro Functions
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* @{
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*/
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/**
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* @brief Enables the input capture.
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*
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* @param[in] timcapp pointer to the @p TIMCAPDriver object
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*
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* @iclass
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*/
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#define timcapEnableI(timcapp) timcap_lld_enable(timcapp)
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/**
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* @brief Disables the input capture.
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*
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* @param[in] timcapp pointer to the @p TIMCAPDriver object
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*
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* @iclass
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*/
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#define timcapDisableI(timcapp) timcap_lld_disable(timcapp)
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/** @} */
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/**
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* @name Low Level driver helper macros
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* @{
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*/
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/**
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* @brief Common ISR code, TIMCAP channel 1 event.
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*
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* @param[in] timcapp pointer to the @p TIMCAPDriver object
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*
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* @notapi
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*/
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#define _timcap_isr_invoke_channel1_cb(timcapp) { \
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timcapstate_t previous_state = (timcapp)->state; \
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(timcapp)->state = TIMCAP_ACTIVE; \
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if (previous_state != TIMCAP_WAITING) \
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(timcapp)->config->capture_cb_array[0](timcapp); \
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}
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/**
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* @brief Common ISR code, TIMCAP channel 2 event.
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*
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* @param[in] timcapp pointer to the @p TIMCAPDriver object
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*
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* @notapi
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*/
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#define _timcap_isr_invoke_channel2_cb(timcapp) { \
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timcapstate_t previous_state = (timcapp)->state; \
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(timcapp)->state = TIMCAP_ACTIVE; \
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if (previous_state != TIMCAP_WAITING) \
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(timcapp)->config->capture_cb_array[1](timcapp); \
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}
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/**
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* @brief Common ISR code, TIMCAP channel 3 event.
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*
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* @param[in] timcapp pointer to the @p TIMCAPDriver object
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*
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* @notapi
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*/
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#define _timcap_isr_invoke_channel3_cb(timcapp) { \
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timcapstate_t previous_state = (timcapp)->state; \
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(timcapp)->state = TIMCAP_ACTIVE; \
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if (previous_state != TIMCAP_WAITING) \
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(timcapp)->config->capture_cb_array[2](timcapp); \
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}
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/**
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* @brief Common ISR code, TIMCAP channel 4 event.
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*
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* @param[in] timcapp pointer to the @p TIMCAPDriver object
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*
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* @notapi
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*/
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#define _timcap_isr_invoke_channel4_cb(timcapp) { \
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timcapstate_t previous_state = (timcapp)->state; \
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(timcapp)->state = TIMCAP_ACTIVE; \
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if (previous_state != TIMCAP_WAITING) \
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(timcapp)->config->capture_cb_array[3](timcapp); \
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}
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/**
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* @brief Common ISR code, TIMCAP timer overflow event.
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*
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* @param[in] timcapp pointer to the @p TIMCAPDriver object
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*
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* @notapi
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*/
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#define _timcap_isr_invoke_overflow_cb(timcapp) { \
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(timcapp)->config->overflow_cb(timcapp); \
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}
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/** @} */
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void timcapInit(void);
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void timcapObjectInit(TIMCAPDriver *timcapp);
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void timcapStart(TIMCAPDriver *timcapp, const TIMCAPConfig *config);
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void timcapStop(TIMCAPDriver *timcapp);
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void timcapEnable(TIMCAPDriver *timcapp);
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void timcapDisable(TIMCAPDriver *timcapp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_TIMCAP */
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#endif /* _TIMCAP_H_ */
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/** @} */
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@ -0,0 +1,818 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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This file was derived from the ICU subsystem code, modified to achieve
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timing measurements on 2 and/or 4 channel STM32 timers by Dave Camarillo.
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*/
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/*
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Concepts and parts of this file have been contributed by Fabio Utzig and
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Xo Wang.
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*/
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/**
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* @file STM32/timcap_lld.c
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* @brief STM32 TIMCAP subsystem low level driver header.
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*
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* @addtogroup TIMCAP
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_TIMCAP || defined(__DOXYGEN__)
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#include "stm32_tim.h"
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#include "timcap.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief TIMCAPD1 driver identifier.
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* @note The driver TIMCAPD1 allocates the complex timer TIM1 when enabled.
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*/
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#if STM32_TIMCAP_USE_TIM1 || defined(__DOXYGEN__)
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TIMCAPDriver TIMCAPD1;
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#endif
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/**
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* @brief TIMCAPD2 driver identifier.
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* @note The driver TIMCAPD1 allocates the timer TIM2 when enabled.
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*/
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#if STM32_TIMCAP_USE_TIM2 || defined(__DOXYGEN__)
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TIMCAPDriver TIMCAPD2;
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#endif
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/**
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* @brief TIMCAPD3 driver identifier.
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* @note The driver TIMCAPD1 allocates the timer TIM3 when enabled.
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*/
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#if STM32_TIMCAP_USE_TIM3 || defined(__DOXYGEN__)
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TIMCAPDriver TIMCAPD3;
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#endif
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/**
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* @brief TIMCAPD4 driver identifier.
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* @note The driver TIMCAPD4 allocates the timer TIM4 when enabled.
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*/
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#if STM32_TIMCAP_USE_TIM4 || defined(__DOXYGEN__)
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TIMCAPDriver TIMCAPD4;
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#endif
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/**
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* @brief TIMCAPD5 driver identifier.
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* @note The driver TIMCAPD5 allocates the timer TIM5 when enabled.
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*/
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#if STM32_TIMCAP_USE_TIM5 || defined(__DOXYGEN__)
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TIMCAPDriver TIMCAPD5;
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#endif
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/**
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* @brief TIMCAPD8 driver identifier.
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* @note The driver TIMCAPD8 allocates the timer TIM8 when enabled.
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*/
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#if STM32_TIMCAP_USE_TIM8 || defined(__DOXYGEN__)
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TIMCAPDriver TIMCAPD8;
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#endif
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/**
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* @brief TIMCAPD9 driver identifier.
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* @note The driver TIMCAPD9 allocates the timer TIM9 when enabled.
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*/
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#if STM32_TIMCAP_USE_TIM9 || defined(__DOXYGEN__)
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TIMCAPDriver TIMCAPD9;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Returns the maximum channel number for the respective TIMCAP driver.
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* Note: different timer perepherials on the STM32 have between 1 and 4
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* CCR registers.
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*
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* @param[in] timcapp pointer to the @p TIMCAPDriver object
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*/
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static timcapchannel_t timcap_get_max_timer_channel(const TIMCAPDriver *timcapp) {
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//Choose a sane default value
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#if STM32_TIMCAP_USE_TIM1 || defined(__DOXYGEN__)
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if( timcapp == &TIMCAPD1 ) {
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return(TIMCAP_CHANNEL_4);
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}
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#endif
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#if STM32_TIMCAP_USE_TIM2 || defined(__DOXYGEN__)
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if( timcapp == &TIMCAPD2 ) {
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return(TIMCAP_CHANNEL_4);
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}
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#endif
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#if STM32_TIMCAP_USE_TIM3 || defined(__DOXYGEN__)
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if( timcapp == &TIMCAPD3 ) {
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return(TIMCAP_CHANNEL_4);
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}
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#endif
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#if STM32_TIMCAP_USE_TIM4 || defined(__DOXYGEN__)
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if( timcapp == &TIMCAPD4 ) {
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return(TIMCAP_CHANNEL_4);
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}
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#endif
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#if STM32_TIMCAP_USE_TIM5 || defined(__DOXYGEN__)
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if( timcapp == &TIMCAPD5 ) {
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return(TIMCAP_CHANNEL_4);
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}
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#endif
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#if STM32_TIMCAP_USE_TIM8 || defined(__DOXYGEN__)
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if( timcapp == &TIMCAPD8 ) {
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return(TIMCAP_CHANNEL_4);
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}
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#endif
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#if STM32_TIMCAP_USE_TIM9 || defined(__DOXYGEN__)
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if( timcapp == &TIMCAPD9 ) {
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return(TIMCAP_CHANNEL_2);
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}
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#endif
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/*Return a conservative default value.*/
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return(TIMCAP_CHANNEL_1);
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}
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/**
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* @brief Returns the maximum value for the ARR register of a given timer.
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*
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* @param[in] timcapp pointer to the @p TIMCAPDriver object
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*/
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static uint32_t timcap_get_max_arr(const TIMCAPDriver *timcapp) {
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//Choose a sane default value
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#if STM32_TIMCAP_USE_TIM1 || defined(__DOXYGEN__)
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if( timcapp == &TIMCAPD1 ) {
|
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return(UINT16_MAX);
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}
|
||||
#endif
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||||
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#if STM32_TIMCAP_USE_TIM2 || defined(__DOXYGEN__)
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if( timcapp == &TIMCAPD2 ) {
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return(UINT32_MAX);
|
||||
}
|
||||
#endif
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#if STM32_TIMCAP_USE_TIM3 || defined(__DOXYGEN__)
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if( timcapp == &TIMCAPD3 ) {
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return(UINT16_MAX);
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}
|
||||
#endif
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||||
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#if STM32_TIMCAP_USE_TIM4 || defined(__DOXYGEN__)
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if( timcapp == &TIMCAPD4 ) {
|
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return(UINT16_MAX);
|
||||
}
|
||||
#endif
|
||||
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||||
#if STM32_TIMCAP_USE_TIM5 || defined(__DOXYGEN__)
|
||||
if( timcapp == &TIMCAPD5 ) {
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return(UINT32_MAX);
|
||||
}
|
||||
#endif
|
||||
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#if STM32_TIMCAP_USE_TIM8 || defined(__DOXYGEN__)
|
||||
if( timcapp == &TIMCAPD8 ) {
|
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return(UINT16_MAX);
|
||||
}
|
||||
#endif
|
||||
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||||
#if STM32_TIMCAP_USE_TIM9 || defined(__DOXYGEN__)
|
||||
if( timcapp == &TIMCAPD9 ) {
|
||||
return(UINT16_MAX);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*Return a conservative default value.*/
|
||||
return(UINT16_MAX);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Shared IRQ handler.
|
||||
*
|
||||
* @param[in] timcapp pointer to the @p TIMCAPDriver object
|
||||
*/
|
||||
static void timcap_lld_serve_interrupt(TIMCAPDriver *timcapp) {
|
||||
uint16_t sr;
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||||
|
||||
sr = timcapp->tim->SR;
|
||||
sr &= timcapp->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
|
||||
timcapp->tim->SR = ~sr;
|
||||
|
||||
if ((sr & STM32_TIM_SR_CC1IF) != 0 && timcapp->config->capture_cb_array[TIMCAP_CHANNEL_1] != NULL )
|
||||
_timcap_isr_invoke_channel1_cb(timcapp);
|
||||
|
||||
if ((sr & STM32_TIM_SR_CC2IF) != 0 && timcapp->config->capture_cb_array[TIMCAP_CHANNEL_2] != NULL )
|
||||
_timcap_isr_invoke_channel2_cb(timcapp);
|
||||
|
||||
if ((sr & STM32_TIM_SR_CC3IF) != 0 && timcapp->config->capture_cb_array[TIMCAP_CHANNEL_3] != NULL )
|
||||
_timcap_isr_invoke_channel3_cb(timcapp);
|
||||
|
||||
if ((sr & STM32_TIM_SR_CC4IF) != 0 && timcapp->config->capture_cb_array[TIMCAP_CHANNEL_4] != NULL )
|
||||
_timcap_isr_invoke_channel4_cb(timcapp);
|
||||
|
||||
if ((sr & STM32_TIM_SR_UIF) != 0 && timcapp->config->overflow_cb != NULL)
|
||||
_timcap_isr_invoke_overflow_cb(timcapp);
|
||||
}
|
||||
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||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM1
|
||||
#if !defined(STM32_TIM1_UP_HANDLER)
|
||||
#error "STM32_TIM1_UP_HANDLER not defined"
|
||||
#endif
|
||||
/**
|
||||
* @brief TIM1 compare interrupt handler.
|
||||
* @note It is assumed that the various sources are only activated if the
|
||||
* associated callback pointer is not equal to @p NULL in order to not
|
||||
* perform an extra check in a potentially critical interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
timcap_lld_serve_interrupt(&TIMCAPD1);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
#if !defined(STM32_TIM1_CC_HANDLER)
|
||||
#error "STM32_TIM1_CC_HANDLER not defined"
|
||||
#endif
|
||||
/**
|
||||
* @brief TIM1 compare interrupt handler.
|
||||
* @note It is assumed that the various sources are only activated if the
|
||||
* associated callback pointer is not equal to @p NULL in order to not
|
||||
* perform an extra check in a potentially critical interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
timcap_lld_serve_interrupt(&TIMCAPD1);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* STM32_TIMCAP_USE_TIM1 */
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM2
|
||||
#if !defined(STM32_TIM2_HANDLER)
|
||||
#error "STM32_TIM2_HANDLER not defined"
|
||||
#endif
|
||||
/**
|
||||
* @brief TIM2 interrupt handler.
|
||||
* @note It is assumed that the various sources are only activated if the
|
||||
* associated callback pointer is not equal to @p NULL in order to not
|
||||
* perform an extra check in a potentially critical interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(STM32_TIM2_HANDLER) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
timcap_lld_serve_interrupt(&TIMCAPD2);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* STM32_TIMCAP_USE_TIM2 */
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM3
|
||||
#if !defined(STM32_TIM3_HANDLER)
|
||||
#error "STM32_TIM3_HANDLER not defined"
|
||||
#endif
|
||||
/**
|
||||
* @brief TIM3 interrupt handler.
|
||||
* @note It is assumed that the various sources are only activated if the
|
||||
* associated callback pointer is not equal to @p NULL in order to not
|
||||
* perform an extra check in a potentially critical interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(STM32_TIM3_HANDLER) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
timcap_lld_serve_interrupt(&TIMCAPD3);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* STM32_TIMCAP_USE_TIM3 */
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM4
|
||||
#if !defined(STM32_TIM4_HANDLER)
|
||||
#error "STM32_TIM4_HANDLER not defined"
|
||||
#endif
|
||||
/**
|
||||
* @brief TIM4 interrupt handler.
|
||||
* @note It is assumed that the various sources are only activated if the
|
||||
* associated callback pointer is not equal to @p NULL in order to not
|
||||
* perform an extra check in a potentially critical interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(STM32_TIM4_HANDLER) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
timcap_lld_serve_interrupt(&TIMCAPD4);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* STM32_TIMCAP_USE_TIM4 */
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM5
|
||||
#if !defined(STM32_TIM5_HANDLER)
|
||||
#error "STM32_TIM5_HANDLER not defined"
|
||||
#endif
|
||||
/**
|
||||
* @brief TIM5 interrupt handler.
|
||||
* @note It is assumed that the various sources are only activated if the
|
||||
* associated callback pointer is not equal to @p NULL in order to not
|
||||
* perform an extra check in a potentially critical interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(STM32_TIM5_HANDLER) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
timcap_lld_serve_interrupt(&TIMCAPD5);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* STM32_TIMCAP_USE_TIM5 */
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM8
|
||||
#if !defined(STM32_TIM8_UP_HANDLER)
|
||||
#error "STM32_TIM8_UP_HANDLER not defined"
|
||||
#endif
|
||||
/**
|
||||
* @brief TIM8 compare interrupt handler.
|
||||
* @note It is assumed that the various sources are only activated if the
|
||||
* associated callback pointer is not equal to @p NULL in order to not
|
||||
* perform an extra check in a potentially critical interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
timcap_lld_serve_interrupt(&TIMCAPD8);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
#if !defined(STM32_TIM8_CC_HANDLER)
|
||||
#error "STM32_TIM8_CC_HANDLER not defined"
|
||||
#endif
|
||||
/**
|
||||
* @brief TIM8 compare interrupt handler.
|
||||
* @note It is assumed that the various sources are only activated if the
|
||||
* associated callback pointer is not equal to @p NULL in order to not
|
||||
* perform an extra check in a potentially critical interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
timcap_lld_serve_interrupt(&TIMCAPD8);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* STM32_TIMCAP_USE_TIM8 */
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM9
|
||||
#if !defined(STM32_TIM9_HANDLER)
|
||||
#error "STM32_TIM9_HANDLER not defined"
|
||||
#endif
|
||||
/**
|
||||
* @brief TIM9 interrupt handler.
|
||||
* @note It is assumed that the various sources are only activated if the
|
||||
* associated callback pointer is not equal to @p NULL in order to not
|
||||
* perform an extra check in a potentially critical interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(STM32_TIM9_HANDLER) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
timcap_lld_serve_interrupt(&TIMCAPD9);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* STM32_TIMCAP_USE_TIM9 */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Low level TIMCAP driver initialization.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void timcap_lld_init(void) {
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM1
|
||||
/* Driver initialization.*/
|
||||
timcapObjectInit(&TIMCAPD1);
|
||||
TIMCAPD1.tim = STM32_TIM1;
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM2
|
||||
/* Driver initialization.*/
|
||||
timcapObjectInit(&TIMCAPD2);
|
||||
TIMCAPD2.tim = STM32_TIM2;
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM3
|
||||
/* Driver initialization.*/
|
||||
timcapObjectInit(&TIMCAPD3);
|
||||
TIMCAPD3.tim = STM32_TIM3;
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM4
|
||||
/* Driver initialization.*/
|
||||
timcapObjectInit(&TIMCAPD4);
|
||||
TIMCAPD4.tim = STM32_TIM4;
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM5
|
||||
/* Driver initialization.*/
|
||||
timcapObjectInit(&TIMCAPD5);
|
||||
TIMCAPD5.tim = STM32_TIM5;
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM8
|
||||
/* Driver initialization.*/
|
||||
timcapObjectInit(&TIMCAPD8);
|
||||
TIMCAPD8.tim = STM32_TIM8;
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM9
|
||||
/* Driver initialization.*/
|
||||
timcapObjectInit(&TIMCAPD9);
|
||||
TIMCAPD9.tim = STM32_TIM9;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures and activates the TIMCAP peripheral.
|
||||
*
|
||||
* @param[in] timcapp pointer to the @p TIMCAPDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void timcap_lld_start(TIMCAPDriver *timcapp) {
|
||||
uint32_t psc;
|
||||
|
||||
const timcapchannel_t tim_max_channel = timcap_get_max_timer_channel(timcapp);
|
||||
|
||||
if (timcapp->state == TIMCAP_STOP) {
|
||||
/* Clock activation and timer reset.*/
|
||||
#if STM32_TIMCAP_USE_TIM1
|
||||
if (&TIMCAPD1 == timcapp) {
|
||||
rccEnableTIM1(FALSE);
|
||||
rccResetTIM1();
|
||||
nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_TIMCAP_TIM1_IRQ_PRIORITY);
|
||||
nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_TIMCAP_TIM1_IRQ_PRIORITY);
|
||||
#if defined(STM32_TIM1CLK)
|
||||
timcapp->clock = STM32_TIM1CLK;
|
||||
#else
|
||||
timcapp->clock = STM32_TIMCLK2;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
#if STM32_TIMCAP_USE_TIM2
|
||||
if (&TIMCAPD2 == timcapp) {
|
||||
rccEnableTIM2(FALSE);
|
||||
rccResetTIM2();
|
||||
nvicEnableVector(STM32_TIM2_NUMBER, STM32_TIMCAP_TIM2_IRQ_PRIORITY);
|
||||
timcapp->clock = STM32_TIMCLK1;
|
||||
}
|
||||
#endif
|
||||
#if STM32_TIMCAP_USE_TIM3
|
||||
if (&TIMCAPD3 == timcapp) {
|
||||
rccEnableTIM3(FALSE);
|
||||
rccResetTIM3();
|
||||
nvicEnableVector(STM32_TIM3_NUMBER, STM32_TIMCAP_TIM3_IRQ_PRIORITY);
|
||||
timcapp->clock = STM32_TIMCLK1;
|
||||
}
|
||||
#endif
|
||||
#if STM32_TIMCAP_USE_TIM4
|
||||
if (&TIMCAPD4 == timcapp) {
|
||||
rccEnableTIM4(FALSE);
|
||||
rccResetTIM4();
|
||||
nvicEnableVector(STM32_TIM4_NUMBER, STM32_TIMCAP_TIM4_IRQ_PRIORITY);
|
||||
timcapp->clock = STM32_TIMCLK1;
|
||||
}
|
||||
#endif
|
||||
#if STM32_TIMCAP_USE_TIM5
|
||||
if (&TIMCAPD5 == timcapp) {
|
||||
rccEnableTIM5(FALSE);
|
||||
rccResetTIM5();
|
||||
nvicEnableVector(STM32_TIM5_NUMBER, STM32_TIMCAP_TIM5_IRQ_PRIORITY);
|
||||
timcapp->clock = STM32_TIMCLK1;
|
||||
}
|
||||
#endif
|
||||
#if STM32_TIMCAP_USE_TIM8
|
||||
if (&TIMCAPD8 == timcapp) {
|
||||
rccEnableTIM8(FALSE);
|
||||
rccResetTIM8();
|
||||
nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_TIMCAP_TIM8_IRQ_PRIORITY);
|
||||
nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_TIMCAP_TIM8_IRQ_PRIORITY);
|
||||
#if defined(STM32_TIM8CLK)
|
||||
timcapp->clock = STM32_TIM8CLK;
|
||||
#else
|
||||
timcapp->clock = STM32_TIMCLK2;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
#if STM32_TIMCAP_USE_TIM9
|
||||
if (&TIMCAPD9 == timcapp) {
|
||||
rccEnableTIM9(FALSE);
|
||||
rccResetTIM9();
|
||||
nvicEnableVector(STM32_TIM9_NUMBER, STM32_TIMCAP_TIM9_IRQ_PRIORITY);
|
||||
timcapp->clock = STM32_TIMCLK1;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
/* Driver re-configuration scenario, it must be stopped first.*/
|
||||
timcapp->tim->CR1 = 0; /* Timer disabled. */
|
||||
timcapp->tim->DIER = timcapp->config->dier &/* DMA-related DIER settings. */
|
||||
~STM32_TIM_DIER_IRQ_MASK;
|
||||
timcapp->tim->SR = 0; /* Clear eventual pending IRQs. */
|
||||
timcapp->tim->CCR[0] = 0; /* Comparator 1 disabled. */
|
||||
timcapp->tim->CCR[1] = 0; /* Comparator 2 disabled. */
|
||||
if( tim_max_channel >= TIMCAP_CHANNEL_3 )
|
||||
timcapp->tim->CCR[2] = 0; /* Comparator 3 disabled. */
|
||||
if( tim_max_channel >= TIMCAP_CHANNEL_4 )
|
||||
timcapp->tim->CCR[3] = 0; /* Comparator 4 disabled. */
|
||||
timcapp->tim->CNT = 0; /* Counter reset to zero. */
|
||||
}
|
||||
|
||||
/* Timer configuration.*/
|
||||
psc = (timcapp->clock / timcapp->config->frequency) - 1;
|
||||
osalDbgAssert((psc <= 0xFFFF) &&
|
||||
((psc + 1) * timcapp->config->frequency) == timcapp->clock,
|
||||
"invalid frequency");
|
||||
timcapp->tim->PSC = (uint16_t)psc;
|
||||
timcapp->tim->ARR = timcap_get_max_arr(timcapp);
|
||||
|
||||
timcapp->tim->CCMR1 = 0;
|
||||
timcapp->tim->CCMR2 = 0;
|
||||
timcapp->tim->CCER = 0;
|
||||
|
||||
timcapchannel_t chan = TIMCAP_CHANNEL_1;
|
||||
|
||||
/*go through each non-NULL callback channel and enable the capture register on rising/falling edge*/
|
||||
for( chan = TIMCAP_CHANNEL_1; chan <= tim_max_channel; chan++ ) {
|
||||
if( timcapp->config->capture_cb_array[chan] == NULL ) {
|
||||
continue;
|
||||
}
|
||||
|
||||
switch (chan) {
|
||||
case TIMCAP_CHANNEL_1:
|
||||
/*CCMR1_CC1S = 01 = CH1 Input on TI1.*/
|
||||
timcapp->tim->CCMR1 |= STM32_TIM_CCMR1_CC1S(1);
|
||||
break;
|
||||
case TIMCAP_CHANNEL_2:
|
||||
/*CCMR1_CC2S = 10 = CH2 Input on TI1.*/
|
||||
timcapp->tim->CCMR1 |= STM32_TIM_CCMR1_CC2S(1);
|
||||
break;
|
||||
case TIMCAP_CHANNEL_3:
|
||||
timcapp->tim->CCMR2 |= STM32_TIM_CCMR2_CC3S(1);
|
||||
break;
|
||||
case TIMCAP_CHANNEL_4:
|
||||
timcapp->tim->CCMR2 |= STM32_TIM_CCMR2_CC4S(1);
|
||||
break;
|
||||
}
|
||||
|
||||
/* The CCER settings depend on the selected trigger mode.
|
||||
TIMCAP_INPUT_DISABLED: Input not used.
|
||||
TIMCAP_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge.
|
||||
TIMCAP_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge.*/
|
||||
if (timcapp->config->modes[chan] == TIMCAP_INPUT_ACTIVE_HIGH) {
|
||||
switch (chan) {
|
||||
case TIMCAP_CHANNEL_1:
|
||||
timcapp->tim->CCER |= STM32_TIM_CCER_CC1E;
|
||||
break;
|
||||
case TIMCAP_CHANNEL_2:
|
||||
timcapp->tim->CCER |= STM32_TIM_CCER_CC2E;
|
||||
break;
|
||||
case TIMCAP_CHANNEL_3:
|
||||
timcapp->tim->CCER |= STM32_TIM_CCER_CC3E;
|
||||
break;
|
||||
case TIMCAP_CHANNEL_4:
|
||||
timcapp->tim->CCER |= STM32_TIM_CCER_CC4E;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (timcapp->config->modes[chan] == TIMCAP_INPUT_ACTIVE_LOW) {
|
||||
switch (chan) {
|
||||
case TIMCAP_CHANNEL_1:
|
||||
timcapp->tim->CCER |= STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P;
|
||||
break;
|
||||
case TIMCAP_CHANNEL_2:
|
||||
timcapp->tim->CCER |= STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P;
|
||||
break;
|
||||
case TIMCAP_CHANNEL_3:
|
||||
timcapp->tim->CCER |= STM32_TIM_CCER_CC3E | STM32_TIM_CCER_CC3P;
|
||||
break;
|
||||
case TIMCAP_CHANNEL_4:
|
||||
timcapp->tim->CCER |= STM32_TIM_CCER_CC4E | STM32_TIM_CCER_CC4P;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else {
|
||||
switch (chan) {
|
||||
case TIMCAP_CHANNEL_1:
|
||||
timcapp->tim->CCER &= ~STM32_TIM_CCER_CC1E;
|
||||
break;
|
||||
case TIMCAP_CHANNEL_2:
|
||||
timcapp->tim->CCER &= ~STM32_TIM_CCER_CC2E;
|
||||
break;
|
||||
case TIMCAP_CHANNEL_3:
|
||||
timcapp->tim->CCER &= ~STM32_TIM_CCER_CC3E;
|
||||
break;
|
||||
case TIMCAP_CHANNEL_4:
|
||||
timcapp->tim->CCER &= ~STM32_TIM_CCER_CC4E;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* Direct pointers to the capture registers in order to make reading
|
||||
data faster from within callbacks.*/
|
||||
timcapp->ccr_p[chan] = &timcapp->tim->CCR[chan];
|
||||
}
|
||||
|
||||
/* SMCR_TS = 101, input is TI1FP1.*/
|
||||
timcapp->tim->SMCR = STM32_TIM_SMCR_TS(5);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivates the TIMCAP peripheral.
|
||||
*
|
||||
* @param[in] timcapp pointer to the @p TIMCAPDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void timcap_lld_stop(TIMCAPDriver *timcapp) {
|
||||
|
||||
if (timcapp->state == TIMCAP_READY) {
|
||||
/* Clock deactivation.*/
|
||||
timcapp->tim->CR1 = 0; /* Timer disabled. */
|
||||
timcapp->tim->DIER = 0; /* All IRQs disabled. */
|
||||
timcapp->tim->SR = 0; /* Clear eventual pending IRQs. */
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM1
|
||||
if (&TIMCAPD1 == timcapp) {
|
||||
nvicDisableVector(STM32_TIM1_UP_NUMBER);
|
||||
nvicDisableVector(STM32_TIM1_CC_NUMBER);
|
||||
rccDisableTIM1(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_TIMCAP_USE_TIM2
|
||||
if (&TIMCAPD2 == timcapp) {
|
||||
nvicDisableVector(STM32_TIM2_NUMBER);
|
||||
rccDisableTIM2(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_TIMCAP_USE_TIM3
|
||||
if (&TIMCAPD3 == timcapp) {
|
||||
nvicDisableVector(STM32_TIM3_NUMBER);
|
||||
rccDisableTIM3(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_TIMCAP_USE_TIM4
|
||||
if (&TIMCAPD4 == timcapp) {
|
||||
nvicDisableVector(STM32_TIM4_NUMBER);
|
||||
rccDisableTIM4(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_TIMCAP_USE_TIM5
|
||||
if (&TIMCAPD5 == timcapp) {
|
||||
nvicDisableVector(STM32_TIM5_NUMBER);
|
||||
rccDisableTIM5(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_TIMCAP_USE_TIM8
|
||||
if (&TIMCAPD8 == timcapp) {
|
||||
nvicDisableVector(STM32_TIM8_UP_NUMBER);
|
||||
nvicDisableVector(STM32_TIM8_CC_NUMBER);
|
||||
rccDisableTIM8(FALSE);
|
||||
}
|
||||
#endif
|
||||
#if STM32_TIMCAP_USE_TIM9
|
||||
if (&TIMCAPD9 == timcapp) {
|
||||
nvicDisableVector(STM32_TIM9_NUMBER);
|
||||
rccDisableTIM9(FALSE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the input capture.
|
||||
*
|
||||
* @param[in] timcapp pointer to the @p TIMCAPDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void timcap_lld_enable(TIMCAPDriver *timcapp) {
|
||||
|
||||
timcapp->tim->EGR |= STM32_TIM_EGR_UG;
|
||||
timcapp->tim->SR = 0; /* Clear pending IRQs (if any). */
|
||||
|
||||
timcapchannel_t chan = TIMCAP_CHANNEL_1;
|
||||
const timcapchannel_t tim_max_channel = timcap_get_max_timer_channel(timcapp);
|
||||
for( chan = TIMCAP_CHANNEL_1; chan <= tim_max_channel; chan++ ) {
|
||||
if( timcapp->config->capture_cb_array[chan] != NULL
|
||||
&& timcapp->config->modes[chan] != TIMCAP_INPUT_DISABLED ) {
|
||||
switch (chan) {
|
||||
case TIMCAP_CHANNEL_1:
|
||||
timcapp->tim->DIER |= STM32_TIM_DIER_CC1IE;
|
||||
break;
|
||||
case TIMCAP_CHANNEL_2:
|
||||
timcapp->tim->DIER |= STM32_TIM_DIER_CC2IE;
|
||||
break;
|
||||
case TIMCAP_CHANNEL_3:
|
||||
timcapp->tim->DIER |= STM32_TIM_DIER_CC3IE;
|
||||
break;
|
||||
case TIMCAP_CHANNEL_4:
|
||||
timcapp->tim->DIER |= STM32_TIM_DIER_CC4IE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (timcapp->config->overflow_cb != NULL)
|
||||
timcapp->tim->DIER |= STM32_TIM_DIER_UIE;
|
||||
|
||||
timcapp->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN | timcapp->config->cr1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the input capture.
|
||||
*
|
||||
* @param[in] timcapp pointer to the @p TIMCAPDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void timcap_lld_disable(TIMCAPDriver *timcapp) {
|
||||
|
||||
timcapp->tim->CR1 = 0; /* Initially stopped. */
|
||||
timcapp->tim->SR = 0; /* Clear pending IRQs (if any). */
|
||||
|
||||
/* All interrupts disabled.*/
|
||||
timcapp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
|
||||
}
|
||||
|
||||
#endif /* HAL_USE_TIMCAP */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,390 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32/timcap_lld.h
|
||||
* @brief STM32 TIMCAP subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup TIMCAP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _TIMCAP_LLD_H_
|
||||
#define _TIMCAP_LLD_H_
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
#include "stm32_tim.h"
|
||||
|
||||
|
||||
#if HAL_USE_TIMCAP || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief TIMCAPD1 driver enable switch.
|
||||
* @details If set to @p TRUE the support for TIMCAPD1 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_USE_TIM1) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_USE_TIM1 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMCAPD2 driver enable switch.
|
||||
* @details If set to @p TRUE the support for TIMCAPD2 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_USE_TIM2) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_USE_TIM2 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMCAPD3 driver enable switch.
|
||||
* @details If set to @p TRUE the support for TIMCAPD3 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_USE_TIM3) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_USE_TIM3 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMCAPD4 driver enable switch.
|
||||
* @details If set to @p TRUE the support for TIMCAPD4 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_USE_TIM4) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_USE_TIM4 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMCAPD5 driver enable switch.
|
||||
* @details If set to @p TRUE the support for TIMCAPD5 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_USE_TIM5) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_USE_TIM5 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMCAPD8 driver enable switch.
|
||||
* @details If set to @p TRUE the support for TIMCAPD8 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_USE_TIM8) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_USE_TIM8 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMCAPD9 driver enable switch.
|
||||
* @details If set to @p TRUE the support for TIMCAPD9 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_USE_TIM9) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_USE_TIM9 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMCAPD1 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_TIM1_IRQ_PRIORITY 7
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMCAPD2 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_TIM2_IRQ_PRIORITY 7
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMCAPD3 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_TIM3_IRQ_PRIORITY 7
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMCAPD4 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_TIM4_IRQ_PRIORITY 7
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMCAPD5 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_TIM5_IRQ_PRIORITY 7
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMCAPD8 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_TIM8_IRQ_PRIORITY 7
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief TIMCAPD9 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_TIMCAP_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCAP_TIM9_IRQ_PRIORITY 7
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM1 && !STM32_HAS_TIM1
|
||||
#error "TIM1 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM2 && !STM32_HAS_TIM2
|
||||
#error "TIM2 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM3 && !STM32_HAS_TIM3
|
||||
#error "TIM3 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM4 && !STM32_HAS_TIM4
|
||||
#error "TIM4 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM5 && !STM32_HAS_TIM5
|
||||
#error "TIM5 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM8 && !STM32_HAS_TIM8
|
||||
#error "TIM8 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM9 && !STM32_HAS_TIM9
|
||||
#error "TIM9 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if !STM32_TIMCAP_USE_TIM1 && !STM32_TIMCAP_USE_TIM2 && \
|
||||
!STM32_TIMCAP_USE_TIM3 && !STM32_TIMCAP_USE_TIM4 && \
|
||||
!STM32_TIMCAP_USE_TIM5 && !STM32_TIMCAP_USE_TIM8 && \
|
||||
!STM32_TIMCAP_USE_TIM9
|
||||
#error "TIMCAP driver activated but no TIM peripheral assigned"
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM1 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM1_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to TIM1"
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM2 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM2_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to TIM2"
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM3 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM3_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to TIM3"
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM4 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM4_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to TIM4"
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM5 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM5_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to TIM5"
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM8 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM8_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to TIM8"
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM9 && \
|
||||
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_TIMCAP_TIM9_IRQ_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to TIM9"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief TIMCAP driver mode.
|
||||
*/
|
||||
typedef enum {
|
||||
TIMCAP_INPUT_DISABLED = 0,
|
||||
TIMCAP_INPUT_ACTIVE_HIGH = 1, /**< Trigger on rising edge. */
|
||||
TIMCAP_INPUT_ACTIVE_LOW = 2, /**< Trigger on falling edge. */
|
||||
} timcapmode_t;
|
||||
|
||||
/**
|
||||
* @brief TIMCAP frequency type.
|
||||
*/
|
||||
typedef uint32_t timcapfreq_t;
|
||||
|
||||
/**
|
||||
* @brief TIMCAP channel type.
|
||||
*/
|
||||
typedef enum {
|
||||
TIMCAP_CHANNEL_1 = 0, /**< Use TIMxCH1. */
|
||||
TIMCAP_CHANNEL_2 = 1, /**< Use TIMxCH2. */
|
||||
TIMCAP_CHANNEL_3 = 2, /**< Use TIMxCH3. */
|
||||
TIMCAP_CHANNEL_4 = 3, /**< Use TIMxCH4. */
|
||||
} timcapchannel_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Driver configuration structure.
|
||||
* @note It could be empty on some architectures.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief Driver mode.
|
||||
*/
|
||||
timcapmode_t modes[4];
|
||||
/**
|
||||
* @brief Timer clock in Hz.
|
||||
* @note The low level can use assertions in order to catch invalid
|
||||
* frequency specifications.
|
||||
*/
|
||||
timcapfreq_t frequency;
|
||||
|
||||
/**
|
||||
* @brief Callback when a capture occurs
|
||||
*/
|
||||
timcapcallback_t capture_cb_array[4];
|
||||
|
||||
/**
|
||||
* @brief Callback for timer overflow.
|
||||
*/
|
||||
timcapcallback_t overflow_cb;
|
||||
|
||||
/* End of the mandatory fields.*/
|
||||
|
||||
/**
|
||||
* @brief TIM DIER register initialization data.
|
||||
* @note The value of this field should normally be equal to zero.
|
||||
* @note Only the DMA-related bits can be specified in this field.
|
||||
*/
|
||||
uint32_t dier;
|
||||
|
||||
/**
|
||||
* @brief TIM CR1 register initialization data.
|
||||
* @note The value of this field should normally be equal to zero.
|
||||
*/
|
||||
uint32_t cr1;
|
||||
} TIMCAPConfig;
|
||||
|
||||
/**
|
||||
* @brief Structure representing an TIMCAP driver.
|
||||
*/
|
||||
struct TIMCAPDriver {
|
||||
/**
|
||||
* @brief Driver state.
|
||||
*/
|
||||
timcapstate_t state;
|
||||
/**
|
||||
* @brief Current configuration data.
|
||||
*/
|
||||
const TIMCAPConfig *config;
|
||||
#if defined(TIMCAP_DRIVER_EXT_FIELDS)
|
||||
TIMCAP_DRIVER_EXT_FIELDS
|
||||
#endif
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Timer base clock.
|
||||
*/
|
||||
uint32_t clock;
|
||||
/**
|
||||
* @brief Pointer to the TIMx registers block.
|
||||
*/
|
||||
stm32_tim_t *tim;
|
||||
/**
|
||||
* @brief CCR register used for capture.
|
||||
*/
|
||||
volatile uint32_t *ccr_p[4];
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
//FIXME document this
|
||||
#define timcap_lld_get_ccr(timcapp, channel) (*((timcapp)->ccr_p[channel]) + 1)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM1 && !defined(__DOXYGEN__)
|
||||
extern TIMCAPDriver TIMCAPD1;
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM2 && !defined(__DOXYGEN__)
|
||||
extern TIMCAPDriver TIMCAPD2;
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM3 && !defined(__DOXYGEN__)
|
||||
extern TIMCAPDriver TIMCAPD3;
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM4 && !defined(__DOXYGEN__)
|
||||
extern TIMCAPDriver TIMCAPD4;
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM5 && !defined(__DOXYGEN__)
|
||||
extern TIMCAPDriver TIMCAPD5;
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM8 && !defined(__DOXYGEN__)
|
||||
extern TIMCAPDriver TIMCAPD8;
|
||||
#endif
|
||||
|
||||
#if STM32_TIMCAP_USE_TIM9 && !defined(__DOXYGEN__)
|
||||
extern TIMCAPDriver TIMCAPD9;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void timcap_lld_init(void);
|
||||
void timcap_lld_start(TIMCAPDriver *timcapp);
|
||||
void timcap_lld_stop(TIMCAPDriver *timcapp);
|
||||
void timcap_lld_enable(TIMCAPDriver *timcapp);
|
||||
void timcap_lld_disable(TIMCAPDriver *timcapp);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_TIMCAP */
|
||||
|
||||
#endif /* _TIMCAP_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -1,6 +1,8 @@
|
|||
include ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/platform.mk
|
||||
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/timcap_lld.c \
|
||||
|
||||
PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD
|
||||
|
|
|
|||
|
|
@ -0,0 +1,9 @@
|
|||
include ${CHIBIOS}/os/hal/ports/STM32/STM32F3xx/platform.mk
|
||||
|
||||
PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/eicu_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/timcap_lld.c
|
||||
|
||||
PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD
|
||||
|
|
@ -6,12 +6,15 @@ PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/stm32_dma2d.c \
|
|||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/stm32_ltdc.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/eicu_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/usbh_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/src/fsmc_sdram.c
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/timcap_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/usbh_lld.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/src/fsmc_sdram.c \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c
|
||||
|
||||
PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1 \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1 \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1 \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1 \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \
|
||||
${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD
|
||||
|
|
|
|||
|
|
@ -68,6 +68,10 @@ void halCommunityInit(void) {
|
|||
#if HAL_USE_USBH || defined(__DOXYGEN__)
|
||||
usbhInit();
|
||||
#endif
|
||||
|
||||
#if HAL_USE_TIMCAP || defined(__DOXYGEN__)
|
||||
timcapInit();
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* HAL_USE_COMMUNITY */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||
2011,2012,2013 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file timcap.c
|
||||
* @brief TIMCAP Driver code.
|
||||
*
|
||||
* @addtogroup TIMCAP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "timcap.h"
|
||||
|
||||
#if HAL_USE_TIMCAP || defined(__DOXYGEN__)
|
||||
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief TIMCAP Driver initialization.
|
||||
* @note This function is implicitly invoked by @p halInit(), there is
|
||||
* no need to explicitly initialize the driver.
|
||||
*
|
||||
* @init
|
||||
*/
|
||||
void timcapInit(void) {
|
||||
|
||||
timcap_lld_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the standard part of a @p TIMCAPDriver structure.
|
||||
*
|
||||
* @param[out] timcapp pointer to the @p TIMCAPDriver object
|
||||
*
|
||||
* @init
|
||||
*/
|
||||
void timcapObjectInit(TIMCAPDriver *timcapp) {
|
||||
|
||||
timcapp->state = TIMCAP_STOP;
|
||||
timcapp->config = NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures and activates the TIMCAP peripheral.
|
||||
*
|
||||
* @param[in] timcapp pointer to the @p TIMCAPDriver object
|
||||
* @param[in] config pointer to the @p TIMCAPConfig object
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
void timcapStart(TIMCAPDriver *timcapp, const TIMCAPConfig *config) {
|
||||
|
||||
osalDbgCheck((timcapp != NULL) && (config != NULL));
|
||||
|
||||
osalSysLock();
|
||||
osalDbgAssert((timcapp->state == TIMCAP_STOP) || (timcapp->state == TIMCAP_READY),
|
||||
"invalid state");
|
||||
timcapp->config = config;
|
||||
timcap_lld_start(timcapp);
|
||||
timcapp->state = TIMCAP_READY;
|
||||
osalSysUnlock();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivates the TIMCAP peripheral.
|
||||
*
|
||||
* @param[in] timcapp pointer to the @p TIMCAPDriver object
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
void timcapStop(TIMCAPDriver *timcapp) {
|
||||
|
||||
osalDbgCheck(timcapp != NULL);
|
||||
|
||||
osalSysLock();
|
||||
osalDbgAssert((timcapp->state == TIMCAP_STOP) || (timcapp->state == TIMCAP_READY),
|
||||
"invalid state");
|
||||
timcap_lld_stop(timcapp);
|
||||
timcapp->state = TIMCAP_STOP;
|
||||
osalSysUnlock();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the input capture.
|
||||
*
|
||||
* @param[in] timcapp pointer to the @p TIMCAPDriver object
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
void timcapEnable(TIMCAPDriver *timcapp) {
|
||||
|
||||
osalDbgCheck(timcapp != NULL);
|
||||
|
||||
osalSysLock();
|
||||
osalDbgAssert(timcapp->state == TIMCAP_READY, "invalid state");
|
||||
timcap_lld_enable(timcapp);
|
||||
timcapp->state = TIMCAP_WAITING;
|
||||
osalSysUnlock();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the input capture.
|
||||
*
|
||||
* @param[in] timcapp pointer to the @p TIMCAPDriver object
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
void timcapDisable(TIMCAPDriver *timcapp) {
|
||||
|
||||
osalDbgCheck(timcapp != NULL);
|
||||
|
||||
osalSysLock();
|
||||
osalDbgAssert((timcapp->state == TIMCAP_READY) || (timcapp->state == TIMCAP_WAITING) ||
|
||||
(timcapp->state == TIMCAP_ACTIVE) || (timcapp->state == TIMCAP_IDLE),
|
||||
"invalid state");
|
||||
timcap_lld_disable(timcapp);
|
||||
timcapp->state = TIMCAP_READY;
|
||||
osalSysUnlock();
|
||||
}
|
||||
|
||||
#endif /* HAL_USE_TIMCAP */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -92,7 +92,7 @@ CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
|
|||
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk
|
||||
# HAL-OSAL files (optional).
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/hal.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/platform.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/STM32/STM32F3xx/platform.mk
|
||||
include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
|
||||
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
|
||||
# RTOS files (optional).
|
||||
|
|
|
|||
|
|
@ -0,0 +1,217 @@
|
|||
##############################################################################
|
||||
# Build global options
|
||||
# NOTE: Can be overridden externally.
|
||||
#
|
||||
|
||||
# Compiler options here.
|
||||
ifeq ($(USE_OPT),)
|
||||
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
|
||||
endif
|
||||
|
||||
# C specific options here (added to USE_OPT).
|
||||
ifeq ($(USE_COPT),)
|
||||
USE_COPT =
|
||||
endif
|
||||
|
||||
# C++ specific options here (added to USE_OPT).
|
||||
ifeq ($(USE_CPPOPT),)
|
||||
USE_CPPOPT = -fno-rtti
|
||||
endif
|
||||
|
||||
# Enable this if you want the linker to remove unused code and data
|
||||
ifeq ($(USE_LINK_GC),)
|
||||
USE_LINK_GC = yes
|
||||
endif
|
||||
|
||||
# Linker extra options here.
|
||||
ifeq ($(USE_LDOPT),)
|
||||
USE_LDOPT =
|
||||
endif
|
||||
|
||||
# Enable this if you want link time optimizations (LTO)
|
||||
ifeq ($(USE_LTO),)
|
||||
USE_LTO = yes
|
||||
endif
|
||||
|
||||
# If enabled, this option allows to compile the application in THUMB mode.
|
||||
ifeq ($(USE_THUMB),)
|
||||
USE_THUMB = yes
|
||||
endif
|
||||
|
||||
# Enable this if you want to see the full log while compiling.
|
||||
ifeq ($(USE_VERBOSE_COMPILE),)
|
||||
USE_VERBOSE_COMPILE = no
|
||||
endif
|
||||
|
||||
# If enabled, this option makes the build process faster by not compiling
|
||||
# modules not used in the current configuration.
|
||||
ifeq ($(USE_SMART_BUILD),)
|
||||
USE_SMART_BUILD = yes
|
||||
endif
|
||||
|
||||
#
|
||||
# Build global options
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Architecture or project specific options
|
||||
#
|
||||
|
||||
# Stack size to be allocated to the Cortex-M process stack. This stack is
|
||||
# the stack used by the main() thread.
|
||||
ifeq ($(USE_PROCESS_STACKSIZE),)
|
||||
USE_PROCESS_STACKSIZE = 0x400
|
||||
endif
|
||||
|
||||
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
|
||||
# stack is used for processing interrupts and exceptions.
|
||||
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
|
||||
USE_EXCEPTIONS_STACKSIZE = 0x400
|
||||
endif
|
||||
|
||||
# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
|
||||
ifeq ($(USE_FPU),)
|
||||
USE_FPU = no
|
||||
endif
|
||||
|
||||
#
|
||||
# Architecture or project specific options
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Project, sources and paths
|
||||
#
|
||||
|
||||
# Define project name here
|
||||
PROJECT = ch
|
||||
|
||||
# Imported source files and paths
|
||||
CHIBIOS = ../../../../../ChibiOS-RT
|
||||
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
|
||||
# Startup files.
|
||||
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk
|
||||
# HAL-OSAL files (optional).
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/hal.mk
|
||||
include $(CHIBIOS_CONTRIB)/os/hal/ports/STM32/STM32F3xx/platform.mk
|
||||
include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
|
||||
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
|
||||
# RTOS files (optional).
|
||||
include $(CHIBIOS)/os/rt/rt.mk
|
||||
include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
|
||||
# Other files (optional).
|
||||
#include $(CHIBIOS)/test/rt/test.mk
|
||||
|
||||
# Define linker script file here
|
||||
LDSCRIPT= $(STARTUPLD)/STM32F303xC.ld
|
||||
|
||||
# C sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CSRC = $(STARTUPSRC) \
|
||||
$(KERNSRC) \
|
||||
$(PORTSRC) \
|
||||
$(OSALSRC) \
|
||||
$(HALSRC) \
|
||||
$(PLATFORMSRC) \
|
||||
$(BOARDSRC) \
|
||||
$(TESTSRC) \
|
||||
main.c
|
||||
|
||||
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
|
||||
# setting.
|
||||
CPPSRC =
|
||||
|
||||
# C sources to be compiled in ARM mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
# option that results in lower performance and larger code size.
|
||||
ACSRC =
|
||||
|
||||
# C++ sources to be compiled in ARM mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
# option that results in lower performance and larger code size.
|
||||
ACPPSRC =
|
||||
|
||||
# C sources to be compiled in THUMB mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
# option that results in lower performance and larger code size.
|
||||
TCSRC =
|
||||
|
||||
# C sources to be compiled in THUMB mode regardless of the global setting.
|
||||
# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
|
||||
# option that results in lower performance and larger code size.
|
||||
TCPPSRC =
|
||||
|
||||
# List ASM source files here
|
||||
ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
|
||||
|
||||
INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
|
||||
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
|
||||
$(CHIBIOS)/os/various
|
||||
|
||||
#
|
||||
# Project, sources and paths
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Compiler settings
|
||||
#
|
||||
|
||||
MCU = cortex-m4
|
||||
|
||||
#TRGT = arm-elf-
|
||||
TRGT = arm-none-eabi-
|
||||
CC = $(TRGT)gcc
|
||||
CPPC = $(TRGT)g++
|
||||
# Enable loading with g++ only if you need C++ runtime support.
|
||||
# NOTE: You can use C++ even without C++ support if you are careful. C++
|
||||
# runtime support makes code size explode.
|
||||
LD = $(TRGT)gcc
|
||||
#LD = $(TRGT)g++
|
||||
CP = $(TRGT)objcopy
|
||||
AS = $(TRGT)gcc -x assembler-with-cpp
|
||||
AR = $(TRGT)ar
|
||||
OD = $(TRGT)objdump
|
||||
SZ = $(TRGT)size
|
||||
HEX = $(CP) -O ihex
|
||||
BIN = $(CP) -O binary
|
||||
|
||||
# ARM-specific options here
|
||||
AOPT =
|
||||
|
||||
# THUMB-specific options here
|
||||
TOPT = -mthumb -DTHUMB
|
||||
|
||||
# Define C warning options here
|
||||
CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
|
||||
|
||||
# Define C++ warning options here
|
||||
CPPWARN = -Wall -Wextra -Wundef
|
||||
|
||||
#
|
||||
# Compiler settings
|
||||
##############################################################################
|
||||
|
||||
##############################################################################
|
||||
# Start of user section
|
||||
#
|
||||
|
||||
# List all user C define here, like -D_DEBUG=1
|
||||
UDEFS =
|
||||
|
||||
# Define ASM defines here
|
||||
UADEFS =
|
||||
|
||||
# List all user directories here
|
||||
UINCDIR =
|
||||
|
||||
# List the user directory to look for the libraries here
|
||||
ULIBDIR =
|
||||
|
||||
# List all user libraries here
|
||||
ULIBS =
|
||||
|
||||
#
|
||||
# End of user defines
|
||||
##############################################################################
|
||||
|
||||
RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
|
||||
include $(RULESPATH)/rules.mk
|
||||
|
|
@ -0,0 +1,499 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file templates/chconf.h
|
||||
* @brief Configuration file template.
|
||||
* @details A copy of this file must be placed in each project directory, it
|
||||
* contains the application specific kernel settings.
|
||||
*
|
||||
* @addtogroup config
|
||||
* @details Kernel related settings and hooks.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _CHCONF_H_
|
||||
#define _CHCONF_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name System timers settings
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System time counter resolution.
|
||||
* @note Allowed values are 16 or 32 bits.
|
||||
*/
|
||||
#define CH_CFG_ST_RESOLUTION 32
|
||||
|
||||
/**
|
||||
* @brief System tick frequency.
|
||||
* @details Frequency of the system timer that drives the system ticks. This
|
||||
* setting also defines the system tick time unit.
|
||||
*/
|
||||
#define CH_CFG_ST_FREQUENCY 10000
|
||||
|
||||
/**
|
||||
* @brief Time delta constant for the tick-less mode.
|
||||
* @note If this value is zero then the system uses the classic
|
||||
* periodic tick. This value represents the minimum number
|
||||
* of ticks that is safe to specify in a timeout directive.
|
||||
* The value one is not valid, timeouts are rounded up to
|
||||
* this value.
|
||||
*/
|
||||
#define CH_CFG_ST_TIMEDELTA 2
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Kernel parameters and options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Round robin interval.
|
||||
* @details This constant is the number of system ticks allowed for the
|
||||
* threads before preemption occurs. Setting this value to zero
|
||||
* disables the preemption for threads with equal priority and the
|
||||
* round robin becomes cooperative. Note that higher priority
|
||||
* threads can still preempt, the kernel is always preemptive.
|
||||
* @note Disabling the round robin preemption makes the kernel more compact
|
||||
* and generally faster.
|
||||
* @note The round robin preemption is not supported in tickless mode and
|
||||
* must be set to zero in that case.
|
||||
*/
|
||||
#define CH_CFG_TIME_QUANTUM 0
|
||||
|
||||
/**
|
||||
* @brief Managed RAM size.
|
||||
* @details Size of the RAM area to be managed by the OS. If set to zero
|
||||
* then the whole available RAM is used. The core memory is made
|
||||
* available to the heap allocator and/or can be used directly through
|
||||
* the simplified core memory allocator.
|
||||
*
|
||||
* @note In order to let the OS manage the whole RAM the linker script must
|
||||
* provide the @p __heap_base__ and @p __heap_end__ symbols.
|
||||
* @note Requires @p CH_CFG_USE_MEMCORE.
|
||||
*/
|
||||
#define CH_CFG_MEMCORE_SIZE 0
|
||||
|
||||
/**
|
||||
* @brief Idle thread automatic spawn suppression.
|
||||
* @details When this option is activated the function @p chSysInit()
|
||||
* does not spawn the idle thread. The application @p main()
|
||||
* function becomes the idle thread and must implement an
|
||||
* infinite loop.
|
||||
*/
|
||||
#define CH_CFG_NO_IDLE_THREAD FALSE
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Performance options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief OS optimization.
|
||||
* @details If enabled then time efficient rather than space efficient code
|
||||
* is used when two possible implementations exist.
|
||||
*
|
||||
* @note This is not related to the compiler optimization options.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_OPTIMIZE_SPEED TRUE
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Subsystem options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Time Measurement APIs.
|
||||
* @details If enabled then the time measurement APIs are included in
|
||||
* the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_TM TRUE
|
||||
|
||||
/**
|
||||
* @brief Threads registry APIs.
|
||||
* @details If enabled then the registry APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_REGISTRY TRUE
|
||||
|
||||
/**
|
||||
* @brief Threads synchronization APIs.
|
||||
* @details If enabled then the @p chThdWait() function is included in
|
||||
* the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_WAITEXIT TRUE
|
||||
|
||||
/**
|
||||
* @brief Semaphores APIs.
|
||||
* @details If enabled then the Semaphores APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_SEMAPHORES TRUE
|
||||
|
||||
/**
|
||||
* @brief Semaphores queuing mode.
|
||||
* @details If enabled then the threads are enqueued on semaphores by
|
||||
* priority rather than in FIFO order.
|
||||
*
|
||||
* @note The default is @p FALSE. Enable this if you have special
|
||||
* requirements.
|
||||
* @note Requires @p CH_CFG_USE_SEMAPHORES.
|
||||
*/
|
||||
#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
|
||||
|
||||
/**
|
||||
* @brief Mutexes APIs.
|
||||
* @details If enabled then the mutexes APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_MUTEXES TRUE
|
||||
|
||||
/**
|
||||
* @brief Enables recursive behavior on mutexes.
|
||||
* @note Recursive mutexes are heavier and have an increased
|
||||
* memory footprint.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||
*/
|
||||
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
|
||||
|
||||
/**
|
||||
* @brief Conditional Variables APIs.
|
||||
* @details If enabled then the conditional variables APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||
*/
|
||||
#define CH_CFG_USE_CONDVARS TRUE
|
||||
|
||||
/**
|
||||
* @brief Conditional Variables APIs with timeout.
|
||||
* @details If enabled then the conditional variables APIs with timeout
|
||||
* specification are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_CONDVARS.
|
||||
*/
|
||||
#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
|
||||
|
||||
/**
|
||||
* @brief Events Flags APIs.
|
||||
* @details If enabled then the event flags APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_EVENTS TRUE
|
||||
|
||||
/**
|
||||
* @brief Events Flags APIs with timeout.
|
||||
* @details If enabled then the events APIs with timeout specification
|
||||
* are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_EVENTS.
|
||||
*/
|
||||
#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
|
||||
|
||||
/**
|
||||
* @brief Synchronous Messages APIs.
|
||||
* @details If enabled then the synchronous messages APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_MESSAGES TRUE
|
||||
|
||||
/**
|
||||
* @brief Synchronous Messages queuing mode.
|
||||
* @details If enabled then messages are served by priority rather than in
|
||||
* FIFO order.
|
||||
*
|
||||
* @note The default is @p FALSE. Enable this if you have special
|
||||
* requirements.
|
||||
* @note Requires @p CH_CFG_USE_MESSAGES.
|
||||
*/
|
||||
#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
|
||||
|
||||
/**
|
||||
* @brief Mailboxes APIs.
|
||||
* @details If enabled then the asynchronous messages (mailboxes) APIs are
|
||||
* included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_SEMAPHORES.
|
||||
*/
|
||||
#define CH_CFG_USE_MAILBOXES TRUE
|
||||
|
||||
/**
|
||||
* @brief I/O Queues APIs.
|
||||
* @details If enabled then the I/O queues APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_QUEUES TRUE
|
||||
|
||||
/**
|
||||
* @brief Core Memory Manager APIs.
|
||||
* @details If enabled then the core memory manager APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_MEMCORE TRUE
|
||||
|
||||
/**
|
||||
* @brief Heap Allocator APIs.
|
||||
* @details If enabled then the memory heap allocator APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
|
||||
* @p CH_CFG_USE_SEMAPHORES.
|
||||
* @note Mutexes are recommended.
|
||||
*/
|
||||
#define CH_CFG_USE_HEAP TRUE
|
||||
|
||||
/**
|
||||
* @brief Memory Pools Allocator APIs.
|
||||
* @details If enabled then the memory pools allocator APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#define CH_CFG_USE_MEMPOOLS TRUE
|
||||
|
||||
/**
|
||||
* @brief Dynamic Threads APIs.
|
||||
* @details If enabled then the dynamic threads creation APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_WAITEXIT.
|
||||
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
|
||||
*/
|
||||
#define CH_CFG_USE_DYNAMIC TRUE
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Debug options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Debug option, kernel statistics.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_STATISTICS TRUE
|
||||
|
||||
/**
|
||||
* @brief Debug option, system state check.
|
||||
* @details If enabled the correct call protocol for system APIs is checked
|
||||
* at runtime.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_SYSTEM_STATE_CHECK TRUE
|
||||
|
||||
/**
|
||||
* @brief Debug option, parameters checks.
|
||||
* @details If enabled then the checks on the API functions input
|
||||
* parameters are activated.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_ENABLE_CHECKS TRUE
|
||||
|
||||
/**
|
||||
* @brief Debug option, consistency checks.
|
||||
* @details If enabled then all the assertions in the kernel code are
|
||||
* activated. This includes consistency checks inside the kernel,
|
||||
* runtime anomalies and port-defined checks.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_ENABLE_ASSERTS TRUE
|
||||
|
||||
/**
|
||||
* @brief Debug option, trace buffer.
|
||||
* @details If enabled then the context switch circular trace buffer is
|
||||
* activated.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_ENABLE_TRACE TRUE
|
||||
|
||||
/**
|
||||
* @brief Debug option, stack checks.
|
||||
* @details If enabled then a runtime stack check is performed.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note The stack check is performed in a architecture/port dependent way.
|
||||
* It may not be implemented or some ports.
|
||||
* @note The default failure mode is to halt the system with the global
|
||||
* @p panic_msg variable set to @p NULL.
|
||||
*/
|
||||
#define CH_DBG_ENABLE_STACK_CHECK TRUE
|
||||
|
||||
/**
|
||||
* @brief Debug option, stacks initialization.
|
||||
* @details If enabled then the threads working area is filled with a byte
|
||||
* value when a thread is created. This can be useful for the
|
||||
* runtime measurement of the used stack.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#define CH_DBG_FILL_THREADS TRUE
|
||||
|
||||
/**
|
||||
* @brief Debug option, threads profiling.
|
||||
* @details If enabled then a field is added to the @p thread_t structure that
|
||||
* counts the system ticks occurred while executing the thread.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note This debug option is not currently compatible with the
|
||||
* tickless mode.
|
||||
*/
|
||||
#define CH_DBG_THREADS_PROFILING FALSE
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Kernel hooks
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Threads descriptor structure extension.
|
||||
* @details User fields added to the end of the @p thread_t structure.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXTRA_FIELDS \
|
||||
/* Add threads custom fields here.*/
|
||||
|
||||
/**
|
||||
* @brief Threads initialization hook.
|
||||
* @details User initialization code added to the @p chThdInit() API.
|
||||
*
|
||||
* @note It is invoked from within @p chThdInit() and implicitly from all
|
||||
* the threads creation APIs.
|
||||
*/
|
||||
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
|
||||
/* Add threads initialization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Threads finalization hook.
|
||||
* @details User finalization code added to the @p chThdExit() API.
|
||||
*
|
||||
* @note It is inserted into lock zone.
|
||||
* @note It is also invoked when the threads simply return in order to
|
||||
* terminate.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
|
||||
/* Add threads finalization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Context switch hook.
|
||||
* @details This hook is invoked just before switching between threads.
|
||||
*/
|
||||
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
|
||||
/* Context switch code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Idle thread enter hook.
|
||||
* @note This hook is invoked within a critical zone, no OS functions
|
||||
* should be invoked from here.
|
||||
* @note This macro can be used to activate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_ENTER_HOOK() { \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Idle thread leave hook.
|
||||
* @note This hook is invoked within a critical zone, no OS functions
|
||||
* should be invoked from here.
|
||||
* @note This macro can be used to deactivate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_LEAVE_HOOK() { \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Idle Loop hook.
|
||||
* @details This hook is continuously invoked by the idle thread loop.
|
||||
*/
|
||||
#define CH_CFG_IDLE_LOOP_HOOK() { \
|
||||
/* Idle loop code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System tick event hook.
|
||||
* @details This hook is invoked in the system tick handler immediately
|
||||
* after processing the virtual timers queue.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_TICK_HOOK() { \
|
||||
/* System tick event code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System halt hook.
|
||||
* @details This hook is invoked in case to a system halting error before
|
||||
* the system is halted.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
|
||||
/* System halt code here.*/ \
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Port-specific settings (override port settings defaulted in chcore.h). */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _CHCONF_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,387 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file templates/halconf.h
|
||||
* @brief HAL configuration header.
|
||||
* @details HAL configuration file, this file allows to enable or disable the
|
||||
* various device drivers from your application. You may also use
|
||||
* this file in order to override the device drivers default settings.
|
||||
*
|
||||
* @addtogroup HAL_CONF
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _HALCONF_H_
|
||||
#define _HALCONF_H_
|
||||
|
||||
#include "mcuconf.h"
|
||||
|
||||
/**
|
||||
* @brief Enables the PAL subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_PAL TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ADC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_ADC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the CAN subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CAN FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the DAC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_DAC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the EXT subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_EXT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the GPT subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_GPT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the I2C subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_I2C FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the I2S subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_I2S FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ICU subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_ICU FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the MAC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_MAC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the MMC_SPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_MMC_SPI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the PWM subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_PWM FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the RTC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_RTC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SDC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SDC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SERIAL subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SERIAL FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SERIAL over USB subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SERIAL_USB FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SPI FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the UART subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_UART FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the USB subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_USB FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the WDG subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_WDG FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* ADC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define ADC_USE_WAIT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define ADC_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* CAN driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Sleep mode related APIs inclusion switch.
|
||||
*/
|
||||
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
|
||||
#define CAN_USE_SLEEP_MODE TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I2C driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the mutual exclusion APIs on the I2C bus.
|
||||
*/
|
||||
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define I2C_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* MAC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables an event sources for incoming packets.
|
||||
*/
|
||||
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
|
||||
#define MAC_USE_ZERO_COPY FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables an event sources for incoming packets.
|
||||
*/
|
||||
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
|
||||
#define MAC_USE_EVENTS TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* MMC_SPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Delays insertions.
|
||||
* @details If enabled this options inserts delays into the MMC waiting
|
||||
* routines releasing some extra CPU time for the threads with
|
||||
* lower priority, this may slow down the driver a bit however.
|
||||
* This option is recommended also if the SPI driver does not
|
||||
* use a DMA channel and heavily loads the CPU.
|
||||
*/
|
||||
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||
#define MMC_NICE_WAITING TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SDC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Number of initialization attempts before rejecting the card.
|
||||
* @note Attempts are performed at 10mS intervals.
|
||||
*/
|
||||
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
|
||||
#define SDC_INIT_RETRY 100
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Include support for MMC cards.
|
||||
* @note MMC support is not yet implemented so this option must be kept
|
||||
* at @p FALSE.
|
||||
*/
|
||||
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
|
||||
#define SDC_MMC_SUPPORT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Delays insertions.
|
||||
* @details If enabled this options inserts delays into the MMC waiting
|
||||
* routines releasing some extra CPU time for the threads with
|
||||
* lower priority, this may slow down the driver a bit however.
|
||||
*/
|
||||
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||
#define SDC_NICE_WAITING TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SERIAL driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Default bit rate.
|
||||
* @details Configuration parameter, this is the baud rate selected for the
|
||||
* default configuration.
|
||||
*/
|
||||
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_DEFAULT_BITRATE 38400
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Serial buffers size.
|
||||
* @details Configuration parameter, you can change the depth of the queue
|
||||
* buffers depending on the requirements of your application.
|
||||
* @note The default is 16 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_BUFFERS_SIZE 16
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SERIAL_USB driver related setting. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Serial over USB buffers size.
|
||||
* @details Configuration parameter, the buffer size must be a multiple of
|
||||
* the USB data endpoint maximum packet size.
|
||||
* @note The default is 256 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_SIZE 256
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Serial over USB number of buffers.
|
||||
* @note The default is 2 buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_NUMBER 2
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define SPI_USE_WAIT TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define SPI_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* UART driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define UART_USE_WAIT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define UART_USE_MUTUAL_EXCLUSION FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* USB driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define USB_USE_WAIT FALSE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Community drivers's includes */
|
||||
/*===========================================================================*/
|
||||
|
||||
#include "halconf_community.h"
|
||||
|
||||
#endif /* _HALCONF_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _HALCONF_COMMUNITY_H_
|
||||
#define _HALCONF_COMMUNITY_H_
|
||||
|
||||
/**
|
||||
* @brief Enables the community overlay.
|
||||
*/
|
||||
#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_COMMUNITY TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the FSMC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_FSMC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the NAND subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_NAND FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the 1-wire subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_ONEWIRE FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the EICU subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_EICU FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the community subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CRC FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the EEPROM subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_EEPROM FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the TIMCAP subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_TIMCAP TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* FSMCNAND driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define NAND_USE_MUTUAL_EXCLUSION TRUE
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* 1-wire driver related settings. */
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @brief Enables strong pull up feature.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#define ONEWIRE_USE_STRONG_PULLUP FALSE
|
||||
|
||||
/**
|
||||
* @brief Enables search ROM feature.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#define ONEWIRE_USE_SEARCH_ROM TRUE
|
||||
|
||||
/*===========================================================================*/
|
||||
/* EEProm driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables 24xx series I2C eeprom device driver.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#define EEPROM_USE_EE24XX TRUE
|
||||
/**
|
||||
* @brief Enables 25xx series SPI eeprom device driver.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#define EEPROM_USE_EE25XX TRUE
|
||||
|
||||
|
||||
#endif /* _HALCONF_COMMUNITY_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,194 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
|
||||
|
||||
static uint8_t TIM3CC1CaptureNumber, TIM3CC2CaptureNumber;
|
||||
static uint16_t TIM3CC1ReadValue1, TIM3CC1ReadValue2;
|
||||
static uint16_t TIM3CC2ReadValue1, TIM3CC2ReadValue2;
|
||||
static bool TIM3CC1UD, TIM3CC2UD;
|
||||
|
||||
static uint16_t freq1, freq2;
|
||||
|
||||
|
||||
void reEnableInputCapture(TIMCAPDriver *timcapp)
|
||||
{
|
||||
|
||||
if ((timcapp->tim->DIER & TIM_DIER_CC1IE) == 0)
|
||||
{
|
||||
TIM3CC1CaptureNumber = 0;
|
||||
TIM3CC1UD = false;
|
||||
timcapp->tim->DIER |= TIM_DIER_CC1IE;
|
||||
}
|
||||
|
||||
if ((timcapp->tim->DIER & TIM_DIER_CC2IE) == 0)
|
||||
{
|
||||
TIM3CC2CaptureNumber = 0;
|
||||
TIM3CC2UD = false;
|
||||
timcapp->tim->DIER |= TIM_DIER_CC2IE;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void captureOverflowCb(TIMCAPDriver *timcapp)
|
||||
{
|
||||
if (TIM3CC1UD && (timcapp->tim->DIER & TIM_DIER_CC1IE))
|
||||
{
|
||||
timcapp->tim->DIER &= ~TIM_DIER_CC1IE;
|
||||
freq1 = 0;
|
||||
}
|
||||
|
||||
if (TIM3CC2UD && (timcapp->tim->DIER & TIM_DIER_CC2IE))
|
||||
{
|
||||
timcapp->tim->DIER &= ~TIM_DIER_CC2IE;
|
||||
freq2 = 0;
|
||||
}
|
||||
|
||||
TIM3CC1UD = true;
|
||||
TIM3CC2UD = true;
|
||||
}
|
||||
|
||||
void capture1Cb(TIMCAPDriver *timcapp)
|
||||
{
|
||||
if(TIM3CC1CaptureNumber == 0)
|
||||
{
|
||||
/* Get the Input Capture value */
|
||||
TIM3CC1ReadValue1 = timcapp->tim->CCR[0];
|
||||
TIM3CC1CaptureNumber = 1;
|
||||
TIM3CC1UD = false;
|
||||
}
|
||||
else if(TIM3CC1CaptureNumber == 1)
|
||||
{
|
||||
uint32_t Capture;
|
||||
/* Get the Input Capture value */
|
||||
TIM3CC1ReadValue2 = timcapp->tim->CCR[0];
|
||||
TIM3CC1UD = false;
|
||||
|
||||
/* Capture computation */
|
||||
if (TIM3CC1ReadValue2 > TIM3CC1ReadValue1)
|
||||
{
|
||||
Capture = ((uint32_t)TIM3CC1ReadValue2 - (uint32_t)TIM3CC1ReadValue1);
|
||||
}
|
||||
else
|
||||
{
|
||||
Capture = (((uint32_t)TIM3CC1ReadValue2 + 0x10000) - (uint32_t)TIM3CC1ReadValue1);
|
||||
}
|
||||
|
||||
/* Frequency computation */
|
||||
freq1 = (timcapp->config->frequency / Capture);
|
||||
|
||||
TIM3CC1ReadValue1 = TIM3CC1ReadValue2;
|
||||
TIM3CC1CaptureNumber = 0;
|
||||
|
||||
/* Disable CC1 interrupt */
|
||||
timcapp->tim->DIER &= ~TIM_DIER_CC1IE;
|
||||
}
|
||||
}
|
||||
|
||||
void capture2Cb(TIMCAPDriver *timcapp)
|
||||
{
|
||||
if(TIM3CC2CaptureNumber == 0)
|
||||
{
|
||||
/* Get the Input Capture value */
|
||||
TIM3CC2ReadValue1 = timcapp->tim->CCR[1];
|
||||
TIM3CC2CaptureNumber = 1;
|
||||
TIM3CC2UD = false;
|
||||
}
|
||||
else if(TIM3CC2CaptureNumber == 1)
|
||||
{
|
||||
uint32_t Capture;
|
||||
/* Get the Input Capture value */
|
||||
TIM3CC2ReadValue2 = timcapp->tim->CCR[1];
|
||||
TIM3CC2UD = false;
|
||||
|
||||
/* Capture computation */
|
||||
if (TIM3CC2ReadValue2 > TIM3CC2ReadValue1)
|
||||
{
|
||||
Capture = ((uint32_t)TIM3CC2ReadValue2 - (uint32_t)TIM3CC2ReadValue1);
|
||||
}
|
||||
else
|
||||
{
|
||||
Capture = (((uint32_t)TIM3CC2ReadValue2 + 0x10000) - (uint32_t)TIM3CC2ReadValue1);
|
||||
}
|
||||
|
||||
/* Frequency computation */
|
||||
freq2 = (timcapp->config->frequency / Capture);
|
||||
|
||||
TIM3CC2ReadValue1 = TIM3CC2ReadValue2;
|
||||
TIM3CC2CaptureNumber = 0;
|
||||
|
||||
/* Disable CC2 interrupt */
|
||||
timcapp->tim->DIER &= ~TIM_DIER_CC2IE;
|
||||
}
|
||||
}
|
||||
|
||||
TIMCAPConfig tc_conf = {
|
||||
{TIMCAP_INPUT_ACTIVE_HIGH,
|
||||
TIMCAP_INPUT_ACTIVE_HIGH,
|
||||
TIMCAP_INPUT_DISABLED,
|
||||
TIMCAP_INPUT_DISABLED},
|
||||
200000, /* TIM3 Runs at 36Mhz max. (1/200000)*65536 = 0.32s Max, 3.12Hz Min */
|
||||
{capture1Cb, capture2Cb, NULL, NULL},
|
||||
captureOverflowCb,
|
||||
0,
|
||||
0
|
||||
};
|
||||
|
||||
THD_WORKING_AREA(waThreadTimcap, 256);
|
||||
static THD_FUNCTION(ThreadTimcap, arg)
|
||||
{
|
||||
(void)arg;
|
||||
|
||||
while (TRUE)
|
||||
{
|
||||
|
||||
reEnableInputCapture(&TIMCAPD3);
|
||||
chThdSleepMilliseconds(200);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Application entry point.
|
||||
*/
|
||||
int main(void) {
|
||||
|
||||
/*
|
||||
* System initializations.
|
||||
* - HAL initialization, this also initializes the configured device drivers
|
||||
* and performs the board-specific initializations.
|
||||
* - Kernel initialization, the main() function becomes a thread and the
|
||||
* RTOS is active.
|
||||
*/
|
||||
halInit();
|
||||
chSysInit();
|
||||
|
||||
timcapStart(&TIMCAPD3, &tc_conf);
|
||||
|
||||
chThdCreateStatic(waThreadTimcap, sizeof(waThreadTimcap), NORMALPRIO, ThreadTimcap, NULL);
|
||||
|
||||
/*
|
||||
* Normal main() thread activity, it resets the watchdog.
|
||||
*/
|
||||
while (true) {
|
||||
palToggleLine(LINE_LED4_BLUE);
|
||||
chThdSleepMilliseconds(500);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _MCUCONF_H_
|
||||
#define _MCUCONF_H_
|
||||
|
||||
/*
|
||||
* STM32F3xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F3xx_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT FALSE
|
||||
#define STM32_PVD_ENABLE FALSE
|
||||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#define STM32_HSE_ENABLED TRUE
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
#define STM32_PREDIV_VALUE 1
|
||||
#define STM32_PLLMUL_VALUE 9
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV2
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
|
||||
#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
|
||||
#define STM32_USART1SW STM32_USART1SW_PCLK
|
||||
#define STM32_USART2SW STM32_USART2SW_PCLK
|
||||
#define STM32_USART3SW STM32_USART3SW_PCLK
|
||||
#define STM32_UART4SW STM32_UART4SW_PCLK
|
||||
#define STM32_UART5SW STM32_UART5SW_PCLK
|
||||
#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
|
||||
#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
|
||||
#define STM32_TIM1SW STM32_TIM1SW_PCLK2
|
||||
#define STM32_TIM8SW STM32_TIM8SW_PCLK2
|
||||
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
||||
#define STM32_USB_CLOCK_REQUIRED TRUE
|
||||
#define STM32_USBPRE STM32_USBPRE_DIV1P5
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_DUAL_MODE FALSE
|
||||
#define STM32_ADC_COMPACT_SAMPLES FALSE
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#define STM32_ADC_USE_ADC2 FALSE
|
||||
#define STM32_ADC_USE_ADC3 FALSE
|
||||
#define STM32_ADC_USE_ADC4 FALSE
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC4_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
|
||||
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
|
||||
#define STM32_ADC_ADC4_IRQ_PRIORITY 5
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
|
||||
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
|
||||
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 TRUE
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE FALSE
|
||||
#define STM32_DAC_USE_DAC1_CH1 TRUE
|
||||
#define STM32_DAC_USE_DAC1_CH2 TRUE
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
*/
|
||||
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI33_IRQ_PRIORITY 6
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 FALSE
|
||||
#define STM32_GPT_USE_TIM2 FALSE
|
||||
#define STM32_GPT_USE_TIM3 FALSE
|
||||
#define STM32_GPT_USE_TIM4 FALSE
|
||||
#define STM32_GPT_USE_TIM6 FALSE
|
||||
#define STM32_GPT_USE_TIM7 FALSE
|
||||
#define STM32_GPT_USE_TIM8 FALSE
|
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 TRUE
|
||||
#define STM32_I2C_USE_I2C2 FALSE
|
||||
#define STM32_I2C_BUSY_TIMEOUT 50
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY 10
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY 10
|
||||
#define STM32_I2C_USE_DMA TRUE
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 1
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 FALSE
|
||||
#define STM32_ICU_USE_TIM2 FALSE
|
||||
#define STM32_ICU_USE_TIM3 FALSE
|
||||
#define STM32_ICU_USE_TIM4 FALSE
|
||||
#define STM32_ICU_USE_TIM8 FALSE
|
||||
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED FALSE
|
||||
#define STM32_PWM_USE_TIM1 FALSE
|
||||
#define STM32_PWM_USE_TIM2 FALSE
|
||||
#define STM32_PWM_USE_TIM3 FALSE
|
||||
#define STM32_PWM_USE_TIM4 FALSE
|
||||
#define STM32_PWM_USE_TIM8 FALSE
|
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 FALSE
|
||||
#define STM32_SERIAL_USE_USART2 FALSE
|
||||
#define STM32_SERIAL_USE_USART3 FALSE
|
||||
#define STM32_SERIAL_USE_UART4 FALSE
|
||||
#define STM32_SERIAL_USE_UART5 FALSE
|
||||
#define STM32_SERIAL_USART1_PRIORITY 12
|
||||
#define STM32_SERIAL_USART2_PRIORITY 12
|
||||
#define STM32_SERIAL_USART3_PRIORITY 12
|
||||
#define STM32_SERIAL_UART4_PRIORITY 12
|
||||
#define STM32_SERIAL_UART5_PRIORITY 12
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 TRUE
|
||||
#define STM32_SPI_USE_SPI2 FALSE
|
||||
#define STM32_SPI_USE_SPI3 FALSE
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY 8
|
||||
#define STM32_ST_USE_TIMER 2
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 FALSE
|
||||
#define STM32_UART_USE_USART2 FALSE
|
||||
#define STM32_UART_USE_USART3 FALSE
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_USB1 FALSE
|
||||
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
|
||||
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
|
||||
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG TRUE
|
||||
|
||||
/*
|
||||
* header for community drivers.
|
||||
*/
|
||||
#include "mcuconf_community.h"
|
||||
|
||||
#endif /* _MCUCONF_H_ */
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* FSMC driver system settings.
|
||||
*/
|
||||
#define STM32_FSMC_USE_FSMC1 FALSE
|
||||
#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10
|
||||
|
||||
/*
|
||||
* FSMC NAND driver system settings.
|
||||
*/
|
||||
#define STM32_NAND_USE_FSMC_NAND1 FALSE
|
||||
#define STM32_NAND_USE_FSMC_NAND2 FALSE
|
||||
#define STM32_NAND_USE_EXT_INT FALSE
|
||||
#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||||
#define STM32_NAND_DMA_PRIORITY 0
|
||||
#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* FSMC SRAM driver system settings.
|
||||
*/
|
||||
#define STM32_USE_FSMC_SRAM FALSE
|
||||
#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
|
||||
#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
|
||||
#define STM32_SRAM_USE_FSMC_SRAM3 FLASE
|
||||
#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
|
||||
|
||||
/*
|
||||
* FSMC SDRAM driver system settings.
|
||||
*/
|
||||
#define STM32_USE_FSMC_SDRAM FALSE
|
||||
|
||||
/*
|
||||
* TIMCAP driver system settings.
|
||||
*/
|
||||
#define STM32_TIMCAP_USE_TIM1 FALSE
|
||||
#define STM32_TIMCAP_USE_TIM2 FALSE
|
||||
#define STM32_TIMCAP_USE_TIM3 TRUE
|
||||
#define STM32_TIMCAP_USE_TIM4 FALSE
|
||||
#define STM32_TIMCAP_USE_TIM5 FALSE
|
||||
#define STM32_TIMCAP_USE_TIM8 FALSE
|
||||
#define STM32_TIMCAP_USE_TIM9 FALSE
|
||||
#define STM32_TIMCAP_TIM1_IRQ_PRIORITY 3
|
||||
#define STM32_TIMCAP_TIM2_IRQ_PRIORITY 3
|
||||
#define STM32_TIMCAP_TIM3_IRQ_PRIORITY 3
|
||||
#define STM32_TIMCAP_TIM4_IRQ_PRIORITY 3
|
||||
#define STM32_TIMCAP_TIM5_IRQ_PRIORITY 3
|
||||
#define STM32_TIMCAP_TIM8_IRQ_PRIORITY 3
|
||||
#define STM32_TIMCAP_TIM9_IRQ_PRIORITY 3
|
||||
|
||||
|
||||
Loading…
Reference in New Issue