diff --git a/os/hal/ports/GD/GD32VF103/OTG/gd32_otg.h b/os/hal/ports/GD/GD32VF103/OTG/gd32_otg.h index 5ec80c88..c4726ad2 100644 --- a/os/hal/ports/GD/GD32VF103/OTG/gd32_otg.h +++ b/os/hal/ports/GD/GD32VF103/OTG/gd32_otg.h @@ -30,11 +30,6 @@ */ #define GD32_OTG1_FIFO_MEM_SIZE 320 -/** - * @brief OTG_HS FIFO memory size in words. - */ -#define GD32_OTG2_FIFO_MEM_SIZE 1024 - /** * @brief Host channel registers group. */ @@ -91,28 +86,28 @@ typedef struct { * @brief USB registers memory map. */ typedef struct { - volatile uint32_t GOTGCTL; /**< @brief OTG control and status register.*/ - volatile uint32_t GOTGINT; /**< @brief OTG interrupt register. */ - volatile uint32_t GAHBCFG; /**< @brief AHB configuration register. */ - volatile uint32_t GUSBCFG; /**< @brief USB configuration register. */ + volatile uint32_t GOTGCS; /**< @brief OTG control and status register.*/ + volatile uint32_t GOTGINTF; /**< @brief OTG interrupt register. */ + volatile uint32_t GAHBCS; /**< @brief AHB configuration register. */ + volatile uint32_t GUSBCS; /**< @brief USB configuration register. */ volatile uint32_t GRSTCTL; /**< @brief Reset register size. */ - volatile uint32_t GINTSTS; /**< @brief Interrupt register. */ - volatile uint32_t GINTMSK; /**< @brief Interrupt mask register. */ - volatile uint32_t GRXSTSR; /**< @brief Receive status debug read + volatile uint32_t GINTF; /**< @brief Interrupt register. */ + volatile uint32_t GINTEN; /**< @brief Interrupt mask register. */ + volatile uint32_t GRSTATR; /**< @brief Receive status debug read register. */ - volatile uint32_t GRXSTSP; /**< @brief Receive status read/pop + volatile uint32_t GRSTATP; /**< @brief Receive status read/pop register. */ - volatile uint32_t GRXFSIZ; /**< @brief Receive FIFO size register. */ + volatile uint32_t GRFLEN; /**< @brief Receive FIFO size register. */ volatile uint32_t DIEPTXF0; /**< @brief Endpoint 0 transmit FIFO size register. */ - volatile uint32_t HNPTXSTS; /**< @brief Non-periodic transmit FIFO/queue + volatile uint32_t HNPTFQSTAT; /**< @brief Non-periodic transmit FIFO/queue status register. */ volatile uint32_t resvd30; volatile uint32_t resvd34; volatile uint32_t GCCFG; /**< @brief General core configuration. */ volatile uint32_t CID; /**< @brief Core ID register. */ volatile uint32_t resvd58[48]; - volatile uint32_t HPTXFSIZ; /**< @brief Host periodic transmit FIFO size + volatile uint32_t HPTFLEN; /**< @brief Host periodic transmit FIFO size register. */ volatile uint32_t DIEPTXF[15];/**< @brief Device IN endpoint transmit FIFO size registers. */ @@ -170,77 +165,77 @@ typedef struct { } gd32_otg_t; /** - * @name GOTGCTL register bit definitions + * @name GOTGCS register bit definitions * @{ */ -#define GOTGCTL_BSVLD (1U<<19) /**< B-Session Valid. */ -#define GOTGCTL_ASVLD (1U<<18) /**< A-Session Valid. */ -#define GOTGCTL_DBCT (1U<<17) /**< Long/Short debounce time. */ -#define GOTGCTL_CIDSTS (1U<<16) /**< Connector ID status. */ -#define GOTGCTL_EHEN (1U<<12) -#define GOTGCTL_DHNPEN (1U<<11) /**< Device HNP enabled. */ -#define GOTGCTL_HSHNPEN (1U<<10) /**< Host Set HNP enable. */ -#define GOTGCTL_HNPRQ (1U<<9) /**< HNP request. */ -#define GOTGCTL_HNGSCS (1U<<8) /**< Host negotiation success. */ -#define GOTGCTL_BVALOVAL (1U<<7) -#define GOTGCTL_BVALOEN (1U<<6) -#define GOTGCTL_AVALOVAL (1U<<5) -#define GOTGCTL_AVALOEN (1U<<4) -#define GOTGCTL_VBVALOVAL (1U<<3) -#define GOTGCTL_VBVALOEN (1U<<2) -#define GOTGCTL_SRQ (1U<<1) /**< Session request. */ -#define GOTGCTL_SRQSCS (1U<<0) /**< Session request success. */ +#define GOTGCS_BSVLD (1U<<19) /**< B-Session Valid. */ +#define GOTGCS_ASVLD (1U<<18) /**< A-Session Valid. */ +#define GOTGCS_DBCT (1U<<17) /**< Long/Short debounce time. */ +#define GOTGCS_CIDSTS (1U<<16) /**< Connector ID status. */ +#define GOTGCS_EHEN (1U<<12) +#define GOTGCS_DHNPEN (1U<<11) /**< Device HNP enabled. */ +#define GOTGCS_HSHNPEN (1U<<10) /**< Host Set HNP enable. */ +#define GOTGCS_HNPRQ (1U<<9) /**< HNP request. */ +#define GOTGCS_HNGSCS (1U<<8) /**< Host negotiation success. */ +#define GOTGCS_BVALOVAL (1U<<7) +#define GOTGCS_BVALOEN (1U<<6) +#define GOTGCS_AVALOVAL (1U<<5) +#define GOTGCS_AVALOEN (1U<<4) +#define GOTGCS_VBVALOVAL (1U<<3) +#define GOTGCS_VBVALOEN (1U<<2) +#define GOTGCS_SRQ (1U<<1) /**< Session request. */ +#define GOTGCS_SRQSCS (1U<<0) /**< Session request success. */ /** @} */ /** - * @name GOTGINT register bit definitions + * @name GOTGINTF register bit definitions * @{ */ -#define GOTGINT_DBCDNE (1U<<19) /**< Debounce done. */ -#define GOTGINT_ADTOCHG (1U<<18) /**< A-Device timeout change. */ -#define GOTGINT_HNGDET (1U<<17) /**< Host negotiation detected. */ -#define GOTGINT_HNSSCHG (1U<<9) /**< Host negotiation success +#define GOTGINTF_DBCDNE (1U<<19) /**< Debounce done. */ +#define GOTGINTF_ADTOCHG (1U<<18) /**< A-Device timeout change. */ +#define GOTGINTF_HNGDET (1U<<17) /**< Host negotiation detected. */ +#define GOTGINTF_HNSSCHG (1U<<9) /**< Host negotiation success status change. */ -#define GOTGINT_SRSSCHG (1U<<8) /**< Session request success +#define GOTGINTF_SRSSCHG (1U<<8) /**< Session request success status change. */ -#define GOTGINT_SEDET (1U<<2) /**< Session end detected. */ +#define GOTGINTF_SEDET (1U<<2) /**< Session end detected. */ /** @} */ /** - * @name GAHBCFG register bit definitions + * @name GAHBCS register bit definitions * @{ */ -#define GAHBCFG_PTXFELVL (1U<<8) /**< Periodic TxFIFO empty +#define GAHBCS_PTXFELVL (1U<<8) /**< Periodic TxFIFO empty level. */ -#define GAHBCFG_TXFELVL (1U<<7) /**< Non-periodic TxFIFO empty +#define GAHBCS_TXFELVL (1U<<7) /**< Non-periodic TxFIFO empty level. */ -#define GAHBCFG_DMAEN (1U<<5) /**< DMA enable (HS only). */ -#define GAHBCFG_HBSTLEN_MASK (15U<<1) /**< Burst length/type mask (HS +#define GAHBCS_DMAEN (1U<<5) /**< DMA enable (HS only). */ +#define GAHBCS_HBSTLEN_MASK (15U<<1) /**< Burst length/type mask (HS only). */ -#define GAHBCFG_HBSTLEN(n) ((n)<<1) /**< Burst length/type (HS +#define GAHBCS_HBSTLEN(n) ((n)<<1) /**< Burst length/type (HS only). */ -#define GAHBCFG_GINTMSK (1U<<0) /**< Global interrupt mask. */ +#define GAHBCS_GINTEN (1U<<0) /**< Global interrupt mask. */ /** @} */ /** - * @name GUSBCFG register bit definitions + * @name GUSBCS register bit definitions * @{ */ -#define GUSBCFG_CTXPKT (1U<<31) /**< Corrupt Tx packet. */ -#define GUSBCFG_FDMOD (1U<<30) /**< Force Device Mode. */ -#define GUSBCFG_FHMOD (1U<<29) /**< Force Host Mode. */ -#define GUSBCFG_TRDT_MASK (15U<<10) /**< USB Turnaround time field +#define GUSBCS_CTXPKT (1U<<31) /**< Corrupt Tx packet. */ +#define GUSBCS_FDMOD (1U<<30) /**< Force Device Mode. */ +#define GUSBCS_FHMOD (1U<<29) /**< Force Host Mode. */ +#define GUSBCS_TRDT_MASK (15U<<10) /**< USB Turnaround time field mask. */ -#define GUSBCFG_TRDT(n) ((n)<<10) /**< USB Turnaround time field +#define GUSBCS_TRDT(n) ((n)<<10) /**< USB Turnaround time field value. */ -#define GUSBCFG_HNPCAP (1U<<9) /**< HNP-Capable. */ -#define GUSBCFG_SRPCAP (1U<<8) /**< SRP-Capable. */ -#define GUSBCFG_PHYSEL (1U<<6) /**< USB 2.0 High-Speed PHY or +#define GUSBCS_HNPCAP (1U<<9) /**< HNP-Capable. */ +#define GUSBCS_SRPCAP (1U<<8) /**< SRP-Capable. */ +#define GUSBCS_PHYSEL (1U<<6) /**< USB 2.0 High-Speed PHY or USB 1.1 Full-Speed serial transceiver Select. */ -#define GUSBCFG_TOCAL_MASK (7U<<0) /**< HS/FS timeout calibration +#define GUSBCS_TOCAL_MASK (7U<<0) /**< HS/FS timeout calibration field mask. */ -#define GUSBCFG_TOCAL(n) ((n)<<0) /**< HS/FS timeout calibration +#define GUSBCS_TOCAL(n) ((n)<<0) /**< HS/FS timeout calibration field value. */ /** @} */ @@ -259,144 +254,144 @@ typedef struct { /** @} */ /** - * @name GINTSTS register bit definitions + * @name GINTF register bit definitions * @{ */ -#define GINTSTS_WKUPINT (1U<<31) /**< Resume/Remote wakeup +#define GINTF_WKUPINT (1U<<31) /**< Resume/Remote wakeup detected interrupt. */ -#define GINTSTS_SRQINT (1U<<30) /**< Session request/New session +#define GINTF_SRQINT (1U<<30) /**< Session request/New session detected interrupt. */ -#define GINTSTS_DISCINT (1U<<29) /**< Disconnect detected +#define GINTF_DISCINT (1U<<29) /**< Disconnect detected interrupt. */ -#define GINTSTS_CIDSCHG (1U<<28) /**< Connector ID status change.*/ -#define GINTSTS_PTXFE (1U<<26) /**< Periodic TxFIFO empty. */ -#define GINTSTS_HCINT (1U<<25) /**< Host channels interrupt. */ -#define GINTSTS_HPRTINT (1U<<24) /**< Host port interrupt. */ -#define GINTSTS_IPXFR (1U<<21) /**< Incomplete periodic +#define GINTF_CIDSCHG (1U<<28) /**< Connector ID status change.*/ +#define GINTF_PTXFE (1U<<26) /**< Periodic TxFIFO empty. */ +#define GINTF_HCINT (1U<<25) /**< Host channels interrupt. */ +#define GINTF_HPRTINT (1U<<24) /**< Host port interrupt. */ +#define GINTF_IPXFR (1U<<21) /**< Incomplete periodic transfer. */ -#define GINTSTS_IISOOXFR (1U<<21) /**< Incomplete isochronous OUT +#define GINTF_IISOOXFR (1U<<21) /**< Incomplete isochronous OUT transfer. */ -#define GINTSTS_IISOIXFR (1U<<20) /**< Incomplete isochronous IN +#define GINTF_IISOIXFR (1U<<20) /**< Incomplete isochronous IN transfer. */ -#define GINTSTS_OEPINT (1U<<19) /**< OUT endpoints interrupt. */ -#define GINTSTS_IEPINT (1U<<18) /**< IN endpoints interrupt. */ -#define GINTSTS_EOPF (1U<<15) /**< End of periodic frame +#define GINTF_OEPINT (1U<<19) /**< OUT endpoints interrupt. */ +#define GINTF_IEPINT (1U<<18) /**< IN endpoints interrupt. */ +#define GINTF_EOPF (1U<<15) /**< End of periodic frame interrupt. */ -#define GINTSTS_ISOODRP (1U<<14) /**< Isochronous OUT packet +#define GINTF_ISOODRP (1U<<14) /**< Isochronous OUT packet dropped interrupt. */ -#define GINTSTS_ENUMDNE (1U<<13) /**< Enumeration done. */ -#define GINTSTS_USBRST (1U<<12) /**< USB reset. */ -#define GINTSTS_USBSUSP (1U<<11) /**< USB suspend. */ -#define GINTSTS_ESUSP (1U<<10) /**< Early suspend. */ -#define GINTSTS_GONAKEFF (1U<<7) /**< Global OUT NAK effective. */ -#define GINTSTS_GINAKEFF (1U<<6) /**< Global IN non-periodic NAK +#define GINTF_ENUMDNE (1U<<13) /**< Enumeration done. */ +#define GINTF_USBRST (1U<<12) /**< USB reset. */ +#define GINTF_USBSUSP (1U<<11) /**< USB suspend. */ +#define GINTF_ESUSP (1U<<10) /**< Early suspend. */ +#define GINTF_GONAKEFF (1U<<7) /**< Global OUT NAK effective. */ +#define GINTF_GINAKEFF (1U<<6) /**< Global IN non-periodic NAK effective. */ -#define GINTSTS_NPTXFE (1U<<5) /**< Non-periodic TxFIFO empty. */ -#define GINTSTS_RXFLVL (1U<<4) /**< RxFIFO non-empty. */ -#define GINTSTS_SOF (1U<<3) /**< Start of frame. */ -#define GINTSTS_OTGINT (1U<<2) /**< OTG interrupt. */ -#define GINTSTS_MMIS (1U<<1) /**< Mode Mismatch interrupt. */ -#define GINTSTS_CMOD (1U<<0) /**< Current mode of operation. */ +#define GINTF_NPTXFE (1U<<5) /**< Non-periodic TxFIFO empty. */ +#define GINTF_RXFLVL (1U<<4) /**< RxFIFO non-empty. */ +#define GINTF_SOF (1U<<3) /**< Start of frame. */ +#define GINTF_OTGINT (1U<<2) /**< OTG interrupt. */ +#define GINTF_MMIS (1U<<1) /**< Mode Mismatch interrupt. */ +#define GINTF_CMOD (1U<<0) /**< Current mode of operation. */ /** @} */ /** - * @name GINTMSK register bit definitions + * @name GINTEN register bit definitions * @{ */ -#define GINTMSK_WKUM (1U<<31) /**< Resume/remote wakeup +#define GINTEN_WKUM (1U<<31) /**< Resume/remote wakeup detected interrupt mask. */ -#define GINTMSK_SRQM (1U<<30) /**< Session request/New session +#define GINTEN_SRQM (1U<<30) /**< Session request/New session detected interrupt mask. */ -#define GINTMSK_DISCM (1U<<29) /**< Disconnect detected +#define GINTEN_DISCM (1U<<29) /**< Disconnect detected interrupt mask. */ -#define GINTMSK_CIDSCHGM (1U<<28) /**< Connector ID status change +#define GINTEN_CIDSCHGM (1U<<28) /**< Connector ID status change mask. */ -#define GINTMSK_PTXFEM (1U<<26) /**< Periodic TxFIFO empty mask.*/ -#define GINTMSK_HCM (1U<<25) /**< Host channels interrupt +#define GINTEN_PTXFEM (1U<<26) /**< Periodic TxFIFO empty mask.*/ +#define GINTEN_HCM (1U<<25) /**< Host channels interrupt mask. */ -#define GINTMSK_HPRTM (1U<<24) /**< Host port interrupt mask. */ -#define GINTMSK_IPXFRM (1U<<21) /**< Incomplete periodic +#define GINTEN_HPRTM (1U<<24) /**< Host port interrupt mask. */ +#define GINTEN_IPXFRM (1U<<21) /**< Incomplete periodic transfer mask. */ -#define GINTMSK_IISOOXFRM (1U<<21) /**< Incomplete isochronous OUT +#define GINTEN_IISOOXFRM (1U<<21) /**< Incomplete isochronous OUT transfer mask. */ -#define GINTMSK_IISOIXFRM (1U<<20) /**< Incomplete isochronous IN +#define GINTEN_IISOIXFRM (1U<<20) /**< Incomplete isochronous IN transfer mask. */ -#define GINTMSK_OEPM (1U<<19) /**< OUT endpoints interrupt +#define GINTEN_OEPM (1U<<19) /**< OUT endpoints interrupt mask. */ -#define GINTMSK_IEPM (1U<<18) /**< IN endpoints interrupt +#define GINTEN_IEPM (1U<<18) /**< IN endpoints interrupt mask. */ -#define GINTMSK_EOPFM (1U<<15) /**< End of periodic frame +#define GINTEN_EOPFM (1U<<15) /**< End of periodic frame interrupt mask. */ -#define GINTMSK_ISOODRPM (1U<<14) /**< Isochronous OUT packet +#define GINTEN_ISOODRPM (1U<<14) /**< Isochronous OUT packet dropped interrupt mask. */ -#define GINTMSK_ENUMDNEM (1U<<13) /**< Enumeration done mask. */ -#define GINTMSK_USBRSTM (1U<<12) /**< USB reset mask. */ -#define GINTMSK_USBSUSPM (1U<<11) /**< USB suspend mask. */ -#define GINTMSK_ESUSPM (1U<<10) /**< Early suspend mask. */ -#define GINTMSK_GONAKEFFM (1U<<7) /**< Global OUT NAK effective +#define GINTEN_ENUMDNEM (1U<<13) /**< Enumeration done mask. */ +#define GINTEN_USBRSTM (1U<<12) /**< USB reset mask. */ +#define GINTEN_USBSUSPM (1U<<11) /**< USB suspend mask. */ +#define GINTEN_ESUSPM (1U<<10) /**< Early suspend mask. */ +#define GINTEN_GONAKEFFM (1U<<7) /**< Global OUT NAK effective mask. */ -#define GINTMSK_GINAKEFFM (1U<<6) /**< Global non-periodic IN NAK +#define GINTEN_GINAKEFFM (1U<<6) /**< Global non-periodic IN NAK effective mask. */ -#define GINTMSK_NPTXFEM (1U<<5) /**< Non-periodic TxFIFO empty +#define GINTEN_NPTXFEM (1U<<5) /**< Non-periodic TxFIFO empty mask. */ -#define GINTMSK_RXFLVLM (1U<<4) /**< Receive FIFO non-empty +#define GINTEN_RXFLVLM (1U<<4) /**< Receive FIFO non-empty mask. */ -#define GINTMSK_SOFM (1U<<3) /**< Start of (micro)frame mask.*/ -#define GINTMSK_OTGM (1U<<2) /**< OTG interrupt mask. */ -#define GINTMSK_MMISM (1U<<1) /**< Mode Mismatch interrupt +#define GINTEN_SOFM (1U<<3) /**< Start of (micro)frame mask.*/ +#define GINTEN_OTGM (1U<<2) /**< OTG interrupt mask. */ +#define GINTEN_MMISM (1U<<1) /**< Mode Mismatch interrupt mask. */ /** @} */ /** - * @name GRXSTSR register bit definitions + * @name GRSTATR register bit definitions * @{ */ -#define GRXSTSR_PKTSTS_MASK (15U<<17) /**< Packet status mask. */ -#define GRXSTSR_PKTSTS(n) ((n)<<17) /**< Packet status value. */ -#define GRXSTSR_OUT_GLOBAL_NAK GRXSTSR_PKTSTS(1) -#define GRXSTSR_OUT_DATA GRXSTSR_PKTSTS(2) -#define GRXSTSR_OUT_COMP GRXSTSR_PKTSTS(3) -#define GRXSTSR_SETUP_COMP GRXSTSR_PKTSTS(4) -#define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6) -#define GRXSTSR_DPID_MASK (3U<<15) /**< Data PID mask. */ -#define GRXSTSR_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ -#define GRXSTSR_BCNT(n) ((n)<<4) /**< Byte count value. */ -#define GRXSTSR_CHNUM_MASK (15U<<0) /**< Channel number mask. */ -#define GRXSTSR_CHNUM(n) ((n)<<0) /**< Channel number value. */ -#define GRXSTSR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ -#define GRXSTSR_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ +#define GRSTATR_PKTSTS_MASK (15U<<17) /**< Packet status mask. */ +#define GRSTATR_PKTSTS(n) ((n)<<17) /**< Packet status value. */ +#define GRSTATR_OUT_GLOBAL_NAK GRSTATR_PKTSTS(1) +#define GRSTATR_OUT_DATA GRSTATR_PKTSTS(2) +#define GRSTATR_OUT_COMP GRSTATR_PKTSTS(3) +#define GRSTATR_SETUP_COMP GRSTATR_PKTSTS(4) +#define GRSTATR_SETUP_DATA GRSTATR_PKTSTS(6) +#define GRSTATR_DPID_MASK (3U<<15) /**< Data PID mask. */ +#define GRSTATR_DPID(n) ((n)<<15) /**< Data PID value. */ +#define GRSTATR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ +#define GRSTATR_BCNT(n) ((n)<<4) /**< Byte count value. */ +#define GRSTATR_CHNUM_MASK (15U<<0) /**< Channel number mask. */ +#define GRSTATR_CHNUM(n) ((n)<<0) /**< Channel number value. */ +#define GRSTATR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ +#define GRSTATR_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ /** @} */ /** - * @name GRXSTSP register bit definitions + * @name GRSTATP register bit definitions * @{ */ -#define GRXSTSP_PKTSTS_MASK (15<<17) /**< Packet status mask. */ -#define GRXSTSP_PKTSTS(n) ((n)<<17) /**< Packet status value. */ -#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1) -#define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2) -#define GRXSTSP_OUT_COMP GRXSTSP_PKTSTS(3) -#define GRXSTSP_SETUP_COMP GRXSTSP_PKTSTS(4) -#define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6) -#define GRXSTSP_DPID_MASK (3U<<15) /**< Data PID mask. */ -#define GRXSTSP_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ -#define GRXSTSP_BCNT_OFF 4 /**< Byte count offset. */ -#define GRXSTSP_BCNT(n) ((n)<<4) /**< Byte count value. */ -#define GRXSTSP_CHNUM_MASK (15U<<0) /**< Channel number mask. */ -#define GRXSTSP_CHNUM(n) ((n)<<0) /**< Channel number value. */ -#define GRXSTSP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ -#define GRXSTSP_EPNUM_OFF 0 /**< Endpoint number offset. */ -#define GRXSTSP_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ +#define GRSTATP_PKTSTS_MASK (15<<17) /**< Packet status mask. */ +#define GRSTATP_PKTSTS(n) ((n)<<17) /**< Packet status value. */ +#define GRSTATP_OUT_GLOBAL_NAK GRSTATP_PKTSTS(1) +#define GRSTATP_OUT_DATA GRSTATP_PKTSTS(2) +#define GRSTATP_OUT_COMP GRSTATP_PKTSTS(3) +#define GRSTATP_SETUP_COMP GRSTATP_PKTSTS(4) +#define GRSTATP_SETUP_DATA GRSTATP_PKTSTS(6) +#define GRSTATP_DPID_MASK (3U<<15) /**< Data PID mask. */ +#define GRSTATP_DPID(n) ((n)<<15) /**< Data PID value. */ +#define GRSTATP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ +#define GRSTATP_BCNT_OFF 4 /**< Byte count offset. */ +#define GRSTATP_BCNT(n) ((n)<<4) /**< Byte count value. */ +#define GRSTATP_CHNUM_MASK (15U<<0) /**< Channel number mask. */ +#define GRSTATP_CHNUM(n) ((n)<<0) /**< Channel number value. */ +#define GRSTATP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ +#define GRSTATP_EPNUM_OFF 0 /**< Endpoint number offset. */ +#define GRSTATP_EPNUM(n) ((n)<<0) /**< Endpoint number value. */ /** @} */ /** - * @name GRXFSIZ register bit definitions + * @name GRFLEN register bit definitions * @{ */ -#define GRXFSIZ_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */ -#define GRXFSIZ_RXFD(n) ((n)<<0) /**< RxFIFO depth value. */ +#define GRFLEN_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */ +#define GRFLEN_RXFD(n) ((n)<<0) /**< RxFIFO depth value. */ /** @} */ /** @@ -431,16 +426,16 @@ typedef struct { /** @} */ /** - * @name HPTXFSIZ register bit definitions + * @name HPTFLEN register bit definitions * @{ */ -#define HPTXFSIZ_PTXFD_MASK (0xFFFFU<<16)/**< Host periodic TxFIFO +#define HPTFLEN_PTXFD_MASK (0xFFFFU<<16)/**< Host periodic TxFIFO depth mask. */ -#define HPTXFSIZ_PTXFD(n) ((n)<<16) /**< Host periodic TxFIFO +#define HPTFLEN_PTXFD(n) ((n)<<16) /**< Host periodic TxFIFO depth value. */ -#define HPTXFSIZ_PTXSA_MASK (0xFFFFU<<0)/**< Host periodic TxFIFO +#define HPTFLEN_PTXSA_MASK (0xFFFFU<<0)/**< Host periodic TxFIFO Start address mask. */ -#define HPTXFSIZ_PTXSA(n) ((n)<<0) /**< Host periodic TxFIFO +#define HPTFLEN_PTXSA(n) ((n)<<0) /**< Host periodic TxFIFO start address value. */ /** @} */ diff --git a/os/hal/ports/GD/GD32VF103/OTG/hal_usb_lld.c b/os/hal/ports/GD/GD32VF103/OTG/hal_usb_lld.c index 1dd09c70..6de2510f 100644 --- a/os/hal/ports/GD/GD32VF103/OTG/hal_usb_lld.c +++ b/os/hal/ports/GD/GD32VF103/OTG/hal_usb_lld.c @@ -65,11 +65,6 @@ USBDriver USBD1; #endif -/** @brief OTG_HS driver identifier.*/ -#if GD32_USB_USE_OTG2 || defined(__DOXYGEN__) -USBDriver USBD2; -#endif - /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -119,14 +114,6 @@ static const gd32_otg_params_t fsparams = { }; #endif -#if GD32_USB_USE_OTG2 -static const gd32_otg_params_t hsparams = { - GD32_USB_OTG2_RX_FIFO_SIZE / 4, - GD32_OTG2_FIFO_MEM_SIZE, - GD32_OTG2_ENDPOINTS -}; -#endif - /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ @@ -286,20 +273,20 @@ static void otg_rxfifo_handler(USBDriver *usbp) { uint32_t sts, cnt, ep; /* Popping the event word out of the RX FIFO.*/ - sts = usbp->otg->GRXSTSP; + sts = usbp->otg->GRSTATP; /* Event details.*/ - cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF; - ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF; + cnt = (sts & GRSTATP_BCNT_MASK) >> GRSTATP_BCNT_OFF; + ep = (sts & GRSTATP_EPNUM_MASK) >> GRSTATP_EPNUM_OFF; - switch (sts & GRXSTSP_PKTSTS_MASK) { - case GRXSTSP_SETUP_DATA: + switch (sts & GRSTATP_PKTSTS_MASK) { + case GRSTATP_SETUP_DATA: otg_fifo_read_to_buffer(usbp->otg->FIFO[0], usbp->epc[ep]->setup_buf, cnt, 8); break; - case GRXSTSP_SETUP_COMP: + case GRSTATP_SETUP_COMP: break; - case GRXSTSP_OUT_DATA: + case GRSTATP_OUT_DATA: otg_fifo_read_to_buffer(usbp->otg->FIFO[0], usbp->epc[ep]->out_state->rxbuf, cnt, @@ -308,9 +295,9 @@ static void otg_rxfifo_handler(USBDriver *usbp) { usbp->epc[ep]->out_state->rxbuf += cnt; usbp->epc[ep]->out_state->rxcnt += cnt; break; - case GRXSTSP_OUT_COMP: + case GRSTATP_OUT_COMP: break; - case GRXSTSP_OUT_GLOBAL_NAK: + case GRSTATP_OUT_GLOBAL_NAK: break; default: break; @@ -537,12 +524,12 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) { gd32_otg_t *otgp = usbp->otg; uint32_t sts, src; - sts = otgp->GINTSTS; - sts &= otgp->GINTMSK; - otgp->GINTSTS = sts; + sts = otgp->GINTF; + sts &= otgp->GINTEN; + otgp->GINTF = sts; /* Reset interrupt handling.*/ - if (sts & GINTSTS_USBRST) { + if (sts & GINTF_USBRST) { /* Default reset action.*/ _usb_reset(usbp); @@ -551,7 +538,7 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) { } /* Wake-up handling.*/ - if (sts & GINTSTS_WKUPINT) { + if (sts & GINTF_WKUPINT) { /* If clocks are gated off, turn them back on (may be the case if coming out of suspend mode).*/ if (otgp->PCGCCTL & (PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK)) { @@ -566,7 +553,7 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) { } /* Suspend handling.*/ - if (sts & GINTSTS_USBSUSP) { + if (sts & GINTF_USBSUSP) { /* Stopping all ongoing transfers.*/ otg_disable_ep(usbp); @@ -575,42 +562,42 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) { } /* Enumeration done.*/ - if (sts & GINTSTS_ENUMDNE) { + if (sts & GINTF_ENUMDNE) { /* Full or High speed timing selection.*/ if ((otgp->DSTS & DSTS_ENUMSPD_MASK) == DSTS_ENUMSPD_HS_480) { - otgp->GUSBCFG = (otgp->GUSBCFG & ~(GUSBCFG_TRDT_MASK)) | - GUSBCFG_TRDT(TRDT_VALUE_HS); + otgp->GUSBCS = (otgp->GUSBCS & ~(GUSBCS_TRDT_MASK)) | + GUSBCS_TRDT(TRDT_VALUE_HS); } else { - otgp->GUSBCFG = (otgp->GUSBCFG & ~(GUSBCFG_TRDT_MASK)) | - GUSBCFG_TRDT(TRDT_VALUE_FS); + otgp->GUSBCS = (otgp->GUSBCS & ~(GUSBCS_TRDT_MASK)) | + GUSBCS_TRDT(TRDT_VALUE_FS); } } /* SOF interrupt handling.*/ - if (sts & GINTSTS_SOF) { + if (sts & GINTF_SOF) { _usb_isr_invoke_sof_cb(usbp); } /* Isochronous IN failed handling */ - if (sts & GINTSTS_IISOIXFR) { + if (sts & GINTF_IISOIXFR) { otg_isoc_in_failed_handler(usbp); } /* Isochronous OUT failed handling */ - if (sts & GINTSTS_IISOOXFR) { + if (sts & GINTF_IISOOXFR) { otg_isoc_out_failed_handler(usbp); } /* Performing the whole FIFO emptying in the ISR, it is advised to keep this IRQ at a very low priority level.*/ - if ((sts & GINTSTS_RXFLVL) != 0U) { + if ((sts & GINTF_RXFLVL) != 0U) { otg_rxfifo_handler(usbp); } /* IN/OUT endpoints event handling.*/ src = otgp->DAINT; - if (sts & GINTSTS_OEPINT) { + if (sts & GINTF_OEPINT) { if (src & (1 << 16)) otg_epout_handler(usbp, 0); if (src & (1 << 17)) @@ -619,28 +606,8 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) { otg_epout_handler(usbp, 2); if (src & (1 << 19)) otg_epout_handler(usbp, 3); -#if USB_MAX_ENDPOINTS >= 4 - if (src & (1 << 20)) - otg_epout_handler(usbp, 4); -#endif -#if USB_MAX_ENDPOINTS >= 5 - if (src & (1 << 21)) - otg_epout_handler(usbp, 5); -#endif -#if USB_MAX_ENDPOINTS >= 6 - if (src & (1 << 22)) - otg_epout_handler(usbp, 6); -#endif -#if USB_MAX_ENDPOINTS >= 7 - if (src & (1 << 23)) - otg_epout_handler(usbp, 7); -#endif -#if USB_MAX_ENDPOINTS >= 8 - if (src & (1 << 24)) - otg_epout_handler(usbp, 8); -#endif } - if (sts & GINTSTS_IEPINT) { + if (sts & GINTF_IEPINT) { if (src & (1 << 0)) otg_epin_handler(usbp, 0); if (src & (1 << 1)) @@ -649,26 +616,6 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) { otg_epin_handler(usbp, 2); if (src & (1 << 3)) otg_epin_handler(usbp, 3); -#if USB_MAX_ENDPOINTS >= 4 - if (src & (1 << 4)) - otg_epin_handler(usbp, 4); -#endif -#if USB_MAX_ENDPOINTS >= 5 - if (src & (1 << 5)) - otg_epin_handler(usbp, 5); -#endif -#if USB_MAX_ENDPOINTS >= 6 - if (src & (1 << 6)) - otg_epin_handler(usbp, 6); -#endif -#if USB_MAX_ENDPOINTS >= 7 - if (src & (1 << 7)) - otg_epin_handler(usbp, 7); -#endif -#if USB_MAX_ENDPOINTS >= 8 - if (src & (1 << 8)) - otg_epin_handler(usbp, 8); -#endif } } @@ -692,22 +639,6 @@ OSAL_IRQ_HANDLER(GD32_OTG1_HANDLER) { } #endif -#if GD32_USB_USE_OTG2 || defined(__DOXYGEN__) -/** - * @brief OTG2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(GD32_OTG2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - usb_lld_serve_interrupt(&USBD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif - /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -720,18 +651,9 @@ OSAL_IRQ_HANDLER(GD32_OTG2_HANDLER) { void usb_lld_init(void) { /* Driver initialization.*/ -#if GD32_USB_USE_OTG1 usbObjectInit(&USBD1); USBD1.otg = OTG_FS; USBD1.otgparams = &fsparams; - -#endif - -#if GD32_USB_USE_OTG2 - usbObjectInit(&USBD2); - USBD2.otg = OTG_HS; - USBD2.otgparams = &hsparams; -#endif } /** @@ -750,98 +672,36 @@ void usb_lld_start(USBDriver *usbp) { if (usbp->state == USB_STOP) { /* Clock activation.*/ -#if GD32_USB_USE_OTG1 - if (&USBD1 == usbp) { - /* OTG FS clock enable and reset.*/ - rccEnableOTG_FS(true); - rccResetOTG_FS(); + if (&USBD1 == usbp) { + /* OTG FS clock enable and reset.*/ + rccEnableOTG_FS(true); + rccResetOTG_FS(); - /* Enables IRQ vector.*/ - eclicEnableVector(GD32_OTG1_NUMBER, GD32_USB_OTG1_IRQ_PRIORITY, GD32_USB_OTG1_IRQ_TRIGGER); + /* Enables IRQ vector.*/ + eclicEnableVector(GD32_OTG1_NUMBER, GD32_USB_OTG1_IRQ_PRIORITY, GD32_USB_OTG1_IRQ_TRIGGER); - /* - Forced device mode. - - USB turn-around time = TRDT_VALUE_FS. - - Full Speed 1.1 PHY.*/ - otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_FS) | - GUSBCFG_PHYSEL; + /* - Forced device mode. + - USB turn-around time = TRDT_VALUE_FS. + - Full Speed 1.1 PHY.*/ + otgp->GUSBCS = GUSBCS_FDMOD | GUSBCS_TRDT(TRDT_VALUE_FS) | + GUSBCS_PHYSEL; - /* 48MHz 1.1 PHY.*/ - otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11; - } -#endif - -#if GD32_USB_USE_OTG2 - if (&USBD2 == usbp) { - /* OTG HS clock enable and reset.*/ - rccEnableOTG_HS(true); - rccResetOTG_HS(); - - /* ULPI clock is managed depending on the presence of an external - PHY.*/ -#if defined(BOARD_OTG2_USES_ULPI) - rccEnableOTG_HSULPI(true); -#else - /* Workaround for the problem described here: - http://forum.chibios.org/phpbb/viewtopic.php?f=16&t=1798.*/ - rccDisableOTG_HSULPI(); -#endif - - /* Enables IRQ vector.*/ - eclicEnableVector(GD32_OTG2_NUMBER, GD32_USB_OTG2_IRQ_PRIORITY, GD32_USB_OTG2_IRQ_TRIGGER); - - /* - Forced device mode. - - USB turn-around time = TRDT_VALUE_HS or TRDT_VALUE_FS.*/ -#if defined(BOARD_OTG2_USES_ULPI) - /* High speed ULPI PHY.*/ - otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_HS) | - GUSBCFG_SRPCAP | GUSBCFG_HNPCAP; -#else - otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_FS) | - GUSBCFG_PHYSEL; -#endif - -#if defined(BOARD_OTG2_USES_ULPI) -#if GD32_USE_USB_OTG2_HS - /* USB 2.0 High Speed PHY in HS mode.*/ - otgp->DCFG = 0x02200000 | DCFG_DSPD_HS; -#else - /* USB 2.0 High Speed PHY in FS mode.*/ - otgp->DCFG = 0x02200000 | DCFG_DSPD_HS_FS; -#endif -#else - /* 48MHz 1.1 PHY.*/ - otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11; -#endif - } -#endif + /* 48MHz 1.1 PHY.*/ + otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11; + } /* PHY enabled.*/ otgp->PCGCCTL = 0; /* VBUS sensing and transceiver enabled.*/ - otgp->GOTGCTL = GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL; - -#if defined(BOARD_OTG2_USES_ULPI) -#if GD32_USB_USE_OTG1 - if (&USBD1 == usbp) { - otgp->GCCFG = GCCFG_INIT_VALUE; - } -#endif - -#if GD32_USB_USE_OTG2 - if (&USBD2 == usbp) { - otgp->GCCFG = 0; - } -#endif -#else + otgp->GOTGCS = GOTGCS_BVALOEN | GOTGCS_BVALOVAL; otgp->GCCFG = GCCFG_INIT_VALUE; -#endif /* Soft core reset.*/ otg_core_reset(usbp); /* Interrupts on TXFIFOs half empty.*/ - otgp->GAHBCFG = 0; + otgp->GAHBCS = 0; /* Endpoints re-initialization.*/ otg_disable_ep(usbp); @@ -852,20 +712,20 @@ void usb_lld_start(USBDriver *usbp) { otgp->DOEPMSK = 0; otgp->DAINTMSK = 0; if (usbp->config->sof_cb == NULL) - otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM | GINTMSK_USBSUSPM | - GINTMSK_ESUSPM | GINTMSK_SRQM | GINTMSK_WKUM | - GINTMSK_IISOIXFRM | GINTMSK_IISOOXFRM; + otgp->GINTEN = GINTEN_ENUMDNEM | GINTEN_USBRSTM | GINTEN_USBSUSPM | + GINTEN_ESUSPM | GINTEN_SRQM | GINTEN_WKUM | + GINTEN_IISOIXFRM | GINTEN_IISOOXFRM; else - otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM | GINTMSK_USBSUSPM | - GINTMSK_ESUSPM | GINTMSK_SRQM | GINTMSK_WKUM | - GINTMSK_IISOIXFRM | GINTMSK_IISOOXFRM | - GINTMSK_SOFM; + otgp->GINTEN = GINTEN_ENUMDNEM | GINTEN_USBRSTM | GINTEN_USBSUSPM | + GINTEN_ESUSPM | GINTEN_SRQM | GINTEN_WKUM | + GINTEN_IISOIXFRM | GINTEN_IISOOXFRM | + GINTEN_SOFM; /* Clears all pending IRQs, if any. */ - otgp->GINTSTS = 0xFFFFFFFF; + otgp->GINTF = 0xFFFFFFFF; /* Global interrupts enable.*/ - otgp->GAHBCFG |= GAHBCFG_GINTMSK; + otgp->GAHBCS |= GAHBCS_GINTEN; } } @@ -887,25 +747,13 @@ void usb_lld_stop(USBDriver *usbp) { otg_disable_ep(usbp); otgp->DAINTMSK = 0; - otgp->GAHBCFG = 0; + otgp->GAHBCS = 0; otgp->GCCFG = 0; -#if GD32_USB_USE_OTG1 if (&USBD1 == usbp) { eclicDisableVector(GD32_OTG1_NUMBER); rccDisableOTG_FS(); } -#endif - -#if GD32_USB_USE_OTG2 - if (&USBD2 == usbp) { - eclicDisableVector(GD32_OTG2_NUMBER); - rccDisableOTG_HS(); -#if defined(BOARD_OTG2_USES_ULPI) - rccDisableOTG_HSULPI() -#endif - } -#endif } } @@ -939,14 +787,14 @@ void usb_lld_reset(USBDriver *usbp) { otg_ram_reset(usbp); /* Receive FIFO size initialization, the address is always zero.*/ - otgp->GRXFSIZ = usbp->otgparams->rx_fifo_size; + otgp->GRFLEN = usbp->otgparams->rx_fifo_size; otg_rxfifo_flush(usbp); /* Resets the device address to zero.*/ otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(0); /* Enables also EP-related interrupt sources.*/ - otgp->GINTMSK |= GINTMSK_RXFLVLM | GINTMSK_OEPM | GINTMSK_IEPM; + otgp->GINTEN |= GINTEN_RXFLVLM | GINTEN_OEPM | GINTEN_IEPM; otgp->DIEPMSK = DIEPMSK_TOCM | DIEPMSK_XFRCM; otgp->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM; diff --git a/os/hal/ports/GD/GD32VF103/OTG/hal_usb_lld.h b/os/hal/ports/GD/GD32VF103/OTG/hal_usb_lld.h index 8d8e380a..bd4ed2d3 100644 --- a/os/hal/ports/GD/GD32VF103/OTG/hal_usb_lld.h +++ b/os/hal/ports/GD/GD32VF103/OTG/hal_usb_lld.h @@ -61,15 +61,6 @@ #define GD32_USB_USE_OTG1 FALSE #endif -/** - * @brief OTG2 driver enable switch. - * @details If set to @p TRUE the support for OTG_HS is included. - * @note The default is @p FALSE. - */ -#if !defined(GD32_USB_USE_OTG2) || defined(__DOXYGEN__) -#define GD32_USB_USE_OTG2 FALSE -#endif - /** * @brief OTG1 interrupt priority level setting. */ @@ -77,13 +68,6 @@ #define GD32_USB_OTG1_IRQ_PRIORITY 1 #endif -/** - * @brief OTG2 interrupt priority level setting. - */ -#if !defined(GD32_USB_OTG2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define GD32_USB_OTG2_IRQ_PRIORITY 1 -#endif - /** * @brief OTG1 RX shared FIFO size. * @note Must be a multiple of 4. @@ -92,23 +76,6 @@ #define GD32_USB_OTG1_RX_FIFO_SIZE 128 #endif -/** - * @brief OTG2 RX shared FIFO size. - * @note Must be a multiple of 4. - */ -#if !defined(GD32_USB_OTG2_RX_FIFO_SIZE) || defined(__DOXYGEN__) -#define GD32_USB_OTG2_RX_FIFO_SIZE 1024 -#endif - -/** - * @brief Enables HS mode on OTG2 else FS mode. - * @note The default is @p TRUE. - * @note Has effect only if @p BOARD_OTG2_USES_ULPI is defined. - */ -#if !defined(GD32_USE_USB_OTG2_HS) || defined(__DOXYGEN__) -#define GD32_USE_USB_OTG2_HS TRUE -#endif - /** * @brief Exception priority level during TXFIFOs operations. * @note Because an undocumented silicon behavior the operation of @@ -148,59 +115,32 @@ #error "unsupported GD32_OTG_STEPPING" #endif -#define GD32_HAS_OTG2 FALSE -#if !defined(GD32_HAS_OTG1) || !defined(GD32_HAS_OTG2) -#error "GD32_HAS_OTGx not defined in registry" -#endif - #if GD32_HAS_OTG1 && !defined(GD32_OTG1_ENDPOINTS) #error "GD32_OTG1_ENDPOINTS not defined in registry" #endif -#if GD32_HAS_OTG2 && !defined(GD32_OTG2_ENDPOINTS) -#error "GD32_OTG2_ENDPOINTS not defined in registry" -#endif - #if GD32_HAS_OTG1 && !defined(GD32_OTG1_FIFO_MEM_SIZE) #error "GD32_OTG1_FIFO_MEM_SIZE not defined in registry" #endif -#if GD32_HAS_OTG2 && !defined(GD32_OTG2_FIFO_MEM_SIZE) -#error "GD32_OTG2_FIFO_MEM_SIZE not defined in registry" -#endif - -#if (GD32_USB_USE_OTG1 && !defined(GD32_OTG1_HANDLER)) || \ - (GD32_USB_USE_OTG2 && !defined(GD32_OTG2_HANDLER)) +#if (GD32_USB_USE_OTG1 && !defined(GD32_OTG1_HANDLER)) #error "GD32_OTGx_HANDLER not defined in registry" #endif -#if (GD32_USB_USE_OTG1 && !defined(GD32_OTG1_NUMBER)) || \ - (GD32_USB_USE_OTG2 && !defined(GD32_OTG2_NUMBER)) +#if (GD32_USB_USE_OTG1 && !defined(GD32_OTG1_NUMBER)) #error "GD32_OTGx_NUMBER not defined in registry" #endif /** * @brief Maximum endpoint address. */ -#if (GD32_HAS_OTG2 && GD32_USB_USE_OTG2) || defined(__DOXYGEN__) -#if (GD32_OTG1_ENDPOINTS < GD32_OTG2_ENDPOINTS) || defined(__DOXYGEN__) -#define USB_MAX_ENDPOINTS GD32_OTG2_ENDPOINTS -#else #define USB_MAX_ENDPOINTS GD32_OTG1_ENDPOINTS -#endif -#else -#define USB_MAX_ENDPOINTS GD32_OTG1_ENDPOINTS -#endif #if GD32_USB_USE_OTG1 && !GD32_HAS_OTG1 #error "OTG1 not present in the selected device" #endif -#if GD32_USB_USE_OTG2 && !GD32_HAS_OTG2 -#error "OTG2 not present in the selected device" -#endif - -#if !GD32_USB_USE_OTG1 && !GD32_USB_USE_OTG2 +#if !GD32_USB_USE_OTG1 #error "USB driver activated but no USB peripheral assigned" #endif @@ -209,38 +149,11 @@ #error "Invalid IRQ priority assigned to OTG1" #endif -#if GD32_USB_USE_OTG2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(GD32_USB_OTG2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to OTG2" -#endif - #if (GD32_USB_OTG1_RX_FIFO_SIZE & 3) != 0 #error "OTG1 RX FIFO size must be a multiple of 4" #endif -#if (GD32_USB_OTG2_RX_FIFO_SIZE & 3) != 0 -#error "OTG2 RX FIFO size must be a multiple of 4" -#endif - -/*#if defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX) -#define GD32_USBCLK GD32_PLL48CLK*/ -#if defined(STM32F10X_CL) || defined (GD32VF103CB) #define GD32_USBCLK GD32_OTGFSCLK -// #elif defined(STM32L4XX) || defined(STM32L4XXP) -// #define GD32_USBCLK GD32_48CLK -// #elif defined(STM32H7XX) -// /* Defines directly GD32_USBCLK.*/ -// #define rccEnableOTG_FS rccEnableUSB2_OTG_HS -// #define rccDisableOTG_FS rccDisableUSB2_OTG_HS -// #define rccResetOTG_FS rccResetUSB2_OTG_HS -// #define rccEnableOTG_HS rccEnableUSB1_OTG_HS -// #define rccDisableOTG_HS rccDisableUSB1_OTG_HS -// #define rccResetOTG_HS rccResetUSB1_OTG_HS -// #define rccEnableOTG_HSULPI rccEnableUSB1_HSULPI -// #define rccDisableOTG_HSULPI rccDisableUSB1_HSULPI -#else -#error "unsupported STM32 platform for OTG functionality" -#endif /* Allowing for a small tolerance.*/ #if GD32_USBCLK < 47880000 || GD32_USBCLK > 48120000 @@ -571,10 +484,6 @@ struct USBDriver { extern USBDriver USBD1; #endif -#if GD32_USB_USE_OTG2 && !defined(__DOXYGEN__) -extern USBDriver USBD2; -#endif - #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/ports/GD/GD32VF103/gd32_isr.h b/os/hal/ports/GD/GD32VF103/gd32_isr.h index ee36b857..03343d42 100644 --- a/os/hal/ports/GD/GD32VF103/gd32_isr.h +++ b/os/hal/ports/GD/GD32VF103/gd32_isr.h @@ -288,7 +288,6 @@ #define GD32_UART_USART3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_UART_USART6_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT #define GD32_USB_OTG1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT -#define GD32_USB_OTG2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/ports/GD/GD32VF103/stm32f105xc.h b/os/hal/ports/GD/GD32VF103/stm32f105xc.h index e31d7a20..c0f5bdb2 100644 --- a/os/hal/ports/GD/GD32VF103/stm32f105xc.h +++ b/os/hal/ports/GD/GD32VF103/stm32f105xc.h @@ -554,23 +554,23 @@ typedef struct typedef struct { - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset: 000h */ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset: 004h */ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset: 008h */ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset: 00Ch */ + __IO uint32_t GOTGCS; /*!< USB_OTG Control and Status Register Address offset: 000h */ + __IO uint32_t GOTGINTF; /*!< USB_OTG Interrupt Register Address offset: 004h */ + __IO uint32_t GAHBCS; /*!< Core AHB Configuration Register Address offset: 008h */ + __IO uint32_t GUSBCS; /*!< Core USB Configuration Register Address offset: 00Ch */ __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset: 010h */ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset: 014h */ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset: 018h */ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset: 01Ch */ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset: 020h */ - __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register Address offset: 024h */ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */ + __IO uint32_t GINTF; /*!< Core Interrupt Register Address offset: 014h */ + __IO uint32_t GINTEN; /*!< Core Interrupt Mask Register Address offset: 018h */ + __IO uint32_t GRSTATR; /*!< Receive Sts Q Read Register Address offset: 01Ch */ + __IO uint32_t GRSTATP; /*!< Receive Sts Q Read & POP Register Address offset: 020h */ + __IO uint32_t GRFLEN; /*!< Receive FIFO Size Register Address offset: 024h */ + __IO uint32_t HNPTFLEN_DIEP0TFLEN; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */ + __IO uint32_t HNPTFQSTAT; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */ uint32_t Reserved30[2]; /*!< Reserved 030h*/ __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */ __IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */ uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ - __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */ + __IO uint32_t HPTFLEN; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */ } USB_OTG_GlobalTypeDef; @@ -12570,39 +12570,39 @@ typedef struct /* */ /******************************************************************************/ -/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/ -#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) -#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ -#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ -#define USB_OTG_GOTGCTL_SRQ_Pos (1U) -#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ -#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ -#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) -#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ -#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host negotiation success */ -#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) -#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ -#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ -#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) -#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ -#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ -#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) -#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ -#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ -#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) -#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ -#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ -#define USB_OTG_GOTGCTL_DBCT_Pos (17U) -#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ -#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ -#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) -#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ -#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ -#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +/******************** Bit definition for USBFS_GOTGCS register ********************/ +#define USBFS_GOTGCS_SRPS_Pos (0U) +#define USBFS_GOTGCS_SRPS_Msk (0x1U << USBFS_GOTGCS_SRPS_Pos) /*!< 0x00000001 */ +#define USBFS_GOTGCS_SRPS USBFS_GOTGCS_SRPS_Msk /*!< Session request success */ +#define USBFS_GOTGCS_SRPREQ_Pos (1U) +#define USBFS_GOTGCS_SRPREQ_Msk (0x1U << USBFS_GOTGCS_SRPREQ_Pos) /*!< 0x00000002 */ +#define USBFS_GOTGCS_SRPREQ USBFS_GOTGCS_SRPREQ_Msk /*!< Session request */ +#define USBFS_GOTGCS_HNPS_Pos (8U) +#define USBFS_GOTGCS_HNPS_Msk (0x1U << USBFS_GOTGCS_HNPS_Pos) /*!< 0x00000100 */ +#define USBFS_GOTGCS_HNPS USBFS_GOTGCS_HNPS_Msk /*!< Host negotiation success */ +#define USBFS_GOTGCS_HNPREQ_Pos (9U) +#define USBFS_GOTGCS_HNPREQ_Msk (0x1U << USBFS_GOTGCS_HNPREQ_Pos) /*!< 0x00000200 */ +#define USBFS_GOTGCS_HNPREQ USBFS_GOTGCS_HNPREQ_Msk /*!< HNP request */ +#define USBFS_GOTGCS_HHNPEN_Pos (10U) +#define USBFS_GOTGCS_HHNPEN_Msk (0x1U << USBFS_GOTGCS_HHNPEN_Pos) /*!< 0x00000400 */ +#define USBFS_GOTGCS_HHNPEN USBFS_GOTGCS_HHNPEN_Msk /*!< Host set HNP enable */ +#define USBFS_GOTGCS_DHNPEN_Pos (11U) +#define USBFS_GOTGCS_DHNPEN_Msk (0x1U << USBFS_GOTGCS_DHNPEN_Pos) /*!< 0x00000800 */ +#define USBFS_GOTGCS_DHNPEN USBFS_GOTGCS_DHNPEN_Msk /*!< Device HNP enabled */ +#define USBFS_GOTGCS_IDPS_Pos (16U) +#define USBFS_GOTGCS_IDPS_Msk (0x1U << USBFS_GOTGCS_IDPS_Pos) /*!< 0x00010000 */ +#define USBFS_GOTGCS_IDPS USBFS_GOTGCS_IDPS_Msk /*!< Connector ID status */ +#define USBFS_GOTGCS_DI_Pos (17U) +#define USBFS_GOTGCS_DI_Msk (0x1U << USBFS_GOTGCS_DI_Pos) /*!< 0x00020000 */ +#define USBFS_GOTGCS_DI USBFS_GOTGCS_DI_Msk /*!< Long/short debounce time */ +#define USBFS_GOTGCS_ASV_Pos (18U) +#define USBFS_GOTGCS_ASV_Msk (0x1U << USBFS_GOTGCS_ASV_Pos) /*!< 0x00040000 */ +#define USBFS_GOTGCS_ASV USBFS_GOTGCS_ASV_Msk /*!< A-session valid */ +#define USBFS_GOTGCS_BSV_Pos (19U) +#define USBFS_GOTGCS_BSV_Msk (0x1U << USBFS_GOTGCS_BSV_Pos) /*!< 0x00080000 */ +#define USBFS_GOTGCS_BSV USBFS_GOTGCS_BSV_Msk /*!< B-session valid */ -/******************** Bit definition forUSB_OTG_HCFG register ********************/ +/******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ @@ -12613,7 +12613,7 @@ typedef struct #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ -/******************** Bit definition forUSB_OTG_DCFG register ********************/ +/******************** Bit definition for USB_OTG_DCFG register ********************/ #define USB_OTG_DCFG_DSPD_Pos (0U) #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ @@ -12658,25 +12658,25 @@ typedef struct #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ -/******************** Bit definition forUSB_OTG_GOTGINT register ******************/ -#define USB_OTG_GOTGINT_SEDET_Pos (2U) -#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ -#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ -#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) -#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ -#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ -#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) -#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ -#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ -#define USB_OTG_GOTGINT_HNGDET_Pos (17U) -#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ -#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ -#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) -#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ -#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ -#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) -#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ +/******************** Bit definition forUSB_OTG_GOTGINTF register ******************/ +#define USB_OTG_GOTGINTF_SEDET_Pos (2U) +#define USB_OTG_GOTGINTF_SEDET_Msk (0x1U << USB_OTG_GOTGINTF_SEDET_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGINTF_SEDET USB_OTG_GOTGINTF_SEDET_Msk /*!< Session end detected */ +#define USB_OTG_GOTGINTF_SRSSCHG_Pos (8U) +#define USB_OTG_GOTGINTF_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINTF_SRSSCHG_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGINTF_SRSSCHG USB_OTG_GOTGINTF_SRSSCHG_Msk /*!< Session request success status change */ +#define USB_OTG_GOTGINTF_HNSSCHG_Pos (9U) +#define USB_OTG_GOTGINTF_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINTF_HNSSCHG_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGINTF_HNSSCHG USB_OTG_GOTGINTF_HNSSCHG_Msk /*!< Host negotiation success status change */ +#define USB_OTG_GOTGINTF_HNGDET_Pos (17U) +#define USB_OTG_GOTGINTF_HNGDET_Msk (0x1U << USB_OTG_GOTGINTF_HNGDET_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGINTF_HNGDET USB_OTG_GOTGINTF_HNGDET_Msk /*!< Host negotiation detected */ +#define USB_OTG_GOTGINTF_ADTOCHG_Pos (18U) +#define USB_OTG_GOTGINTF_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINTF_ADTOCHG_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGINTF_ADTOCHG USB_OTG_GOTGINTF_ADTOCHG_Msk /*!< A-device timeout change */ +#define USB_OTG_GOTGINTF_DBCDNE_Pos (19U) +#define USB_OTG_GOTGINTF_DBCDNE_Msk (0x1U << USB_OTG_GOTGINTF_DBCDNE_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGINTF_DBCDNE USB_OTG_GOTGINTF_DBCDNE_Msk /*!< Debounce done */ /******************** Bit definition forUSB_OTG_DCTL register ********************/ #define USB_OTG_DCTL_RWUSIG_Pos (0U) @@ -12744,93 +12744,93 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ -/******************** Bit definition forUSB_OTG_GAHBCFG register *****************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +/******************** Bit definition forUSB_OTG_GAHBCS register *****************/ +#define USB_OTG_GAHBCS_GINT_Pos (0U) +#define USB_OTG_GAHBCS_GINT_Msk (0x1U << USB_OTG_GAHBCS_GINT_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCS_GINT USB_OTG_GAHBCS_GINT_Msk /*!< Global interrupt mask */ -#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) -#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ -#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ -#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ -#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ -#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ -#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ -#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ -#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) -#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ -#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ -#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) -#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ -#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ -#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) -#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ -#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ +#define USB_OTG_GAHBCS_HBSTLEN_Pos (1U) +#define USB_OTG_GAHBCS_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCS_HBSTLEN_Pos) /*!< 0x0000001E */ +#define USB_OTG_GAHBCS_HBSTLEN USB_OTG_GAHBCS_HBSTLEN_Msk /*!< Burst length/type */ +#define USB_OTG_GAHBCS_HBSTLEN_0 (0x0U << USB_OTG_GAHBCS_HBSTLEN_Pos) /*!< Single */ +#define USB_OTG_GAHBCS_HBSTLEN_1 (0x1U << USB_OTG_GAHBCS_HBSTLEN_Pos) /*!< INCR */ +#define USB_OTG_GAHBCS_HBSTLEN_2 (0x3U << USB_OTG_GAHBCS_HBSTLEN_Pos) /*!< INCR4 */ +#define USB_OTG_GAHBCS_HBSTLEN_3 (0x5U << USB_OTG_GAHBCS_HBSTLEN_Pos) /*!< INCR8 */ +#define USB_OTG_GAHBCS_HBSTLEN_4 (0x7U << USB_OTG_GAHBCS_HBSTLEN_Pos) /*!< INCR16 */ +#define USB_OTG_GAHBCS_DMAEN_Pos (5U) +#define USB_OTG_GAHBCS_DMAEN_Msk (0x1U << USB_OTG_GAHBCS_DMAEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_GAHBCS_DMAEN USB_OTG_GAHBCS_DMAEN_Msk /*!< DMA enable */ +#define USB_OTG_GAHBCS_TXFELVL_Pos (7U) +#define USB_OTG_GAHBCS_TXFELVL_Msk (0x1U << USB_OTG_GAHBCS_TXFELVL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GAHBCS_TXFELVL USB_OTG_GAHBCS_TXFELVL_Msk /*!< TxFIFO empty level */ +#define USB_OTG_GAHBCS_PTXFELVL_Pos (8U) +#define USB_OTG_GAHBCS_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCS_PTXFELVL_Pos) /*!< 0x00000100 */ +#define USB_OTG_GAHBCS_PTXFELVL USB_OTG_GAHBCS_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ -/******************** Bit definition forUSB_OTG_GUSBCFG register *****************/ +/******************** Bit definition forUSB_OTG_GUSBCS register *****************/ -#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) -#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ -#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ -#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ -#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ -#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ -#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) -#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ -#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ -#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) -#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ -#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ -#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) -#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ -#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ +#define USB_OTG_GUSBCS_TOCAL_Pos (0U) +#define USB_OTG_GUSBCS_TOCAL_Msk (0x7U << USB_OTG_GUSBCS_TOCAL_Pos) /*!< 0x00000007 */ +#define USB_OTG_GUSBCS_TOCAL USB_OTG_GUSBCS_TOCAL_Msk /*!< FS timeout calibration */ +#define USB_OTG_GUSBCS_TOCAL_0 (0x1U << USB_OTG_GUSBCS_TOCAL_Pos) /*!< 0x00000001 */ +#define USB_OTG_GUSBCS_TOCAL_1 (0x2U << USB_OTG_GUSBCS_TOCAL_Pos) /*!< 0x00000002 */ +#define USB_OTG_GUSBCS_TOCAL_2 (0x4U << USB_OTG_GUSBCS_TOCAL_Pos) /*!< 0x00000004 */ +#define USB_OTG_GUSBCS_PHYSEL_Pos (6U) +#define USB_OTG_GUSBCS_PHYSEL_Msk (0x1U << USB_OTG_GUSBCS_PHYSEL_Pos) /*!< 0x00000040 */ +#define USB_OTG_GUSBCS_PHYSEL USB_OTG_GUSBCS_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define USB_OTG_GUSBCS_SRPCAP_Pos (8U) +#define USB_OTG_GUSBCS_SRPCAP_Msk (0x1U << USB_OTG_GUSBCS_SRPCAP_Pos) /*!< 0x00000100 */ +#define USB_OTG_GUSBCS_SRPCAP USB_OTG_GUSBCS_SRPCAP_Msk /*!< SRP-capable */ +#define USB_OTG_GUSBCS_HNPCAP_Pos (9U) +#define USB_OTG_GUSBCS_HNPCAP_Msk (0x1U << USB_OTG_GUSBCS_HNPCAP_Pos) /*!< 0x00000200 */ +#define USB_OTG_GUSBCS_HNPCAP USB_OTG_GUSBCS_HNPCAP_Msk /*!< HNP-capable */ -#define USB_OTG_GUSBCFG_TRDT_Pos (10U) -#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ -#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ -#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ -#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ -#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ -#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ -#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) -#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ -#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ -#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) -#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ -#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ -#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) -#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ -#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ -#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) -#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ -#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ -#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) -#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ -#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ -#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) -#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ -#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ -#define USB_OTG_GUSBCFG_PCCI_Pos (23U) -#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ -#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ -#define USB_OTG_GUSBCFG_PTCI_Pos (24U) -#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ -#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ -#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) -#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ -#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ -#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) -#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ -#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ -#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) -#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ -#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ -#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) -#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCS_TRDT_Pos (10U) +#define USB_OTG_GUSBCS_TRDT_Msk (0xFU << USB_OTG_GUSBCS_TRDT_Pos) /*!< 0x00003C00 */ +#define USB_OTG_GUSBCS_TRDT USB_OTG_GUSBCS_TRDT_Msk /*!< USB turnaround time */ +#define USB_OTG_GUSBCS_TRDT_0 (0x1U << USB_OTG_GUSBCS_TRDT_Pos) /*!< 0x00000400 */ +#define USB_OTG_GUSBCS_TRDT_1 (0x2U << USB_OTG_GUSBCS_TRDT_Pos) /*!< 0x00000800 */ +#define USB_OTG_GUSBCS_TRDT_2 (0x4U << USB_OTG_GUSBCS_TRDT_Pos) /*!< 0x00001000 */ +#define USB_OTG_GUSBCS_TRDT_3 (0x8U << USB_OTG_GUSBCS_TRDT_Pos) /*!< 0x00002000 */ +#define USB_OTG_GUSBCS_PHYLPCS_Pos (15U) +#define USB_OTG_GUSBCS_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCS_PHYLPCS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCS_PHYLPCS USB_OTG_GUSBCS_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCS_ULPIFSLS_Pos (17U) +#define USB_OTG_GUSBCS_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCS_ULPIFSLS_Pos) /*!< 0x00020000 */ +#define USB_OTG_GUSBCS_ULPIFSLS USB_OTG_GUSBCS_ULPIFSLS_Msk /*!< ULPI FS/LS select */ +#define USB_OTG_GUSBCS_ULPIAR_Pos (18U) +#define USB_OTG_GUSBCS_ULPIAR_Msk (0x1U << USB_OTG_GUSBCS_ULPIAR_Pos) /*!< 0x00040000 */ +#define USB_OTG_GUSBCS_ULPIAR USB_OTG_GUSBCS_ULPIAR_Msk /*!< ULPI Auto-resume */ +#define USB_OTG_GUSBCS_ULPICSM_Pos (19U) +#define USB_OTG_GUSBCS_ULPICSM_Msk (0x1U << USB_OTG_GUSBCS_ULPICSM_Pos) /*!< 0x00080000 */ +#define USB_OTG_GUSBCS_ULPICSM USB_OTG_GUSBCS_ULPICSM_Msk /*!< ULPI Clock SuspendM */ +#define USB_OTG_GUSBCS_ULPIEVBUSD_Pos (20U) +#define USB_OTG_GUSBCS_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCS_ULPIEVBUSD_Pos) /*!< 0x00100000 */ +#define USB_OTG_GUSBCS_ULPIEVBUSD USB_OTG_GUSBCS_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ +#define USB_OTG_GUSBCS_ULPIEVBUSI_Pos (21U) +#define USB_OTG_GUSBCS_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCS_ULPIEVBUSI_Pos) /*!< 0x00200000 */ +#define USB_OTG_GUSBCS_ULPIEVBUSI USB_OTG_GUSBCS_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ +#define USB_OTG_GUSBCS_TSDPS_Pos (22U) +#define USB_OTG_GUSBCS_TSDPS_Msk (0x1U << USB_OTG_GUSBCS_TSDPS_Pos) /*!< 0x00400000 */ +#define USB_OTG_GUSBCS_TSDPS USB_OTG_GUSBCS_TSDPS_Msk /*!< TermSel DLine pulsing selection */ +#define USB_OTG_GUSBCS_PCCI_Pos (23U) +#define USB_OTG_GUSBCS_PCCI_Msk (0x1U << USB_OTG_GUSBCS_PCCI_Pos) /*!< 0x00800000 */ +#define USB_OTG_GUSBCS_PCCI USB_OTG_GUSBCS_PCCI_Msk /*!< Indicator complement */ +#define USB_OTG_GUSBCS_PTCI_Pos (24U) +#define USB_OTG_GUSBCS_PTCI_Msk (0x1U << USB_OTG_GUSBCS_PTCI_Pos) /*!< 0x01000000 */ +#define USB_OTG_GUSBCS_PTCI USB_OTG_GUSBCS_PTCI_Msk /*!< Indicator pass through */ +#define USB_OTG_GUSBCS_ULPIIPD_Pos (25U) +#define USB_OTG_GUSBCS_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCS_ULPIIPD_Pos) /*!< 0x02000000 */ +#define USB_OTG_GUSBCS_ULPIIPD USB_OTG_GUSBCS_ULPIIPD_Msk /*!< ULPI interface protect disable */ +#define USB_OTG_GUSBCS_FHMOD_Pos (29U) +#define USB_OTG_GUSBCS_FHMOD_Msk (0x1U << USB_OTG_GUSBCS_FHMOD_Pos) /*!< 0x20000000 */ +#define USB_OTG_GUSBCS_FHMOD USB_OTG_GUSBCS_FHMOD_Msk /*!< Forced host mode */ +#define USB_OTG_GUSBCS_FDMOD_Pos (30U) +#define USB_OTG_GUSBCS_FDMOD_Msk (0x1U << USB_OTG_GUSBCS_FDMOD_Pos) /*!< 0x40000000 */ +#define USB_OTG_GUSBCS_FDMOD USB_OTG_GUSBCS_FDMOD_Msk /*!< Forced peripheral mode */ +#define USB_OTG_GUSBCS_CTXPKT_Pos (31U) +#define USB_OTG_GUSBCS_CTXPKT_Msk (0x1U << USB_OTG_GUSBCS_CTXPKT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GUSBCS_CTXPKT USB_OTG_GUSBCS_CTXPKT_Msk /*!< Corrupt Tx packet */ /******************** Bit definition forUSB_OTG_GRSTCTL register *****************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U) @@ -12947,165 +12947,165 @@ typedef struct #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ -/******************** Bit definition forUSB_OTG_GINTSTS register *****************/ -#define USB_OTG_GINTSTS_CMOD_Pos (0U) -#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ -#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ -#define USB_OTG_GINTSTS_MMIS_Pos (1U) -#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ -#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ -#define USB_OTG_GINTSTS_OTGINT_Pos (2U) -#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ -#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ -#define USB_OTG_GINTSTS_SOF_Pos (3U) -#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ -#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ -#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) -#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ -#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ -#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) -#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ -#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ -#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) -#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ -#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ -#define USB_OTG_GINTSTS_ESUSP_Pos (10U) -#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ -#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ -#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) -#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ -#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ -#define USB_OTG_GINTSTS_USBRST_Pos (12U) -#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ -#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ -#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) -#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ -#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ -#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) -#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ -#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ -#define USB_OTG_GINTSTS_EOPF_Pos (15U) -#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ -#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ -#define USB_OTG_GINTSTS_IEPINT_Pos (18U) -#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ -#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ -#define USB_OTG_GINTSTS_OEPINT_Pos (19U) -#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ -#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ -#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) -#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ -#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ -#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) -#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ -#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ -#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) -#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ -#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ -#define USB_OTG_GINTSTS_HCINT_Pos (25U) -#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ -#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ -#define USB_OTG_GINTSTS_PTXFE_Pos (26U) -#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ -#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ -#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) -#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ -#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ -#define USB_OTG_GINTSTS_DISCINT_Pos (29U) -#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ -#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ -#define USB_OTG_GINTSTS_SRQINT_Pos (30U) -#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ -#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +/******************** Bit definition forUSB_OTG_GINTF register *****************/ +#define USB_OTG_GINTF_CMOD_Pos (0U) +#define USB_OTG_GINTF_CMOD_Msk (0x1U << USB_OTG_GINTF_CMOD_Pos) /*!< 0x00000001 */ +#define USB_OTG_GINTF_CMOD USB_OTG_GINTF_CMOD_Msk /*!< Current mode of operation */ +#define USB_OTG_GINTF_MMIS_Pos (1U) +#define USB_OTG_GINTF_MMIS_Msk (0x1U << USB_OTG_GINTF_MMIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTF_MMIS USB_OTG_GINTF_MMIS_Msk /*!< Mode mismatch interrupt */ +#define USB_OTG_GINTF_OTGINT_Pos (2U) +#define USB_OTG_GINTF_OTGINT_Msk (0x1U << USB_OTG_GINTF_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTF_OTGINT USB_OTG_GINTF_OTGINT_Msk /*!< OTG interrupt */ +#define USB_OTG_GINTF_SOF_Pos (3U) +#define USB_OTG_GINTF_SOF_Msk (0x1U << USB_OTG_GINTF_SOF_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTF_SOF USB_OTG_GINTF_SOF_Msk /*!< Start of frame */ +#define USB_OTG_GINTF_RXFLVL_Pos (4U) +#define USB_OTG_GINTF_RXFLVL_Msk (0x1U << USB_OTG_GINTF_RXFLVL_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTF_RXFLVL USB_OTG_GINTF_RXFLVL_Msk /*!< RxFIFO nonempty */ +#define USB_OTG_GINTF_NPTXFE_Pos (5U) +#define USB_OTG_GINTF_NPTXFE_Msk (0x1U << USB_OTG_GINTF_NPTXFE_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTF_NPTXFE USB_OTG_GINTF_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ +#define USB_OTG_GINTF_GINAKEFF_Pos (6U) +#define USB_OTG_GINTF_GINAKEFF_Msk (0x1U << USB_OTG_GINTF_GINAKEFF_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTF_GINAKEFF USB_OTG_GINTF_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ +#define USB_OTG_GINTF_BOUTNAKEFF_Pos (7U) +#define USB_OTG_GINTF_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTF_BOUTNAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTF_BOUTNAKEFF USB_OTG_GINTF_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTF_ESUSP_Pos (10U) +#define USB_OTG_GINTF_ESUSP_Msk (0x1U << USB_OTG_GINTF_ESUSP_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTF_ESUSP USB_OTG_GINTF_ESUSP_Msk /*!< Early suspend */ +#define USB_OTG_GINTF_USBSUSP_Pos (11U) +#define USB_OTG_GINTF_USBSUSP_Msk (0x1U << USB_OTG_GINTF_USBSUSP_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTF_USBSUSP USB_OTG_GINTF_USBSUSP_Msk /*!< USB suspend */ +#define USB_OTG_GINTF_USBRST_Pos (12U) +#define USB_OTG_GINTF_USBRST_Msk (0x1U << USB_OTG_GINTF_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTF_USBRST USB_OTG_GINTF_USBRST_Msk /*!< USB reset */ +#define USB_OTG_GINTF_ENUMDNE_Pos (13U) +#define USB_OTG_GINTF_ENUMDNE_Msk (0x1U << USB_OTG_GINTF_ENUMDNE_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTF_ENUMDNE USB_OTG_GINTF_ENUMDNE_Msk /*!< Enumeration done */ +#define USB_OTG_GINTF_ISOODRP_Pos (14U) +#define USB_OTG_GINTF_ISOODRP_Msk (0x1U << USB_OTG_GINTF_ISOODRP_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTF_ISOODRP USB_OTG_GINTF_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ +#define USB_OTG_GINTF_EOPF_Pos (15U) +#define USB_OTG_GINTF_EOPF_Msk (0x1U << USB_OTG_GINTF_EOPF_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTF_EOPF USB_OTG_GINTF_EOPF_Msk /*!< End of periodic frame interrupt */ +#define USB_OTG_GINTF_IEPINT_Pos (18U) +#define USB_OTG_GINTF_IEPINT_Msk (0x1U << USB_OTG_GINTF_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTF_IEPINT USB_OTG_GINTF_IEPINT_Msk /*!< IN endpoint interrupt */ +#define USB_OTG_GINTF_OEPINT_Pos (19U) +#define USB_OTG_GINTF_OEPINT_Msk (0x1U << USB_OTG_GINTF_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTF_OEPINT USB_OTG_GINTF_OEPINT_Msk /*!< OUT endpoint interrupt */ +#define USB_OTG_GINTF_IISOIXFR_Pos (20U) +#define USB_OTG_GINTF_IISOIXFR_Msk (0x1U << USB_OTG_GINTF_IISOIXFR_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTF_IISOIXFR USB_OTG_GINTF_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ +#define USB_OTG_GINTF_PXFR_INCOMPISOOUT_Pos (21U) +#define USB_OTG_GINTF_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTF_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTF_PXFR_INCOMPISOOUT USB_OTG_GINTF_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ +#define USB_OTG_GINTF_DATAFSUSP_Pos (22U) +#define USB_OTG_GINTF_DATAFSUSP_Msk (0x1U << USB_OTG_GINTF_DATAFSUSP_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTF_DATAFSUSP USB_OTG_GINTF_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTF_HPRTINT_Pos (24U) +#define USB_OTG_GINTF_HPRTINT_Msk (0x1U << USB_OTG_GINTF_HPRTINT_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTF_HPRTINT USB_OTG_GINTF_HPRTINT_Msk /*!< Host port interrupt */ +#define USB_OTG_GINTF_HCINT_Pos (25U) +#define USB_OTG_GINTF_HCINT_Msk (0x1U << USB_OTG_GINTF_HCINT_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTF_HCINT USB_OTG_GINTF_HCINT_Msk /*!< Host channels interrupt */ +#define USB_OTG_GINTF_PTXFE_Pos (26U) +#define USB_OTG_GINTF_PTXFE_Msk (0x1U << USB_OTG_GINTF_PTXFE_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTF_PTXFE USB_OTG_GINTF_PTXFE_Msk /*!< Periodic TxFIFO empty */ +#define USB_OTG_GINTF_CIDSCHG_Pos (28U) +#define USB_OTG_GINTF_CIDSCHG_Msk (0x1U << USB_OTG_GINTF_CIDSCHG_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTF_CIDSCHG USB_OTG_GINTF_CIDSCHG_Msk /*!< Connector ID status change */ +#define USB_OTG_GINTF_DISCINT_Pos (29U) +#define USB_OTG_GINTF_DISCINT_Msk (0x1U << USB_OTG_GINTF_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTF_DISCINT USB_OTG_GINTF_DISCINT_Msk /*!< Disconnect detected interrupt */ +#define USB_OTG_GINTF_SRQINT_Pos (30U) +#define USB_OTG_GINTF_SRQINT_Msk (0x1U << USB_OTG_GINTF_SRQINT_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTF_SRQINT USB_OTG_GINTF_SRQINT_Msk /*!< Session request/new session detected interrupt */ +#define USB_OTG_GINTF_WKUINT_Pos (31U) +#define USB_OTG_GINTF_WKUINT_Msk (0x1U << USB_OTG_GINTF_WKUINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTF_WKUINT USB_OTG_GINTF_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ -/******************** Bit definition forUSB_OTG_GINTMSK register *****************/ -#define USB_OTG_GINTMSK_MMISM_Pos (1U) -#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ -#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ -#define USB_OTG_GINTMSK_OTGINT_Pos (2U) -#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ -#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ -#define USB_OTG_GINTMSK_SOFM_Pos (3U) -#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ -#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ -#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) -#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ -#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ -#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) -#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ -#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ -#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) -#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ -#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ -#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) -#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ -#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) -#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ -#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ -#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) -#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ -#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ -#define USB_OTG_GINTMSK_USBRST_Pos (12U) -#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ -#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ -#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) -#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ -#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ -#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) -#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ -#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ -#define USB_OTG_GINTMSK_EOPFM_Pos (15U) -#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ -#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ -#define USB_OTG_GINTMSK_EPMISM_Pos (17U) -#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ -#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ -#define USB_OTG_GINTMSK_IEPINT_Pos (18U) -#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ -#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ -#define USB_OTG_GINTMSK_OEPINT_Pos (19U) -#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ -#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ -#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) -#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ -#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ -#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) -#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ -#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ -#define USB_OTG_GINTMSK_PRTIM_Pos (24U) -#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ -#define USB_OTG_GINTMSK_HCIM_Pos (25U) -#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ -#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ -#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) -#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ -#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ -#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) -#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ -#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ -#define USB_OTG_GINTMSK_DISCINT_Pos (29U) -#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ -#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ -#define USB_OTG_GINTMSK_SRQIM_Pos (30U) -#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ -#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ -#define USB_OTG_GINTMSK_WUIM_Pos (31U) -#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ +/******************** Bit definition forUSB_OTG_GINTEN register *****************/ +#define USB_OTG_GINTEN_MMISM_Pos (1U) +#define USB_OTG_GINTEN_MMISM_Msk (0x1U << USB_OTG_GINTEN_MMISM_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTEN_MMISM USB_OTG_GINTEN_MMISM_Msk /*!< Mode mismatch interrupt mask */ +#define USB_OTG_GINTEN_OTGINT_Pos (2U) +#define USB_OTG_GINTEN_OTGINT_Msk (0x1U << USB_OTG_GINTEN_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTEN_OTGINT USB_OTG_GINTEN_OTGINT_Msk /*!< OTG interrupt mask */ +#define USB_OTG_GINTEN_SOFM_Pos (3U) +#define USB_OTG_GINTEN_SOFM_Msk (0x1U << USB_OTG_GINTEN_SOFM_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTEN_SOFM USB_OTG_GINTEN_SOFM_Msk /*!< Start of frame mask */ +#define USB_OTG_GINTEN_RXFLVLM_Pos (4U) +#define USB_OTG_GINTEN_RXFLVLM_Msk (0x1U << USB_OTG_GINTEN_RXFLVLM_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTEN_RXFLVLM USB_OTG_GINTEN_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ +#define USB_OTG_GINTEN_NPTXFEM_Pos (5U) +#define USB_OTG_GINTEN_NPTXFEM_Msk (0x1U << USB_OTG_GINTEN_NPTXFEM_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTEN_NPTXFEM USB_OTG_GINTEN_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ +#define USB_OTG_GINTEN_GINAKEFFM_Pos (6U) +#define USB_OTG_GINTEN_GINAKEFFM_Msk (0x1U << USB_OTG_GINTEN_GINAKEFFM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTEN_GINAKEFFM USB_OTG_GINTEN_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ +#define USB_OTG_GINTEN_GONAKEFFM_Pos (7U) +#define USB_OTG_GINTEN_GONAKEFFM_Msk (0x1U << USB_OTG_GINTEN_GONAKEFFM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTEN_GONAKEFFM USB_OTG_GINTEN_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ +#define USB_OTG_GINTEN_ESUSPM_Pos (10U) +#define USB_OTG_GINTEN_ESUSPM_Msk (0x1U << USB_OTG_GINTEN_ESUSPM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTEN_ESUSPM USB_OTG_GINTEN_ESUSPM_Msk /*!< Early suspend mask */ +#define USB_OTG_GINTEN_USBSUSPM_Pos (11U) +#define USB_OTG_GINTEN_USBSUSPM_Msk (0x1U << USB_OTG_GINTEN_USBSUSPM_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTEN_USBSUSPM USB_OTG_GINTEN_USBSUSPM_Msk /*!< USB suspend mask */ +#define USB_OTG_GINTEN_USBRST_Pos (12U) +#define USB_OTG_GINTEN_USBRST_Msk (0x1U << USB_OTG_GINTEN_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTEN_USBRST USB_OTG_GINTEN_USBRST_Msk /*!< USB reset mask */ +#define USB_OTG_GINTEN_ENUMDNEM_Pos (13U) +#define USB_OTG_GINTEN_ENUMDNEM_Msk (0x1U << USB_OTG_GINTEN_ENUMDNEM_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTEN_ENUMDNEM USB_OTG_GINTEN_ENUMDNEM_Msk /*!< Enumeration done mask */ +#define USB_OTG_GINTEN_ISOODRPM_Pos (14U) +#define USB_OTG_GINTEN_ISOODRPM_Msk (0x1U << USB_OTG_GINTEN_ISOODRPM_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTEN_ISOODRPM USB_OTG_GINTEN_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ +#define USB_OTG_GINTEN_EOPFM_Pos (15U) +#define USB_OTG_GINTEN_EOPFM_Msk (0x1U << USB_OTG_GINTEN_EOPFM_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTEN_EOPFM USB_OTG_GINTEN_EOPFM_Msk /*!< End of periodic frame interrupt mask */ +#define USB_OTG_GINTEN_EPMISM_Pos (17U) +#define USB_OTG_GINTEN_EPMISM_Msk (0x1U << USB_OTG_GINTEN_EPMISM_Pos) /*!< 0x00020000 */ +#define USB_OTG_GINTEN_EPMISM USB_OTG_GINTEN_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ +#define USB_OTG_GINTEN_IEPINT_Pos (18U) +#define USB_OTG_GINTEN_IEPINT_Msk (0x1U << USB_OTG_GINTEN_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTEN_IEPINT USB_OTG_GINTEN_IEPINT_Msk /*!< IN endpoints interrupt mask */ +#define USB_OTG_GINTEN_OEPINT_Pos (19U) +#define USB_OTG_GINTEN_OEPINT_Msk (0x1U << USB_OTG_GINTEN_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTEN_OEPINT USB_OTG_GINTEN_OEPINT_Msk /*!< OUT endpoints interrupt mask */ +#define USB_OTG_GINTEN_IISOIXFRM_Pos (20U) +#define USB_OTG_GINTEN_IISOIXFRM_Msk (0x1U << USB_OTG_GINTEN_IISOIXFRM_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTEN_IISOIXFRM USB_OTG_GINTEN_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ +#define USB_OTG_GINTEN_PXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTEN_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTEN_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTEN_PXFRM_IISOOXFRM USB_OTG_GINTEN_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTEN_FSUSPM_Pos (22U) +#define USB_OTG_GINTEN_FSUSPM_Msk (0x1U << USB_OTG_GINTEN_FSUSPM_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTEN_FSUSPM USB_OTG_GINTEN_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTEN_PRTIM_Pos (24U) +#define USB_OTG_GINTEN_PRTIM_Msk (0x1U << USB_OTG_GINTEN_PRTIM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTEN_PRTIM USB_OTG_GINTEN_PRTIM_Msk /*!< Host port interrupt mask */ +#define USB_OTG_GINTEN_HCIM_Pos (25U) +#define USB_OTG_GINTEN_HCIM_Msk (0x1U << USB_OTG_GINTEN_HCIM_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTEN_HCIM USB_OTG_GINTEN_HCIM_Msk /*!< Host channels interrupt mask */ +#define USB_OTG_GINTEN_PTXFEM_Pos (26U) +#define USB_OTG_GINTEN_PTXFEM_Msk (0x1U << USB_OTG_GINTEN_PTXFEM_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTEN_PTXFEM USB_OTG_GINTEN_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ +#define USB_OTG_GINTEN_CIDSCHGM_Pos (28U) +#define USB_OTG_GINTEN_CIDSCHGM_Msk (0x1U << USB_OTG_GINTEN_CIDSCHGM_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTEN_CIDSCHGM USB_OTG_GINTEN_CIDSCHGM_Msk /*!< Connector ID status change mask */ +#define USB_OTG_GINTEN_DISCINT_Pos (29U) +#define USB_OTG_GINTEN_DISCINT_Msk (0x1U << USB_OTG_GINTEN_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTEN_DISCINT USB_OTG_GINTEN_DISCINT_Msk /*!< Disconnect detected interrupt mask */ +#define USB_OTG_GINTEN_SRQIM_Pos (30U) +#define USB_OTG_GINTEN_SRQIM_Msk (0x1U << USB_OTG_GINTEN_SRQIM_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTEN_SRQIM USB_OTG_GINTEN_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ +#define USB_OTG_GINTEN_WUIM_Pos (31U) +#define USB_OTG_GINTEN_WUIM_Msk (0x1U << USB_OTG_GINTEN_WUIM_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTEN_WUIM USB_OTG_GINTEN_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ /******************** Bit definition forUSB_OTG_DAINT register *******************/ #define USB_OTG_DAINT_IEPINT_Pos (0U) @@ -13120,19 +13120,19 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ -/******************** Bit definition for USB_OTG_GRXSTSP register ****************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_BCNT_Pos (4U) -#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_DPID_Pos (15U) -#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +/******************** Bit definition for USB_OTG_GRSTATP register ****************/ +#define USB_OTG_GRSTATP_EPNUM_Pos (0U) +#define USB_OTG_GRSTATP_EPNUM_Msk (0xFU << USB_OTG_GRSTATP_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRSTATP_EPNUM USB_OTG_GRSTATP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRSTATP_BCNT_Pos (4U) +#define USB_OTG_GRSTATP_BCNT_Msk (0x7FFU << USB_OTG_GRSTATP_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRSTATP_BCNT USB_OTG_GRSTATP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRSTATP_DPID_Pos (15U) +#define USB_OTG_GRSTATP_DPID_Msk (0x3U << USB_OTG_GRSTATP_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRSTATP_DPID USB_OTG_GRSTATP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRSTATP_PKTSTS_Pos (17U) +#define USB_OTG_GRSTATP_PKTSTS_Msk (0xFU << USB_OTG_GRSTATP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRSTATP_PKTSTS USB_OTG_GRSTATP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ /******************** Bit definition forUSB_OTG_DAINTMSK register ****************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -13226,10 +13226,10 @@ typedef struct #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ -/******************** Bit definition forUSB_OTG_GRXFSIZ register *****************/ -#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) -#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ +/******************** Bit definition forUSB_OTG_GRFLEN register *****************/ +#define USB_OTG_GRFLEN_RXFD_Pos (0U) +#define USB_OTG_GRFLEN_RXFD_Msk (0xFFFFU << USB_OTG_GRFLEN_RXFD_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GRFLEN_RXFD USB_OTG_GRFLEN_RXFD_Msk /*!< RxFIFO depth */ /******************** Bit definition forUSB_OTG_DVBUSDIS register ****************/ #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) @@ -13479,13 +13479,13 @@ typedef struct #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ -/******************** Bit definition forUSB_OTG_HPTXFSIZ register ****************/ -#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) -#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +/******************** Bit definition forUSB_OTG_HPTFLEN register ****************/ +#define USB_OTG_HPTFLEN_PTXSA_Pos (0U) +#define USB_OTG_HPTFLEN_PTXSA_Msk (0xFFFFU << USB_OTG_HPTFLEN_PTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTFLEN_PTXSA USB_OTG_HPTFLEN_PTXSA_Msk /*!< Host periodic TxFIFO start address */ +#define USB_OTG_HPTFLEN_PTXFD_Pos (16U) +#define USB_OTG_HPTFLEN_PTXFD_Msk (0xFFFFU << USB_OTG_HPTFLEN_PTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTFLEN_PTXFD USB_OTG_HPTFLEN_PTXFD_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition forUSB_OTG_DIEPCTL register *****************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)