EICU. Added support of single channel timers.
Tested in hardware with TIM11.
This commit is contained in:
parent
ceb3c861d5
commit
bfac876090
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@ -56,6 +56,7 @@
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/**
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/**
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* @brief EICUD1 driver identifier.
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* @brief EICUD1 driver identifier.
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* @note The driver EICUD1 allocates the complex timer TIM1 when enabled.
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* @note The driver EICUD1 allocates the complex timer TIM1 when enabled.
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@ -120,6 +121,38 @@ EICUDriver EICUD9;
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EICUDriver EICUD12;
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EICUDriver EICUD12;
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#endif
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#endif
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/**
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* @brief EICUD10 driver identifier.
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* @note The driver EICUD10 allocates the timer TIM10 when enabled.
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*/
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#if STM32_EICU_USE_TIM10 && !defined(__DOXYGEN__)
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EICUDriver EICUD10;
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#endif
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/**
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* @brief EICUD11 driver identifier.
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* @note The driver EICUD11 allocates the timer TIM11 when enabled.
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*/
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#if STM32_EICU_USE_TIM11 && !defined(__DOXYGEN__)
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EICUDriver EICUD11;
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#endif
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/**
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* @brief EICUD13 driver identifier.
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* @note The driver EICUD13 allocates the timer TIM13 when enabled.
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*/
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#if STM32_EICU_USE_TIM13 && !defined(__DOXYGEN__)
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EICUDriver EICUD13;
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#endif
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/**
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* @brief EICUD14 driver identifier.
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* @note The driver EICUD14 allocates the timer TIM14 when enabled.
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*/
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#if STM32_EICU_USE_TIM14 && !defined(__DOXYGEN__)
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EICUDriver EICUD14;
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#endif
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -635,6 +668,94 @@ OSAL_IRQ_HANDLER(STM32_TIM12_HANDLER) {
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}
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}
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#endif /* STM32_EICU_USE_TIM12 */
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#endif /* STM32_EICU_USE_TIM12 */
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#if STM32_EICU_USE_TIM10
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#if !defined(STM32_TIM10_HANDLER)
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#error "STM32_TIM10_HANDLER not defined"
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#endif
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/**
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* @brief TIM10 interrupt handler.
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* @note It is assumed that the various sources are only activated if the
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* associated callback pointer is not equal to @p NULL in order to not
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* perform an extra check in a potentially critical interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_TIM10_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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eicu_lld_serve_interrupt(&EICUD10);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* STM32_EICU_USE_TIM10 */
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#if STM32_EICU_USE_TIM11
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#if !defined(STM32_TIM11_HANDLER)
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#error "STM32_TIM11_HANDLER not defined"
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#endif
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/**
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* @brief TIM11 interrupt handler.
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* @note It is assumed that the various sources are only activated if the
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* associated callback pointer is not equal to @p NULL in order to not
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* perform an extra check in a potentially critical interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_TIM11_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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eicu_lld_serve_interrupt(&EICUD11);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* STM32_EICU_USE_TIM11 */
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#if STM32_EICU_USE_TIM13
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#if !defined(STM32_TIM13_HANDLER)
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#error "STM32_TIM13_HANDLER not defined"
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#endif
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/**
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* @brief TIM13 interrupt handler.
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* @note It is assumed that the various sources are only activated if the
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* associated callback pointer is not equal to @p NULL in order to not
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* perform an extra check in a potentially critical interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_TIM13_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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eicu_lld_serve_interrupt(&EICUD13);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* STM32_EICU_USE_TIM13 */
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#if STM32_EICU_USE_TIM14
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#if !defined(STM32_TIM14_HANDLER)
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#error "STM32_TIM14_HANDLER not defined"
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#endif
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/**
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* @brief TIM14 interrupt handler.
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* @note It is assumed that the various sources are only activated if the
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* associated callback pointer is not equal to @p NULL in order to not
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* perform an extra check in a potentially critical interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_TIM14_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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eicu_lld_serve_interrupt(&EICUD14);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* STM32_EICU_USE_TIM14 */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/* Driver exported functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -692,6 +813,30 @@ void eicu_lld_init(void) {
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eicuObjectInit(&EICUD12);
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eicuObjectInit(&EICUD12);
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EICUD12.tim = STM32_TIM12;
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EICUD12.tim = STM32_TIM12;
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#endif
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#endif
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#if STM32_EICU_USE_TIM10
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/* Driver initialization.*/
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eicuObjectInit(&EICUD10);
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EICUD10.tim = STM32_TIM10;
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#endif
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#if STM32_EICU_USE_TIM11
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/* Driver initialization.*/
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eicuObjectInit(&EICUD11);
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EICUD11.tim = STM32_TIM11;
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#endif
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#if STM32_EICU_USE_TIM13
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/* Driver initialization.*/
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eicuObjectInit(&EICUD13);
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EICUD13.tim = STM32_TIM13;
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#endif
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#if STM32_EICU_USE_TIM14
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/* Driver initialization.*/
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eicuObjectInit(&EICUD14);
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EICUD14.tim = STM32_TIM14;
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#endif
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}
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}
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/**
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/**
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@ -794,6 +939,42 @@ void eicu_lld_start(EICUDriver *eicup) {
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eicup->channels = 2;
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eicup->channels = 2;
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eicup->clock = STM32_TIMCLK1;
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eicup->clock = STM32_TIMCLK1;
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}
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}
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#endif
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#if STM32_EICU_USE_TIM10
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if (&EICUD10 == eicup) {
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rccEnableTIM10(FALSE);
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rccResetTIM10();
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nvicEnableVector(STM32_TIM10_NUMBER, STM32_EICU_TIM10_IRQ_PRIORITY);
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eicup->channels = 1;
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eicup->clock = STM32_TIMCLK1;
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}
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#endif
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#if STM32_EICU_USE_TIM11
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if (&EICUD11 == eicup) {
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rccEnableTIM11(FALSE);
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rccResetTIM11();
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nvicEnableVector(STM32_TIM11_NUMBER, STM32_EICU_TIM11_IRQ_PRIORITY);
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eicup->channels = 1;
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eicup->clock = STM32_TIMCLK1;
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}
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#endif
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#if STM32_EICU_USE_TIM13
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if (&EICUD13 == eicup) {
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rccEnableTIM13(FALSE);
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rccResetTIM13();
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nvicEnableVector(STM32_TIM13_NUMBER, STM32_EICU_TIM13_IRQ_PRIORITY);
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eicup->channels = 1;
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eicup->clock = STM32_TIMCLK1;
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}
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#endif
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#if STM32_EICU_USE_TIM14
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if (&EICUD14 == eicup) {
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rccEnableTIM14(FALSE);
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rccResetTIM14();
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nvicEnableVector(STM32_TIM14_NUMBER, STM32_EICU_TIM14_IRQ_PRIORITY);
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eicup->channels = 1;
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eicup->clock = STM32_TIMCLK1;
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}
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#endif
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#endif
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}
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}
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else {
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else {
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@ -920,6 +1101,30 @@ void eicu_lld_stop(EICUDriver *eicup) {
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}
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}
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#endif
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#endif
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}
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}
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#if STM32_EICU_USE_TIM10
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if (&EICUD10 == eicup) {
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nvicDisableVector(STM32_TIM10_NUMBER);
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rccDisableTIM10(FALSE);
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}
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#endif
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#if STM32_EICU_USE_TIM11
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if (&EICUD11 == eicup) {
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nvicDisableVector(STM32_TIM11_NUMBER);
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rccDisableTIM11(FALSE);
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}
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#endif
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#if STM32_EICU_USE_TIM13
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if (&EICUD13 == eicup) {
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nvicDisableVector(STM32_TIM13_NUMBER);
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rccDisableTIM13(FALSE);
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}
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#endif
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#if STM32_EICU_USE_TIM14
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if (&EICUD14 == eicup) {
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nvicDisableVector(STM32_TIM14_NUMBER);
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rccDisableTIM14(FALSE);
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}
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#endif
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}
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}
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/**
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/**
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@ -25,6 +25,78 @@
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#if HAL_USE_EICU || defined(__DOXYGEN__)
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#if HAL_USE_EICU || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Temporal definitions to be moved in main repository. */
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/*===========================================================================*/
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#define STM32_TIM10_NUMBER 25
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#define STM32_TIM13_NUMBER 44
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#define STM32_TIM10_HANDLER VectorA4
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#define STM32_TIM13_HANDLER VectorF0
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/**
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* @brief Enables the TIM10 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp)
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/**
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* @brief Disables the TIM10 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp)
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/**
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* @brief Resets the TIM10 peripheral.
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*
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* @api
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*/
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#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST)
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/**
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* @brief Enables the TIM13 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp)
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/**
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* @brief Disables the TIM13 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp)
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/**
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* @brief Resets the TIM13 peripheral.
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*
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* @api
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*/
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#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver constants. */
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -164,6 +236,34 @@
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#if !defined(STM32_EICU_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#if !defined(STM32_EICU_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM12_IRQ_PRIORITY 7
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#define STM32_EICU_TIM12_IRQ_PRIORITY 7
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#endif
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#endif
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/**
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* @brief EICUD10 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM10_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM10_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD11 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM11_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD13 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM13_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM13_IRQ_PRIORITY 7
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#endif
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/**
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* @brief EICUD14 interrupt priority level setting.
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*/
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#if !defined(STM32_EICU_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_EICU_TIM14_IRQ_PRIORITY 7
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#endif
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/** @} */
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/** @} */
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/*===========================================================================*/
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/*===========================================================================*/
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@ -202,53 +302,91 @@
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#error "TIM12 not present in the selected device"
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#error "TIM12 not present in the selected device"
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#endif
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#endif
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#if !STM32_EICU_USE_TIM1 && !STM32_EICU_USE_TIM2 && \
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#if STM32_EICU_USE_TIM10 && !STM32_HAS_TIM10
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!STM32_EICU_USE_TIM3 && !STM32_EICU_USE_TIM4 && \
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#error "TIM10 not present in the selected device"
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!STM32_EICU_USE_TIM5 && !STM32_EICU_USE_TIM8 && \
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#endif
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!STM32_EICU_USE_TIM9 && !STM32_EICU_USE_TIM12
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#if STM32_EICU_USE_TIM11 && !STM32_HAS_TIM11
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#error "TIM11 not present in the selected device"
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#endif
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#if STM32_EICU_USE_TIM13 && !STM32_HAS_TIM13
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#error "TIM13 not present in the selected device"
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#endif
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||||||
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#if STM32_EICU_USE_TIM14 && !STM32_HAS_TIM14
|
||||||
|
#error "TIM14 not present in the selected device"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !STM32_EICU_USE_TIM1 && !STM32_EICU_USE_TIM2 && \
|
||||||
|
!STM32_EICU_USE_TIM3 && !STM32_EICU_USE_TIM4 && \
|
||||||
|
!STM32_EICU_USE_TIM5 && !STM32_EICU_USE_TIM8 && \
|
||||||
|
!STM32_EICU_USE_TIM9 && !STM32_EICU_USE_TIM12 && \
|
||||||
|
!STM32_EICU_USE_TIM10 && !STM32_EICU_USE_TIM11 && \
|
||||||
|
!STM32_EICU_USE_TIM13 && !STM32_EICU_USE_TIM14
|
||||||
#error "EICU driver activated but no TIM peripheral assigned"
|
#error "EICU driver activated but no TIM peripheral assigned"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_EICU_USE_TIM1 && \
|
#if STM32_EICU_USE_TIM1 && \
|
||||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM1_IRQ_PRIORITY)
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM1_IRQ_PRIORITY)
|
||||||
#error "Invalid IRQ priority assigned to TIM1"
|
#error "Invalid IRQ priority assigned to TIM1"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_EICU_USE_TIM2 && \
|
#if STM32_EICU_USE_TIM2 && \
|
||||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM2_IRQ_PRIORITY)
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM2_IRQ_PRIORITY)
|
||||||
#error "Invalid IRQ priority assigned to TIM2"
|
#error "Invalid IRQ priority assigned to TIM2"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_EICU_USE_TIM3 && \
|
#if STM32_EICU_USE_TIM3 && \
|
||||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM3_IRQ_PRIORITY)
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM3_IRQ_PRIORITY)
|
||||||
#error "Invalid IRQ priority assigned to TIM3"
|
#error "Invalid IRQ priority assigned to TIM3"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_EICU_USE_TIM4 && \
|
#if STM32_EICU_USE_TIM4 && \
|
||||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM4_IRQ_PRIORITY)
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM4_IRQ_PRIORITY)
|
||||||
#error "Invalid IRQ priority assigned to TIM4"
|
#error "Invalid IRQ priority assigned to TIM4"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_EICU_USE_TIM5 && \
|
#if STM32_EICU_USE_TIM5 && \
|
||||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM5_IRQ_PRIORITY)
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM5_IRQ_PRIORITY)
|
||||||
#error "Invalid IRQ priority assigned to TIM5"
|
#error "Invalid IRQ priority assigned to TIM5"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_EICU_USE_TIM8 && \
|
#if STM32_EICU_USE_TIM8 && \
|
||||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM8_IRQ_PRIORITY)
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM8_IRQ_PRIORITY)
|
||||||
#error "Invalid IRQ priority assigned to TIM8"
|
#error "Invalid IRQ priority assigned to TIM8"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_EICU_USE_TIM9 && \
|
#if STM32_EICU_USE_TIM9 && \
|
||||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM9_IRQ_PRIORITY)
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM9_IRQ_PRIORITY)
|
||||||
#error "Invalid IRQ priority assigned to TIM9"
|
#error "Invalid IRQ priority assigned to TIM9"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if STM32_EICU_USE_TIM12 && \
|
#if STM32_EICU_USE_TIM12 && \
|
||||||
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM12_IRQ_PRIORITY)
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM12_IRQ_PRIORITY)
|
||||||
#error "Invalid IRQ priority assigned to TIM12"
|
#error "Invalid IRQ priority assigned to TIM12"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if STM32_EICU_USE_TIM10 && \
|
||||||
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM10_IRQ_PRIORITY)
|
||||||
|
#error "Invalid IRQ priority assigned to TIM10"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_EICU_USE_TIM11 && \
|
||||||
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM11_IRQ_PRIORITY)
|
||||||
|
#error "Invalid IRQ priority assigned to TIM11"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_EICU_USE_TIM13 && \
|
||||||
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM13_IRQ_PRIORITY)
|
||||||
|
#error "Invalid IRQ priority assigned to TIM13"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_EICU_USE_TIM14 && \
|
||||||
|
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_EICU_TIM14_IRQ_PRIORITY)
|
||||||
|
#error "Invalid IRQ priority assigned to TIM14"
|
||||||
|
#endif
|
||||||
|
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
/* Driver data structures and types. */
|
/* Driver data structures and types. */
|
||||||
/*===========================================================================*/
|
/*===========================================================================*/
|
||||||
|
@ -451,6 +589,22 @@ extern EICUDriver EICUD9;
|
||||||
extern EICUDriver EICUD12;
|
extern EICUDriver EICUD12;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if STM32_EICU_USE_TIM10 && !defined(__DOXYGEN__)
|
||||||
|
extern EICUDriver EICUD10;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_EICU_USE_TIM11 && !defined(__DOXYGEN__)
|
||||||
|
extern EICUDriver EICUD11;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_EICU_USE_TIM13 && !defined(__DOXYGEN__)
|
||||||
|
extern EICUDriver EICUD13;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32_EICU_USE_TIM14 && !defined(__DOXYGEN__)
|
||||||
|
extern EICUDriver EICUD14;
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in New Issue