rusefi
/
ChibiOS-Contrib
mirror of https://github.com/rusefi/ChibiOS-Contrib.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Revert "Add R/W memory and instruction barrier after mstatus access" 

This reverts commit b875108cd0.
This commit is contained in:
Stefan Kerkmann 2021-04-16 21:52:41 +02:00
parent 9dbe061083
commit c1dfb65aa0
2 changed files with 13 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
os/common/ports/RISCV-ECLIC/chcore.h
View File

@ -377,9 +377,7 @@ static inline void port_init(void) {}
* @return The interrupts status. * @return The interrupts status.
*/ */
static inline syssts_t port_get_irq_status(void) { static inline syssts_t port_get_irq_status(void) {
syssts_t mstatus = __RV_CSR_READ(CSR_MSTATUS); return (syssts_t)__RV_CSR_READ(CSR_MSTATUS);
__RWMB();
return mstatus;
} }
/** /**
@ -401,9 +399,7 @@ static inline bool port_irq_enabled(syssts_t sts) { return sts & MSTATUS_MIE; }
* @retval true running in ISR mode. * @retval true running in ISR mode.
*/ */
static inline bool port_is_isr_context(void) { static inline bool port_is_isr_context(void) {
bool is_irq_context = (__RV_CSR_READ(CSR_MSUBM) & MSUBM_TYP) != 0; return __RV_CSR_READ(CSR_MSUBM) & MSUBM_TYP;
__RWMB();
return is_irq_context;
} }
/** /**
@ -411,22 +407,14 @@ static inline bool port_is_isr_context(void) {
* @details Usually this function just disables interrupts but may perform more * @details Usually this function just disables interrupts but may perform more
* actions. * actions.
*/ */
static inline void port_lock(void) { static inline void port_lock(void) { __disable_irq(); }
__disable_irq();
__RWMB();
__FENCE_I();
}
/** /**
* @brief Kernel-unlock action. * @brief Kernel-unlock action.
* @details Usually this function just enables interrupts but may perform more * @details Usually this function just enables interrupts but may perform more
* actions. * actions.
*/ */
static inline void port_unlock(void) { static inline void port_unlock(void) { __enable_irq(); }
__enable_irq();
__RWMB();
__FENCE_I();
}
/** /**
* @brief Kernel-lock action from an interrupt handler. * @brief Kernel-lock action from an interrupt handler.
@ -448,18 +436,18 @@ static inline void port_unlock_from_isr(void) { port_unlock(); }
* @brief Disables all the interrupt sources. * @brief Disables all the interrupt sources.
* @note Of course non-maskable interrupt sources are not included. * @note Of course non-maskable interrupt sources are not included.
*/ */
static inline void port_disable(void) { port_lock(); } static inline void port_disable(void) { __disable_irq(); }
/** /**
* @brief Disables the interrupt sources below kernel-level priority. * @brief Disables the interrupt sources below kernel-level priority.
* @note Interrupt sources above kernel level remains enabled. * @note Interrupt sources above kernel level remains enabled.
*/ */
static inline void port_suspend(void) { port_lock(); } static inline void port_suspend(void) { __disable_irq(); }
/** /**
* @brief Enables all the interrupt sources. * @brief Enables all the interrupt sources.
*/ */
static inline void port_enable(void) { port_unlock(); } static inline void port_enable(void) { __enable_irq(); }
/** /**
* @details The function is meant to return when an interrupt becomes pending. * @details The function is meant to return when an interrupt becomes pending.

8
os/common/ports/RISCV-ECLIC/compilers/GCC/chcoreasm.S
View File

@ -57,15 +57,11 @@
# Disable Interrupts globally. # Disable Interrupts globally.
.macro DISABLE_MIE .macro DISABLE_MIE
csrc CSR_MSTATUS, MSTATUS_MIE csrc CSR_MSTATUS, MSTATUS_MIE
fence iorw, iorw
fence.i
.endm .endm
# Enable Interrupts globally. # Enable Interrupts globally.
.macro ENABLE_MIE .macro ENABLE_MIE
csrs CSR_MSTATUS, MSTATUS_MIE csrs CSR_MSTATUS, MSTATUS_MIE
fence iorw, iorw
fence.i
.endm .endm
# Clear previous machine interrupt enable bit in mstatus (mstatus.mpie). # Clear previous machine interrupt enable bit in mstatus (mstatus.mpie).
@ -74,16 +70,12 @@
.macro DISABLE_MPIE .macro DISABLE_MPIE
li a0, MSTATUS_MPIE li a0, MSTATUS_MPIE
csrc CSR_MSTATUS, a0 csrc CSR_MSTATUS, a0
fence iorw, iorw
fence.i
.endm .endm
# Set previous machine interrupt enable bit in mstatus (mstatus.mpie). # Set previous machine interrupt enable bit in mstatus (mstatus.mpie).
.macro ENABLE_MPIE .macro ENABLE_MPIE
li a0, MSTATUS_MPIE li a0, MSTATUS_MPIE
csrs CSR_MSTATUS, a0 csrs CSR_MSTATUS, a0
fence iorw, iorw
fence.i
.endm .endm
# -------------------------------------------------------------------------- # --------------------------------------------------------------------------