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Rename DAC1 to just DAC

This commit is contained in:
Stefan Kerkmann 2021-04-05 17:29:59 +02:00
parent 389dbc2514
commit c7e847a17a
5 changed files with 91 additions and 97 deletions
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75
os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.c
View File

@ -30,18 +30,13 @@
/* Driver local definitions. */
/*===========================================================================*/
/* Because ST headers naming inconsistencies.*/
#if !defined(DAC1)
#define DAC1 DAC
#endif
#define DAC_CH1_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_DAC_DAC_CH1_DMA_STREAM, \
GD32_DAC_CH1_DMA_CHN)
#define DAC1_CH1_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_DAC_DAC1_CH1_DMA_STREAM, \
GD32_DAC1_CH1_DMA_CHN)
#define DAC1_CH2_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_DAC_DAC1_CH2_DMA_STREAM, \
GD32_DAC1_CH2_DMA_CHN)
#define DAC_CH2_DMA_CHANNEL \
GD32_DMA_GETCHANNEL(GD32_DAC_DAC_CH2_DMA_STREAM, \
GD32_DAC_CH2_DMA_CHN)
#define CHANNEL_DATA_OFFSET 3U
@ -49,13 +44,13 @@
/* Driver exported variables. */
/*===========================================================================*/
/** @brief DAC1 CH1 driver identifier.*/
#if GD32_DAC_USE_DAC1_CH1 || defined(__DOXYGEN__)
/** @brief DAC CH1 driver identifier.*/
#if GD32_DAC_USE_DAC_CH1 || defined(__DOXYGEN__)
DACDriver DACD1;
#endif
/** @brief DAC1 CH2 driver identifier.*/
#if (GD32_DAC_USE_DAC1_CH2 && !GD32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
/** @brief DAC CH2 driver identifier.*/
#if (GD32_DAC_USE_DAC_CH2 && !GD32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
DACDriver DACD2;
#endif
@ -63,35 +58,35 @@ DACDriver DACD2;
/* Driver local variables. */
/*===========================================================================*/
#if GD32_DAC_USE_DAC1_CH1 == TRUE
#if GD32_DAC_USE_DAC_CH1 == TRUE
static const dacparams_t dac1_ch1_params = {
.dac = DAC1,
.dac = DAC,
.dataoffset = 0U,
.regshift = 0U,
.regmask = 0xFFFF0000U,
.dmastream = GD32_DAC_DAC1_CH1_DMA_STREAM,
.dmamode = GD32_DMA_CTL_CHSEL(DAC1_CH1_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_DAC_DAC1_CH1_DMA_PRIORITY) |
.dmastream = GD32_DAC_DAC_CH1_DMA_STREAM,
.dmamode = GD32_DMA_CTL_CHSEL(DAC_CH1_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_DAC_DAC_CH1_DMA_PRIORITY) |
GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_CMEN | GD32_DMA_CTL_DIR_M2P |
GD32_DMA_CTL_ERRIE | GD32_DMA_CTL_HTFIE |
GD32_DMA_CTL_FTFIE,
.dmairqprio = GD32_DAC_DAC1_CH1_IRQ_PRIORITY
.dmairqprio = GD32_DAC_DAC_CH1_IRQ_PRIORITY
};
#endif
#if GD32_DAC_USE_DAC1_CH2 == TRUE
#if GD32_DAC_USE_DAC_CH2 == TRUE
static const dacparams_t dac1_ch2_params = {
.dac = DAC1,
.dac = DAC,
.dataoffset = CHANNEL_DATA_OFFSET,
.regshift = 16U,
.regmask = 0x0000FFFFU,
.dmastream = GD32_DAC_DAC1_CH2_DMA_STREAM,
.dmamode = GD32_DMA_CTL_CHSEL(DAC1_CH2_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_DAC_DAC1_CH2_DMA_PRIORITY) |
.dmastream = GD32_DAC_DAC_CH2_DMA_STREAM,
.dmamode = GD32_DMA_CTL_CHSEL(DAC_CH2_DMA_CHANNEL) |
GD32_DMA_CTL_PRIO(GD32_DAC_DAC_CH2_DMA_PRIORITY) |
GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_CMEN | GD32_DMA_CTL_DIR_M2P |
GD32_DMA_CTL_ERRIE | GD32_DMA_CTL_HTFIE |
GD32_DMA_CTL_FTFIE,
.dmairqprio = GD32_DAC_DAC1_CH2_IRQ_PRIORITY
.dmairqprio = GD32_DAC_DAC_CH2_IRQ_PRIORITY
};
#endif
@ -139,13 +134,13 @@ static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
*/
void dac_lld_init(void) {
#if GD32_DAC_USE_DAC1_CH1
#if GD32_DAC_USE_DAC_CH1
dacObjectInit(&DACD1);
DACD1.params = &dac1_ch1_params;
DACD1.dma = NULL;
#endif
#if GD32_DAC_USE_DAC1_CH2
#if GD32_DAC_USE_DAC_CH2
dacObjectInit(&DACD2);
DACD2.params = &dac1_ch2_params;
DACD2.dma = NULL;
@ -167,15 +162,15 @@ void dac_lld_start(DACDriver *dacp) {
dacchannel_t channel = 0;
/* Enabling the clock source.*/
#if GD32_DAC_USE_DAC1_CH1
#if GD32_DAC_USE_DAC_CH1
if (&DACD1 == dacp) {
rcuEnableDAC1(true);
rcuEnableDAC(true);
}
#endif
#if GD32_DAC_USE_DAC1_CH2
#if GD32_DAC_USE_DAC_CH2
if (&DACD2 == dacp) {
rcuEnableDAC1(true);
rcuEnableDAC(true);
channel = 1;
}
#endif
@ -222,18 +217,18 @@ void dac_lld_stop(DACDriver *dacp) {
/* Disabling DAC.*/
dacp->params->dac->CTL &= dacp->params->regmask;
#if GD32_DAC_USE_DAC1_CH1
#if GD32_DAC_USE_DAC_CH1
if (&DACD1 == dacp) {
if ((dacp->params->dac->CTL & DAC_CTL_DEN1) == 0U) {
rcuDisableDAC1();
rcuDisableDAC();
}
}
#endif
#if GD32_DAC_USE_DAC1_CH2
#if GD32_DAC_USE_DAC_CH2
if (&DACD2 == dacp) {
if ((dacp->params->dac->CTL & DAC_CTL_DEN0) == 0U) {
rcuDisableDAC1();
rcuDisableDAC();
}
}
#endif
@ -265,7 +260,7 @@ void dac_lld_put_channel(DACDriver *dacp,
*(&dacp->params->dac->R12DH0 + dacp->params->dataoffset) = (uint32_t)sample;
#endif
}
#if (GD32_HAS_DAC1_CH2)
#if (GD32_HAS_DAC_CH2)
else {
dacp->params->dac->R12DH1 = (uint32_t)sample;
}
@ -282,7 +277,7 @@ void dac_lld_put_channel(DACDriver *dacp,
*(&dacp->params->dac->L12DH0 + dacp->params->dataoffset) = (uint32_t)sample;
#endif
}
#if (GD32_HAS_DAC1_CH2)
#if (GD32_HAS_DAC_CH2)
else {
dacp->params->dac->L12DH1 = (uint32_t)sample;
}
@ -299,7 +294,7 @@ void dac_lld_put_channel(DACDriver *dacp,
*(&dacp->params->dac->R8DH0 + dacp->params->dataoffset) = (uint32_t)sample;
#endif
}
#if (GD32_HAS_DAC1_CH2)
#if (GD32_HAS_DAC_CH2)
else {
dacp->params->dac->R8DH1 = (uint32_t)sample;
}

88
os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.h
View File

@ -56,49 +56,49 @@
#endif
/**
* @brief DAC1 CH1 driver enable switch.
* @details If set to @p TRUE the support for DAC1 channel 1 is included.
* @brief DAC CH1 driver enable switch.
* @details If set to @p TRUE the support for DAC channel 1 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_DAC_USE_DAC1_CH1) || defined(__DOXYGEN__)
#define GD32_DAC_USE_DAC1_CH1 FALSE
#if !defined(GD32_DAC_USE_DAC_CH1) || defined(__DOXYGEN__)
#define GD32_DAC_USE_DAC_CH1 FALSE
#endif
/**
* @brief DAC1 CH2 driver enable switch.
* @details If set to @p TRUE the support for DAC1 channel 2 is included.
* @brief DAC CH2 driver enable switch.
* @details If set to @p TRUE the support for DAC channel 2 is included.
* @note The default is @p FALSE.
*/
#if !defined(GD32_DAC_USE_DAC1_CH2) || defined(__DOXYGEN__)
#define GD32_DAC_USE_DAC1_CH2 FALSE
#if !defined(GD32_DAC_USE_DAC_CH2) || defined(__DOXYGEN__)
#define GD32_DAC_USE_DAC_CH2 FALSE
#endif
/**
* @brief DAC1 CH1 interrupt priority level setting.
* @brief DAC CH1 interrupt priority level setting.
*/
#if !defined(GD32_DAC_DAC1_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#if !defined(GD32_DAC_DAC_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC_CH1_IRQ_PRIORITY 10
#endif
/**
* @brief DAC1 CH2 interrupt priority level setting.
* @brief DAC CH2 interrupt priority level setting.
*/
#if !defined(GD32_DAC_DAC1_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#if !defined(GD32_DAC_DAC_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC_CH2_IRQ_PRIORITY 10
#endif
/**
* @brief DAC1 CH1 DMA priority (0..3|lowest..highest).
* @brief DAC CH1 DMA priority (0..3|lowest..highest).
*/
#if !defined(GD32_DAC_DAC1_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC1_CH1_DMA_PRIORITY 2
#if !defined(GD32_DAC_DAC_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC_CH1_DMA_PRIORITY 2
#endif
/**
* @brief DAC1 CH2 DMA priority (0..3|lowest..highest).
* @brief DAC CH2 DMA priority (0..3|lowest..highest).
*/
#if !defined(GD32_DAC_DAC1_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC1_CH2_DMA_PRIORITY 2
#if !defined(GD32_DAC_DAC_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define GD32_DAC_DAC_CH2_DMA_PRIORITY 2
#endif
/** @} */
@ -107,48 +107,48 @@
/*===========================================================================*/
/* Handling missing registry keys.*/
#if !defined(GD32_HAS_DAC1_CH1)
#define GD32_HAS_DAC1_CH1 FALSE
#if !defined(GD32_HAS_DAC_CH1)
#define GD32_HAS_DAC_CH1 FALSE
#endif
#if !defined(GD32_HAS_DAC1_CH2)
#define GD32_HAS_DAC1_CH2 FALSE
#if !defined(GD32_HAS_DAC_CH2)
#define GD32_HAS_DAC_CH2 FALSE
#endif
#if GD32_DAC_USE_DAC1_CH1 && !GD32_HAS_DAC1_CH1
#error "DAC1 CH1 not present in the selected device"
#if GD32_DAC_USE_DAC_CH1 && !GD32_HAS_DAC_CH1
#error "DAC CH1 not present in the selected device"
#endif
#if GD32_DAC_USE_DAC1_CH2 && !GD32_HAS_DAC1_CH2
#error "DAC1 CH2 not present in the selected device"
#if GD32_DAC_USE_DAC_CH2 && !GD32_HAS_DAC_CH2
#error "DAC CH2 not present in the selected device"
#endif
#if GD32_DAC_USE_DAC1_CH2 && GD32_DAC_DUAL_MODE
#if GD32_DAC_USE_DAC_CH2 && GD32_DAC_DUAL_MODE
#error "DACx CH2 cannot be used independently in dual mode"
#endif
#if !GD32_DAC_USE_DAC1_CH1 && !GD32_DAC_USE_DAC1_CH2
#if !GD32_DAC_USE_DAC_CH1 && !GD32_DAC_USE_DAC_CH2
#error "DAC driver activated but no DAC peripheral assigned"
#endif
#if GD32_DAC_USE_DAC1_CH1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC1_CH1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC1 CH1"
#if GD32_DAC_USE_DAC_CH1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC_CH1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC CH1"
#endif
#if GD32_DAC_USE_DAC1_CH2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC1_CH2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC1 CH2"
#if GD32_DAC_USE_DAC_CH2 && \
!OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_DAC_CH2_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to DAC CH2"
#endif
#if GD32_DAC_USE_DAC1_CH1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC1_CH1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC1 CH1"
#if GD32_DAC_USE_DAC_CH1 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC_CH1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC CH1"
#endif
#if GD32_DAC_USE_DAC1_CH2 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC1_CH2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC1 CH2"
#if GD32_DAC_USE_DAC_CH2 && \
!GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_DAC_CH2_DMA_PRIORITY)
#error "Invalid DMA priority assigned to DAC CH2"
#endif
#if !defined(GD32_DMA_REQUIRED)
@ -273,11 +273,11 @@ typedef enum {
/* External declarations. */
/*===========================================================================*/
#if GD32_DAC_USE_DAC1_CH1 && !defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC_CH1 && !defined(__DOXYGEN__)
extern DACDriver DACD1;
#endif
#if GD32_DAC_USE_DAC1_CH2 && !GD32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
#if GD32_DAC_USE_DAC_CH2 && !GD32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
extern DACDriver DACD2;
#endif

12
os/hal/ports/GD/GD32VF103/gd32_rcu.h
View File

@ -206,27 +206,27 @@
* @{
*/
/**
* @brief Enables the DAC1 peripheral clock.
* @brief Enables the DAC peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rcuEnableDAC1(lp) rcuEnableAPB1(RCU_APB1ENR_DACEN, lp)
#define rcuEnableDAC(lp) rcuEnableAPB1(RCU_APB1ENR_DACEN, lp)
/**
* @brief Disables the DAC1 peripheral clock.
* @brief Disables the DAC peripheral clock.
*
* @api
*/
#define rcuDisableDAC1() rcuDisableAPB1(RCU_APB1ENR_DACEN)
#define rcuDisableDAC() rcuDisableAPB1(RCU_APB1ENR_DACEN)
/**
* @brief Resets the DAC1 peripheral.
* @brief Resets the DAC peripheral.
*
* @api
*/
#define rcuResetDAC1() rcuResetAPB1(RCU_APB1RSTR_DACRST)
#define rcuResetDAC() rcuResetAPB1(RCU_APB1RSTR_DACRST)
/** @} */
/**

8
os/hal/ports/GD/GD32VF103/gd32_registry.h
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@ -107,11 +107,11 @@
#define GD32_CAN_MAX_FILTERS 28
/* DAC attributes.*/
#define GD32_HAS_DAC1_CH1 TRUE
#define GD32_DAC_DAC1_CH1_DMA_STREAM GD32_DMA_STREAM_ID(0, 2)
#define GD32_HAS_DAC_CH1 TRUE
#define GD32_DAC_DAC_CH1_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
#define GD32_HAS_DAC1_CH2 TRUE
#define GD32_DAC_DAC1_CH2_DMA_STREAM GD32_DMA_STREAM_ID(0, 3)
#define GD32_HAS_DAC_CH2 TRUE
#define GD32_DAC_DAC_CH2_DMA_STREAM GD32_DMA_STREAM_ID(2, 3)
/* DMA attributes.*/
#define GD32_DMA0_NUM_CHANNELS 7

5
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -756,8 +756,7 @@ typedef struct
#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
#define BKP ((BKP_TypeDef *)BKP_BASE)
#define PMU ((PMU_TypeDef *)PMU_BASE)
#define DAC1 ((DAC_TypeDef *)DAC_BASE)
#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
#define DAC ((DAC_TypeDef *)DAC_BASE)
#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
@ -12513,7 +12512,7 @@ typedef struct
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/****************************** DAC Instances *********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA0_Channel0) || \