diff --git a/os/hal/ports/KINETIS/K60x/hal_lld.c b/os/hal/ports/KINETIS/K60x/hal_lld.c
index 45b20132..1efa47aa 100644
--- a/os/hal/ports/KINETIS/K60x/hal_lld.c
+++ b/os/hal/ports/KINETIS/K60x/hal_lld.c
@@ -186,9 +186,9 @@ void k60x_clock_init(void) {
   /*
    * Now in FBE mode
    */
-  #define KINETIS_PLLIN_FREQUENCY 2000000UL
+  #define KINETIS_PLLIN_FREQUENCY 4000000UL
   /*
-   * Config PLL input for 2 MHz
+   * Config PLL input for 4 MHz
    * TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz
    */
   MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
@@ -220,7 +220,7 @@ void k60x_clock_init(void) {
   SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
                  SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
                  SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
-  SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1);
+  SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC;
 
   /* Configure peripherals to use MCGPLLCLK */
   SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL_MCGPLL;