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Rename RTC registers

This commit is contained in:
Stefan Kerkmann 2021-03-29 13:29:23 +02:00
parent b4dd59eae6
commit ccaf60ac66
3 changed files with 87 additions and 115 deletions
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54
os/hal/ports/GD/GD32VF103/RTC/hal_rtc_lld.c
View File

@ -20,7 +20,7 @@
/**
* @file RTC/hal_rtc_lld.c
* @brief STM32 RTC subsystem low level driver header.
* @brief GD32 RTC subsystem low level driver header.
*
* @addtogroup RTC
* @{
@ -61,7 +61,7 @@ RTCDriver RTCD1;
*/
static void rtc_apb1_sync(void) {
while ((RTC->CRL & RTC_CRL_RSF) == 0)
while ((RTC->CTL & RTC_CTL_RSYNF) == 0)
;
}
@ -73,7 +73,7 @@ static void rtc_apb1_sync(void) {
*/
static void rtc_wait_write_completed(void) {
while ((RTC->CRL & RTC_CRL_RTOFF) == 0)
while ((RTC->CTL & RTC_CTL_LWOFF) == 0)
;
}
@ -88,7 +88,7 @@ static void rtc_wait_write_completed(void) {
static void rtc_acquire_access(void) {
rtc_wait_write_completed();
RTC->CRL |= RTC_CRL_CNF;
RTC->CTL |= RTC_CTL_CMF;
}
/**
@ -98,7 +98,7 @@ static void rtc_acquire_access(void) {
*/
static void rtc_release_access(void) {
RTC->CRL &= ~RTC_CRL_CNF;
RTC->CTL &= ~RTC_CTL_CMF;
}
/**
@ -164,16 +164,16 @@ OSAL_IRQ_HANDLER(GD32_RTC1_HANDLER) {
rtc_apb1_sync();
/* Mask of all enabled and pending sources.*/
flags = RTCD1.rtc->CRH & RTCD1.rtc->CRL;
RTCD1.rtc->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF);
flags = RTCD1.rtc->INTEN & RTCD1.rtc->CTL;
RTCD1.rtc->CTL &= ~(RTC_CTL_SCIF | RTC_CTL_ALRMIF | RTC_CTL_OVIF);
if (flags & RTC_CRL_SECF)
if (flags & RTC_CTL_SCIF)
RTCD1.callback(&RTCD1, RTC_EVENT_SECOND);
if (flags & RTC_CRL_ALRF)
if (flags & RTC_CTL_ALRMIF)
RTCD1.callback(&RTCD1, RTC_EVENT_ALARM);
if (flags & RTC_CRL_OWF)
if (flags & RTC_CTL_OVIF)
RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW);
OSAL_IRQ_EPILOGUE();
@ -200,8 +200,8 @@ void rtc_lld_set_prescaler(void) {
sts = osalSysGetStatusAndLockX();
rtc_acquire_access();
RTC->PRLH = (uint16_t)((GD32_RTCCLK - 1) >> 16) & 0x000F;
RTC->PRLL = (uint16_t)(((GD32_RTCCLK - 1)) & 0xFFFF);
RTC->PSCH = (uint16_t)((GD32_RTCCLK - 1) >> 16) & 0x000F;
RTC->PSCL = (uint16_t)(((GD32_RTCCLK - 1)) & 0xFFFF);
rtc_release_access();
/* Leaving a reentrant critical zone.*/
@ -223,14 +223,14 @@ void rtc_lld_init(void) {
/* RSF bit must be cleared by software after an APB1 reset or an APB1 clock
stop. Otherwise its value will not be actual. */
RTCD1.rtc->CRL &= ~RTC_CRL_RSF;
RTCD1.rtc->CTL &= ~RTC_CTL_RSYNF;
/* Required because access to PRL.*/
rtc_apb1_sync();
/* All interrupts initially disabled.*/
rtc_wait_write_completed();
RTCD1.rtc->CRH = 0;
RTCD1.rtc->INTEN = 0;
/* Callback initially disabled.*/
RTCD1.callback = NULL;
@ -242,7 +242,7 @@ void rtc_lld_init(void) {
/**
* @brief Set current time.
* @note Fractional part will be silently ignored. There is no possibility
* to change it on STM32F1xx platform.
* to change it on GD32F1xx platform.
* @note The function can be called from any context.
*
* @param[in] rtcp pointer to RTC driver structure
@ -253,7 +253,7 @@ void rtc_lld_init(void) {
void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) {
time_t tv_sec = rtc_encode(timespec);
rtcSTM32SetSec(rtcp, tv_sec);
rtcGD32SetSec(rtcp, tv_sec);
}
/**
@ -268,7 +268,7 @@ void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) {
void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) {
uint32_t tv_sec, tv_msec;
rtcSTM32GetSecMsec(rtcp, &tv_sec, &tv_msec);
rtcGD32GetSecMsec(rtcp, &tv_sec, &tv_msec);
rtc_decode(tv_sec, tv_msec, timespec);
}
@ -295,12 +295,12 @@ void rtc_lld_set_alarm(RTCDriver *rtcp,
rtc_acquire_access();
if (alarmspec != NULL) {
rtcp->rtc->ALRH = (uint16_t)(alarmspec->tv_sec >> 16);
rtcp->rtc->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF);
rtcp->rtc->ALRMH = (uint16_t)(alarmspec->tv_sec >> 16);
rtcp->rtc->ALRML = (uint16_t)(alarmspec->tv_sec & 0xFFFF);
}
else {
rtcp->rtc->ALRH = 0;
rtcp->rtc->ALRL = 0;
rtcp->rtc->ALRMH = 0;
rtcp->rtc->ALRML = 0;
}
rtc_release_access();
@ -333,7 +333,7 @@ void rtc_lld_get_alarm(RTCDriver *rtcp,
/* Required because access to ALR.*/
rtc_apb1_sync();
alarmspec->tv_sec = ((rtcp->rtc->ALRH << 16) + rtcp->rtc->ALRL);
alarmspec->tv_sec = ((rtcp->rtc->ALRMH << 16) + rtcp->rtc->ALRML);
/* Leaving a reentrant critical zone.*/
osalSysRestoreStatusX(sts);
@ -362,12 +362,12 @@ void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
rtcp->callback = callback;
rtc_wait_write_completed();
rtcp->rtc->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF);
rtcp->rtc->CRH = RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE;
rtcp->rtc->CTL &= ~(RTC_CTL_OVIF | RTC_CTL_ALRMIF | RTC_CTL_SCIF);
rtcp->rtc->INTEN = RTC_INTEN_OVIE | RTC_INTEN_ALRMIE | RTC_INTEN_SCIE;
}
else {
rtc_wait_write_completed();
rtcp->rtc->CRH = 0;
rtcp->rtc->INTEN = 0;
/* Callback set to NULL only after disabling the IRQ sources.*/
rtcp->callback = NULL;
@ -388,7 +388,7 @@ void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
*
* @api
*/
void rtcSTM32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec) {
void rtcGD32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec) {
uint32_t time_frac;
syssts_t sts;
@ -425,7 +425,7 @@ void rtcSTM32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec) {
*
* @api
*/
void rtcSTM32SetSec(RTCDriver *rtcp, uint32_t tv_sec) {
void rtcGD32SetSec(RTCDriver *rtcp, uint32_t tv_sec) {
syssts_t sts;
osalDbgCheck(NULL != rtcp);

6
os/hal/ports/GD/GD32VF103/RTC/hal_rtc_lld.h
View File

@ -20,7 +20,7 @@
/**
* @file RTC/hal_rtc_lld.h
* @brief STM32 RTC subsystem low level driver header.
* @brief GD32 RTC subsystem low level driver header.
*
* @addtogroup RTC
* @{
@ -139,8 +139,8 @@ extern "C" {
rtcalarm_t alarm_number,
RTCAlarm *alarmspec);
void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback);
void rtcSTM32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec);
void rtcSTM32SetSec(RTCDriver *rtcp, uint32_t tv_sec);
void rtcGD32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec);
void rtcGD32SetSec(RTCDriver *rtcp, uint32_t tv_sec);
#ifdef __cplusplus
}
#endif

142
os/hal/ports/GD/GD32VF103/stm32f105xc.h
View File

@ -448,46 +448,18 @@ typedef struct
typedef struct
{
__IO uint32_t CRH;
__IO uint32_t CRL;
__IO uint32_t PRLH;
__IO uint32_t PRLL;
__IO uint32_t INTEN;
__IO uint32_t CTL;
__IO uint32_t PSCH;
__IO uint32_t PSCL;
__IO uint32_t DIVH;
__IO uint32_t DIVL;
__IO uint32_t CNTH;
__IO uint32_t CNTL;
__IO uint32_t ALRH;
__IO uint32_t ALRL;
__IO uint32_t ALRMH;
__IO uint32_t ALRML;
} RTC_TypeDef;
/**
* @brief SD host Interface
*/
typedef struct
{
__IO uint32_t POWER;
__IO uint32_t CLKCR;
__IO uint32_t ARG;
__IO uint32_t CMD;
__I uint32_t RESPCMD;
__I uint32_t RESP1;
__I uint32_t RESP2;
__I uint32_t RESP3;
__I uint32_t RESP4;
__IO uint32_t DTIMER;
__IO uint32_t DLEN;
__IO uint32_t DCTRL;
__I uint32_t DCOUNT;
__I uint32_t STA;
__IO uint32_t ICR;
__IO uint32_t MASK;
uint32_t RESERVED0[2];
__I uint32_t FIFOCNT;
uint32_t RESERVED1[13];
__IO uint32_t FIFO;
} SDIO_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
@ -5127,56 +5099,56 @@ typedef struct
/* */
/******************************************************************************/
/******************* Bit definition for RTC_CRH register ********************/
#define RTC_CRH_SECIE_Pos (0U)
#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
#define RTC_CRH_ALRIE_Pos (1U)
#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
#define RTC_CRH_OWIE_Pos (2U)
#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
/******************* Bit definition for RTC_INTEN register ********************/
#define RTC_INTEN_SCIE_Pos (0U)
#define RTC_INTEN_SCIE_Msk (0x1U << RTC_INTEN_SCIE_Pos) /*!< 0x00000001 */
#define RTC_INTEN_SCIE RTC_INTEN_SCIE_Msk /*!< Second Interrupt Enable */
#define RTC_INTEN_ALRMIE_Pos (1U)
#define RTC_INTEN_ALRMIE_Msk (0x1U << RTC_INTEN_ALRMIE_Pos) /*!< 0x00000002 */
#define RTC_INTEN_ALRMIE RTC_INTEN_ALRMIE_Msk /*!< Alarm Interrupt Enable */
#define RTC_INTEN_OVIE_Pos (2U)
#define RTC_INTEN_OVIE_Msk (0x1U << RTC_INTEN_OVIE_Pos) /*!< 0x00000004 */
#define RTC_INTEN_OVIE RTC_INTEN_OVIE_Msk /*!< OverfloW Interrupt Enable */
/******************* Bit definition for RTC_CRL register ********************/
#define RTC_CRL_SECF_Pos (0U)
#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
#define RTC_CRL_ALRF_Pos (1U)
#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
#define RTC_CRL_OWF_Pos (2U)
#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
#define RTC_CRL_RSF_Pos (3U)
#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
#define RTC_CRL_CNF_Pos (4U)
#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
#define RTC_CRL_RTOFF_Pos (5U)
#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
/******************* Bit definition for RTC_CTL register ********************/
#define RTC_CTL_SCIF_Pos (0U)
#define RTC_CTL_SCIF_Msk (0x1U << RTC_CTL_SCIF_Pos) /*!< 0x00000001 */
#define RTC_CTL_SCIF RTC_CTL_SCIF_Msk /*!< Second Flag */
#define RTC_CTL_ALRMIF_Pos (1U)
#define RTC_CTL_ALRMIF_Msk (0x1U << RTC_CTL_ALRMIF_Pos) /*!< 0x00000002 */
#define RTC_CTL_ALRMIF RTC_CTL_ALRMIF_Msk /*!< Alarm Flag */
#define RTC_CTL_OVIF_Pos (2U)
#define RTC_CTL_OVIF_Msk (0x1U << RTC_CTL_OVIF_Pos) /*!< 0x00000004 */
#define RTC_CTL_OVIF RTC_CTL_OVIF_Msk /*!< OverfloW Flag */
#define RTC_CTL_RSYNF_Pos (3U)
#define RTC_CTL_RSYNF_Msk (0x1U << RTC_CTL_RSYNF_Pos) /*!< 0x00000008 */
#define RTC_CTL_RSYNF RTC_CTL_RSYNF_Msk /*!< Registers Synchronized Flag */
#define RTC_CTL_CMF_Pos (4U)
#define RTC_CTL_CMF_Msk (0x1U << RTC_CTL_CMF_Pos) /*!< 0x00000010 */
#define RTC_CTL_CMF RTC_CTL_CMF_Msk /*!< Configuration Flag */
#define RTC_CTL_LWOFF_Pos (5U)
#define RTC_CTL_LWOFF_Msk (0x1U << RTC_CTL_LWOFF_Pos) /*!< 0x00000020 */
#define RTC_CTL_LWOFF RTC_CTL_LWOFF_Msk /*!< RTC operation OFF */
/******************* Bit definition for RTC_PRLH register *******************/
#define RTC_PRLH_PRL_Pos (0U)
#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
/******************* Bit definition for RTC_PSCH register *******************/
#define RTC_PSCH_PSC_Pos (0U)
#define RTC_PSCH_PSC_Msk (0xFU << RTC_PSCH_PSC_Pos) /*!< 0x0000000F */
#define RTC_PSCH_PSC RTC_PSCH_PSC_Msk /*!< RTC Prescaler Reload Value High */
/******************* Bit definition for RTC_PRLL register *******************/
#define RTC_PRLL_PRL_Pos (0U)
#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
/******************* Bit definition for RTC_PSCL register *******************/
#define RTC_PSCL_PSC_Pos (0U)
#define RTC_PSCL_PSC_Msk (0xFFFFU << RTC_PSCL_PSC_Pos) /*!< 0x0000FFFF */
#define RTC_PSCL_PSC RTC_PSCL_PSC_Msk /*!< RTC Prescaler Reload Value Low */
/******************* Bit definition for RTC_DIVH register *******************/
#define RTC_DIVH_RTC_DIV_Pos (0U)
#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
#define RTC_DIVH_DIV_Pos (0U)
#define RTC_DIVH_DIV_Msk (0xFU << RTC_DIVH_DIV_Pos) /*!< 0x0000000F */
#define RTC_DIVH_RTC_DIV RTC_DIVH_DIV_Msk /*!< RTC Clock Divider High */
/******************* Bit definition for RTC_DIVL register *******************/
#define RTC_DIVL_RTC_DIV_Pos (0U)
#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
#define RTC_DIVL_DIV_Pos (0U)
#define RTC_DIVL_DIV_Msk (0xFFFFU << RTC_DIVL_DIV_Pos) /*!< 0x0000FFFF */
#define RTC_DIVL_RTC_DIV RTC_DIVL_DIV_Msk /*!< RTC Clock Divider Low */
/******************* Bit definition for RTC_CNTH register *******************/
#define RTC_CNTH_RTC_CNT_Pos (0U)
@ -5188,15 +5160,15 @@ typedef struct
#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
/******************* Bit definition for RTC_ALRH register *******************/
#define RTC_ALRH_RTC_ALR_Pos (0U)
#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
/******************* Bit definition for RTC_ALRMH register *******************/
#define RTC_ALRMH_RTC_ALRM_Pos (0U)
#define RTC_ALRMH_RTC_ALRM_Msk (0xFFFFU << RTC_ALRMH_RTC_ALRM_Pos) /*!< 0x0000FFFF */
#define RTC_ALRMH_RTC_ALRM RTC_ALRMH_RTC_ALRM_Msk /*!< RTC Alarm High */
/******************* Bit definition for RTC_ALRL register *******************/
#define RTC_ALRL_RTC_ALR_Pos (0U)
#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
/******************* Bit definition for RTC_ALRML register *******************/
#define RTC_ALRML_RTC_ALRM_Pos (0U)
#define RTC_ALRML_RTC_ALRM_Msk (0xFFFFU << RTC_ALRML_RTC_ALRM_Pos) /*!< 0x0000FFFF */
#define RTC_ALRML_RTC_ALRM RTC_ALRML_RTC_ALRM_Msk /*!< RTC Alarm Low */
/******************************************************************************/
/* */