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Remove CAN peripheral not present on this device

This commit is contained in:
Stefan Kerkmann 2021-03-26 10:43:22 +01:00
parent 8d45fbc68c
commit cfdbcfe8d9
2 changed files with 1 additions and 193 deletions
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160
os/hal/ports/GD/GD32VF103/CAN/hal_can_lld.c
View File

@ -53,11 +53,6 @@ CANDriver CAND1;
CANDriver CAND2;
#endif
/** @brief CAN3 driver identifier.*/
#if GD32_CAN_USE_CAN3 || defined(__DOXYGEN__)
CANDriver CAND3;
#endif
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@ -99,14 +94,6 @@ static void can_lld_set_filters(CANDriver* canp,
}
#endif
#if GD32_CAN_USE_CAN3
if (canp == &CAND3) {
rccEnableCAN3(true);
/* Filters initialization.*/
canp->can->FMR = (canp->can->FMR & 0xFFFF0000) | CAN_FMR_FINIT;
}
#endif
if (num > 0) {
uint32_t i, fmask;
@ -125,15 +112,6 @@ static void can_lld_set_filters(CANDriver* canp,
}
#endif
#if GD32_CAN_USE_CAN3
if (canp == &CAND3) {
for (i = 0; i < GD32_CAN3_MAX_FILTERS; i++) {
canp->can->sFilterRegister[i].FR1 = 0;
canp->can->sFilterRegister[i].FR2 = 0;
}
}
#endif
/* Scanning the filters array.*/
for (i = 0; i < num; i++) {
fmask = 1 << cfp->filter;
@ -180,11 +158,6 @@ static void can_lld_set_filters(CANDriver* canp,
rccDisableCAN1();
}
#endif
#if GD32_CAN_USE_CAN3
if (canp == &CAND3) {
rccDisableCAN3();
}
#endif
}
/**
@ -512,97 +485,6 @@ OSAL_IRQ_HANDLER(GD32_CAN1_EWMC_HANDLER) {
#endif /* !defined(GD32_CAN1_UNIFIED_HANDLER) */
#endif /* GD32_CAN_USE_CAN2 */
#if GD32_CAN_USE_CAN3 || defined(__DOXYGEN__)
#if defined(GD32_CAN3_UNIFIED_HANDLER)
/**
* @brief CAN1 unified interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_CAN3_UNIFIED_HANDLER) {
OSAL_IRQ_PROLOGUE();
can_lld_tx_handler(&CAND3);
can_lld_rx0_handler(&CAND3);
can_lld_rx1_handler(&CAND3);
can_lld_sce_handler(&CAND3);
OSAL_IRQ_EPILOGUE();
}
#else /* !defined(GD32_CAN3_UNIFIED_HANDLER) */
#if !defined(GD32_CAN3_TX_HANDLER)
#error "GD32_CAN3_TX_HANDLER not defined"
#endif
#if !defined(GD32_CAN3_RX0_HANDLER)
#error "GD32_CAN3_RX0_HANDLER not defined"
#endif
#if !defined(GD32_CAN3_RX1_HANDLER)
#error "GD32_CAN3_RX1_HANDLER not defined"
#endif
#if !defined(GD32_CAN3_EWMC_HANDLER)
#error "GD32_CAN3_EWMC_HANDLER not defined"
#endif
/**
* @brief CAN3 TX interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_CAN3_TX_HANDLER) {
OSAL_IRQ_PROLOGUE();
can_lld_tx_handler(&CAND3);
OSAL_IRQ_EPILOGUE();
}
/**
* @brief CAN3 RX0 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_CAN3_RX0_HANDLER) {
OSAL_IRQ_PROLOGUE();
can_lld_rx0_handler(&CAND3);
OSAL_IRQ_EPILOGUE();
}
/**
* @brief CAN1 RX3 interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_CAN3_RX1_HANDLER) {
OSAL_IRQ_PROLOGUE();
can_lld_rx1_handler(&CAND3);
OSAL_IRQ_EPILOGUE();
}
/**
* @brief CAN1 SCE interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(GD32_CAN3_EWMC_HANDLER) {
OSAL_IRQ_PROLOGUE();
can_lld_sce_handler(&CAND3);
OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(GD32_CAN0_UNIFIED_HANDLER) */
#endif /* GD32_CAN_USE_CAN1 */
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@ -640,20 +522,6 @@ void can_lld_init(void) {
eclicEnableVector(GD32_CAN1_RX1_NUMBER, GD32_CAN_CAN2_IRQ_PRIORITY, GD32_CAN_CAN2_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN1_EWMC_NUMBER, GD32_CAN_CAN2_IRQ_PRIORITY, GD32_CAN_CAN2_IRQ_TRIGGER);
#endif
#endif
#if GD32_CAN_USE_CAN3
/* Driver initialization.*/
canObjectInit(&CAND3);
CAND3.can = CAN3;
#if defined(GD32_CAN3_UNIFIED_NUMBER)
eclicEnableVector(GD32_CAN3_UNIFIED_NUMBER, GD32_CAN_CAN3_IRQ_PRIORITY, GD32_CAN_CAN3_IRQ_TRIGGER);
#else
eclicEnableVector(GD32_CAN3_TX_NUMBER, GD32_CAN_CAN3_IRQ_PRIORITY, GD32_CAN_CAN3_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN3_RX0_NUMBER, GD32_CAN_CAN3_IRQ_PRIORITY, GD32_CAN_CAN3_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN3_RX1_NUMBER, GD32_CAN_CAN3_IRQ_PRIORITY, GD32_CAN_CAN3_IRQ_TRIGGER);
eclicEnableVector(GD32_CAN3_EWMC_NUMBER, GD32_CAN_CAN3_IRQ_PRIORITY, GD32_CAN_CAN3_IRQ_TRIGGER);
#endif
#endif
/* Filters initialization.*/
@ -664,12 +532,6 @@ void can_lld_init(void) {
can_lld_set_filters(&CAND1, GD32_CAN_MAX_FILTERS, 0, NULL);
#endif
#endif
#if GD32_HAS_CAN3
#if GD32_CAN_USE_CAN3
can_lld_set_filters(&CAND3, GD32_CAN3_MAX_FILTERS, 0, NULL);
#endif
#endif
}
/**
@ -695,12 +557,6 @@ void can_lld_start(CANDriver *canp) {
}
#endif
#if GD32_CAN_USE_CAN3
if (&CAND3 == canp) {
rccEnableCAN3(true);
}
#endif
/* Configuring CAN. */
canp->can->MCR = CAN_MCR_INRQ;
while ((canp->can->MSR & CAN_MSR_INAK) == 0)
@ -761,14 +617,6 @@ void can_lld_stop(CANDriver *canp) {
rccDisableCAN2();
}
#endif
#if GD32_CAN_USE_CAN3
if (&CAND3 == canp) {
CAN3->MCR = 0x00010002; /* Register reset value. */
CAN3->IER = 0x00000000; /* All sources disabled. */
rccDisableCAN3();
}
#endif
}
}
@ -1011,20 +859,12 @@ void canSTM32SetFilters(CANDriver *canp, uint32_t can2sb,
#if GD32_CAN_USE_CAN2
osalDbgAssert(CAND2.state == CAN_STOP, "invalid state");
#endif
#if GD32_CAN_USE_CAN3
osalDbgAssert(CAND3.state == CAN_STOP, "invalid state");
#endif
#if GD32_CAN_USE_CAN1
if (canp == &CAND1) {
can_lld_set_filters(canp, can2sb, num, cfp);
}
#endif
#if GD32_CAN_USE_CAN3
if (canp == &CAND3) {
can_lld_set_filters(canp, can2sb, num, cfp);
}
#endif
}
#endif /* HAL_USE_CAN */

34
os/hal/ports/GD/GD32VF103/CAN/hal_can_lld.h
View File

@ -104,14 +104,6 @@
#define GD32_CAN_USE_CAN2 FALSE
#endif
/**
* @brief CAN3 driver enable switch.
* @details If set to @p TRUE the support for CAN3 is included.
*/
#if !defined(GD32_CAN_USE_CAN3) || defined(__DOXYGEN__)
#define GD32_CAN_USE_CAN3 FALSE
#endif
/**
* @brief CAN1 interrupt priority level setting.
*/
@ -128,14 +120,6 @@
#endif
/** @} */
/**
* @brief CAN3 interrupt priority level setting.
*/
#if !defined(GD32_CAN_CAN3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define GD32_CAN_CAN3_IRQ_PRIORITY 11
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@ -148,18 +132,10 @@
#error "GD32_HAS_CAN2 not defined in registry"
#endif
#if !defined(GD32_HAS_CAN3)
#error "GD32_HAS_CAN3 not defined in registry"
#endif
#if (GD32_HAS_CAN1 | GD32_HAS_CAN2) && !defined(GD32_CAN_MAX_FILTERS)
#error "GD32_CAN_MAX_FILTERS not defined in registry"
#endif
#if GD32_HAS_CAN3 && !defined(GD32_CAN3_MAX_FILTERS)
#error "GD32_CAN3_MAX_FILTERS not defined in registry"
#endif
#if GD32_CAN_USE_CAN1 && !GD32_HAS_CAN1
#error "CAN1 not present in the selected device"
#endif
@ -168,11 +144,7 @@
#error "CAN2 not present in the selected device"
#endif
#if GD32_CAN_USE_CAN3 && !GD32_HAS_CAN3
#error "CAN2 not present in the selected device"
#endif
#if !GD32_CAN_USE_CAN1 && !GD32_CAN_USE_CAN2 && !GD32_CAN_USE_CAN3
#if !GD32_CAN_USE_CAN1 && !GD32_CAN_USE_CAN2
#error "CAN driver activated but no CAN peripheral assigned"
#endif
@ -434,10 +406,6 @@ extern CANDriver CAND1;
extern CANDriver CAND2;
#endif
#if GD32_CAN_USE_CAN3 && !defined(__DOXYGEN__)
extern CANDriver CAND3;
#endif
#ifdef __cplusplus
extern "C" {
#endif