From 97b7064031ed2be5980a59cdab8174a9074febb4 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Tue, 29 Oct 2019 19:38:09 +0100 Subject: [PATCH 1/9] Updating FSMC driver (SDRAM part first) --- os/hal/hal.mk | 6 +- .../hal_nand_lld.h => include/fsmc/nand.h} | 27 +- .../hal_fsmc_sdram.h => include/fsmc/sdram.h} | 24 +- os/hal/include/fsmc/sram.h | 170 +++++++++++ os/hal/include/hal_community.h | 5 + .../STM32/LLD/FSMCv1 => include}/hal_fsmc.h | 81 ++++- os/hal/ports/STM32/LLD/FSMCv1/driver.mk | 20 +- .../{hal_nand_lld.c => hal_fsmc_nand_lld.c} | 6 +- .../STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h | 289 ++++++++++++++++++ ...{hal_fsmc_sdram.c => hal_fsmc_sdram_lld.c} | 91 ++---- .../STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h | 117 +++++++ .../{hal_fsmc_sram.c => hal_fsmc_sram_lld.c} | 0 .../{hal_fsmc_sram.h => hal_fsmc_sram_lld.h} | 0 os/hal/src/hal_community.c | 4 + .../STM32/LLD/FSMCv1 => src}/hal_fsmc.c | 79 ++++- .../STM32F4xx/FSMC_SDRAM/halconf_community.h | 18 +- testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c | 1 - .../STM32F4xx/FSMC_SDRAM/mcuconf_community.h | 26 +- 18 files changed, 807 insertions(+), 157 deletions(-) rename os/hal/{ports/STM32/LLD/FSMCv1/hal_nand_lld.h => include/fsmc/nand.h} (92%) rename os/hal/{ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h => include/fsmc/sdram.h} (89%) create mode 100644 os/hal/include/fsmc/sram.h rename os/hal/{ports/STM32/LLD/FSMCv1 => include}/hal_fsmc.h (89%) rename os/hal/ports/STM32/LLD/FSMCv1/{hal_nand_lld.c => hal_fsmc_nand_lld.c} (99%) create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h rename os/hal/ports/STM32/LLD/FSMCv1/{hal_fsmc_sdram.c => hal_fsmc_sdram_lld.c} (72%) create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h rename os/hal/ports/STM32/LLD/FSMCv1/{hal_fsmc_sram.c => hal_fsmc_sram_lld.c} (100%) rename os/hal/ports/STM32/LLD/FSMCv1/{hal_fsmc_sram.h => hal_fsmc_sram_lld.h} (100%) rename os/hal/{ports/STM32/LLD/FSMCv1 => src}/hal_fsmc.c (77%) diff --git a/os/hal/hal.mk b/os/hal/hal.mk index ae27ea54..9908965c 100644 --- a/os/hal/hal.mk +++ b/os/hal/hal.mk @@ -10,8 +10,8 @@ endif HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c -ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c +ifneq ($(findstring HAL_USE_FSMC_SDRAM TRUE,$(HALCONF)), $(findstring HAL_USE_FSMC_SRAM TRUE,$(HALCONF)), $(findstring HAL_USE_FSMC_NAND TRUE,$(HALCONF))) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c endif ifneq ($(findstring HAL_USE_ONEWIRE TRUE,$(HALCONF)),) HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c @@ -75,7 +75,7 @@ HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_opamp.c endif else HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c \ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h b/os/hal/include/fsmc/nand.h similarity index 92% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h rename to os/hal/include/fsmc/nand.h index 52661386..b2d9001f 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h +++ b/os/hal/include/fsmc/nand.h @@ -22,13 +22,12 @@ * @{ */ -#ifndef HAL_NAND_LLD_H_ -#define HAL_NAND_LLD_H_ +#ifndef NAND_H_ +#define NAND_H_ -#include "hal_fsmc.h" #include "bitmap.h" -#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -55,16 +54,16 @@ * @brief NAND driver enable switch. * @details If set to @p TRUE the support for NAND1 is included. */ -#if !defined(STM32_NAND_USE_NAND1) || defined(__DOXYGEN__) -#define STM32_NAND_USE_NAND1 FALSE +#if !defined(STM32_FSMC_USE_NAND1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_NAND1 FALSE #endif /** * @brief NAND driver enable switch. * @details If set to @p TRUE the support for NAND2 is included. */ -#if !defined(STM32_NAND_USE_NAND2) || defined(__DOXYGEN__) -#define STM32_NAND_USE_NAND2 FALSE +#if !defined(STM32_FSMC_USE_NAND2) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_NAND2 FALSE #endif /** @@ -112,11 +111,11 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if !STM32_NAND_USE_FSMC_NAND1 && !STM32_NAND_USE_FSMC_NAND2 +#if !STM32_FSMC_USE_NAND1 && !STM32_FSMC_USE_NAND2 #error "NAND driver activated but no NAND peripheral assigned" #endif -#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && !STM32_HAS_FSMC +#if (STM32_FSMC_USE_NAND1 || STM32_FSMC_USE_NAND2) && !STM32_HAS_FSMC #error "FSMC not present in the selected device" #endif @@ -260,11 +259,11 @@ struct NANDDriver { /* External declarations. */ /*===========================================================================*/ -#if STM32_NAND_USE_FSMC_NAND1 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_NAND1 && !defined(__DOXYGEN__) extern NANDDriver NANDD1; #endif -#if STM32_NAND_USE_FSMC_NAND2 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_NAND2 && !defined(__DOXYGEN__) extern NANDDriver NANDD2; #endif @@ -287,8 +286,8 @@ extern "C" { } #endif -#endif /* HAL_USE_NAND */ +#endif /* HAL_USE_FSMC_NAND */ -#endif /* HAL_NAND_LLD_H_ */ +#endif /* NAND_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/os/hal/include/fsmc/sdram.h similarity index 89% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h rename to os/hal/include/fsmc/sdram.h index c9f9de09..83b78a67 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h +++ b/os/hal/include/fsmc/sdram.h @@ -25,8 +25,8 @@ * @{ */ -#ifndef HAL_FMC_SDRAM_H_ -#define HAL_FMC_SDRAM_H_ +#ifndef SDRAM_H_ +#define SDRAM_H_ #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ @@ -35,9 +35,7 @@ defined(STM32F769xx) || defined(STM32F777xx) || \ defined(STM32F779xx)) -#include "hal_fsmc.h" - -#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -55,8 +53,8 @@ * @brief SDRAM driver enable switch. * @details If set to @p TRUE the support for SDRAM1 is included. */ -#if !defined(STM32_SDRAM_USE_FSMC_SDRAM1) || defined(__DOXYGEN__) -#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE +#if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SDRAM1 FALSE #else #define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE #endif @@ -65,8 +63,8 @@ * @brief SDRAM driver enable switch. * @details If set to @p TRUE the support for SDRAM2 is included. */ -#if !defined(STM32_SDRAM_USE_FSMC_SDRAM2) || defined(__DOXYGEN__) -#define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE +#if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SDRAM2 FALSE #else #define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE #endif @@ -77,11 +75,11 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if !STM32_SDRAM_USE_FSMC_SDRAM1 && !STM32_SDRAM_USE_FSMC_SDRAM2 +#if !STM32_FSMC_USE_SDRAM1 && !STM32_FSMC_USE_SDRAM2 #error "SDRAM driver activated but no SDRAM peripheral assigned" #endif -#if (STM32_SDRAM_USE_FSMC_SDRAM1 || STM32_SDRAM_USE_FSMC_SDRAM2) && !STM32_HAS_FSMC +#if (STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2) && !STM32_HAS_FSMC #error "FMC not present in the selected device" #endif @@ -166,10 +164,10 @@ extern "C" { } #endif -#endif /* STM32_USE_FSMC_SDRAM */ +#endif /* HAL_USE_FSMC_SDRAM */ #endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ -#endif /* HAL_FMC_SDRAM_H_ */ +#endif /* SDRAM_H_ */ /** @} */ diff --git a/os/hal/include/fsmc/sram.h b/os/hal/include/fsmc/sram.h new file mode 100644 index 00000000..6eed97a5 --- /dev/null +++ b/os/hal/include/fsmc/sram.h @@ -0,0 +1,170 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc_sram.h + * @brief SRAM Driver subsystem low level driver header. + * + * @addtogroup SRAM + * @{ + */ + +#ifndef SRAM_H_ +#define SRAM_H_ + +#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM1 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM1 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM2 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM2 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM3 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM3 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM4 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM4 FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \ + !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4 +#error "SRAM driver activated but no SRAM peripheral assigned" +#endif + +#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \ + STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SRAM_UNINIT = 0, /**< Not initialized. */ + SRAM_STOP = 1, /**< Stopped. */ + SRAM_READY = 2, /**< Ready. */ +} sramstate_t; + +/** + * @brief Type of a structure representing an NAND driver. + */ +typedef struct SRAMDriver SRAMDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + * @note Some bits in BCR register will be forced by driver. + */ +typedef struct { + uint32_t bcr; + uint32_t btr; + uint32_t bwtr; +} SRAMConfig; + +/** + * @brief Structure representing an NAND driver. + */ +struct SRAMDriver { + /** + * @brief Driver state. + */ + sramstate_t state; + /** + * @brief Pointer to the FSMC SRAM registers block. + */ + FSMC_SRAM_NOR_TypeDef *sram; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD1; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD2; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD3; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void fsmcSramInit(void); + void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); + void fsmcSramStop(SRAMDriver *sramp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_FSMC_SRAM */ + +#endif /* SRAM_H_ */ + +/** @} */ diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index f84e90a5..ad5c4721 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -79,6 +79,10 @@ #define HAL_USE_OPAMP FALSE #endif +#if !defined(HAL_USE_FSMC) +#define HAL_USE_FSMC FALSE +#endif + /* Abstract interfaces.*/ /* Shared headers.*/ @@ -99,6 +103,7 @@ #include "hal_eeprom.h" #include "hal_usb_hid.h" #include "hal_usb_msd.h" +#include "hal_fsmc.h" /*===========================================================================*/ /* Driver constants. */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/include/hal_fsmc.h similarity index 89% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h rename to os/hal/include/hal_fsmc.h index 80c5d269..f85079a5 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h +++ b/os/hal/include/hal_fsmc.h @@ -25,7 +25,9 @@ #ifndef HAL_FSMC_H_ #define HAL_FSMC_H_ -#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__) +#include "hal.h" + +#if (HAL_USE_FSMC_SDRAM == TRUE) || (HAL_USE_FSMC_SRAM == TRUE) || (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -246,6 +248,10 @@ typedef struct { /* Driver pre-compile time settings. */ /*===========================================================================*/ +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + /** * @name Configuration options * @{ @@ -258,6 +264,31 @@ typedef struct { #define STM32_FSMC_USE_FSMC1 FALSE #endif +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM is included. + */ +#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SDRAM FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM is included. + */ +#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SRAM FALSE +#endif + +/** + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND is included. + */ +#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_NAND FALSE +#endif + + /** @} */ /*===========================================================================*/ @@ -295,29 +326,35 @@ struct FSMCDriver { fsmcstate_t state; /* End of the mandatory fields.*/ -#if STM32_SRAM_USE_FSMC_SRAM1 +#if HAL_USE_FSMC_SRAM + #if STM32_SRAM_USE_FSMC_SRAM1 FSMC_SRAM_NOR_TypeDef *sram1; -#endif -#if STM32_SRAM_USE_FSMC_SRAM2 + #endif + #if STM32_SRAM_USE_FSMC_SRAM2 FSMC_SRAM_NOR_TypeDef *sram2; -#endif -#if STM32_SRAM_USE_FSMC_SRAM3 + #endif + #if STM32_SRAM_USE_FSMC_SRAM3 FSMC_SRAM_NOR_TypeDef *sram3; -#endif -#if STM32_SRAM_USE_FSMC_SRAM4 + #endif + #if STM32_SRAM_USE_FSMC_SRAM4 FSMC_SRAM_NOR_TypeDef *sram4; + #endif #endif -#if STM32_NAND_USE_FSMC_NAND1 + +#if HAL_USE_FSMC_NAND + #if STM32_NAND_USE_FSMC_NAND1 FSMC_NAND_TypeDef *nand1; -#endif -#if STM32_NAND_USE_FSMC_NAND2 + #endif + #if STM32_NAND_USE_FSMC_NAND2 FSMC_NAND_TypeDef *nand2; + #endif #endif + #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ defined(STM32F7)) - #if STM32_USE_FSMC_SDRAM - FSMC_SDRAM_TypeDef *sdram; + #if HAL_USE_FSMC_SDRAM + FSMC_SDRAM_TypeDef *sdram; #endif #endif }; @@ -337,13 +374,25 @@ extern FSMCDriver FSMCD1; #ifdef __cplusplus extern "C" { #endif - void fsmc_init(void); - void fsmc_start(FSMCDriver *fsmcp); - void fsmc_stop(FSMCDriver *fsmcp); + void fsmcInit(void); + void fsmcStart(FSMCDriver *fsmcp); + void fsmcStop(FSMCDriver *fsmcp); #ifdef __cplusplus } #endif +#if HAL_USE_FSMC_SDRAM == TRUE +#include "fsmc/sdram.h" +#endif + +#if HAL_USE_FSMC_SRAM == TRUE +#include "fsmc/sram.h" +#endif + +#if HAL_USE_FSMC_NAND == TRUE +#include "fsmc/nand.h" +#endif + #endif /* HAL_USE_FSMC */ #endif /* HAL_FSMC_H_ */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/driver.mk b/os/hal/ports/STM32/LLD/FSMCv1/driver.mk index d92230d9..cffa3f74 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/driver.mk +++ b/os/hal/ports/STM32/LLD/FSMCv1/driver.mk @@ -1,17 +1,17 @@ ifeq ($(USE_SMART_BUILD),yes) -ifneq ($(findstring HAL_USE_FSMC TRUE,$(HALCONF)),) -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c +ifneq ($(findstring HAL_USE_FSMC_SDRAM TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c endif -ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),) -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c +ifneq ($(findstring HAL_USE_FSMC_SRAM TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c +endif +ifneq ($(findstring HAL_USE_FSMC_NAND TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c endif else -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c endif PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c similarity index 99% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c rename to os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c index cc6dc20a..895fd28e 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c @@ -15,8 +15,8 @@ */ /** - * @file hal_nand_lld.c - * @brief NAND Driver subsystem low level driver source. + * @file hal_fsmc_nand_lld.c + * @brief FSMC NAND Driver subsystem low level driver source. * * @addtogroup NAND * @{ @@ -24,7 +24,7 @@ #include "hal.h" -#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver local definitions. */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h new file mode 100644 index 00000000..f47ee752 --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h @@ -0,0 +1,289 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc_nand_lld.h + * @brief FSMC NAND Driver subsystem low level driver header. + * + * @addtogroup NAND + * @{ + */ + +#ifndef HAL_FSMC_NAND_LLD_H_ +#define HAL_FSMC_NAND_LLD_H_ + +#include "bitmap.h" + +#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ +#define NAND_MIN_PAGE_SIZE 256 +#define NAND_MAX_PAGE_SIZE 8192 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief FSMC1 interrupt priority level setting. + */ +#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EMC_FSMC1_IRQ_PRIORITY 10 +#endif + +/** + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND1 is included. + */ +#if !defined(STM32_FSMC_USE_NAND1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_NAND1 FALSE +#endif + +/** + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND2 is included. + */ +#if !defined(STM32_FSMC_USE_NAND2) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_NAND2 FALSE +#endif + +/** + * @brief NAND DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_FSMC_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") +#endif + +/** + * @brief NAND interrupt enable switch. + * @details If set to @p TRUE the support for internal FSMC interrupt included. + */ +#if !defined(STM32_FSMC_NAND_USE_INT) || defined(__DOXYGEN__) +#define STM32_FSMC_NAND_USE_INT FALSE +#endif + +/** +* @brief NAND1 DMA priority (0..3|lowest..highest). +*/ +#if !defined(STM32_FSMC_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_FSMC_NAND1_DMA_PRIORITY 0 +#endif + +/** +* @brief NAND2 DMA priority (0..3|lowest..highest). +*/ +#if !defined(STM32_FSMC_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_FSMC_NAND2_DMA_PRIORITY 0 +#endif + +/** + * @brief DMA stream used for NAND operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_FSMC_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_FSMC_USE_NAND1 && !STM32_FSMC_USE_NAND2 +#error "NAND driver activated but no NAND peripheral assigned" +#endif + +#if (STM32_FSMC_USE_NAND1 || STM32_FSMC_USE_NAND2) && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an NAND driver. + */ +typedef struct NANDDriver NANDDriver; + +/** + * @brief Type of interrupt handler function. + */ +typedef void (*nandisrhandler_t)(NANDDriver *nandp); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Number of erase blocks in NAND device. + */ + uint32_t blocks; + /** + * @brief Number of data bytes in page. + */ + uint32_t page_data_size; + /** + * @brief Number of spare bytes in page. + */ + uint32_t page_spare_size; + /** + * @brief Number of pages in block. + */ + uint32_t pages_per_block; + /** + * @brief Number of write cycles for row addressing. + */ + uint8_t rowcycles; + /** + * @brief Number of write cycles for column addressing. + */ + uint8_t colcycles; + + /* End of the mandatory fields.*/ + /** + * @brief Number of wait cycles. This value will be used both for + * PMEM and PATTR registers + * + * @note For proper calculation procedure please look at AN2784 document + * from STMicroelectronics. + */ + uint32_t pmem; +} NANDConfig; + +/** + * @brief Structure representing an NAND driver. + */ +struct NANDDriver { + /** + * @brief Driver state. + */ + nandstate_t state; + /** + * @brief Current configuration data. + */ + const NANDConfig *config; + /** + * @brief Array to store bad block map. + */ +#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + mutex_t mutex; +#elif CH_CFG_USE_SEMAPHORES + semaphore_t semaphore; +#endif +#endif /* NAND_USE_MUTUAL_EXCLUSION */ + /* End of the mandatory fields.*/ + /** + * @brief Function enabling interrupts from FSMC. + */ + nandisrhandler_t isr_handler; + /** + * @brief Pointer to current transaction buffer. + */ + void *rxdata; + /** + * @brief Current transaction length in bytes. + */ + size_t datalen; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; + /** + * @brief DMA channel. + */ + const stm32_dma_stream_t *dma; + /** + * @brief Thread waiting for I/O completion. + */ + thread_t *thread; + /** + * @brief Pointer to the FSMC NAND registers block. + */ + FSMC_NAND_TypeDef *nand; + /** + * @brief Memory mapping for data. + */ + uint16_t *map_data; + /** + * @brief Memory mapping for commands. + */ + uint16_t *map_cmd; + /** + * @brief Memory mapping for addresses. + */ + uint16_t *map_addr; + /** + * @brief Pointer to bad block map. + * @details One bit per block. All memory allocation is user's responsibility. + */ + bitmap_t *bb_map; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_FSMC_USE_NAND1 && !defined(__DOXYGEN__) +extern NANDDriver NANDD1; +#endif + +#if STM32_FSMC_USE_NAND2 && !defined(__DOXYGEN__) +extern NANDDriver NANDD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void nand_lld_init(void); + void nand_lld_start(NANDDriver *nandp); + void nand_lld_stop(NANDDriver *nandp); + uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); + void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); + void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); + void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); + uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); + uint8_t nand_lld_read_status(NANDDriver *nandp); + void nand_lld_reset(NANDDriver *nandp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_FSMC_NAND */ + +#endif /* HAL_FSMC_NAND_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c similarity index 72% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c rename to os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c index 6d727c85..5934f88a 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c @@ -34,9 +34,9 @@ defined(STM32F769xx) || defined(STM32F777xx) || \ defined(STM32F779xx)) -#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) +#if (STM32_FSMC_USE_SDRAM1 == TRUE) || (STM32_FSMC_USE_SDRAM2 == TRUE) || defined(__DOXYGEN__) -#include "hal_fsmc_sdram.h" +#include "hal_fsmc_sdram_lld.h" /*===========================================================================*/ /* Driver local definitions. */ @@ -78,7 +78,7 @@ SDRAMDriver SDRAMD; * * @notapi */ -static void _sdram_wait_ready(void) { +static void lld_sdram_wait_ready(void) { /* Wait until the SDRAM controller is ready */ while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY); } @@ -90,48 +90,48 @@ static void _sdram_wait_ready(void) { * * @notapi */ -static void _sdram_init_sequence(const SDRAMConfig *cfgp) { +static void lld_sdram_init_sequence(const SDRAMConfig *cfgp) { uint32_t command_target = 0; -#if STM32_SDRAM_USE_FSMC_SDRAM1 +#if STM32_FSMC_USE_SDRAM1 command_target |= FMC_SDCMR_CTB1; #endif -#if STM32_SDRAM_USE_FSMC_SDRAM2 +#if STM32_FSMC_USE_SDRAM2 command_target |= FMC_SDCMR_CTB2; #endif /* Step 3: Configure a clock configuration enable command.*/ - _sdram_wait_ready(); + lld_sdram_wait_ready(); SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target; /* Step 4: Insert delay (tipically 100uS).*/ osalThreadSleepMilliseconds(1); /* Step 5: Configure a PALL (precharge all) command.*/ - _sdram_wait_ready(); + lld_sdram_wait_ready(); SDRAMD.sdram->SDCMR = FMCCM_PALL | command_target; /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/ - _sdram_wait_ready(); + lld_sdram_wait_ready(); SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | (cfgp->sdcmr & FMC_SDCMR_NRFS); /* Step 6.2: Send the second command.*/ - _sdram_wait_ready(); + lld_sdram_wait_ready(); SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | (cfgp->sdcmr & FMC_SDCMR_NRFS); /* Step 7: Program the external memory mode register.*/ - _sdram_wait_ready(); + lld_sdram_wait_ready(); SDRAMD.sdram->SDCMR = FMCCM_LOAD_MODE | command_target | (cfgp->sdcmr & FMC_SDCMR_MRD); /* Step 8: Set clock.*/ - _sdram_wait_ready(); + lld_sdram_wait_ready(); SDRAMD.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT; - _sdram_wait_ready(); + lld_sdram_wait_ready(); } /*===========================================================================*/ @@ -142,71 +142,28 @@ static void _sdram_init_sequence(const SDRAMConfig *cfgp) { /* Driver exported functions. */ /*===========================================================================*/ -/** - * @brief Low level SDRAM driver initialization. - */ -void fsmcSdramInit(void) { +void lld_sdram_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) +{ + sdramp->sdram->SDCR1 = cfgp->sdcr; + sdramp->sdram->SDTR1 = cfgp->sdtr; + sdramp->sdram->SDCR2 = cfgp->sdcr; + sdramp->sdram->SDTR2 = cfgp->sdtr; - fsmc_init(); - - SDRAMD.sdram = FSMCD1.sdram; - SDRAMD.state = SDRAM_STOP; + lld_sdram_init_sequence(cfgp); } -/** - * @brief Configures and activates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * @param[in] cfgp pointer to the @p SDRAMConfig object - */ -void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) { - - if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); - - osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), - "SDRAM. Invalid state."); - - if (sdramp->state == SDRAM_STOP) { - - /* Even if you need only bank2 you must properly set up SDCR and SDTR - regitsters for bank1 too. Both banks will be tuned equally assuming - connected memory ICs are equal.*/ - sdramp->sdram->SDCR1 = cfgp->sdcr; - sdramp->sdram->SDTR1 = cfgp->sdtr; - sdramp->sdram->SDCR2 = cfgp->sdcr; - sdramp->sdram->SDTR2 = cfgp->sdtr; - - _sdram_init_sequence(cfgp); - - sdramp->state = SDRAM_READY; - } -} - -/** - * @brief Deactivates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * - * @notapi - */ -void fsmcSdramStop(SDRAMDriver *sdramp) { - +void lld_sdram_stop(SDRAMDriver *sdramp) { uint32_t command_target = 0; -#if STM32_SDRAM_USE_FSMC_SDRAM1 +#if STM32_FSMC_USE_SDRAM1 command_target |= FMC_SDCMR_CTB1; #endif -#if STM32_SDRAM_USE_FSMC_SDRAM2 +#if STM32_FSMC_USE_SDRAM2 command_target |= FMC_SDCMR_CTB2; #endif - if (sdramp->state == SDRAM_READY) { - SDRAMD.sdram->SDCMR = FMCCM_POWER_DOWN | command_target; - sdramp->state = SDRAM_STOP; - } + sdramp->sdram->SDCMR = FMCCM_POWER_DOWN | command_target; } - #endif /* STM32_USE_FSMC_SDRAM */ #endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h new file mode 100644 index 00000000..0e533b64 --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h @@ -0,0 +1,117 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + SDRAM routines added by Nick Klimov aka progfin. + */ + +/** + * @file hal_fsmc_sdram.h + * @brief SDRAM Driver subsystem low level driver header. + * + * @addtogroup SDRAM + * @{ + */ + +#ifndef HAL_FMC_SDRAM_H_ +#define HAL_FMC_SDRAM_H_ + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + +#include "hal_fsmc.h" + +#if (STM32_FSMC_USE_SDRAM1 == TRUE) || (STM32_FSMC_USE_SDRAM2 == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM1 is included. + */ +#if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SDRAM1 FALSE +#else +#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE +#endif + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM2 is included. + */ +#if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SDRAM2 FALSE +#else +#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_FSMC_USE_SDRAM1 && !STM32_FSMC_USE_SDRAM2 +#error "SDRAM driver activated but no SDRAM peripheral assigned" +#endif + +#if (STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2) && !STM32_HAS_FSMC +#error "FMC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern SDRAMDriver SDRAMD; + +#ifdef __cplusplus +extern "C" { +#endif + void lld_sdram_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); + void lld_sdram_stop(SDRAMDriver *sdramp); +#ifdef __cplusplus +} +#endif + +#endif /* STM32_FSMC_USE_SDRAM */ + +#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ + +#endif /* HAL_FSMC_SDRAM_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c similarity index 100% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c rename to os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h similarity index 100% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h rename to os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h diff --git a/os/hal/src/hal_community.c b/os/hal/src/hal_community.c index ad05fe42..02de5cd8 100644 --- a/os/hal/src/hal_community.c +++ b/os/hal/src/hal_community.c @@ -84,6 +84,10 @@ void halCommunityInit(void) { #if HAL_USE_COMP || defined(__DOXYGEN__) compInit(); #endif + +#if HAL_USE_FSMC || defined(__DOXYGEN__) + fsmcInit(); +#endif } #endif /* HAL_USE_COMMUNITY */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/src/hal_fsmc.c similarity index 77% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c rename to os/hal/src/hal_fsmc.c index 71c6ada3..7304866a 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c +++ b/os/hal/src/hal_fsmc.c @@ -22,14 +22,15 @@ * @{ */ #include "hal.h" -#include "hal_fsmc.h" -#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC_SDRAM == TRUE) || (HAL_USE_FSMC_SRAM == TRUE) || (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ + + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -61,37 +62,39 @@ FSMCDriver FSMCD1; /* Driver exported functions. */ /*===========================================================================*/ +#include "hal_fsmc_sdram_lld.h" + /** * @brief Low level FSMC driver initialization. * * @notapi */ -void fsmc_init(void) { +void fsmcInit(void) { if (FSMCD1.state == FSMC_UNINIT) { FSMCD1.state = FSMC_STOP; -#if STM32_SRAM_USE_FSMC_SRAM1 +#if STM32_FSMC_USE_SRAM1 FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE); #endif -#if STM32_SRAM_USE_FSMC_SRAM2 +#if STM32_FSMC_USE_SRAM2 FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8); #endif -#if STM32_SRAM_USE_FSMC_SRAM3 +#if STM32_FSMC_USE_SRAM3 FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2); #endif -#if STM32_SRAM_USE_FSMC_SRAM4 +#if STM32_FSMC_USE_SRAM4 FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3); #endif -#if STM32_NAND_USE_FSMC_NAND1 +#if STM32_FSMC_USE_NAND1 FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; #endif -#if STM32_NAND_USE_FSMC_NAND2 +#if STM32_FSMC_USE_NAND2 FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; #endif @@ -101,7 +104,7 @@ void fsmc_init(void) { defined(STM32F756xx) || defined(STM32F767xx) || \ defined(STM32F769xx) || defined(STM32F777xx) || \ defined(STM32F779xx)) - #if STM32_USE_FSMC_SDRAM + #if STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2 FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; #endif #endif @@ -115,7 +118,7 @@ void fsmc_init(void) { * * @notapi */ -void fsmc_start(FSMCDriver *fsmcp) { +void fsmcStart(FSMCDriver *fsmcp) { osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY), "invalid state"); @@ -145,7 +148,7 @@ void fsmc_start(FSMCDriver *fsmcp) { * * @notapi */ -void fsmc_stop(FSMCDriver *fsmcp) { +void fsmcStop(FSMCDriver *fsmcp) { if (fsmcp->state == FSMC_READY) { /* Resets the peripheral.*/ @@ -175,12 +178,12 @@ void fsmc_stop(FSMCDriver *fsmcp) { CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { CH_IRQ_PROLOGUE(); -#if STM32_NAND_USE_FSMC_NAND1 +#if STM32_FSMC_USE_NAND1 if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) { NANDD1.isr_handler(&NANDD1); } #endif -#if STM32_NAND_USE_FSMC_NAND2 +#if STM32_FSMC_USE_NAND2 if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) { NANDD2.isr_handler(&NANDD2); } @@ -188,6 +191,54 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { CH_IRQ_EPILOGUE(); } + +/** + * @brief FSMC SDRAM Driver init + */ +void fsmcSdramInit(void) { + + fsmcInit(); + SDRAMD.sdram = FSMCD1.sdram; + SDRAMD.state = SDRAM_STOP; +} + +/** + * @brief Configures and activates the SDRAM peripheral. + * + * @param[in] sdramp pointer to the @p SDRAMDriver object + * @param[in] cfgp pointer to the @p SDRAMConfig object + */ +void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) { + + if (FSMCD1.state == FSMC_STOP) + fsmcStart(&FSMCD1); + + osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), + "SDRAM. Invalid state."); + + if (sdramp->state == SDRAM_STOP) { + + lld_sdram_start(sdramp, cfgp); + + sdramp->state = SDRAM_READY; + } +} + +/** + * @brief Deactivates the SDRAM peripheral. + * + * @param[in] sdramp pointer to the @p SDRAMDriver object + * + * @notapi + */ +void fsmcSdramStop(SDRAMDriver *sdramp) { + + if (sdramp->state == SDRAM_READY) { + lld_sdram_stop(sdramp); + sdramp->state = SDRAM_STOP; + } +} + #endif /* HAL_USE_FSMC */ /** @} */ diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h index da9c6078..d1d3ada5 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h @@ -27,8 +27,22 @@ /** * @brief Enables the FSMC subsystem. */ -#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) -#define HAL_USE_FSMC TRUE +#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SDRAM TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SRAM FALSE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_NAND FALSE #endif /** diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c index 1ec34d26..45e8db6e 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c @@ -23,7 +23,6 @@ #include "string.h" -#include "hal_fsmc_sdram.h" #include "membench.h" #include "memtest.h" diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h index c8d995f7..44949294 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h @@ -22,32 +22,30 @@ #define STM32_FSMC_USE_FSMC1 TRUE #define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 #define STM32_FSMC_DMA_CHN 0x03010201 +#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_FSMC_DMA_PRIORITY 0 +#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("FSMC DMA failure") /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE -#define STM32_NAND_USE_EXT_INT FALSE -#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_NAND_DMA_PRIORITY 0 -#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") +#define STM32_FSMC_USE_NAND1 FALSE +#define STM32_FSMC_USE_NAND2 FALSE +#define STM32_FSMC_USE_NAND_EXT_INT FALSE /* * FSMC SRAM driver system settings. */ -#define STM32_USE_FSMC_SRAM FALSE -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE +#define STM32_FSMC_USE_SRAM1 FALSE +#define STM32_FSMC_USE_SRAM2 FALSE +#define STM32_FSMC_USE_SRAM3 FALSE +#define STM32_FSMC_USE_SRAM4 FALSE /* * FSMC SDRAM driver system settings. */ -#define STM32_USE_FSMC_SDRAM TRUE -#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE -#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE +#define STM32_FSMC_USE_SDRAM1 FALSE +#define STM32_FSMC_USE_SDRAM2 TRUE /* * TIMCAP driver system settings. From 90f32c35466c9edbd59716de66903b3f537f5abb Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Tue, 29 Oct 2019 20:16:08 +0100 Subject: [PATCH 2/9] Updating FSMC driver (SRAM part) --- os/hal/include/fsmc/sram.h | 32 +++--- os/hal/include/hal_fsmc.h | 12 +-- .../STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c | 2 +- .../STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h | 2 +- .../STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c | 61 ++---------- .../STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h | 97 ++----------------- os/hal/src/hal_fsmc.c | 79 ++++++++++++++- .../STM32F4xx/FSMC_SDRAM/halconf_community.h | 7 -- .../STM32F4xx/FSMC_SRAM/halconf_community.h | 17 +++- testhal/STM32/STM32F4xx/FSMC_SRAM/main.c | 1 - .../STM32F4xx/FSMC_SRAM/mcuconf_community.h | 26 +++-- 11 files changed, 143 insertions(+), 193 deletions(-) diff --git a/os/hal/include/fsmc/sram.h b/os/hal/include/fsmc/sram.h index 6eed97a5..4a192467 100644 --- a/os/hal/include/fsmc/sram.h +++ b/os/hal/include/fsmc/sram.h @@ -43,32 +43,32 @@ * @brief SRAM driver enable switch. * @details If set to @p TRUE the support for SRAM1 is included. */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE +#if !defined(STM32_FSMC_USE_SRAM1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SRAM1 FALSE #endif /** * @brief SRAM driver enable switch. * @details If set to @p TRUE the support for SRAM2 is included. */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE +#if !defined(STM32_FSMC_USE_SRAM2) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SRAM2 FALSE #endif /** * @brief SRAM driver enable switch. * @details If set to @p TRUE the support for SRAM3 is included. */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE +#if !defined(STM32_FSMC_USE_SRAM3) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SRAM3 FALSE #endif /** * @brief SRAM driver enable switch. * @details If set to @p TRUE the support for SRAM4 is included. */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE +#if !defined(STM32_FSMC_USE_SRAM4) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SRAM4 FALSE #endif /** @} */ @@ -77,13 +77,13 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \ - !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4 +#if !STM32_FSMC_USE_SRAM1 && !STM32_FSMC_USE_SRAM2 && \ + !STM32_FSMC_USE_SRAM3 && !STM32_FSMC_USE_SRAM4 #error "SRAM driver activated but no SRAM peripheral assigned" #endif -#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \ - STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC +#if (STM32_FSMC_USE_SRAM1 || STM32_FSMC_USE_SRAM2 || \ + STM32_FSMC_USE_SRAM3 || STM32_FSMC_USE_SRAM4) && !STM32_HAS_FSMC #error "FSMC not present in the selected device" #endif @@ -137,19 +137,19 @@ struct SRAMDriver { /* External declarations. */ /*===========================================================================*/ -#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM1 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD1; #endif -#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM2 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD2; #endif -#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM3 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD3; #endif -#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM4 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD4; #endif diff --git a/os/hal/include/hal_fsmc.h b/os/hal/include/hal_fsmc.h index f85079a5..834fa8de 100644 --- a/os/hal/include/hal_fsmc.h +++ b/os/hal/include/hal_fsmc.h @@ -327,25 +327,25 @@ struct FSMCDriver { /* End of the mandatory fields.*/ #if HAL_USE_FSMC_SRAM - #if STM32_SRAM_USE_FSMC_SRAM1 + #if STM32_FSMC_USE_SRAM1 FSMC_SRAM_NOR_TypeDef *sram1; #endif - #if STM32_SRAM_USE_FSMC_SRAM2 + #if STM32_FSMC_USE_SRAM2 FSMC_SRAM_NOR_TypeDef *sram2; #endif - #if STM32_SRAM_USE_FSMC_SRAM3 + #if STM32_FSMC_USE_SRAM3 FSMC_SRAM_NOR_TypeDef *sram3; #endif - #if STM32_SRAM_USE_FSMC_SRAM4 + #if STM32_FSMC_USE_SRAM4 FSMC_SRAM_NOR_TypeDef *sram4; #endif #endif #if HAL_USE_FSMC_NAND - #if STM32_NAND_USE_FSMC_NAND1 + #if STM32_FSMC_USE_NAND1 FSMC_NAND_TypeDef *nand1; #endif - #if STM32_NAND_USE_FSMC_NAND2 + #if STM32_FSMC_USE_NAND1 FSMC_NAND_TypeDef *nand2; #endif #endif diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c index 5934f88a..1b0c0db4 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c @@ -34,7 +34,7 @@ defined(STM32F769xx) || defined(STM32F777xx) || \ defined(STM32F779xx)) -#if (STM32_FSMC_USE_SDRAM1 == TRUE) || (STM32_FSMC_USE_SDRAM2 == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) #include "hal_fsmc_sdram_lld.h" diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h index 0e533b64..1fc7993d 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h @@ -37,7 +37,7 @@ #include "hal_fsmc.h" -#if (STM32_FSMC_USE_SDRAM1 == TRUE) || (STM32_FSMC_USE_SDRAM2 == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c index da13ca5b..49b7826c 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c @@ -22,9 +22,10 @@ * @{ */ #include "hal.h" -#include "hal_fsmc_sram.h" -#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) + +#include "hal_fsmc_sram_lld.h" /*===========================================================================*/ /* Driver local definitions. */ @@ -36,28 +37,28 @@ /** * @brief SRAM1 driver identifier. */ -#if STM32_SRAM_USE_FSMC_SRAM1 || defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM1 || defined(__DOXYGEN__) SRAMDriver SRAMD1; #endif /** * @brief SRAM2 driver identifier. */ -#if STM32_SRAM_USE_FSMC_SRAM2 || defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM2 || defined(__DOXYGEN__) SRAMDriver SRAMD2; #endif /** * @brief SRAM3 driver identifier. */ -#if STM32_SRAM_USE_FSMC_SRAM3 || defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM3 || defined(__DOXYGEN__) SRAMDriver SRAMD3; #endif /** * @brief SRAM4 driver identifier. */ -#if STM32_SRAM_USE_FSMC_SRAM4 || defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM4 || defined(__DOXYGEN__) SRAMDriver SRAMD4; #endif @@ -81,36 +82,6 @@ SRAMDriver SRAMD4; /* Driver exported functions. */ /*===========================================================================*/ -/** - * @brief Low level SRAM driver initialization. - * - * @notapi - */ -void fsmcSramInit(void) { - - fsmc_init(); - -#if STM32_SRAM_USE_FSMC_SRAM1 - SRAMD1.sram = FSMCD1.sram1; - SRAMD1.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM1 */ - -#if STM32_SRAM_USE_FSMC_SRAM2 - SRAMD2.sram = FSMCD1.sram2; - SRAMD2.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM2 */ - -#if STM32_SRAM_USE_FSMC_SRAM3 - SRAMD3.sram = FSMCD1.sram3; - SRAMD3.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM3 */ - -#if STM32_SRAM_USE_FSMC_SRAM4 - SRAMD4.sram = FSMCD1.sram4; - SRAMD4.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM4 */ -} - /** * @brief Configures and activates the SRAM peripheral. * @@ -119,20 +90,11 @@ void fsmcSramInit(void) { * * @notapi */ -void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { +void lld_sram_start(SRAMDriver *sramp, const SRAMConfig *cfgp) { - if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); - - osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), - "invalid state"); - - if (sramp->state == SRAM_STOP) { sramp->sram->BTR = cfgp->btr; sramp->sram->BWTR = cfgp->bwtr; sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN; - sramp->state = SRAM_READY; - } } /** @@ -142,9 +104,8 @@ void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { * * @notapi */ -void fsmcSramStop(SRAMDriver *sramp) { +void lld_sram_stop(SRAMDriver *sramp) { - if (sramp->state == SRAM_READY) { uint32_t mask = FSMC_BCR_MBKEN; #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ @@ -155,11 +116,9 @@ void fsmcSramStop(SRAMDriver *sramp) { mask |= FSMC_BCR_CCLKEN; #endif sramp->sram->BCR &= ~mask; - sramp->state = SRAM_STOP; - } } -#endif /* STM32_USE_FSMC_SRAM */ +#endif /* STM32_FSMC_USE_SRAM */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h index 5e749a8f..bfd878fe 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h @@ -27,7 +27,7 @@ #include "hal_fsmc.h" -#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -41,95 +41,15 @@ * @{ */ -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM1 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM2 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM3 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM4 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE -#endif - /** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ -#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \ - !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4 -#error "SRAM driver activated but no SRAM peripheral assigned" -#endif - -#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \ - STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC -#error "FSMC not present in the selected device" -#endif - /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SRAM_UNINIT = 0, /**< Not initialized. */ - SRAM_STOP = 1, /**< Stopped. */ - SRAM_READY = 2, /**< Ready. */ -} sramstate_t; - -/** - * @brief Type of a structure representing an NAND driver. - */ -typedef struct SRAMDriver SRAMDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - * @note Some bits in BCR register will be forced by driver. - */ -typedef struct { - uint32_t bcr; - uint32_t btr; - uint32_t bwtr; -} SRAMConfig; - -/** - * @brief Structure representing an NAND driver. - */ -struct SRAMDriver { - /** - * @brief Driver state. - */ - sramstate_t state; - /** - * @brief Pointer to the FSMC SRAM registers block. - */ - FSMC_SRAM_NOR_TypeDef *sram; -}; /*===========================================================================*/ /* Driver macros. */ @@ -139,33 +59,32 @@ struct SRAMDriver { /* External declarations. */ /*===========================================================================*/ -#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM1 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD1; #endif -#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM2 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD2; #endif -#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM3 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD3; #endif -#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM4 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD4; #endif #ifdef __cplusplus extern "C" { #endif - void fsmcSramInit(void); - void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); - void fsmcSramStop(SRAMDriver *sramp); + void lld_sram_start(SRAMDriver *sramp, const SRAMConfig *cfgp); + void lld_sram_stop(SRAMDriver *sramp); #ifdef __cplusplus } #endif -#endif /* STM32_USE_FSMC_SRAM */ +#endif /* STM32_FSMC_USE_SRAM */ #endif /* HAL_FSMC_SRAM_H_ */ diff --git a/os/hal/src/hal_fsmc.c b/os/hal/src/hal_fsmc.c index 7304866a..cdbb3875 100644 --- a/os/hal/src/hal_fsmc.c +++ b/os/hal/src/hal_fsmc.c @@ -62,8 +62,6 @@ FSMCDriver FSMCD1; /* Driver exported functions. */ /*===========================================================================*/ -#include "hal_fsmc_sdram_lld.h" - /** * @brief Low level FSMC driver initialization. * @@ -191,7 +189,9 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { CH_IRQ_EPILOGUE(); } +#if (HAL_USE_FSMC_SDRAM == TRUE) +#include "hal_fsmc_sdram_lld.h" /** * @brief FSMC SDRAM Driver init */ @@ -238,6 +238,81 @@ void fsmcSdramStop(SDRAMDriver *sdramp) { sdramp->state = SDRAM_STOP; } } +#endif /* HAL_USE_FSMC_SDRAM == TRUE */ + + +#if (HAL_USE_FSMC_SRAM == TRUE) + +#include "hal_fsmc_sram_lld.h" + +/** + * @brief Low level SRAM driver initialization. + * + * @notapi + */ +void fsmcSramInit(void) { + + fsmcInit(); + +#if STM32_FSMC_USE_SRAM1 + SRAMD1.sram = FSMCD1.sram1; + SRAMD1.state = SRAM_STOP; +#endif /* STM32_FSMC_USE_SRAM1 */ + +#if STM32_FSMC_USE_SRAM2 + SRAMD2.sram = FSMCD1.sram2; + SRAMD2.state = SRAM_STOP; +#endif /* STM32_FSMC_USE_SRAM2 */ + +#if STM32_FSMC_USE_SRAM3 + SRAMD3.sram = FSMCD1.sram3; + SRAMD3.state = SRAM_STOP; +#endif /* STM32_FSMC_USE_SRAM3 */ + +#if STM32_FSMC_USE_SRAM4 + SRAMD4.sram = FSMCD1.sram4; + SRAMD4.state = SRAM_STOP; +#endif /* STM32_FSMC_USE_SRAM4 */ +} + +/** + * @brief Configures and activates the SRAM peripheral. + * + * @param[in] sramp pointer to the @p SRAMDriver object + * @param[in] cfgp pointer to the @p SRAMConfig object + * + * @notapi + */ +void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { + + if (FSMCD1.state == FSMC_STOP) + fsmcStart(&FSMCD1); + + osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), + "invalid state"); + + if (sramp->state == SRAM_STOP) { + lld_sram_start(sramp, cfgp); + sramp->state = SRAM_READY; + } +} + +/** + * @brief Deactivates the SRAM peripheral. + * + * @param[in] sramp pointer to the @p SRAMDriver object + * + * @notapi + */ +void fsmcSramStop(SRAMDriver *sramp) { + + if (sramp->state == SRAM_READY) { + lld_sram_stop(sramp); + sramp->state = SRAM_STOP; + } +} + +#endif /* HAL_USE_FSMC_SRAM == TRUE */ #endif /* HAL_USE_FSMC */ diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h index d1d3ada5..9ad41fd9 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h @@ -45,13 +45,6 @@ #define HAL_USE_FSMC_NAND FALSE #endif -/** - * @brief Enables the NAND subsystem. - */ -#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) -#define HAL_USE_NAND FALSE -#endif - /** * @brief Enables the 1-wire subsystem. */ diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h index da9c6078..f9cfcbeb 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h @@ -27,15 +27,22 @@ /** * @brief Enables the FSMC subsystem. */ -#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) -#define HAL_USE_FSMC TRUE +#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SDRAM FALSE #endif /** - * @brief Enables the NAND subsystem. + * @brief Enables the FSMC subsystem. */ -#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) -#define HAL_USE_NAND FALSE +#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SRAM TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_NAND FALSE #endif /** diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c index c94bd737..64138355 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c @@ -17,7 +17,6 @@ #include "ch.h" #include "hal.h" -#include "hal_fsmc_sram.h" #include "membench.h" #include "memtest.h" diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h index 317fe5d8..8abb48dd 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h @@ -22,32 +22,30 @@ #define STM32_FSMC_USE_FSMC1 TRUE #define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 #define STM32_FSMC_DMA_CHN 0x03010201 +#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_FSMC_DMA_PRIORITY 0 +#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("FSMC DMA failure") /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE -#define STM32_NAND_USE_EXT_INT FALSE -#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_NAND_DMA_PRIORITY 0 -#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") +#define STM32_FSMC_USE_NAND1 FALSE +#define STM32_FSMC_USE_NAND2 FALSE +#define STM32_FSMC_USE_NAND_EXT_INT FALSE /* * FSMC SRAM driver system settings. */ -#define STM32_USE_FSMC_SRAM TRUE -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#define STM32_SRAM_USE_FSMC_SRAM4 TRUE +#define STM32_FSMC_USE_SRAM1 FALSE +#define STM32_FSMC_USE_SRAM2 FALSE +#define STM32_FSMC_USE_SRAM3 FALSE +#define STM32_FSMC_USE_SRAM4 TRUE /* * FSMC SDRAM driver system settings. */ -#define STM32_USE_FSMC_SDRAM FALSE -#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE -#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE +#define STM32_FSMC_USE_SDRAM1 FALSE +#define STM32_FSMC_USE_SDRAM2 FALSE /* * TIMCAP driver system settings. From 13ebce61e2f0af08d6ffa0c13397da5ad31292c4 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 30 Oct 2019 10:53:30 +0100 Subject: [PATCH 3/9] Moved SDRAM defines out of example --- os/hal/include/fsmc/sdram.h | 83 ++++++++++++++++++++++- testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c | 78 --------------------- 2 files changed, 81 insertions(+), 80 deletions(-) diff --git a/os/hal/include/fsmc/sdram.h b/os/hal/include/fsmc/sdram.h index 83b78a67..7a04bdc9 100644 --- a/os/hal/include/fsmc/sdram.h +++ b/os/hal/include/fsmc/sdram.h @@ -41,6 +41,85 @@ /* Driver constants. */ /*===========================================================================*/ +/* + * FMC SDRAM Mode definition register defines + */ +#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001) +#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002) +#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004) +#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020) +#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030) +#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +/* + * FMC_ReadPipe_Delay + */ +#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) +#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) +#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) +#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000) + +/* + * FMC_Read_Burst + */ +#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) +#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) +#define FMC_Read_Burst_Mask ((uint32_t)0x00001000) + +/* + * FMC_SDClock_Period + */ +#define FMC_SDClock_Disable ((uint32_t)0x00000000) +#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) +#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) +#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00) + +/* + * FMC_ColumnBits_Number + */ +#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) +#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) +#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) +#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) + +/* + * FMC_RowBits_Number + */ +#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) +#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) +#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) + +/* + * FMC_SDMemory_Data_Width + */ +#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) +#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) +#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) + +/* + * FMC_InternalBank_Number + */ +#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) +#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) + +/* + * FMC_CAS_Latency + */ +#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) +#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) +#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) + +/* + * FMC_Write_Protection + */ +#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) +#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -56,7 +135,7 @@ #if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__) #define STM32_FSMC_USE_SDRAM1 FALSE #else -#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE +#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE #endif /** @@ -66,7 +145,7 @@ #if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__) #define STM32_FSMC_USE_SDRAM2 FALSE #else -#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE +#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE #endif /** @} */ diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c index 45e8db6e..1ff77409 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c @@ -32,84 +32,6 @@ ****************************************************************************** */ -/* - * FMC SDRAM Mode definition register defines - */ -#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001) -#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002) -#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004) -#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020) -#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030) -#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -/* - * FMC_ReadPipe_Delay - */ -#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) -#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) -#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) -#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000) - -/* - * FMC_Read_Burst - */ -#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) -#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) -#define FMC_Read_Burst_Mask ((uint32_t)0x00001000) - -/* - * FMC_SDClock_Period - */ -#define FMC_SDClock_Disable ((uint32_t)0x00000000) -#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) -#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) -#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00) - -/* - * FMC_ColumnBits_Number - */ -#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) -#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) -#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) -#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) - -/* - * FMC_RowBits_Number - */ -#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) -#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) -#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) - -/* - * FMC_SDMemory_Data_Width - */ -#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) -#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) -#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) - -/* - * FMC_InternalBank_Number - */ -#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) -#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) - -/* - * FMC_CAS_Latency - */ -#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) -#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) -#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) - -/* - * FMC_Write_Protection - */ -#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) -#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) #define SDRAM_SIZE (8 * 1024 * 1024) #define SDRAM_START ((void *)FSMC_Bank6_MAP_BASE) From 915b474b02349add9c17fa43ff0351503c3c5020 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 30 Oct 2019 12:52:31 +0100 Subject: [PATCH 4/9] Re-organised FSMC drivers --- .../mcuconf_community.h | 4 +- .../RT-STM32F429-DISCOVERY-DMA2D/.cproject | 4 +- .../STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c | 4 +- .../mcuconf_community.h | 4 +- os/common/ext/CMSIS/KINETIS/MK66F18.h | 4 +- os/hal/hal.mk | 14 +- os/hal/include/fsmc/nand.h | 293 ------------------ os/hal/include/hal_community.h | 27 +- os/hal/include/hal_fsmc.h | 67 +--- os/hal/include/{fsmc/sdram.h => hal_sdram.h} | 42 +-- os/hal/include/{fsmc/sram.h => hal_sram.h} | 51 +-- os/hal/ports/STM32/LLD/FSMCv1/driver.mk | 18 +- .../{hal_fsmc_nand_lld.c => hal_nand_lld.c} | 22 +- .../{hal_fsmc_nand_lld.h => hal_nand_lld.h} | 27 +- .../{hal_fsmc_sdram_lld.c => hal_sdram_lld.c} | 52 ++-- .../{hal_fsmc_sdram_lld.h => hal_sdram_lld.h} | 41 +-- .../{hal_fsmc_sram_lld.c => hal_sram_lld.c} | 18 +- .../{hal_fsmc_sram_lld.h => hal_sram_lld.h} | 16 +- os/hal/src/hal_fsmc.c | 153 +-------- os/hal/src/hal_sdram.c | 122 ++++++++ os/hal/src/hal_sram.c | 146 +++++++++ .../STM32/STM32F0xx/COMP/mcuconf_community.h | 4 +- .../STM32/STM32F0xx/crc/mcuconf_community.h | 4 +- .../STM32F0xx/onewire/mcuconf_community.h | 4 +- .../STM32/STM32F0xx/qei/mcuconf_community.h | 4 +- .../STM32F1xx/onewire/mcuconf_community.h | 4 +- .../STM32/STM32F1xx/qei/mcuconf_community.h | 4 +- .../STM32/STM32F3xx/COMP/mcuconf_community.h | 4 +- .../STM32F3xx/EEProm/mcuconf_community.h | 4 +- .../STM32/STM32F3xx/OPAMP/mcuconf_community.h | 4 +- .../STM32F3xx/TIMCAP/mcuconf_community.h | 4 +- .../STM32/STM32F4xx/EICU/mcuconf_community.h | 4 +- .../STM32F4xx/FSMC_NAND/halconf_community.h | 14 + testhal/STM32/STM32F4xx/FSMC_NAND/main.c | 4 +- .../STM32F4xx/FSMC_NAND/mcuconf_community.h | 18 +- .../STM32F4xx/FSMC_SDRAM/halconf_community.h | 22 +- testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c | 4 +- .../STM32F4xx/FSMC_SDRAM/mcuconf_community.h | 24 +- .../STM32F4xx/FSMC_SRAM/halconf_community.h | 23 +- testhal/STM32/STM32F4xx/FSMC_SRAM/main.c | 4 +- .../STM32F4xx/FSMC_SRAM/mcuconf_community.h | 24 +- .../STM32F4xx/USB_HOST/mcuconf_community.h | 4 +- .../STM32F4xx/onewire/mcuconf_community.h | 4 +- .../STM32F7xx/USB_MSD/mcuconf_community.h | 4 +- .../STM32/STM32L0xx/COMP/mcuconf_community.h | 4 +- tools/templates/mcuconf_community.h | 4 +- 46 files changed, 594 insertions(+), 736 deletions(-) delete mode 100644 os/hal/include/fsmc/nand.h rename os/hal/include/{fsmc/sdram.h => hal_sdram.h} (86%) rename os/hal/include/{fsmc/sram.h => hal_sram.h} (76%) rename os/hal/ports/STM32/LLD/FSMCv1/{hal_fsmc_nand_lld.c => hal_nand_lld.c} (97%) rename os/hal/ports/STM32/LLD/FSMCv1/{hal_fsmc_nand_lld.h => hal_nand_lld.h} (92%) rename os/hal/ports/STM32/LLD/FSMCv1/{hal_fsmc_sdram_lld.c => hal_sdram_lld.c} (81%) rename os/hal/ports/STM32/LLD/FSMCv1/{hal_fsmc_sdram_lld.h => hal_sdram_lld.h} (83%) rename os/hal/ports/STM32/LLD/FSMCv1/{hal_fsmc_sram_lld.c => hal_sram_lld.c} (89%) rename os/hal/ports/STM32/LLD/FSMCv1/{hal_fsmc_sram_lld.h => hal_sram_lld.h} (86%) create mode 100644 os/hal/src/hal_sdram.c create mode 100644 os/hal/src/hal_sram.c diff --git a/demos/STM32/RT-STM32F303-DISCOVERY-PID/mcuconf_community.h b/demos/STM32/RT-STM32F303-DISCOVERY-PID/mcuconf_community.h index cf6a1ce9..785529b0 100644 --- a/demos/STM32/RT-STM32F303-DISCOVERY-PID/mcuconf_community.h +++ b/demos/STM32/RT-STM32F303-DISCOVERY-PID/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject index a2a9791b..ea4ffa90 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c index 25f42ab3..55a66a50 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c @@ -556,8 +556,8 @@ int main(void) { /* * Initialise FSMC for SDRAM. */ - fsmcSdramInit(); - fsmcSdramStart(&SDRAMD, &sdram_cfg); + sdramInit(); + sdramStart(&SDRAMD, &sdram_cfg); sdram_bulk_erase(); /* diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h index 36763ded..6ecfe916 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE /* diff --git a/os/common/ext/CMSIS/KINETIS/MK66F18.h b/os/common/ext/CMSIS/KINETIS/MK66F18.h index 432944fb..2fdfbbda 100644 --- a/os/common/ext/CMSIS/KINETIS/MK66F18.h +++ b/os/common/ext/CMSIS/KINETIS/MK66F18.h @@ -14379,7 +14379,7 @@ typedef struct { __IO uint32_t AC; /**< Address and Control Register, array offset: 0x48, array step: 0x8 */ __IO uint32_t CM; /**< Control Mask, array offset: 0x4C, array step: 0x8 */ } BLOCK[2]; -} SDRAM_TypeDef; +} FSMC_SDRAM_TypeDef; /* ---------------------------------------------------------------------------- -- SDRAM Register Masks @@ -14464,7 +14464,7 @@ typedef struct { /** Peripheral SDRAM base address */ #define SDRAM_BASE (0x4000F000u) /** Peripheral SDRAM base pointer */ -#define SDRAM ((SDRAM_TypeDef *)SDRAM_BASE) +#define SDRAM ((FSMC_SDRAM_TypeDef *)SDRAM_BASE) /** Array initializer of SDRAM peripheral base addresses */ #define SDRAM_BASE_ADDRS { SDRAM_BASE } /** Array initializer of SDRAM peripheral base pointers */ diff --git a/os/hal/hal.mk b/os/hal/hal.mk index 9908965c..63c1faec 100644 --- a/os/hal/hal.mk +++ b/os/hal/hal.mk @@ -10,9 +10,18 @@ endif HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c -ifneq ($(findstring HAL_USE_FSMC_SDRAM TRUE,$(HALCONF)), $(findstring HAL_USE_FSMC_SRAM TRUE,$(HALCONF)), $(findstring HAL_USE_FSMC_NAND TRUE,$(HALCONF))) +ifneq ($(findstring HAL_USE_FSMC TRUE,$(HALCONF)),) HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c endif +ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c +endif +ifneq ($(findstring HAL_USE_SRAM TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_sram.c +endif +ifneq ($(findstring HAL_USE_SDRAM TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_sdram.c +endif ifneq ($(findstring HAL_USE_ONEWIRE TRUE,$(HALCONF)),) HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c endif @@ -76,6 +85,9 @@ endif else HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_sram.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_sdram.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c \ diff --git a/os/hal/include/fsmc/nand.h b/os/hal/include/fsmc/nand.h deleted file mode 100644 index b2d9001f..00000000 --- a/os/hal/include/fsmc/nand.h +++ /dev/null @@ -1,293 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_nand_lld.h - * @brief NAND Driver subsystem low level driver header. - * - * @addtogroup NAND - * @{ - */ - -#ifndef NAND_H_ -#define NAND_H_ - -#include "bitmap.h" - -#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ -#define NAND_MIN_PAGE_SIZE 256 -#define NAND_MAX_PAGE_SIZE 8192 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief FSMC1 interrupt priority level setting. - */ -#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EMC_FSMC1_IRQ_PRIORITY 10 -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND1 is included. - */ -#if !defined(STM32_FSMC_USE_NAND1) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_NAND1 FALSE -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND2 is included. - */ -#if !defined(STM32_FSMC_USE_NAND2) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_NAND2 FALSE -#endif - -/** - * @brief NAND DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") -#endif - -/** - * @brief NAND interrupt enable switch. - * @details If set to @p TRUE the support for internal FSMC interrupt included. - */ -#if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__) -#define STM32_NAND_USE_INT FALSE -#endif - -/** -* @brief NAND1 DMA priority (0..3|lowest..highest). -*/ -#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_NAND_NAND1_DMA_PRIORITY 0 -#endif - -/** -* @brief NAND2 DMA priority (0..3|lowest..highest). -*/ -#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_NAND_NAND2_DMA_PRIORITY 0 -#endif - -/** - * @brief DMA stream used for NAND operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_NAND_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_FSMC_USE_NAND1 && !STM32_FSMC_USE_NAND2 -#error "NAND driver activated but no NAND peripheral assigned" -#endif - -#if (STM32_FSMC_USE_NAND1 || STM32_FSMC_USE_NAND2) && !STM32_HAS_FSMC -#error "FSMC not present in the selected device" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an NAND driver. - */ -typedef struct NANDDriver NANDDriver; - -/** - * @brief Type of interrupt handler function. - */ -typedef void (*nandisrhandler_t)(NANDDriver *nandp); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Number of erase blocks in NAND device. - */ - uint32_t blocks; - /** - * @brief Number of data bytes in page. - */ - uint32_t page_data_size; - /** - * @brief Number of spare bytes in page. - */ - uint32_t page_spare_size; - /** - * @brief Number of pages in block. - */ - uint32_t pages_per_block; - /** - * @brief Number of write cycles for row addressing. - */ - uint8_t rowcycles; - /** - * @brief Number of write cycles for column addressing. - */ - uint8_t colcycles; - - /* End of the mandatory fields.*/ - /** - * @brief Number of wait cycles. This value will be used both for - * PMEM and PATTR registers - * - * @note For proper calculation procedure please look at AN2784 document - * from STMicroelectronics. - */ - uint32_t pmem; -} NANDConfig; - -/** - * @brief Structure representing an NAND driver. - */ -struct NANDDriver { - /** - * @brief Driver state. - */ - nandstate_t state; - /** - * @brief Current configuration data. - */ - const NANDConfig *config; - /** - * @brief Array to store bad block map. - */ -#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#elif CH_CFG_USE_SEMAPHORES - semaphore_t semaphore; -#endif -#endif /* NAND_USE_MUTUAL_EXCLUSION */ - /* End of the mandatory fields.*/ - /** - * @brief Function enabling interrupts from FSMC. - */ - nandisrhandler_t isr_handler; - /** - * @brief Pointer to current transaction buffer. - */ - void *rxdata; - /** - * @brief Current transaction length in bytes. - */ - size_t datalen; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief DMA channel. - */ - const stm32_dma_stream_t *dma; - /** - * @brief Thread waiting for I/O completion. - */ - thread_t *thread; - /** - * @brief Pointer to the FSMC NAND registers block. - */ - FSMC_NAND_TypeDef *nand; - /** - * @brief Memory mapping for data. - */ - uint16_t *map_data; - /** - * @brief Memory mapping for commands. - */ - uint16_t *map_cmd; - /** - * @brief Memory mapping for addresses. - */ - uint16_t *map_addr; - /** - * @brief Pointer to bad block map. - * @details One bit per block. All memory allocation is user's responsibility. - */ - bitmap_t *bb_map; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_FSMC_USE_NAND1 && !defined(__DOXYGEN__) -extern NANDDriver NANDD1; -#endif - -#if STM32_FSMC_USE_NAND2 && !defined(__DOXYGEN__) -extern NANDDriver NANDD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void nand_lld_init(void); - void nand_lld_start(NANDDriver *nandp); - void nand_lld_stop(NANDDriver *nandp); - uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); - void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); - void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); - uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - uint8_t nand_lld_read_status(NANDDriver *nandp); - void nand_lld_reset(NANDDriver *nandp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_FSMC_NAND */ - -#endif /* NAND_H_ */ - -/** @} */ diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index ad5c4721..889da4f3 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -27,6 +27,10 @@ /* Error checks on the configuration header file.*/ +#if !defined(HAL_USE_COMP) +#define HAL_USE_COMP FALSE +#endif + #if !defined(HAL_USE_CRC) #define HAL_USE_CRC FALSE #endif @@ -39,6 +43,10 @@ #define HAL_USE_EICU FALSE #endif +#if !defined(HAL_USE_FSMC) +#define HAL_USE_FSMC FALSE +#endif + #if !defined(HAL_USE_NAND) #define HAL_USE_NAND FALSE #endif @@ -47,6 +55,10 @@ #define HAL_USE_ONEWIRE FALSE #endif +#if !defined(HAL_USE_OPAMP) +#define HAL_USE_OPAMP FALSE +#endif + #if !defined(HAL_USE_QEI) #define HAL_USE_QEI FALSE #endif @@ -71,15 +83,11 @@ #define HAL_USE_USB_MSD FALSE #endif -#if !defined(HAL_USE_COMP) -#define HAL_USE_COMP FALSE +#if !defined(HAL_USE_SDRAM) +#define HAL_USE_FSMC FALSE #endif -#if !defined(HAL_USE_OPAMP) -#define HAL_USE_OPAMP FALSE -#endif - -#if !defined(HAL_USE_FSMC) +#if !defined(HAL_USE_SRAM) #define HAL_USE_FSMC FALSE #endif @@ -96,6 +104,7 @@ #include "hal_qei.h" #include "hal_comp.h" #include "hal_opamp.h" +#include "hal_fsmc.h" /* Complex drivers.*/ #include "hal_onewire.h" @@ -103,7 +112,9 @@ #include "hal_eeprom.h" #include "hal_usb_hid.h" #include "hal_usb_msd.h" -#include "hal_fsmc.h" +#include "hal_nand.h" +#include "hal_sram.h" +#include "hal_sdram.h" /*===========================================================================*/ /* Driver constants. */ diff --git a/os/hal/include/hal_fsmc.h b/os/hal/include/hal_fsmc.h index 834fa8de..3b27941a 100644 --- a/os/hal/include/hal_fsmc.h +++ b/os/hal/include/hal_fsmc.h @@ -27,7 +27,7 @@ #include "hal.h" -#if (HAL_USE_FSMC_SDRAM == TRUE) || (HAL_USE_FSMC_SRAM == TRUE) || (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -161,7 +161,7 @@ typedef struct { __IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */ uint32_t RESERVED[63]; /**< Reserved */ __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */ -} FSMC_SRAM_NOR_TypeDef; +} FSMC_SRAM_TypeDef; #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ @@ -264,31 +264,6 @@ typedef struct { #define STM32_FSMC_USE_FSMC1 FALSE #endif -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM is included. - */ -#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_SDRAM FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM is included. - */ -#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_SRAM FALSE -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND is included. - */ -#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_NAND FALSE -#endif - - /** @} */ /*===========================================================================*/ @@ -326,26 +301,26 @@ struct FSMCDriver { fsmcstate_t state; /* End of the mandatory fields.*/ -#if HAL_USE_FSMC_SRAM - #if STM32_FSMC_USE_SRAM1 - FSMC_SRAM_NOR_TypeDef *sram1; +#if HAL_USE_SRAM + #if STM32_SRAM_USE_SRAM1 + FSMC_SRAM_TypeDef *sram1; #endif - #if STM32_FSMC_USE_SRAM2 - FSMC_SRAM_NOR_TypeDef *sram2; + #if STM32_SRAM_USE_SRAM2 + FSMC_SRAM_TypeDef *sram2; #endif - #if STM32_FSMC_USE_SRAM3 - FSMC_SRAM_NOR_TypeDef *sram3; + #if STM32_SRAM_USE_SRAM3 + FSMC_SRAM_TypeDef *sram3; #endif - #if STM32_FSMC_USE_SRAM4 - FSMC_SRAM_NOR_TypeDef *sram4; + #if STM32_SRAM_USE_SRAM4 + FSMC_SRAM_TypeDef *sram4; #endif #endif -#if HAL_USE_FSMC_NAND - #if STM32_FSMC_USE_NAND1 +#if HAL_USE_NAND + #if STM32_NAND_USE_NAND1 FSMC_NAND_TypeDef *nand1; #endif - #if STM32_FSMC_USE_NAND1 + #if STM32_NAND_USE_NAND1 FSMC_NAND_TypeDef *nand2; #endif #endif @@ -353,7 +328,7 @@ struct FSMCDriver { #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ defined(STM32F7)) - #if HAL_USE_FSMC_SDRAM + #if HAL_USE_SDRAM FSMC_SDRAM_TypeDef *sdram; #endif #endif @@ -381,18 +356,6 @@ extern "C" { } #endif -#if HAL_USE_FSMC_SDRAM == TRUE -#include "fsmc/sdram.h" -#endif - -#if HAL_USE_FSMC_SRAM == TRUE -#include "fsmc/sram.h" -#endif - -#if HAL_USE_FSMC_NAND == TRUE -#include "fsmc/nand.h" -#endif - #endif /* HAL_USE_FSMC */ #endif /* HAL_FSMC_H_ */ diff --git a/os/hal/include/fsmc/sdram.h b/os/hal/include/hal_sdram.h similarity index 86% rename from os/hal/include/fsmc/sdram.h rename to os/hal/include/hal_sdram.h index 7a04bdc9..297b715c 100644 --- a/os/hal/include/fsmc/sdram.h +++ b/os/hal/include/hal_sdram.h @@ -25,17 +25,10 @@ * @{ */ -#ifndef SDRAM_H_ -#define SDRAM_H_ +#ifndef HAL_SDRAM_H_ +#define HAL_SDRAM_H_ -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F745xx) || defined(STM32F746xx) || \ - defined(STM32F756xx) || defined(STM32F767xx) || \ - defined(STM32F769xx) || defined(STM32F777xx) || \ - defined(STM32F779xx)) - -#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -132,20 +125,20 @@ * @brief SDRAM driver enable switch. * @details If set to @p TRUE the support for SDRAM1 is included. */ -#if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SDRAM1 FALSE +#if !defined(STM32_SDRAM_USE_SDRAM1) || defined(__DOXYGEN__) +#define STM32_SDRAM_USE_SDRAM1 FALSE #else -#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE +#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE #endif /** * @brief SDRAM driver enable switch. * @details If set to @p TRUE the support for SDRAM2 is included. */ -#if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SDRAM2 FALSE +#if !defined(STM32_SDRAM_USE_SDRAM2) || defined(__DOXYGEN__) +#define STM32_SDRAM_USE_SDRAM2 FALSE #else -#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE +#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE #endif /** @} */ @@ -154,11 +147,11 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if !STM32_FSMC_USE_SDRAM1 && !STM32_FSMC_USE_SDRAM2 +#if !STM32_SDRAM_USE_SDRAM1 && !STM32_SDRAM_USE_SDRAM2 #error "SDRAM driver activated but no SDRAM peripheral assigned" #endif -#if (STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2) && !STM32_HAS_FSMC +#if (STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2) && !STM32_HAS_FSMC #error "FMC not present in the selected device" #endif @@ -231,21 +224,20 @@ struct SDRAMDriver { /* External declarations. */ /*===========================================================================*/ -extern SDRAMDriver SDRAMD; +extern SDRAMDriver SDRAMD1; #ifdef __cplusplus extern "C" { #endif - void fsmcSdramInit(void); - void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); - void fsmcSdramStop(SDRAMDriver *sdramp); + void sdramInit(void); + void sdramObjectInit(SDRAMDriver *sdramp); + void sdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); + void sdramStop(SDRAMDriver *sdramp); #ifdef __cplusplus } #endif -#endif /* HAL_USE_FSMC_SDRAM */ - -#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ +#endif /* HAL_USE_SDRAM */ #endif /* SDRAM_H_ */ diff --git a/os/hal/include/fsmc/sram.h b/os/hal/include/hal_sram.h similarity index 76% rename from os/hal/include/fsmc/sram.h rename to os/hal/include/hal_sram.h index 4a192467..bcf362a7 100644 --- a/os/hal/include/fsmc/sram.h +++ b/os/hal/include/hal_sram.h @@ -22,10 +22,10 @@ * @{ */ -#ifndef SRAM_H_ -#define SRAM_H_ +#ifndef HAL_SRAM_H_ +#define HAL_SRAM_H_ -#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_SRAM == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -43,32 +43,32 @@ * @brief SRAM driver enable switch. * @details If set to @p TRUE the support for SRAM1 is included. */ -#if !defined(STM32_FSMC_USE_SRAM1) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SRAM1 FALSE +#if !defined(STM32_SRAM_USE_SRAM1) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_SRAM1 FALSE #endif /** * @brief SRAM driver enable switch. * @details If set to @p TRUE the support for SRAM2 is included. */ -#if !defined(STM32_FSMC_USE_SRAM2) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SRAM2 FALSE +#if !defined(STM32_SRAM_USE_SRAM2) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_SRAM2 FALSE #endif /** * @brief SRAM driver enable switch. * @details If set to @p TRUE the support for SRAM3 is included. */ -#if !defined(STM32_FSMC_USE_SRAM3) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SRAM3 FALSE +#if !defined(STM32_SRAM_USE_SRAM3) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_SRAM3 FALSE #endif /** * @brief SRAM driver enable switch. * @details If set to @p TRUE the support for SRAM4 is included. */ -#if !defined(STM32_FSMC_USE_SRAM4) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SRAM4 FALSE +#if !defined(STM32_SRAM_USE_SRAM4) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_SRAM4 FALSE #endif /** @} */ @@ -77,13 +77,13 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if !STM32_FSMC_USE_SRAM1 && !STM32_FSMC_USE_SRAM2 && \ - !STM32_FSMC_USE_SRAM3 && !STM32_FSMC_USE_SRAM4 +#if !STM32_SRAM_USE_SRAM1 && !STM32_SRAM_USE_SRAM2 && \ + !STM32_SRAM_USE_SRAM3 && !STM32_SRAM_USE_SRAM4 #error "SRAM driver activated but no SRAM peripheral assigned" #endif -#if (STM32_FSMC_USE_SRAM1 || STM32_FSMC_USE_SRAM2 || \ - STM32_FSMC_USE_SRAM3 || STM32_FSMC_USE_SRAM4) && !STM32_HAS_FSMC +#if (STM32_SRAM_USE_SRAM1 || STM32_SRAM_USE_SRAM2 || \ + STM32_SRAM_USE_SRAM3 || STM32_SRAM_USE_SRAM4) && !STM32_HAS_FSMC #error "FSMC not present in the selected device" #endif @@ -126,7 +126,7 @@ struct SRAMDriver { /** * @brief Pointer to the FSMC SRAM registers block. */ - FSMC_SRAM_NOR_TypeDef *sram; + FSMC_SRAM_TypeDef *sram; }; /*===========================================================================*/ @@ -137,34 +137,35 @@ struct SRAMDriver { /* External declarations. */ /*===========================================================================*/ -#if STM32_FSMC_USE_SRAM1 && !defined(__DOXYGEN__) +#if STM32_SRAM_USE_SRAM1 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD1; #endif -#if STM32_FSMC_USE_SRAM2 && !defined(__DOXYGEN__) +#if STM32_SRAM_USE_SRAM2 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD2; #endif -#if STM32_FSMC_USE_SRAM3 && !defined(__DOXYGEN__) +#if STM32_SRAM_USE_SRAM3 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD3; #endif -#if STM32_FSMC_USE_SRAM4 && !defined(__DOXYGEN__) +#if STM32_SRAM_USE_SRAM4 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD4; #endif #ifdef __cplusplus extern "C" { #endif - void fsmcSramInit(void); - void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); - void fsmcSramStop(SRAMDriver *sramp); + void sramInit(void); + void sramObjectInit(SRAMDriver *sdramp); + void sramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); + void sramStop(SRAMDriver *sramp); #ifdef __cplusplus } #endif -#endif /* HAL_USE_FSMC_SRAM */ +#endif /* HAL_USE_SRAM */ -#endif /* SRAM_H_ */ +#endif /* HAL_SRAM_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/driver.mk b/os/hal/ports/STM32/LLD/FSMCv1/driver.mk index cffa3f74..8c354a56 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/driver.mk +++ b/os/hal/ports/STM32/LLD/FSMCv1/driver.mk @@ -1,17 +1,17 @@ ifeq ($(USE_SMART_BUILD),yes) -ifneq ($(findstring HAL_USE_FSMC_SDRAM TRUE,$(HALCONF)),) -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c +ifneq ($(findstring HAL_USE_SDRAM TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c endif -ifneq ($(findstring HAL_USE_FSMC_SRAM TRUE,$(HALCONF)),) -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c +ifneq ($(findstring HAL_USE_SRAM TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c endif -ifneq ($(findstring HAL_USE_FSMC_NAND TRUE,$(HALCONF)),) -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c +ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c endif else -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c endif PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c similarity index 97% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c rename to os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c index 895fd28e..abd5aa3f 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c @@ -24,7 +24,9 @@ #include "hal.h" -#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) + +#include "hal_nand_lld.h" /*===========================================================================*/ /* Driver local definitions. */ @@ -53,14 +55,14 @@ /** * @brief NAND1 driver identifier. */ -#if STM32_NAND_USE_FSMC_NAND1 || defined(__DOXYGEN__) +#if STM32_NAND_USE_NAND1 || defined(__DOXYGEN__) NANDDriver NANDD1; #endif /** * @brief NAND2 driver identifier. */ -#if STM32_NAND_USE_FSMC_NAND2 || defined(__DOXYGEN__) +#if STM32_NAND_USE_NAND2 || defined(__DOXYGEN__) NANDDriver NANDD2; #endif @@ -280,9 +282,9 @@ static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) { */ void nand_lld_init(void) { - fsmc_init(); + fsmcInit(); -#if STM32_NAND_USE_FSMC_NAND1 +#if STM32_NAND_USE_NAND1 /* Driver initialization.*/ nandObjectInit(&NANDD1); NANDD1.rxdata = NULL; @@ -294,9 +296,9 @@ void nand_lld_init(void) { NANDD1.map_cmd = (uint16_t *)FSMC_Bank2_MAP_COMMON_CMD; NANDD1.map_addr = (uint16_t *)FSMC_Bank2_MAP_COMMON_ADDR; NANDD1.bb_map = NULL; -#endif /* STM32_NAND_USE_FSMC_NAND1 */ +#endif /* STM32_NAND_USE_NAND1 */ -#if STM32_NAND_USE_FSMC_NAND2 +#if STM32_NAND_USE_NAND2 /* Driver initialization.*/ nandObjectInit(&NANDD2); NANDD2.rxdata = NULL; @@ -308,7 +310,7 @@ void nand_lld_init(void) { NANDD2.map_cmd = (uint16_t *)FSMC_Bank3_MAP_COMMON_CMD; NANDD2.map_addr = (uint16_t *)FSMC_Bank3_MAP_COMMON_ADDR; NANDD2.bb_map = NULL; -#endif /* STM32_NAND_USE_FSMC_NAND2 */ +#endif /* STM32_NAND_USE_NAND2 */ } /** @@ -325,7 +327,7 @@ void nand_lld_start(NANDDriver *nandp) { uint32_t pcr_bus_width; if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); + fsmcStart(&FSMCD1); if (nandp->state == NAND_STOP) { b = dmaStreamAlloc(nandp->dma, @@ -345,7 +347,7 @@ void nand_lld_start(NANDDriver *nandp) { #endif nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) | + STM32_DMA_CR_PL(STM32_NAND_DMA_PRIORITY) | dmasize | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h similarity index 92% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h rename to os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h index f47ee752..c4f8595b 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h @@ -22,12 +22,13 @@ * @{ */ -#ifndef HAL_FSMC_NAND_LLD_H_ -#define HAL_FSMC_NAND_LLD_H_ +#ifndef HAL_NAND_LLD_H_ +#define HAL_NAND_LLD_H_ #include "bitmap.h" +#include "hal_fsmc.h" -#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -54,16 +55,16 @@ * @brief NAND driver enable switch. * @details If set to @p TRUE the support for NAND1 is included. */ -#if !defined(STM32_FSMC_USE_NAND1) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_NAND1 FALSE +#if !defined(STM32_NAND_USE_NAND1) || defined(__DOXYGEN__) +#define STM32_NAND_USE_NAND1 FALSE #endif /** * @brief NAND driver enable switch. * @details If set to @p TRUE the support for NAND2 is included. */ -#if !defined(STM32_FSMC_USE_NAND2) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_NAND2 FALSE +#if !defined(STM32_NAND_USE_NAND2) || defined(__DOXYGEN__) +#define STM32_NAND_USE_NAND2 FALSE #endif /** @@ -111,11 +112,11 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if !STM32_FSMC_USE_NAND1 && !STM32_FSMC_USE_NAND2 +#if !STM32_NAND_USE_NAND1 && !STM32_NAND_USE_NAND2 #error "NAND driver activated but no NAND peripheral assigned" #endif -#if (STM32_FSMC_USE_NAND1 || STM32_FSMC_USE_NAND2) && !STM32_HAS_FSMC +#if (STM32_NAND_USE_NAND1 || STM32_NAND_USE_NAND2) && !STM32_HAS_FSMC #error "FSMC not present in the selected device" #endif @@ -255,11 +256,11 @@ struct NANDDriver { /* External declarations. */ /*===========================================================================*/ -#if STM32_FSMC_USE_NAND1 && !defined(__DOXYGEN__) +#if STM32_NAND_USE_NAND1 && !defined(__DOXYGEN__) extern NANDDriver NANDD1; #endif -#if STM32_FSMC_USE_NAND2 && !defined(__DOXYGEN__) +#if STM32_NAND_USE_NAND2 && !defined(__DOXYGEN__) extern NANDDriver NANDD2; #endif @@ -282,8 +283,8 @@ extern "C" { } #endif -#endif /* HAL_USE_FSMC_NAND */ +#endif /* HAL_USE_NAND */ -#endif /* HAL_FSMC_NAND_LLD_H_ */ +#endif /* HAL_NAND_LLD_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c similarity index 81% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c rename to os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c index 1b0c0db4..66f7b808 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c @@ -34,9 +34,9 @@ defined(STM32F769xx) || defined(STM32F777xx) || \ defined(STM32F779xx)) -#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__) -#include "hal_fsmc_sdram_lld.h" +#include "hal_sdram_lld.h" /*===========================================================================*/ /* Driver local definitions. */ @@ -59,7 +59,7 @@ /** * @brief SDRAM driver identifier. */ -SDRAMDriver SDRAMD; +SDRAMDriver SDRAMD1; /*===========================================================================*/ /* Driver local types. */ @@ -78,9 +78,9 @@ SDRAMDriver SDRAMD; * * @notapi */ -static void lld_sdram_wait_ready(void) { +static void sdram_lld_wait_ready(void) { /* Wait until the SDRAM controller is ready */ - while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY); + while (SDRAMD1.sdram->SDSR & FMC_SDSR_BUSY); } /** @@ -90,48 +90,48 @@ static void lld_sdram_wait_ready(void) { * * @notapi */ -static void lld_sdram_init_sequence(const SDRAMConfig *cfgp) { +static void sdram_lld_init_sequence(const SDRAMConfig *cfgp) { uint32_t command_target = 0; -#if STM32_FSMC_USE_SDRAM1 +#if STM32_SDRAM_USE_SDRAM1 command_target |= FMC_SDCMR_CTB1; #endif -#if STM32_FSMC_USE_SDRAM2 +#if STM32_SDRAM_USE_SDRAM2 command_target |= FMC_SDCMR_CTB2; #endif /* Step 3: Configure a clock configuration enable command.*/ - lld_sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target; + sdram_lld_wait_ready(); + SDRAMD1.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target; /* Step 4: Insert delay (tipically 100uS).*/ osalThreadSleepMilliseconds(1); /* Step 5: Configure a PALL (precharge all) command.*/ - lld_sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_PALL | command_target; + sdram_lld_wait_ready(); + SDRAMD1.sdram->SDCMR = FMCCM_PALL | command_target; /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/ - lld_sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | + sdram_lld_wait_ready(); + SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | (cfgp->sdcmr & FMC_SDCMR_NRFS); /* Step 6.2: Send the second command.*/ - lld_sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | + sdram_lld_wait_ready(); + SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | (cfgp->sdcmr & FMC_SDCMR_NRFS); /* Step 7: Program the external memory mode register.*/ - lld_sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_LOAD_MODE | command_target | + sdram_lld_wait_ready(); + SDRAMD1.sdram->SDCMR = FMCCM_LOAD_MODE | command_target | (cfgp->sdcmr & FMC_SDCMR_MRD); /* Step 8: Set clock.*/ - lld_sdram_wait_ready(); - SDRAMD.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT; + sdram_lld_wait_ready(); + SDRAMD1.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT; - lld_sdram_wait_ready(); + sdram_lld_wait_ready(); } /*===========================================================================*/ @@ -142,23 +142,23 @@ static void lld_sdram_init_sequence(const SDRAMConfig *cfgp) { /* Driver exported functions. */ /*===========================================================================*/ -void lld_sdram_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) +void sdram_lld_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) { sdramp->sdram->SDCR1 = cfgp->sdcr; sdramp->sdram->SDTR1 = cfgp->sdtr; sdramp->sdram->SDCR2 = cfgp->sdcr; sdramp->sdram->SDTR2 = cfgp->sdtr; - lld_sdram_init_sequence(cfgp); + sdram_lld_init_sequence(cfgp); } -void lld_sdram_stop(SDRAMDriver *sdramp) { +void sdram_lld_stop(SDRAMDriver *sdramp) { uint32_t command_target = 0; -#if STM32_FSMC_USE_SDRAM1 +#if STM32_SDRAM_USE_SDRAM1 command_target |= FMC_SDCMR_CTB1; #endif -#if STM32_FSMC_USE_SDRAM2 +#if STM32_SDRAM_USE_SDRAM2 command_target |= FMC_SDCMR_CTB2; #endif diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h similarity index 83% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h rename to os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h index 1fc7993d..6a19728a 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h @@ -28,16 +28,9 @@ #ifndef HAL_FMC_SDRAM_H_ #define HAL_FMC_SDRAM_H_ -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F745xx) || defined(STM32F746xx) || \ - defined(STM32F756xx) || defined(STM32F767xx) || \ - defined(STM32F769xx) || defined(STM32F777xx) || \ - defined(STM32F779xx)) - #include "hal_fsmc.h" -#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -55,8 +48,8 @@ * @brief SDRAM driver enable switch. * @details If set to @p TRUE the support for SDRAM1 is included. */ -#if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SDRAM1 FALSE +#if !defined(STM32_SDRAM_USE_SDRAM1) || defined(__DOXYGEN__) +#define STM32_SDRAM_USE_SDRAM1 FALSE #else #define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE #endif @@ -65,8 +58,8 @@ * @brief SDRAM driver enable switch. * @details If set to @p TRUE the support for SDRAM2 is included. */ -#if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SDRAM2 FALSE +#if !defined(STM32_SDRAM_USE_SDRAM2) || defined(__DOXYGEN__) +#define STM32_SDRAM_USE_SDRAM2 FALSE #else #define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE #endif @@ -77,14 +70,24 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if !STM32_FSMC_USE_SDRAM1 && !STM32_FSMC_USE_SDRAM2 +#if !STM32_SDRAM_USE_SDRAM1 && !STM32_SDRAM_USE_SDRAM2 #error "SDRAM driver activated but no SDRAM peripheral assigned" #endif -#if (STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2) && !STM32_HAS_FSMC +#if (STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2) && !STM32_HAS_FSMC #error "FMC not present in the selected device" #endif +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) +#else +#error "Device is not compatible with SDRAM" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -97,20 +100,18 @@ /* External declarations. */ /*===========================================================================*/ -extern SDRAMDriver SDRAMD; +extern SDRAMDriver SDRAMD1; #ifdef __cplusplus extern "C" { #endif - void lld_sdram_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); - void lld_sdram_stop(SDRAMDriver *sdramp); + void sdram_lld_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); + void sdram_lld_stop(SDRAMDriver *sdramp); #ifdef __cplusplus } #endif -#endif /* STM32_FSMC_USE_SDRAM */ - -#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ +#endif /* STM32_SDRAM_USE_SDRAM */ #endif /* HAL_FSMC_SDRAM_H_ */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c similarity index 89% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c rename to os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c index 49b7826c..71ecacd6 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c @@ -23,9 +23,9 @@ */ #include "hal.h" -#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_SRAM == TRUE) || defined(__DOXYGEN__) -#include "hal_fsmc_sram_lld.h" +#include "hal_sram_lld.h" /*===========================================================================*/ /* Driver local definitions. */ @@ -37,28 +37,28 @@ /** * @brief SRAM1 driver identifier. */ -#if STM32_FSMC_USE_SRAM1 || defined(__DOXYGEN__) +#if STM32_SRAM_USE_SRAM1 || defined(__DOXYGEN__) SRAMDriver SRAMD1; #endif /** * @brief SRAM2 driver identifier. */ -#if STM32_FSMC_USE_SRAM2 || defined(__DOXYGEN__) +#if STM32_SRAM_USE_SRAM2 || defined(__DOXYGEN__) SRAMDriver SRAMD2; #endif /** * @brief SRAM3 driver identifier. */ -#if STM32_FSMC_USE_SRAM3 || defined(__DOXYGEN__) +#if STM32_SRAM_USE_SRAM3 || defined(__DOXYGEN__) SRAMDriver SRAMD3; #endif /** * @brief SRAM4 driver identifier. */ -#if STM32_FSMC_USE_SRAM4 || defined(__DOXYGEN__) +#if STM32_SRAM_USE_SRAM4 || defined(__DOXYGEN__) SRAMDriver SRAMD4; #endif @@ -90,7 +90,7 @@ SRAMDriver SRAMD4; * * @notapi */ -void lld_sram_start(SRAMDriver *sramp, const SRAMConfig *cfgp) { +void sram_lld_start(SRAMDriver *sramp, const SRAMConfig *cfgp) { sramp->sram->BTR = cfgp->btr; sramp->sram->BWTR = cfgp->bwtr; @@ -104,7 +104,7 @@ void lld_sram_start(SRAMDriver *sramp, const SRAMConfig *cfgp) { * * @notapi */ -void lld_sram_stop(SRAMDriver *sramp) { +void sram_lld_stop(SRAMDriver *sramp) { uint32_t mask = FSMC_BCR_MBKEN; #if (defined(STM32F427xx) || defined(STM32F437xx) || \ @@ -118,7 +118,7 @@ void lld_sram_stop(SRAMDriver *sramp) { sramp->sram->BCR &= ~mask; } -#endif /* STM32_FSMC_USE_SRAM */ +#endif /* STM32_SRAM_USE_SRAM */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h similarity index 86% rename from os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h rename to os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h index bfd878fe..7af18c40 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h @@ -27,7 +27,7 @@ #include "hal_fsmc.h" -#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_SRAM == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -59,32 +59,32 @@ /* External declarations. */ /*===========================================================================*/ -#if STM32_FSMC_USE_SRAM1 && !defined(__DOXYGEN__) +#if STM32_SRAM_USE_SRAM1 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD1; #endif -#if STM32_FSMC_USE_SRAM2 && !defined(__DOXYGEN__) +#if STM32_SRAM_USE_SRAM2 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD2; #endif -#if STM32_FSMC_USE_SRAM3 && !defined(__DOXYGEN__) +#if STM32_SRAM_USE_SRAM3 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD3; #endif -#if STM32_FSMC_USE_SRAM4 && !defined(__DOXYGEN__) +#if STM32_SRAM_USE_SRAM4 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD4; #endif #ifdef __cplusplus extern "C" { #endif - void lld_sram_start(SRAMDriver *sramp, const SRAMConfig *cfgp); - void lld_sram_stop(SRAMDriver *sramp); + void sram_lld_start(SRAMDriver *sramp, const SRAMConfig *cfgp); + void sram_lld_stop(SRAMDriver *sramp); #ifdef __cplusplus } #endif -#endif /* STM32_FSMC_USE_SRAM */ +#endif /* STM32_SRAM_USE_SRAM */ #endif /* HAL_FSMC_SRAM_H_ */ diff --git a/os/hal/src/hal_fsmc.c b/os/hal/src/hal_fsmc.c index cdbb3875..7d30720b 100644 --- a/os/hal/src/hal_fsmc.c +++ b/os/hal/src/hal_fsmc.c @@ -23,7 +23,7 @@ */ #include "hal.h" -#if (HAL_USE_FSMC_SDRAM == TRUE) || (HAL_USE_FSMC_SRAM == TRUE) || (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_SDRAM == TRUE) || (HAL_USE_SRAM == TRUE) || (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver local definitions. */ @@ -72,27 +72,27 @@ void fsmcInit(void) { if (FSMCD1.state == FSMC_UNINIT) { FSMCD1.state = FSMC_STOP; -#if STM32_FSMC_USE_SRAM1 - FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE); +#if STM32_SRAM_USE_SRAM1 + FSMCD1.sram1 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE); #endif -#if STM32_FSMC_USE_SRAM2 - FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8); +#if STM32_SRAM_USE_SRAM2 + FSMCD1.sram2 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE + 8); #endif -#if STM32_FSMC_USE_SRAM3 - FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2); +#if STM32_SRAM_USE_SRAM3 + FSMCD1.sram3 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2); #endif -#if STM32_FSMC_USE_SRAM4 - FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3); +#if STM32_SRAM_USE_SRAM4 + FSMCD1.sram4 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3); #endif -#if STM32_FSMC_USE_NAND1 +#if STM32_NAND_USE_NAND1 FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; #endif -#if STM32_FSMC_USE_NAND2 +#if STM32_NAND_USE_NAND2 FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; #endif @@ -102,7 +102,7 @@ void fsmcInit(void) { defined(STM32F756xx) || defined(STM32F767xx) || \ defined(STM32F769xx) || defined(STM32F777xx) || \ defined(STM32F779xx)) - #if STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2 + #if STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2 FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; #endif #endif @@ -176,12 +176,12 @@ void fsmcStop(FSMCDriver *fsmcp) { CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { CH_IRQ_PROLOGUE(); -#if STM32_FSMC_USE_NAND1 +#if STM32_NAND_USE_NAND1 if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) { NANDD1.isr_handler(&NANDD1); } #endif -#if STM32_FSMC_USE_NAND2 +#if STM32_NAND_USE_NAND2 if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) { NANDD2.isr_handler(&NANDD2); } @@ -189,131 +189,6 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { CH_IRQ_EPILOGUE(); } -#if (HAL_USE_FSMC_SDRAM == TRUE) - -#include "hal_fsmc_sdram_lld.h" -/** - * @brief FSMC SDRAM Driver init - */ -void fsmcSdramInit(void) { - - fsmcInit(); - SDRAMD.sdram = FSMCD1.sdram; - SDRAMD.state = SDRAM_STOP; -} - -/** - * @brief Configures and activates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * @param[in] cfgp pointer to the @p SDRAMConfig object - */ -void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) { - - if (FSMCD1.state == FSMC_STOP) - fsmcStart(&FSMCD1); - - osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), - "SDRAM. Invalid state."); - - if (sdramp->state == SDRAM_STOP) { - - lld_sdram_start(sdramp, cfgp); - - sdramp->state = SDRAM_READY; - } -} - -/** - * @brief Deactivates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * - * @notapi - */ -void fsmcSdramStop(SDRAMDriver *sdramp) { - - if (sdramp->state == SDRAM_READY) { - lld_sdram_stop(sdramp); - sdramp->state = SDRAM_STOP; - } -} -#endif /* HAL_USE_FSMC_SDRAM == TRUE */ - - -#if (HAL_USE_FSMC_SRAM == TRUE) - -#include "hal_fsmc_sram_lld.h" - -/** - * @brief Low level SRAM driver initialization. - * - * @notapi - */ -void fsmcSramInit(void) { - - fsmcInit(); - -#if STM32_FSMC_USE_SRAM1 - SRAMD1.sram = FSMCD1.sram1; - SRAMD1.state = SRAM_STOP; -#endif /* STM32_FSMC_USE_SRAM1 */ - -#if STM32_FSMC_USE_SRAM2 - SRAMD2.sram = FSMCD1.sram2; - SRAMD2.state = SRAM_STOP; -#endif /* STM32_FSMC_USE_SRAM2 */ - -#if STM32_FSMC_USE_SRAM3 - SRAMD3.sram = FSMCD1.sram3; - SRAMD3.state = SRAM_STOP; -#endif /* STM32_FSMC_USE_SRAM3 */ - -#if STM32_FSMC_USE_SRAM4 - SRAMD4.sram = FSMCD1.sram4; - SRAMD4.state = SRAM_STOP; -#endif /* STM32_FSMC_USE_SRAM4 */ -} - -/** - * @brief Configures and activates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * @param[in] cfgp pointer to the @p SRAMConfig object - * - * @notapi - */ -void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { - - if (FSMCD1.state == FSMC_STOP) - fsmcStart(&FSMCD1); - - osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), - "invalid state"); - - if (sramp->state == SRAM_STOP) { - lld_sram_start(sramp, cfgp); - sramp->state = SRAM_READY; - } -} - -/** - * @brief Deactivates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * - * @notapi - */ -void fsmcSramStop(SRAMDriver *sramp) { - - if (sramp->state == SRAM_READY) { - lld_sram_stop(sramp); - sramp->state = SRAM_STOP; - } -} - -#endif /* HAL_USE_FSMC_SRAM == TRUE */ - #endif /* HAL_USE_FSMC */ /** @} */ diff --git a/os/hal/src/hal_sdram.c b/os/hal/src/hal_sdram.c new file mode 100644 index 00000000..efa876be --- /dev/null +++ b/os/hal/src/hal_sdram.c @@ -0,0 +1,122 @@ +/* + ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio + Copyright (C) 2017 Fabien Poussin (fabien.poussin (at) google's mail) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in sdramliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_sdram.c + * @brief SDRAM Driver code. + * + * @addtogroup SDRAM + * @{ + */ + +#include "hal.h" + +#if HAL_USE_SDRAM || defined(__DOXYGEN__) + + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +#include "hal_sdram_lld.h" + +/** + * @brief SDRAM Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void sdramInit(void) { + fsmcInit(); + sdramObjectInit(&SDRAMD1); +} + +/** + * @brief Initializes the standard part of a @p SDRAMDriver structure. + * + * @param[out] sdramp pointer to the @p SDRAMDriver object + * + * @init + */ +void sdramObjectInit(SDRAMDriver *sdramp) { + + sdramp->sdram = FSMCD1.sdram; + sdramp->state = SDRAM_STOP; +} + +/** + * @brief Configures and activates the SDRAM peripheral. + * + * @param[in] sdramp pointer to the @p SDRAMDriver object + * @param[in] config pointer to the @p SDRAMConfig object + * + * @api + */ +void sdramStart(SDRAMDriver *sdramp, const SDRAMConfig *config) { + + osalDbgCheck((sdramp != NULL) && (config != NULL)); + + if (FSMCD1.state == FSMC_STOP) + fsmcStart(&FSMCD1); + + osalSysLock(); + osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), + "invalid state"); + sdram_lld_start(sdramp, config); + sdramp->state = SDRAM_READY; + osalSysUnlock(); +} + +/** + * @brief Deactivates the SDRAM peripheral. + * + * @param[in] sdramp pointer to the @p SDRAMDriver object + * + * @api + */ +void sdramStop(SDRAMDriver *sdramp) { + + osalDbgCheck(sdramp != NULL); + + osalSysLock(); + osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), + "invalid state"); + sdram_lld_stop(sdramp); + sdramp->state = SDRAM_STOP; + osalSysUnlock(); +} + +#endif /* HAL_USE_SDRAM */ + +/** @} */ diff --git a/os/hal/src/hal_sram.c b/os/hal/src/hal_sram.c new file mode 100644 index 00000000..892e9a2d --- /dev/null +++ b/os/hal/src/hal_sram.c @@ -0,0 +1,146 @@ +/* + ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio + Copyright (C) 2017 Fabien Poussin (fabien.poussin (at) google's mail) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in sramliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_sram.c + * @brief SRAM Driver code. + * + * @addtogroup SRAM + * @{ + */ + +#include "hal.h" + +#if HAL_USE_SRAM || defined(__DOXYGEN__) + + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +#include "hal_sram_lld.h" + +/** + * @brief SRAM Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void sramInit(void) { + + fsmcInit(); + +#if STM32_SRAM_USE_SRAM1 + SRAMD1.sram = FSMCD1.sram1; + SRAMD1.state = SRAM_STOP; + sramObjectInit(&SRAMD1); +#endif /* STM32_SRAM_USE_SRAM1 */ + +#if STM32_SRAM_USE_SRAM2 + SRAMD2.sram = FSMCD1.sram2; + SRAMD2.state = SRAM_STOP; + sramObjectInit(&SRAMD2); +#endif /* STM32_SRAM_USE_SRAM2 */ + +#if STM32_SRAM_USE_SRAM3 + SRAMD3.sram = FSMCD1.sram3; + SRAMD3.state = SRAM_STOP; + sramObjectInit(&SRAMD3); +#endif /* STM32_SRAM_USE_SRAM3 */ + +#if STM32_SRAM_USE_SRAM4 + SRAMD4.sram = FSMCD1.sram4; + SRAMD4.state = SRAM_STOP; + sramObjectInit(&SRAMD4); +#endif /* STM32_SRAM_USE_SRAM4 */ + +} + +/** + * @brief Initializes the standard part of a @p SRAMDriver structure. + * + * @param[out] sramp pointer to the @p SRAMDriver object + * + * @init + */ +void sramObjectInit(SRAMDriver *sramp) { + + sramp->state = SRAM_STOP; +} + +/** + * @brief Configures and activates the SRAM peripheral. + * + * @param[in] sramp pointer to the @p SRAMDriver object + * @param[in] config pointer to the @p SRAMConfig object + * + * @api + */ +void sramStart(SRAMDriver *sramp, const SRAMConfig *config) { + + osalDbgCheck((sramp != NULL) && (config != NULL)); + + if (FSMCD1.state == FSMC_STOP) + fsmcStart(&FSMCD1); + + osalSysLock(); + osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), + "invalid state"); + sram_lld_start(sramp, config); + sramp->state = SRAM_READY; + osalSysUnlock(); +} + +/** + * @brief Deactivates the SRAM peripheral. + * + * @param[in] sramp pointer to the @p SRAMDriver object + * + * @api + */ +void sramStop(SRAMDriver *sramp) { + + osalDbgCheck(sramp != NULL); + + osalSysLock(); + osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), + "invalid state"); + sram_lld_stop(sramp); + sramp->state = SRAM_STOP; + osalSysUnlock(); +} + +#endif /* HAL_USE_SRAM */ + +/** @} */ diff --git a/testhal/STM32/STM32F0xx/COMP/mcuconf_community.h b/testhal/STM32/STM32F0xx/COMP/mcuconf_community.h index 1be93a64..0af8b158 100644 --- a/testhal/STM32/STM32F0xx/COMP/mcuconf_community.h +++ b/testhal/STM32/STM32F0xx/COMP/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F0xx/crc/mcuconf_community.h b/testhal/STM32/STM32F0xx/crc/mcuconf_community.h index 1ebe24c9..3b9709ad 100644 --- a/testhal/STM32/STM32F0xx/crc/mcuconf_community.h +++ b/testhal/STM32/STM32F0xx/crc/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F0xx/onewire/mcuconf_community.h b/testhal/STM32/STM32F0xx/onewire/mcuconf_community.h index 1ebe24c9..3b9709ad 100644 --- a/testhal/STM32/STM32F0xx/onewire/mcuconf_community.h +++ b/testhal/STM32/STM32F0xx/onewire/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F0xx/qei/mcuconf_community.h b/testhal/STM32/STM32F0xx/qei/mcuconf_community.h index 1ebe24c9..3b9709ad 100644 --- a/testhal/STM32/STM32F0xx/qei/mcuconf_community.h +++ b/testhal/STM32/STM32F0xx/qei/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F1xx/onewire/mcuconf_community.h b/testhal/STM32/STM32F1xx/onewire/mcuconf_community.h index 1ebe24c9..3b9709ad 100644 --- a/testhal/STM32/STM32F1xx/onewire/mcuconf_community.h +++ b/testhal/STM32/STM32F1xx/onewire/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F1xx/qei/mcuconf_community.h b/testhal/STM32/STM32F1xx/qei/mcuconf_community.h index 1ebe24c9..3b9709ad 100644 --- a/testhal/STM32/STM32F1xx/qei/mcuconf_community.h +++ b/testhal/STM32/STM32F1xx/qei/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F3xx/COMP/mcuconf_community.h b/testhal/STM32/STM32F3xx/COMP/mcuconf_community.h index 1ebe24c9..3b9709ad 100644 --- a/testhal/STM32/STM32F3xx/COMP/mcuconf_community.h +++ b/testhal/STM32/STM32F3xx/COMP/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h b/testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h index 1ebe24c9..3b9709ad 100644 --- a/testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h +++ b/testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F3xx/OPAMP/mcuconf_community.h b/testhal/STM32/STM32F3xx/OPAMP/mcuconf_community.h index b862d6e8..d62e3905 100644 --- a/testhal/STM32/STM32F3xx/OPAMP/mcuconf_community.h +++ b/testhal/STM32/STM32F3xx/OPAMP/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F3xx/TIMCAP/mcuconf_community.h b/testhal/STM32/STM32F3xx/TIMCAP/mcuconf_community.h index a462bae6..822b972d 100644 --- a/testhal/STM32/STM32F3xx/TIMCAP/mcuconf_community.h +++ b/testhal/STM32/STM32F3xx/TIMCAP/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h b/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h index 36e182ba..c6b04668 100644 --- a/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h index 20fd46cb..a72fba89 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC TRUE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c index 73c9cb3d..c4e2324a 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c @@ -78,9 +78,9 @@ #define NAND_TEST_KILL_BLOCK 8000 #endif -#if STM32_NAND_USE_FSMC_NAND1 +#if STM32_NAND_USE_NAND1 #define NAND NANDD1 -#elif STM32_NAND_USE_FSMC_NAND2 +#elif STM32_NAND_USE_NAND2 #define NAND NANDD2 #else #error "You should enable at least one NAND interface" diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h index 108d84ca..bba7f084 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h @@ -24,8 +24,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 TRUE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 TRUE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 @@ -34,18 +34,16 @@ /* * FSMC SRAM driver system settings. */ -#define STM32_USE_FSMC_SRAM FALSE -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE +#define STM32_SRAM_USE_SRAM1 FALSE +#define STM32_SRAM_USE_SRAM2 FALSE +#define STM32_SRAM_USE_SRAM3 FALSE +#define STM32_SRAM_USE_SRAM4 FALSE /* * FSMC SDRAM driver system settings. */ -#define STM32_USE_FSMC_SDRAM FALSE -#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE -#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE +#define STM32_SDRAM_USE_SDRAM1 FALSE +#define STM32_SDRAM_USE_SDRAM2 FALSE /* * TIMCAP driver system settings. diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h index 9ad41fd9..91ad6373 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h @@ -27,24 +27,30 @@ /** * @brief Enables the FSMC subsystem. */ -#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_SDRAM TRUE +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC TRUE #endif /** - * @brief Enables the FSMC subsystem. + * @brief Enables the SDRAM subsystem. */ -#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_SRAM FALSE +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM TRUE #endif /** - * @brief Enables the FSMC subsystem. + * @brief Enables the SRAM subsystem. */ -#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_NAND FALSE +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE #endif +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif /** * @brief Enables the 1-wire subsystem. */ diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c index 1ff77409..0d3feee1 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c @@ -183,8 +183,8 @@ int main(void) { halInit(); chSysInit(); - fsmcSdramInit(); - fsmcSdramStart(&SDRAMD, &sdram_cfg); + sdramInit(); + sdramStart(&SDRAMD1, &sdram_cfg); membench(); memtest(); diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h index 44949294..4e08dfe4 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h @@ -22,30 +22,30 @@ #define STM32_FSMC_USE_FSMC1 TRUE #define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 #define STM32_FSMC_DMA_CHN 0x03010201 -#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_FSMC_DMA_PRIORITY 0 -#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("FSMC DMA failure") /* * FSMC NAND driver system settings. */ -#define STM32_FSMC_USE_NAND1 FALSE -#define STM32_FSMC_USE_NAND2 FALSE -#define STM32_FSMC_USE_NAND_EXT_INT FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE +#define STM32_NAND_USE_EXT_INT FALSE +#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_NAND_DMA_PRIORITY 0 +#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") /* * FSMC SRAM driver system settings. */ -#define STM32_FSMC_USE_SRAM1 FALSE -#define STM32_FSMC_USE_SRAM2 FALSE -#define STM32_FSMC_USE_SRAM3 FALSE -#define STM32_FSMC_USE_SRAM4 FALSE +#define STM32_SRAM_USE_SRAM1 FALSE +#define STM32_SRAM_USE_SRAM2 FALSE +#define STM32_SRAM_USE_SRAM3 FALSE +#define STM32_SRAM_USE_SRAM4 FALSE /* * FSMC SDRAM driver system settings. */ -#define STM32_FSMC_USE_SDRAM1 FALSE -#define STM32_FSMC_USE_SDRAM2 TRUE +#define STM32_SDRAM_USE_SDRAM1 FALSE +#define STM32_SDRAM_USE_SDRAM2 TRUE /* * TIMCAP driver system settings. diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h index f9cfcbeb..a19553b8 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h @@ -27,22 +27,29 @@ /** * @brief Enables the FSMC subsystem. */ -#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_SDRAM FALSE +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC TRUE #endif /** - * @brief Enables the FSMC subsystem. + * @brief Enables the SDRAM subsystem. */ -#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_SRAM TRUE +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE #endif /** - * @brief Enables the FSMC subsystem. + * @brief Enables the SRAM subsystem. */ -#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_NAND FALSE +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM TRUE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE #endif /** diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c index 64138355..4bd94f8f 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c @@ -172,8 +172,8 @@ int main(void) { halInit(); chSysInit(); - fsmcSramInit(); - fsmcSramStart(&SRAMD4, &sram_cfg); + sramInit(); + sramStart(&SRAMD4, &sram_cfg); membench(); memtest(); diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h index 8abb48dd..b601a5f6 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h @@ -22,30 +22,30 @@ #define STM32_FSMC_USE_FSMC1 TRUE #define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 #define STM32_FSMC_DMA_CHN 0x03010201 -#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_FSMC_DMA_PRIORITY 0 -#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("FSMC DMA failure") /* * FSMC NAND driver system settings. */ -#define STM32_FSMC_USE_NAND1 FALSE -#define STM32_FSMC_USE_NAND2 FALSE -#define STM32_FSMC_USE_NAND_EXT_INT FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE +#define STM32_NAND_USE_EXT_INT FALSE +#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_NAND_DMA_PRIORITY 0 +#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") /* * FSMC SRAM driver system settings. */ -#define STM32_FSMC_USE_SRAM1 FALSE -#define STM32_FSMC_USE_SRAM2 FALSE -#define STM32_FSMC_USE_SRAM3 FALSE -#define STM32_FSMC_USE_SRAM4 TRUE +#define STM32_SRAM_USE_SRAM1 FALSE +#define STM32_SRAM_USE_SRAM2 FALSE +#define STM32_SRAM_USE_SRAM3 FALSE +#define STM32_SRAM_USE_SRAM4 TRUE /* * FSMC SDRAM driver system settings. */ -#define STM32_FSMC_USE_SDRAM1 FALSE -#define STM32_FSMC_USE_SDRAM2 FALSE +#define STM32_SDRAM_USE_SDRAM1 FALSE +#define STM32_SDRAM_USE_SDRAM2 FALSE /* * TIMCAP driver system settings. diff --git a/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h b/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h index 1ebe24c9..3b9709ad 100644 --- a/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h b/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h index 1ebe24c9..3b9709ad 100644 --- a/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F7xx/USB_MSD/mcuconf_community.h b/testhal/STM32/STM32F7xx/USB_MSD/mcuconf_community.h index 1ebe24c9..3b9709ad 100644 --- a/testhal/STM32/STM32F7xx/USB_MSD/mcuconf_community.h +++ b/testhal/STM32/STM32F7xx/USB_MSD/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32L0xx/COMP/mcuconf_community.h b/testhal/STM32/STM32L0xx/COMP/mcuconf_community.h index 142ed57e..e7718766 100644 --- a/testhal/STM32/STM32L0xx/COMP/mcuconf_community.h +++ b/testhal/STM32/STM32L0xx/COMP/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/tools/templates/mcuconf_community.h b/tools/templates/mcuconf_community.h index b862d6e8..d62e3905 100644 --- a/tools/templates/mcuconf_community.h +++ b/tools/templates/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 From 05913b8055080125374af839f0f6baba53792d1b Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 30 Oct 2019 13:03:32 +0100 Subject: [PATCH 5/9] Cleaning FSMC code --- os/hal/include/hal_community.h | 1 - os/hal/include/hal_sdram.h | 2 +- os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h | 2 +- os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h | 6 +++--- os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h | 6 +++--- os/hal/src/hal_fsmc.c | 9 ++++++++- .../STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h | 13 ++++++------- 7 files changed, 22 insertions(+), 17 deletions(-) diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index 889da4f3..d4924f50 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -96,7 +96,6 @@ /* Shared headers.*/ /* Normal drivers.*/ -#include "hal_nand.h" #include "hal_eicu.h" #include "hal_rng.h" #include "hal_usbh.h" diff --git a/os/hal/include/hal_sdram.h b/os/hal/include/hal_sdram.h index 297b715c..af4a1ad3 100644 --- a/os/hal/include/hal_sdram.h +++ b/os/hal/include/hal_sdram.h @@ -239,6 +239,6 @@ extern "C" { #endif /* HAL_USE_SDRAM */ -#endif /* SDRAM_H_ */ +#endif /* HAL_SDRAM_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h index c4f8595b..51f2b952 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h @@ -15,7 +15,7 @@ */ /** - * @file hal_fsmc_nand_lld.h + * @file hal_nand_lld.h * @brief FSMC NAND Driver subsystem low level driver header. * * @addtogroup NAND diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h index 6a19728a..3991695f 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h @@ -25,8 +25,8 @@ * @{ */ -#ifndef HAL_FMC_SDRAM_H_ -#define HAL_FMC_SDRAM_H_ +#ifndef HAL_SDRAM_LLD_H_ +#define HAL_SDRAM_LLD_H_ #include "hal_fsmc.h" @@ -113,6 +113,6 @@ extern "C" { #endif /* STM32_SDRAM_USE_SDRAM */ -#endif /* HAL_FSMC_SDRAM_H_ */ +#endif /* HAL_SDRAM_LLD_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h index 7af18c40..857a96e3 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h @@ -22,8 +22,8 @@ * @{ */ -#ifndef HAL_FSMC_SRAM_H_ -#define HAL_FSMC_SRAM_H_ +#ifndef HAL_SRAM_LLD_H_ +#define HAL_SRAM_LLD_H_ #include "hal_fsmc.h" @@ -86,6 +86,6 @@ extern "C" { #endif /* STM32_SRAM_USE_SRAM */ -#endif /* HAL_FSMC_SRAM_H_ */ +#endif /* HAL_SRAM_LLD_H_ */ /** @} */ diff --git a/os/hal/src/hal_fsmc.c b/os/hal/src/hal_fsmc.c index 7d30720b..c3f2a99f 100644 --- a/os/hal/src/hal_fsmc.c +++ b/os/hal/src/hal_fsmc.c @@ -71,7 +71,7 @@ void fsmcInit(void) { if (FSMCD1.state == FSMC_UNINIT) { FSMCD1.state = FSMC_STOP; - +#if HAL_USE_SRAM #if STM32_SRAM_USE_SRAM1 FSMCD1.sram1 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE); #endif @@ -87,7 +87,9 @@ void fsmcInit(void) { #if STM32_SRAM_USE_SRAM4 FSMCD1.sram4 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3); #endif +#endif +#if HAL_USE_NAND #if STM32_NAND_USE_NAND1 FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; #endif @@ -95,7 +97,9 @@ void fsmcInit(void) { #if STM32_NAND_USE_NAND2 FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; #endif +#endif +#if HAL_USE_SDRAM #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ defined(STM32F745xx) || defined(STM32F746xx) || \ @@ -105,6 +109,7 @@ void fsmcInit(void) { #if STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2 FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; #endif +#endif #endif } } @@ -176,6 +181,7 @@ void fsmcStop(FSMCDriver *fsmcp) { CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { CH_IRQ_PROLOGUE(); +#if HAL_USE_NAND #if STM32_NAND_USE_NAND1 if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) { NANDD1.isr_handler(&NANDD1); @@ -185,6 +191,7 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) { NANDD2.isr_handler(&NANDD2); } +#endif #endif CH_IRQ_EPILOGUE(); } diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h index bba7f084..0a5db9b1 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h @@ -34,17 +34,16 @@ /* * FSMC SRAM driver system settings. */ -#define STM32_SRAM_USE_SRAM1 FALSE -#define STM32_SRAM_USE_SRAM2 FALSE -#define STM32_SRAM_USE_SRAM3 FALSE -#define STM32_SRAM_USE_SRAM4 FALSE +#define STM32_SRAM_USE_SRAM1 FALSE +#define STM32_SRAM_USE_SRAM2 FALSE +#define STM32_SRAM_USE_SRAM3 FALSE +#define STM32_SRAM_USE_SRAM4 FALSE /* * FSMC SDRAM driver system settings. */ -#define STM32_SDRAM_USE_SDRAM1 FALSE -#define STM32_SDRAM_USE_SDRAM2 FALSE - +#define STM32_SDRAM_USE_SDRAM1 FALSE +#define STM32_SDRAM_USE_SDRAM2 FALSE /* * TIMCAP driver system settings. */ From b15b68c1c4dd59a846c36e52ef4502eb8ad84a5a Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 30 Oct 2019 13:12:29 +0100 Subject: [PATCH 6/9] Fixed default hal defines --- os/hal/include/hal_community.h | 4 ++-- os/hal/include/hal_fsmc.h | 1 + os/hal/include/hal_nand.h | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index d4924f50..435115b0 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -84,11 +84,11 @@ #endif #if !defined(HAL_USE_SDRAM) -#define HAL_USE_FSMC FALSE +#define HAL_USE_SDRAM FALSE #endif #if !defined(HAL_USE_SRAM) -#define HAL_USE_FSMC FALSE +#define HAL_USE_SRAM FALSE #endif /* Abstract interfaces.*/ diff --git a/os/hal/include/hal_fsmc.h b/os/hal/include/hal_fsmc.h index 3b27941a..3c5d9999 100644 --- a/os/hal/include/hal_fsmc.h +++ b/os/hal/include/hal_fsmc.h @@ -256,6 +256,7 @@ typedef struct { * @name Configuration options * @{ */ + /** * @brief FSMC driver enable switch. * @details If set to @p TRUE the support for FSMC is included. diff --git a/os/hal/include/hal_nand.h b/os/hal/include/hal_nand.h index f9071524..0c95e89a 100644 --- a/os/hal/include/hal_nand.h +++ b/os/hal/include/hal_nand.h @@ -51,6 +51,7 @@ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ + /** * @brief Enables the mutual exclusion APIs on the NAND. */ From f6b1a12ecf14e4c703b18f3d13537e878215e91a Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 30 Oct 2019 13:19:08 +0100 Subject: [PATCH 7/9] Fixed DMA2D example --- .../halconf_community.h | 14 +++++++++ .../STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c | 3 +- .../mcuconf_community.h | 30 ++++++++++--------- os/hal/include/hal_sdram.h | 2 +- os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h | 2 +- .../STM32F4xx/FSMC_SDRAM/halconf_community.h | 1 + 6 files changed, 34 insertions(+), 18 deletions(-) diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h index c28b90bb..8082fce3 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC TRUE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM TRUE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c index 55a66a50..ce99e3b2 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c @@ -23,7 +23,6 @@ #include "usbcfg.h" #endif -#include "hal_fsmc_sdram.h" #include "ili9341.h" #include "hal_stm32_ltdc.h" #include "hal_stm32_dma2d.h" @@ -557,7 +556,7 @@ int main(void) { * Initialise FSMC for SDRAM. */ sdramInit(); - sdramStart(&SDRAMD, &sdram_cfg); + sdramStart(&SDRAMD1, &sdram_cfg); sdram_bulk_erase(); /* diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h index 6ecfe916..2528ef47 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h @@ -19,29 +19,31 @@ */ #define STM32_FSMC_USE_FSMC1 TRUE #define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 +#define STM32_FSMC_DMA_CHN 0x03010201 /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_NAND1 FALSE -#define STM32_NAND_USE_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE - -/* - * FSMC SDRAM driver system settings. - */ -#define STM32_USE_FSMC_SDRAM TRUE -#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE -#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE +#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_NAND_DMA_PRIORITY 0 +#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") /* * FSMC SRAM driver system settings. */ -#define STM32_USE_FSMC_SRAM FALSE -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE +#define STM32_SRAM_USE_SRAM1 FALSE +#define STM32_SRAM_USE_SRAM2 FALSE +#define STM32_SRAM_USE_SRAM3 FALSE +#define STM32_SRAM_USE_SRAM4 FALSE + +/* + * FSMC SDRAM driver system settings. + */ +#define STM32_SDRAM_USE_SDRAM1 FALSE +#define STM32_SDRAM_USE_SDRAM2 TRUE /* * LTDC driver system settings. diff --git a/os/hal/include/hal_sdram.h b/os/hal/include/hal_sdram.h index af4a1ad3..eaca0fb0 100644 --- a/os/hal/include/hal_sdram.h +++ b/os/hal/include/hal_sdram.h @@ -18,7 +18,7 @@ */ /** - * @file hal_fsmc_sdram.h + * @file hal_sdram.h * @brief SDRAM Driver subsystem low level driver header. * * @addtogroup SDRAM diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h index 3991695f..665c570c 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h @@ -18,7 +18,7 @@ */ /** - * @file hal_fsmc_sdram.h + * @file hal_sdram.h * @brief SDRAM Driver subsystem low level driver header. * * @addtogroup SDRAM diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h index 91ad6373..51524e10 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h @@ -51,6 +51,7 @@ #if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) #define HAL_USE_NAND FALSE #endif + /** * @brief Enables the 1-wire subsystem. */ From cf7e66ddaed1f5f0e02b79a691a84a3dbae72348 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 30 Oct 2019 13:35:59 +0100 Subject: [PATCH 8/9] Updating halconf_community.h for demos/testhal --- .../RT-STM32F303-DISCOVERY-PID/halconf_community.h | 14 ++++++++++++++ .../halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F0xx/COMP/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F0xx/crc/halconf_community.h | 14 ++++++++++++++ .../STM32/STM32F0xx/onewire/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F0xx/qei/halconf_community.h | 14 ++++++++++++++ .../STM32/STM32F1xx/onewire/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F1xx/qei/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F3xx/COMP/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F3xx/EEProm/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F3xx/OPAMP/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F4xx/EICU/halconf_community.h | 14 ++++++++++++++ .../STM32/STM32F4xx/USB_HOST/halconf_community.h | 14 ++++++++++++++ .../STM32/STM32F4xx/onewire/halconf_community.h | 14 ++++++++++++++ .../STM32/STM32F7xx/USB_MSD/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32L0xx/COMP/halconf_community.h | 14 ++++++++++++++ 17 files changed, 238 insertions(+) diff --git a/demos/STM32/RT-STM32F303-DISCOVERY-PID/halconf_community.h b/demos/STM32/RT-STM32F303-DISCOVERY-PID/halconf_community.h index 631bb9f8..246e3cbf 100644 --- a/demos/STM32/RT-STM32F303-DISCOVERY-PID/halconf_community.h +++ b/demos/STM32/RT-STM32F303-DISCOVERY-PID/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h index 2e8b241a..2e6d6334 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F0xx/COMP/halconf_community.h b/testhal/STM32/STM32F0xx/COMP/halconf_community.h index 76d48562..3279b50e 100644 --- a/testhal/STM32/STM32F0xx/COMP/halconf_community.h +++ b/testhal/STM32/STM32F0xx/COMP/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F0xx/crc/halconf_community.h b/testhal/STM32/STM32F0xx/crc/halconf_community.h index 91233edd..ad52c4b0 100644 --- a/testhal/STM32/STM32F0xx/crc/halconf_community.h +++ b/testhal/STM32/STM32F0xx/crc/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F0xx/onewire/halconf_community.h b/testhal/STM32/STM32F0xx/onewire/halconf_community.h index df56d7e5..42bdd726 100644 --- a/testhal/STM32/STM32F0xx/onewire/halconf_community.h +++ b/testhal/STM32/STM32F0xx/onewire/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F0xx/qei/halconf_community.h b/testhal/STM32/STM32F0xx/qei/halconf_community.h index 14fb2ca3..2017e790 100644 --- a/testhal/STM32/STM32F0xx/qei/halconf_community.h +++ b/testhal/STM32/STM32F0xx/qei/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F1xx/onewire/halconf_community.h b/testhal/STM32/STM32F1xx/onewire/halconf_community.h index df56d7e5..42bdd726 100644 --- a/testhal/STM32/STM32F1xx/onewire/halconf_community.h +++ b/testhal/STM32/STM32F1xx/onewire/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F1xx/qei/halconf_community.h b/testhal/STM32/STM32F1xx/qei/halconf_community.h index 14fb2ca3..2017e790 100644 --- a/testhal/STM32/STM32F1xx/qei/halconf_community.h +++ b/testhal/STM32/STM32F1xx/qei/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F3xx/COMP/halconf_community.h b/testhal/STM32/STM32F3xx/COMP/halconf_community.h index 76d48562..3279b50e 100644 --- a/testhal/STM32/STM32F3xx/COMP/halconf_community.h +++ b/testhal/STM32/STM32F3xx/COMP/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F3xx/EEProm/halconf_community.h b/testhal/STM32/STM32F3xx/EEProm/halconf_community.h index 75035b3c..2f4cf609 100644 --- a/testhal/STM32/STM32F3xx/EEProm/halconf_community.h +++ b/testhal/STM32/STM32F3xx/EEProm/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F3xx/OPAMP/halconf_community.h b/testhal/STM32/STM32F3xx/OPAMP/halconf_community.h index 41bc0df3..d56022ff 100644 --- a/testhal/STM32/STM32F3xx/OPAMP/halconf_community.h +++ b/testhal/STM32/STM32F3xx/OPAMP/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h b/testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h index dbd6debc..2ef054b3 100644 --- a/testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h +++ b/testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F4xx/EICU/halconf_community.h b/testhal/STM32/STM32F4xx/EICU/halconf_community.h index f5cb75e7..007550c5 100644 --- a/testhal/STM32/STM32F4xx/EICU/halconf_community.h +++ b/testhal/STM32/STM32F4xx/EICU/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h b/testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h index c76d1ef4..60452b81 100644 --- a/testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h +++ b/testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F4xx/onewire/halconf_community.h b/testhal/STM32/STM32F4xx/onewire/halconf_community.h index df56d7e5..42bdd726 100644 --- a/testhal/STM32/STM32F4xx/onewire/halconf_community.h +++ b/testhal/STM32/STM32F4xx/onewire/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h b/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h index 32d02719..6e804ec4 100644 --- a/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h +++ b/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32L0xx/COMP/halconf_community.h b/testhal/STM32/STM32L0xx/COMP/halconf_community.h index 76d48562..3279b50e 100644 --- a/testhal/STM32/STM32L0xx/COMP/halconf_community.h +++ b/testhal/STM32/STM32L0xx/COMP/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ From c65efdcfa1d281a8f0a29bb864e86dd0c892c156 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Thu, 31 Oct 2019 14:45:33 +0100 Subject: [PATCH 9/9] Fixed unwanted rename --- os/common/ext/CMSIS/KINETIS/MK66F18.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/os/common/ext/CMSIS/KINETIS/MK66F18.h b/os/common/ext/CMSIS/KINETIS/MK66F18.h index 2fdfbbda..432944fb 100644 --- a/os/common/ext/CMSIS/KINETIS/MK66F18.h +++ b/os/common/ext/CMSIS/KINETIS/MK66F18.h @@ -14379,7 +14379,7 @@ typedef struct { __IO uint32_t AC; /**< Address and Control Register, array offset: 0x48, array step: 0x8 */ __IO uint32_t CM; /**< Control Mask, array offset: 0x4C, array step: 0x8 */ } BLOCK[2]; -} FSMC_SDRAM_TypeDef; +} SDRAM_TypeDef; /* ---------------------------------------------------------------------------- -- SDRAM Register Masks @@ -14464,7 +14464,7 @@ typedef struct { /** Peripheral SDRAM base address */ #define SDRAM_BASE (0x4000F000u) /** Peripheral SDRAM base pointer */ -#define SDRAM ((FSMC_SDRAM_TypeDef *)SDRAM_BASE) +#define SDRAM ((SDRAM_TypeDef *)SDRAM_BASE) /** Array initializer of SDRAM peripheral base addresses */ #define SDRAM_BASE_ADDRS { SDRAM_BASE } /** Array initializer of SDRAM peripheral base pointers */