Delete unused exti and control defines
This commit is contained in:
Stefan Kerkmann
parent
387ccb8dea
commit
d25731f7cf
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@ -3092,517 +3092,6 @@ typedef struct
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#define AFIO_PCF1_EXMC_NADV_REMAP_Msk (0x1U << AFIO_PCF1_EXMC_NADV_REMAP_Pos) /*!< 0x00000400 */
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#define AFIO_PCF1_EXMC_NADV_REMAP AFIO_PCF1_EXMC_NADV_REMAP_Msk /*!< EXMC NADV remapping */
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/******************************************************************************/
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/* */
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/* External Interrupt/Event Controller */
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/* */
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/******************************************************************************/
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/******************* Bit definition for EXTI_IMR register *******************/
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#define EXTI_IMR_MR0_Pos (0U)
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#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
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#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
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#define EXTI_IMR_MR1_Pos (1U)
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#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
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#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
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#define EXTI_IMR_MR2_Pos (2U)
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#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
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#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
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#define EXTI_IMR_MR3_Pos (3U)
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#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
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#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
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#define EXTI_IMR_MR4_Pos (4U)
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#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
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#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
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#define EXTI_IMR_MR5_Pos (5U)
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#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
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#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
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#define EXTI_IMR_MR6_Pos (6U)
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#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
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#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
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#define EXTI_IMR_MR7_Pos (7U)
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#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
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#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
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#define EXTI_IMR_MR8_Pos (8U)
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#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
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#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
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#define EXTI_IMR_MR9_Pos (9U)
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#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
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#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
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#define EXTI_IMR_MR10_Pos (10U)
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#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
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#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
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#define EXTI_IMR_MR11_Pos (11U)
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#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
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#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
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#define EXTI_IMR_MR12_Pos (12U)
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#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
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#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
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#define EXTI_IMR_MR13_Pos (13U)
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#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
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#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
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#define EXTI_IMR_MR14_Pos (14U)
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#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
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#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
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#define EXTI_IMR_MR15_Pos (15U)
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#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
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#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
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#define EXTI_IMR_MR16_Pos (16U)
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#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
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#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
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#define EXTI_IMR_MR17_Pos (17U)
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#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
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#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
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#define EXTI_IMR_MR18_Pos (18U)
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#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
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#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
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#define EXTI_IMR_MR19_Pos (19U)
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#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
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#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
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/* References Defines */
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#define EXTI_IMR_IM0 EXTI_IMR_MR0
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#define EXTI_IMR_IM1 EXTI_IMR_MR1
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#define EXTI_IMR_IM2 EXTI_IMR_MR2
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#define EXTI_IMR_IM3 EXTI_IMR_MR3
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#define EXTI_IMR_IM4 EXTI_IMR_MR4
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#define EXTI_IMR_IM5 EXTI_IMR_MR5
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#define EXTI_IMR_IM6 EXTI_IMR_MR6
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#define EXTI_IMR_IM7 EXTI_IMR_MR7
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#define EXTI_IMR_IM8 EXTI_IMR_MR8
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#define EXTI_IMR_IM9 EXTI_IMR_MR9
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#define EXTI_IMR_IM10 EXTI_IMR_MR10
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#define EXTI_IMR_IM11 EXTI_IMR_MR11
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#define EXTI_IMR_IM12 EXTI_IMR_MR12
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#define EXTI_IMR_IM13 EXTI_IMR_MR13
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#define EXTI_IMR_IM14 EXTI_IMR_MR14
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#define EXTI_IMR_IM15 EXTI_IMR_MR15
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#define EXTI_IMR_IM16 EXTI_IMR_MR16
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#define EXTI_IMR_IM17 EXTI_IMR_MR17
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#define EXTI_IMR_IM18 EXTI_IMR_MR18
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#define EXTI_IMR_IM19 EXTI_IMR_MR19
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#define EXTI_IMR_IM 0x000FFFFFU /*!< Interrupt Mask All */
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/******************* Bit definition for EXTI_EMR register *******************/
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#define EXTI_EMR_MR0_Pos (0U)
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#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
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#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
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#define EXTI_EMR_MR1_Pos (1U)
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#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
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#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
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#define EXTI_EMR_MR2_Pos (2U)
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#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
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#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
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#define EXTI_EMR_MR3_Pos (3U)
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#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
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#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
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#define EXTI_EMR_MR4_Pos (4U)
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#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
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#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
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#define EXTI_EMR_MR5_Pos (5U)
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#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
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#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
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#define EXTI_EMR_MR6_Pos (6U)
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#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
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#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
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#define EXTI_EMR_MR7_Pos (7U)
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#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
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#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
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#define EXTI_EMR_MR8_Pos (8U)
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#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
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#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
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#define EXTI_EMR_MR9_Pos (9U)
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#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
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#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
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#define EXTI_EMR_MR10_Pos (10U)
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#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
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#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
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#define EXTI_EMR_MR11_Pos (11U)
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#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
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#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
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#define EXTI_EMR_MR12_Pos (12U)
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#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
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#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
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#define EXTI_EMR_MR13_Pos (13U)
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#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
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#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
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#define EXTI_EMR_MR14_Pos (14U)
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#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
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#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
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#define EXTI_EMR_MR15_Pos (15U)
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#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
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#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
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#define EXTI_EMR_MR16_Pos (16U)
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#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
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#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
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#define EXTI_EMR_MR17_Pos (17U)
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#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
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#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
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#define EXTI_EMR_MR18_Pos (18U)
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#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
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#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
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#define EXTI_EMR_MR19_Pos (19U)
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#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
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#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
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/* References Defines */
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#define EXTI_EMR_EM0 EXTI_EMR_MR0
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#define EXTI_EMR_EM1 EXTI_EMR_MR1
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#define EXTI_EMR_EM2 EXTI_EMR_MR2
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#define EXTI_EMR_EM3 EXTI_EMR_MR3
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#define EXTI_EMR_EM4 EXTI_EMR_MR4
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#define EXTI_EMR_EM5 EXTI_EMR_MR5
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#define EXTI_EMR_EM6 EXTI_EMR_MR6
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#define EXTI_EMR_EM7 EXTI_EMR_MR7
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#define EXTI_EMR_EM8 EXTI_EMR_MR8
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#define EXTI_EMR_EM9 EXTI_EMR_MR9
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#define EXTI_EMR_EM10 EXTI_EMR_MR10
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#define EXTI_EMR_EM11 EXTI_EMR_MR11
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#define EXTI_EMR_EM12 EXTI_EMR_MR12
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#define EXTI_EMR_EM13 EXTI_EMR_MR13
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#define EXTI_EMR_EM14 EXTI_EMR_MR14
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#define EXTI_EMR_EM15 EXTI_EMR_MR15
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#define EXTI_EMR_EM16 EXTI_EMR_MR16
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#define EXTI_EMR_EM17 EXTI_EMR_MR17
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#define EXTI_EMR_EM18 EXTI_EMR_MR18
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#define EXTI_EMR_EM19 EXTI_EMR_MR19
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/****************** Bit definition for EXTI_RTSR register *******************/
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#define EXTI_RTSR_TR0_Pos (0U)
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#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
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#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
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#define EXTI_RTSR_TR1_Pos (1U)
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#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
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#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
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#define EXTI_RTSR_TR2_Pos (2U)
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#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
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#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
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#define EXTI_RTSR_TR3_Pos (3U)
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#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
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#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
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#define EXTI_RTSR_TR4_Pos (4U)
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#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
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#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
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#define EXTI_RTSR_TR5_Pos (5U)
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#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
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#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
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#define EXTI_RTSR_TR6_Pos (6U)
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#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
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#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
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#define EXTI_RTSR_TR7_Pos (7U)
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#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
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#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
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#define EXTI_RTSR_TR8_Pos (8U)
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#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
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#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
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#define EXTI_RTSR_TR9_Pos (9U)
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#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
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#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
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#define EXTI_RTSR_TR10_Pos (10U)
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#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
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#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
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#define EXTI_RTSR_TR11_Pos (11U)
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#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
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#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
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#define EXTI_RTSR_TR12_Pos (12U)
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#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
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#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
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#define EXTI_RTSR_TR13_Pos (13U)
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#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
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#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
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#define EXTI_RTSR_TR14_Pos (14U)
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#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
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#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
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#define EXTI_RTSR_TR15_Pos (15U)
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#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
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#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
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#define EXTI_RTSR_TR16_Pos (16U)
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#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
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#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
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#define EXTI_RTSR_TR17_Pos (17U)
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#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
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#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
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#define EXTI_RTSR_TR18_Pos (18U)
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#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
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#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
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#define EXTI_RTSR_TR19_Pos (19U)
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#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
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#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
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/* References Defines */
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#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
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#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
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#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
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#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
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#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
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#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
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#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
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#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
|
||||
#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
|
||||
#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
|
||||
#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
|
||||
#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
|
||||
#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
|
||||
#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
|
||||
#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
|
||||
#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
|
||||
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
|
||||
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
|
||||
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
|
||||
#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR register *******************/
|
||||
#define EXTI_FTSR_TR0_Pos (0U)
|
||||
#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
|
||||
#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
|
||||
#define EXTI_FTSR_TR1_Pos (1U)
|
||||
#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
|
||||
#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
|
||||
#define EXTI_FTSR_TR2_Pos (2U)
|
||||
#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
|
||||
#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
|
||||
#define EXTI_FTSR_TR3_Pos (3U)
|
||||
#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
|
||||
#define EXTI_FTSR_TR4_Pos (4U)
|
||||
#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
|
||||
#define EXTI_FTSR_TR5_Pos (5U)
|
||||
#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
|
||||
#define EXTI_FTSR_TR6_Pos (6U)
|
||||
#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
|
||||
#define EXTI_FTSR_TR7_Pos (7U)
|
||||
#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
|
||||
#define EXTI_FTSR_TR8_Pos (8U)
|
||||
#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
|
||||
#define EXTI_FTSR_TR9_Pos (9U)
|
||||
#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
|
||||
#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
|
||||
#define EXTI_FTSR_TR10_Pos (10U)
|
||||
#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
|
||||
#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
|
||||
#define EXTI_FTSR_TR11_Pos (11U)
|
||||
#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
|
||||
#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
|
||||
#define EXTI_FTSR_TR12_Pos (12U)
|
||||
#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
|
||||
#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
|
||||
#define EXTI_FTSR_TR13_Pos (13U)
|
||||
#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
|
||||
#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
|
||||
#define EXTI_FTSR_TR14_Pos (14U)
|
||||
#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
|
||||
#define EXTI_FTSR_TR15_Pos (15U)
|
||||
#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
|
||||
#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
|
||||
#define EXTI_FTSR_TR16_Pos (16U)
|
||||
#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
|
||||
#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
|
||||
#define EXTI_FTSR_TR17_Pos (17U)
|
||||
#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
|
||||
#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
|
||||
#define EXTI_FTSR_TR18_Pos (18U)
|
||||
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
|
||||
#define EXTI_FTSR_TR19_Pos (19U)
|
||||
#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
|
||||
#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
|
||||
|
||||
/* References Defines */
|
||||
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
|
||||
#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
|
||||
#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
|
||||
#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
|
||||
#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
|
||||
#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
|
||||
#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
|
||||
#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
|
||||
#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
|
||||
#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
|
||||
#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
|
||||
#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
|
||||
#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
|
||||
#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
|
||||
#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
|
||||
#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
|
||||
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
|
||||
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
|
||||
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
|
||||
#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER register ******************/
|
||||
#define EXTI_SWIER_SWIER0_Pos (0U)
|
||||
#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
|
||||
#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
|
||||
#define EXTI_SWIER_SWIER1_Pos (1U)
|
||||
#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
|
||||
#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
|
||||
#define EXTI_SWIER_SWIER2_Pos (2U)
|
||||
#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
|
||||
#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
|
||||
#define EXTI_SWIER_SWIER3_Pos (3U)
|
||||
#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
|
||||
#define EXTI_SWIER_SWIER4_Pos (4U)
|
||||
#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
|
||||
#define EXTI_SWIER_SWIER5_Pos (5U)
|
||||
#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
|
||||
#define EXTI_SWIER_SWIER6_Pos (6U)
|
||||
#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
|
||||
#define EXTI_SWIER_SWIER7_Pos (7U)
|
||||
#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
|
||||
#define EXTI_SWIER_SWIER8_Pos (8U)
|
||||
#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
|
||||
#define EXTI_SWIER_SWIER9_Pos (9U)
|
||||
#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
|
||||
#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
|
||||
#define EXTI_SWIER_SWIER10_Pos (10U)
|
||||
#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
|
||||
#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
|
||||
#define EXTI_SWIER_SWIER11_Pos (11U)
|
||||
#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
|
||||
#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
|
||||
#define EXTI_SWIER_SWIER12_Pos (12U)
|
||||
#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
|
||||
#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
|
||||
#define EXTI_SWIER_SWIER13_Pos (13U)
|
||||
#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
|
||||
#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
|
||||
#define EXTI_SWIER_SWIER14_Pos (14U)
|
||||
#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
|
||||
#define EXTI_SWIER_SWIER15_Pos (15U)
|
||||
#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
|
||||
#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
|
||||
#define EXTI_SWIER_SWIER16_Pos (16U)
|
||||
#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
|
||||
#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
|
||||
#define EXTI_SWIER_SWIER17_Pos (17U)
|
||||
#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
|
||||
#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
|
||||
#define EXTI_SWIER_SWIER18_Pos (18U)
|
||||
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
|
||||
#define EXTI_SWIER_SWIER19_Pos (19U)
|
||||
#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
|
||||
#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
|
||||
|
||||
/* References Defines */
|
||||
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
|
||||
#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
|
||||
#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
|
||||
#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
|
||||
#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
|
||||
#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
|
||||
#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
|
||||
#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
|
||||
#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
|
||||
#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
|
||||
#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
|
||||
#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
|
||||
#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
|
||||
#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
|
||||
#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
|
||||
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
|
||||
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
|
||||
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
|
||||
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
|
||||
#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
|
||||
|
||||
/******************* Bit definition for EXTI_PR register ********************/
|
||||
#define EXTI_PR_PR0_Pos (0U)
|
||||
#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
|
||||
#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
|
||||
#define EXTI_PR_PR1_Pos (1U)
|
||||
#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
|
||||
#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
|
||||
#define EXTI_PR_PR2_Pos (2U)
|
||||
#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
|
||||
#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
|
||||
#define EXTI_PR_PR3_Pos (3U)
|
||||
#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
|
||||
#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
|
||||
#define EXTI_PR_PR4_Pos (4U)
|
||||
#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
|
||||
#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
|
||||
#define EXTI_PR_PR5_Pos (5U)
|
||||
#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
|
||||
#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
|
||||
#define EXTI_PR_PR6_Pos (6U)
|
||||
#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
|
||||
#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
|
||||
#define EXTI_PR_PR7_Pos (7U)
|
||||
#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
|
||||
#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
|
||||
#define EXTI_PR_PR8_Pos (8U)
|
||||
#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
|
||||
#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
|
||||
#define EXTI_PR_PR9_Pos (9U)
|
||||
#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
|
||||
#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
|
||||
#define EXTI_PR_PR10_Pos (10U)
|
||||
#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
|
||||
#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
|
||||
#define EXTI_PR_PR11_Pos (11U)
|
||||
#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
|
||||
#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
|
||||
#define EXTI_PR_PR12_Pos (12U)
|
||||
#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
|
||||
#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
|
||||
#define EXTI_PR_PR13_Pos (13U)
|
||||
#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
|
||||
#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
|
||||
#define EXTI_PR_PR14_Pos (14U)
|
||||
#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
|
||||
#define EXTI_PR_PR15_Pos (15U)
|
||||
#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
|
||||
#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
|
||||
#define EXTI_PR_PR16_Pos (16U)
|
||||
#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
|
||||
#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
|
||||
#define EXTI_PR_PR17_Pos (17U)
|
||||
#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
|
||||
#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
|
||||
#define EXTI_PR_PR18_Pos (18U)
|
||||
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
|
||||
#define EXTI_PR_PR19_Pos (19U)
|
||||
#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
|
||||
#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
|
||||
|
||||
/* References Defines */
|
||||
#define EXTI_PR_PIF0 EXTI_PR_PR0
|
||||
#define EXTI_PR_PIF1 EXTI_PR_PR1
|
||||
#define EXTI_PR_PIF2 EXTI_PR_PR2
|
||||
#define EXTI_PR_PIF3 EXTI_PR_PR3
|
||||
#define EXTI_PR_PIF4 EXTI_PR_PR4
|
||||
#define EXTI_PR_PIF5 EXTI_PR_PR5
|
||||
#define EXTI_PR_PIF6 EXTI_PR_PR6
|
||||
#define EXTI_PR_PIF7 EXTI_PR_PR7
|
||||
#define EXTI_PR_PIF8 EXTI_PR_PR8
|
||||
#define EXTI_PR_PIF9 EXTI_PR_PR9
|
||||
#define EXTI_PR_PIF10 EXTI_PR_PR10
|
||||
#define EXTI_PR_PIF11 EXTI_PR_PR11
|
||||
#define EXTI_PR_PIF12 EXTI_PR_PR12
|
||||
#define EXTI_PR_PIF13 EXTI_PR_PR13
|
||||
#define EXTI_PR_PIF14 EXTI_PR_PR14
|
||||
#define EXTI_PR_PIF15 EXTI_PR_PR15
|
||||
#define EXTI_PR_PIF16 EXTI_PR_PR16
|
||||
#define EXTI_PR_PIF17 EXTI_PR_PR17
|
||||
#define EXTI_PR_PIF18 EXTI_PR_PR18
|
||||
#define EXTI_PR_PIF19 EXTI_PR_PR19
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* DMA Controller */
|
||||
|
|
@ -12482,423 +11971,6 @@ typedef struct
|
|||
#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
|
||||
#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
/****************************** ADC Instances *********************************/
|
||||
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC0) || \
|
||||
((INSTANCE) == ADC1))
|
||||
|
||||
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC02_COMMON)
|
||||
|
||||
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC0)
|
||||
|
||||
#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC0)
|
||||
|
||||
/****************************** CAN Instances *********************************/
|
||||
#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
|
||||
((INSTANCE) == CAN2))
|
||||
|
||||
/****************************** CRC Instances *********************************/
|
||||
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
|
||||
|
||||
/****************************** DAC Instances *********************************/
|
||||
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
|
||||
|
||||
/****************************** DMA Instances *********************************/
|
||||
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA0_Channel0) || \
|
||||
((INSTANCE) == DMA0_Channel1) || \
|
||||
((INSTANCE) == DMA0_Channel2) || \
|
||||
((INSTANCE) == DMA0_Channel3) || \
|
||||
((INSTANCE) == DMA0_Channel4) || \
|
||||
((INSTANCE) == DMA0_Channel5) || \
|
||||
((INSTANCE) == DMA0_Channel6) || \
|
||||
((INSTANCE) == DMA1_Channel0) || \
|
||||
((INSTANCE) == DMA1_Channel1) || \
|
||||
((INSTANCE) == DMA1_Channel2) || \
|
||||
((INSTANCE) == DMA1_Channel3) || \
|
||||
((INSTANCE) == DMA1_Channel4))
|
||||
|
||||
/******************************* GPIO Instances *******************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOD) || \
|
||||
((INSTANCE) == GPIOE))
|
||||
|
||||
/**************************** GPIO Alternate Function Instances ***************/
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
|
||||
|
||||
/**************************** GPIO Lock Instances *****************************/
|
||||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
|
||||
|
||||
/******************************** I2C Instances *******************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C0) || \
|
||||
((INSTANCE) == I2C1))
|
||||
|
||||
/******************************* SMBUS Instances ******************************/
|
||||
#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
|
||||
|
||||
/******************************** I2S Instances *******************************/
|
||||
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
|
||||
((INSTANCE) == SPI3))
|
||||
|
||||
/****************************** IWDG Instances ********************************/
|
||||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||||
|
||||
/******************************** SPI Instances *******************************/
|
||||
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
|
||||
((INSTANCE) == SPI2) || \
|
||||
((INSTANCE) == SPI3))
|
||||
|
||||
/****************************** START TIM Instances ***************************/
|
||||
/****************************** TIM Instances *********************************/
|
||||
#define IS_TIM_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM6))
|
||||
|
||||
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM0)
|
||||
|
||||
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CC2_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CC3_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CC4_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_XOR_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM6))
|
||||
|
||||
#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
|
||||
((INSTANCE) == TIM0)
|
||||
|
||||
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
|
||||
((((INSTANCE) == TIM0) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3) || \
|
||||
((CHANNEL) == TIM_CHANNEL_4))) \
|
||||
|| \
|
||||
(((INSTANCE) == TIM1) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3) || \
|
||||
((CHANNEL) == TIM_CHANNEL_4))) \
|
||||
|| \
|
||||
(((INSTANCE) == TIM2) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3) || \
|
||||
((CHANNEL) == TIM_CHANNEL_4))) \
|
||||
|| \
|
||||
(((INSTANCE) == TIM3) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3) || \
|
||||
((CHANNEL) == TIM_CHANNEL_4))) \
|
||||
|| \
|
||||
(((INSTANCE) == TIM4) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3) || \
|
||||
((CHANNEL) == TIM_CHANNEL_4))))
|
||||
|
||||
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
|
||||
(((INSTANCE) == TIM0) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3)))
|
||||
|
||||
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
|
||||
((INSTANCE) == TIM0)
|
||||
|
||||
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_DMA_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM6))
|
||||
|
||||
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
|
||||
(((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
|
||||
((INSTANCE) == TIM0)
|
||||
|
||||
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM0) || \
|
||||
((INSTANCE) == TIM1) || \
|
||||
((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM3) || \
|
||||
((INSTANCE) == TIM4))
|
||||
|
||||
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
|
||||
|
||||
/****************************** END TIM Instances *****************************/
|
||||
|
||||
|
||||
/******************** USART Instances : Synchronous mode **********************/
|
||||
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
|
||||
((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2))
|
||||
|
||||
/******************** UART Instances : Asynchronous mode **********************/
|
||||
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
|
||||
((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == UART3) || \
|
||||
((INSTANCE) == UART4))
|
||||
|
||||
/******************** UART Instances : Half-Duplex mode **********************/
|
||||
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
|
||||
((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == UART3) || \
|
||||
((INSTANCE) == UART4))
|
||||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
|
||||
((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == UART3) || \
|
||||
((INSTANCE) == UART4))
|
||||
|
||||
/****************** UART Instances : Hardware Flow control ********************/
|
||||
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
|
||||
((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2))
|
||||
|
||||
/********************* UART Instances : Smard card mode ***********************/
|
||||
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
|
||||
((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2))
|
||||
|
||||
/*********************** UART Instances : IRDA mode ***************************/
|
||||
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
|
||||
((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == UART3) || \
|
||||
((INSTANCE) == UART4))
|
||||
|
||||
/***************** UART Instances : Multi-Processor mode **********************/
|
||||
#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
|
||||
((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == UART3) || \
|
||||
((INSTANCE) == UART4))
|
||||
|
||||
/***************** UART Instances : DMA mode available **********************/
|
||||
#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
|
||||
((INSTANCE) == USART1) || \
|
||||
((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == UART3))
|
||||
|
||||
/****************************** RTC Instances *********************************/
|
||||
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
||||
|
||||
/**************************** WWDG Instances *****************************/
|
||||
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
||||
|
||||
|
||||
/****************************** USB Instances ********************************/
|
||||
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_USBFS)
|
||||
|
||||
|
||||
#define RCU_HXTAL_MIN 3000000U
|
||||
#define RCU_HXTAL_MAX 25000000U
|
||||
|
||||
#define RCU_MAX_FREQUENCY 72000000U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************************************************************************/
|
||||
/* For a painless codes migration between the GD32VF103 device product */
|
||||
/* lines, the aliases defined below are put in place to overcome the */
|
||||
/* differences in the interrupt handlers and IRQn definitions. */
|
||||
/* No need to update developed interrupt code when moving across */
|
||||
/* product lines within the same STM32F1 Family */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Aliases for __IRQn */
|
||||
#define ADC0_IRQn ADC0_2_IRQn
|
||||
#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
|
||||
#define USB_LP_IRQn CAN1_RX0_IRQn
|
||||
#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
|
||||
#define USB_HP_IRQn CAN1_TX_IRQn
|
||||
#define DMA1_Channel3_5_IRQn DMA1_Channel3_IRQn
|
||||
#define USBWakeUp_IRQn USBFS_WKUP_IRQn
|
||||
#define CEC_IRQn USBFS_WKUP_IRQn
|
||||
#define TIM0_BRK_TIM9_IRQn TIM0_BRK_IRQn
|
||||
#define TIM0_BRK_TIM05_IRQn TIM0_BRK_IRQn
|
||||
#define TIM9_IRQn TIM0_BRK_IRQn
|
||||
#define TIM01_IRQn TIM0_TRG_COM_IRQn
|
||||
#define TIM0_TRG_COM_TIM01_IRQn TIM0_TRG_COM_IRQn
|
||||
#define TIM0_TRG_COM_TIM07_IRQn TIM0_TRG_COM_IRQn
|
||||
#define TIM00_IRQn TIM0_UP_IRQn
|
||||
#define TIM0_UP_TIM06_IRQn TIM0_UP_IRQn
|
||||
#define TIM0_UP_TIM00_IRQn TIM0_UP_IRQn
|
||||
#define TIM4_DAC_IRQn TIM4_IRQn
|
||||
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
#define ADC0_IRQHandler ADC0_2_IRQHandler
|
||||
#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
|
||||
#define USB_LP_IRQHandler CAN1_RX0_IRQHandler
|
||||
#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
|
||||
#define USB_HP_IRQHandler CAN1_TX_IRQHandler
|
||||
#define DMA1_Channel3_5_IRQHandler DMA1_Channel3_IRQHandler
|
||||
#define USBWakeUp_IRQHandler USBFS_WKUP_IRQHandler
|
||||
#define CEC_IRQHandler USBFS_WKUP_IRQHandler
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#define TIM0_BRK_TIM9_IRQHandler TIM0_BRK_IRQHandler
|
||||
#define TIM0_BRK_TIM05_IRQHandler TIM0_BRK_IRQHandler
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#define TIM9_IRQHandler TIM0_BRK_IRQHandler
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#define TIM01_IRQHandler TIM0_TRG_COM_IRQHandler
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#define TIM0_TRG_COM_TIM01_IRQHandler TIM0_TRG_COM_IRQHandler
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#define TIM0_TRG_COM_TIM07_IRQHandler TIM0_TRG_COM_IRQHandler
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#define TIM00_IRQHandler TIM0_UP_IRQHandler
|
||||
#define TIM0_UP_TIM06_IRQHandler TIM0_UP_IRQHandler
|
||||
#define TIM0_UP_TIM00_IRQHandler TIM0_UP_IRQHandler
|
||||
#define TIM4_DAC_IRQHandler TIM4_IRQHandler
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
|
|
|||
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Reference in New Issue