Merge pull request #276 from KarlK90/gd32vf103-add-crc
[GD32VF103] Add CRC driver
This commit is contained in:
Fabien Poussin
GitHub
commit
d53c82a884
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@ -55,7 +55,7 @@
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#define LINE_GREEN_LED PAL_LINE(GPIOA, PIN_GREEN_LED)
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#define LINE_BLUE_LED PAL_LINE(GPIOA, PIN_BLUE_LED)
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#define LINE_RED_LED PAL_LINE(GPIOA, PIN_RED_LED)
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#define LINE_RED_LED PAL_LINE(GPIOC, PIN_RED_LED)
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#define LINE_DISPLAY_MISO PAL_LINE(GPIOA, PIN_DISPLAY_MISO)
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#define LINE_DISPLAY_MOSI PAL_LINE(GPIOA, PIN_DISPLAY_MOSI)
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@ -113,9 +113,10 @@
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/*
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* Port C setup.
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* Everything input with pull-up except:
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* C13 - RED LED - Push Pull output 50MHz
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*/
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#define VAL_GPIOCCRL 0x88888888 /* PC7...PC0 */
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#define VAL_GPIOCCRH 0x88888888 /* PC15...PC8 */
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#define VAL_GPIOCCRH 0x88388888 /* PC15...PC8 */
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#define VAL_GPIOCODR 0xFFFFFFFF
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/*
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@ -0,0 +1,11 @@
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ifeq ($(USE_SMART_BUILD),yes)
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ifneq ($(findstring HAL_USE_CRC TRUE,$(HALCONF)),)
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PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.c \
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${CHIBIOS_CONTRIB}/os/various/crcsw.c
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endif
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else
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PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.c \
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${CHIBIOS_CONTRIB}/os/various/crcsw.c
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endif
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PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/CRC
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@ -0,0 +1,259 @@
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/*
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ChibiOS - Copyright (C) 2015 Michael D. Spradling
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file GD32VF103/CRC/hal_crc_lld.c
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* @brief GD32 CRC subsystem low level driver source.
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*
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* @addtogroup CRC
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* @{
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*/
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#include "hal.h"
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#if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__)
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/**
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* Allow CRC Software override for ST drivers. Some ST CRC implimentations
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* have limited capabilities.
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*/
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#if CRCSW_USE_CRC1 != TRUE
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @brief CRC default configuration.
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*/
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static const CRCConfig default_config = {
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.poly_size = 32,
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.poly = 0x04C11DB7,
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.initial_val = 0xFFFFFFFF,
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.final_val = 0xFFFFFFFF,
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.reflect_data = 1,
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.reflect_remainder = 1
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};
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief CRC1 driver identifier.*/
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#if GD32_CRC_USE_CRC0 || defined(__DOXYGEN__)
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CRCDriver CRCD1;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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void _crc_lld_calc_byte(CRCDriver *crcp, uint8_t data) {
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__IO uint8_t *crc8 = (__IO uint8_t*)&(crcp->crc->DATA);
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*crc8 = data;
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}
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/*
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* @brief Returns calculated CRC from last reset
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*
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* @param[in] crcp pointer to the @p CRCDriver object
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* @param[in] data data to be added to crc
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*
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* @notapi
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*/
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void _crc_lld_calc_halfword(CRCDriver *crcp, uint16_t data) {
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__IO uint16_t *crc16 = (__IO uint16_t*)&(crcp->crc->DATA);
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*crc16 = data;
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}
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/*
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* @brief Returns calculated CRC from last reset
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*
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* @param[in] crcp pointer to the @p CRCDriver object
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* @param[in] data data to be added to crc
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*
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* @notapi
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*/
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void _crc_lld_calc_word(CRCDriver *crcp, uint32_t data) {
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crcp->crc->DATA = data;
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/**
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* @brief Shared end-of-rx service routine.
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*
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* @param[in] crcp pointer to the @p CRCDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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#if CRC_USE_DMA == TRUE
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static void crc_lld_serve_interrupt(CRCDriver *crcp, uint32_t flags) {
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/* DMA errors handling.*/
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#if defined(GD32_CRC_DMA_ERROR_HOOK)
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if ((flags & (GD32_DMA_INTF_ERRIF)) != 0) {
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GD32_CRC_DMA_ERROR_HOOK(crcp);
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}
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#else
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(void)flags;
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#endif
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/* Stop everything.*/
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dmaStreamDisable(crcp->dmastp);
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if (crcp->rem_data_size) {
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/* Start DMA follow up transfer for next data chunk */
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crc_lld_start_calc(crcp, crcp->rem_data_size,
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(const void *)crcp->dmastp->channel->PADDR+0xffff);
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} else {
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/* Portable CRC ISR code defined in the high level driver, note, it is a macro.*/
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_crc_isr_code(crcp, crcp->crc->DATA ^ crcp->config->final_val);
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}
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level CRC driver initialization.
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*
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* @notapi
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*/
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void crc_lld_init(void) {
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crcObjectInit(&CRCD1);
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CRCD1.crc = CRC;
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}
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/**
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* @brief Configures and activates the CRC peripheral.
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*
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* @param[in] crcp pointer to the @p CRCDriver object
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*
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* @notapi
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*/
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void crc_lld_start(CRCDriver *crcp) {
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if (crcp->config == NULL)
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crcp->config = &default_config;
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rcuEnableCRC( FALSE );
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osalDbgAssert(crcp->config->initial_val == default_config.initial_val,
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"hardware doesn't support programmable initial value");
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osalDbgAssert(crcp->config->poly_size == default_config.poly_size,
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"hardware doesn't support programmable polynomial size");
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osalDbgAssert(crcp->config->poly == default_config.poly,
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"hardware doesn't support programmable polynomial");
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osalDbgAssert(crcp->config->reflect_data == default_config.reflect_data,
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"hardware doesn't support reflect of input data");
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osalDbgAssert(crcp->config->reflect_remainder == default_config.reflect_remainder,
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"hardware doesn't support reflect of output remainder");
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#if CRC_USE_DMA == TRUE
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crcp->dmamode = GD32_DMA_CTL_DIR_M2M | GD32_DMA_CTL_PNAGA |
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GD32_DMA_CTL_MWIDTH_WORD | GD32_DMA_CTL_PWIDTH_WORD |
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GD32_DMA_CTL_ERRIE | GD32_DMA_CTL_FTFIE |
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GD32_DMA_CTL_PRIO(GD32_CRC_CRC0_DMA_PRIORITY);
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{
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crcp->dmastp = dmaStreamAlloc(GD32_CRC_CRC0_DMA_STREAM,
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GD32_CRC_CRC0_DMA_IRQ_PRIORITY,
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(gd32_dmaisr_t)crc_lld_serve_interrupt,
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(void *)crcp);
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osalDbgAssert(crcp->dmastp != NULL, "unable to allocate stream");
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}
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#endif
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}
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/**
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* @brief Deactivates the CRC peripheral.
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*
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* @param[in] crcp pointer to the @p CRCDriver object
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*
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* @notapi
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*/
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void crc_lld_stop(CRCDriver *crcp) {
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#if CRC_USE_DMA == TRUE
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dmaStreamFree(crcp->dmastp);
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#else
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(void)crcp;
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#endif
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rcuDisableCRC();
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}
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/**
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* @brief Resets current CRC calculation.
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*
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* @param[in] crcp pointer to the @p CRCDriver object
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*
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* @notapi
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*/
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void crc_lld_reset(CRCDriver *crcp) {
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crcp->crc->CTL |= CRC_CTL_RST;
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}
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/**
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* @brief Returns calculated CRC from last reset
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*
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* @param[in] crcp pointer to the @p CRCDriver object
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* @param[in] n size of buf in bytes
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* @param[in] buf @p buffer location
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*
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* @notapi
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*/
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uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) {
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#if CRC_USE_DMA == TRUE
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crc_lld_start_calc(crcp, n, buf);
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(void) osalThreadSuspendS(&crcp->thread);
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#else
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while(n > 3) {
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_crc_lld_calc_word(crcp, *(uint32_t*)buf);
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buf+=4;
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n-=4;
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}
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osalDbgAssert(n == 0, "GD32 CRC Unit only supports WORD accesses");
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#endif
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return crcp->crc->DATA ^ crcp->config->final_val;
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}
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#if CRC_USE_DMA == TRUE
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void crc_lld_start_calc(CRCDriver *crcp, size_t n, const void *buf) {
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/* The GD32 DMA can only handle max 65535 bytes per transfer
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* because it's data count register has only 16 bit. */
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size_t sz = (n > 0xffff) ? 0xffff : n;
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crcp->rem_data_size = n-sz;
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dmaStreamSetPeripheral(crcp->dmastp, buf);
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dmaStreamSetMemory0(crcp->dmastp, &crcp->crc->DATA);
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dmaStreamSetTransactionSize(crcp->dmastp, (sz / 4));
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dmaStreamSetMode(crcp->dmastp, crcp->dmamode);
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dmaStreamEnable(crcp->dmastp);
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}
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#endif
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#endif /* CRCSW_USE_CRC1 */
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#endif /* HAL_USE_CRC */
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/** @} */
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@ -0,0 +1,255 @@
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/*
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ChibiOS - Copyright (C) 2015 Michael D. Spradling
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ChibiOS - Copyright (C) 2021 Stefan Kerkmann
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file GD32VF103/CRC/hal_crc_lld.h
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* @brief GD CRC subsystem low level driver header.
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*
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* @addtogroup CRC
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* @{
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*/
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#ifndef HAL_CRC_LLD_H_
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#define HAL_CRC_LLD_H_
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#if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__)
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/*
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* This error check must occur outsite of CRCSW_USE_CRC1 to check if
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* two LLD drivers are enabled at the same time
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*/
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#if GD32_CRC_USE_CRC0 == TRUE && \
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CRCSW_USE_CRC1 == TRUE
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#error "Software CRC can't be enable with GD32_CRC_USE_CRC0"
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#endif
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/**
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* Allow CRC Software override for ST drivers. Some ST CRC implimentations
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* have limited capabilities.
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*/
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#if CRCSW_USE_CRC1 != TRUE
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief CRC0 driver enable switch.
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* @details If set to @p TRUE the support for CRC1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(GD32_CRC_USE_CRC0) || defined(__DOXYGEN__)
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#define GD32_CRC_USE_CRC0 FALSE
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#endif
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/**
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* @brief CRC0 DMA priority (0..3|lowest..highest).
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* @note The priority level is for CRC DMA stream.
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*/
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#if !defined(GD32_CRC_CRC0_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_CRC_CRC0_DMA_PRIORITY 2
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#endif
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/**
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* @brief CRC0 DMA interrupt priority level setting.
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*/
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#if !defined(GD32_CRC_CRC0_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define GD32_CRC_CRC0_DMA_IRQ_PRIORITY 14
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#endif
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/**
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* @brief CRC0 DMA STREAM to use when performing CRC calculation.
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*/
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#if !defined(GD32_CRC_CRC0_DMA_STREAM) || defined(__DOXYGEN__)
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#define GD32_CRC_CRC0_DMA_STREAM GD32_DMA_STREAM_ID(0, 1)
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#endif
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/**
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* @brief CRC DMA error hook.
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*/
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#if !defined(GD32_CRC_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define GD32_CRC_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if GD32_CRC_USE_CRC0 && !GD32_HAS_CRC
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#error "Hardware CRC not present in the selected device"
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#error "Use CRCSW_USE_CRC1 for software implementation"
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#endif
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#if CRC_USE_DMA
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#if GD32_CRC_USE_CRC0 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(GD32_CRC_CRC0_DMA_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to CRC0"
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#endif
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#if GD32_CRC_USE_CRC0 && \
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!GD32_DMA_IS_VALID_PRIORITY(GD32_CRC_CRC0_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to CRC0"
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#endif
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#if !defined(GD32_DMA_REQUIRED)
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#define GD32_DMA_REQUIRED
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#endif
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Type of a structure representing an CRC driver.
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*/
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typedef struct CRCDriver CRCDriver;
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/**
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* @brief CRC notification callback type
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*
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* @param[in] crcp pointer to the @ CRCDriver object triggering the
|
||||
* callback
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*/
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typedef void (*crccallback_t)(CRCDriver *crcp, uint32_t crc);
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/**
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* @brief Driver configuration structure.
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*/
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typedef struct {
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/**
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* @brief The size of polynomial to be used for CRC.
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*/
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uint32_t poly_size;
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/**
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* @brief The coefficients of the polynomial to be used for CRC.
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*/
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uint32_t poly;
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/**
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* @brief The inital value
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*/
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uint32_t initial_val;
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/**
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* @brief The final XOR value
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*/
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uint32_t final_val;
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/**
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* @brief Reflect bit order data going into CRC
|
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*/
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bool reflect_data;
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/**
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* @brief Reflect bit order of final remainder
|
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*/
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bool reflect_remainder;
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/* End of the mandatory fields.*/
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/**
|
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* @brief Operation complete callback or @p NULL
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*/
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crccallback_t end_cb;
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} CRCConfig;
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||||
|
||||
|
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/**
|
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* @brief Structure representing an CRC driver.
|
||||
*/
|
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struct CRCDriver {
|
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/**
|
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* @brief Driver state.
|
||||
*/
|
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crcstate_t state;
|
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/**
|
||||
* @brief Current configuration data.
|
||||
*/
|
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const CRCConfig *config;
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#if CRC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Mutex protecting the peripheral.
|
||||
*/
|
||||
mutex_t mutex;
|
||||
#endif /* CRC_USE_MUTUAL_EXCLUSION */
|
||||
#if defined(CRC_DRIVER_EXT_FIELDS)
|
||||
CRC_DRIVER_EXT_FIELDS
|
||||
#endif
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Pointer to the CRCx registers block.
|
||||
*/
|
||||
CRC_TypeDef *crc;
|
||||
|
||||
#if CRC_USE_DMA == TRUE
|
||||
/**
|
||||
* @brief Waiting thread.
|
||||
*/
|
||||
thread_reference_t thread;
|
||||
/**
|
||||
* @brief Remaining data size.
|
||||
* @note The DMA can handle only 65535 bytes per transfer because
|
||||
* it's data count register is only 16 bits wide.
|
||||
*/
|
||||
size_t rem_data_size;
|
||||
/**
|
||||
* @brief CRC DMA stream
|
||||
*/
|
||||
const gd32_dma_stream_t *dmastp;
|
||||
/**
|
||||
* @brief DMA mode bit mask.
|
||||
*/
|
||||
uint32_t dmamode;
|
||||
#endif
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if GD32_CRC_USE_CRC0 && !defined(__DOXYGEN__)
|
||||
extern CRCDriver CRCD1;
|
||||
#endif /* GD32_CRC_USE_CRC0 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void crc_lld_init(void);
|
||||
void crc_lld_start(CRCDriver *crcp);
|
||||
void crc_lld_stop(CRCDriver *crcp);
|
||||
void crc_lld_reset(CRCDriver *crcp);
|
||||
uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf);
|
||||
#if CRC_USE_DMA
|
||||
void crc_lld_start_calc(CRCDriver *crcp, size_t n, const void *buf);
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CRCSW_USE_CRC1 */
|
||||
|
||||
#endif /* HAL_USE_CRC */
|
||||
|
||||
#endif /* HAL_CRC_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -347,6 +347,28 @@
|
|||
#define rcuResetCAN1() rcuResetAPB1(RCU_APB1RST_CAN1RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name CRC peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the CRC peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rcuEnableCRC(lp) rcuEnableAHB(RCU_AHBEN_CRCEN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the CRC peripheral clock.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rcuDisableCRC() rcuDisableAHB(RCU_AHBEN_CRCEN)
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name DMA peripherals specific RCU operations
|
||||
* @{
|
||||
|
|
|
|||
|
|
@ -161,6 +161,17 @@
|
|||
#define GD32_HAS_CAN1 TRUE
|
||||
#define GD32_CAN_MAX_FILTERS 28
|
||||
|
||||
/* CRC attributes.*/
|
||||
#define GD32_HAS_CRC TRUE
|
||||
#define GD32_CRC_PROGRAMMABLE FALSE
|
||||
|
||||
/* STM32 compatibility define. */
|
||||
#if GD32_CRC_USE_CRC0 == TRUE
|
||||
#define STM32_CRC_USE_CRC1 TRUE
|
||||
#else
|
||||
#define STM32_CRC_USE_CRC1 FALSE
|
||||
#endif
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define GD32_HAS_DAC_CH1 TRUE
|
||||
#define GD32_DAC_CH1_DMA_STREAM GD32_DMA_STREAM_ID(1, 2)
|
||||
|
|
|
|||
|
|
@ -199,11 +199,11 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
|
||||
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
|
||||
__IO uint32_t DATA; /*!< CRC Data register, Address offset: 0x00 */
|
||||
__IO uint8_t FDATA; /*!< CRC Independent data register, Address offset: 0x04 */
|
||||
uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
|
||||
uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
|
||||
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
|
||||
__IO uint32_t CTL; /*!< CRC Control register, Address offset: 0x08 */
|
||||
} CRC_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -637,20 +637,20 @@ typedef struct
|
|||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************* Bit definition for CRC_DR register *********************/
|
||||
#define CRC_DR_DR_Pos (0U)
|
||||
#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
|
||||
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
|
||||
/******************* Bit definition for CRC_DATA register *********************/
|
||||
#define CRC_DATA_DATA_Pos (0U)
|
||||
#define CRC_DATA_DATA_Msk (0xFFFFFFFFU << CRC_DATA_DATA_Pos) /*!< 0xFFFFFFFF */
|
||||
#define CRC_DATA_DATA CRC_DATA_DATA_Msk /*!< Data register bits */
|
||||
|
||||
/******************* Bit definition for CRC_IDR register ********************/
|
||||
#define CRC_IDR_IDR_Pos (0U)
|
||||
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
|
||||
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
|
||||
/******************* Bit definition for CRC_FDATA register ********************/
|
||||
#define CRC_FDATA_FDATA_Pos (0U)
|
||||
#define CRC_FDATA_FDATA_Msk (0xFFU << CRC_FDATA_FDATA_Pos) /*!< 0x000000FF */
|
||||
#define CRC_FDATA_FDATA CRC_FDATA_FDATA_Msk /*!< General-purpose 8-bit data register bits */
|
||||
|
||||
/******************** Bit definition for CRC_CR register ********************/
|
||||
#define CRC_CR_RESET_Pos (0U)
|
||||
#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
|
||||
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
|
||||
/******************** Bit definition for CRC_CTL register ********************/
|
||||
#define CRC_CTL_RST_Pos (0U)
|
||||
#define CRC_CTL_RST_Msk (0x1U << CRC_CTL_RST_Pos) /*!< 0x00000001 */
|
||||
#define CRC_CTL_RST CRC_CTL_RST_Msk /*!< RESET bit */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ ifeq ($(HALCONFDIR),)
|
|||
endif
|
||||
endif
|
||||
|
||||
HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
|
||||
HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h $(HALCONFDIR)/halconf_community.h | egrep -e "\#define"))
|
||||
|
||||
ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
|
||||
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/GD/GD32VF103/hal_adc_lld.c
|
||||
|
|
@ -31,6 +31,7 @@ endif
|
|||
|
||||
# Drivers compatible with the platform.
|
||||
include ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/CAN/driver.mk
|
||||
include ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/CRC/driver.mk
|
||||
include ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/DAC/driver.mk
|
||||
include ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/DMA/driver.mk
|
||||
include ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/GPIO/driver.mk
|
||||
|
|
|
|||
Loading…
Reference in New Issue